NT128D64SH4B0GM / NT128D64SH4BBGM 128MB : 16M x 64 PC3200 / PC2700 / PC2100 Unbuffered DDR SO-DIMM 200 pin Unbuffered DDR SO-DIMM Based on DDR400/333/266 16Mx16 SDRAM Features * 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM) * Data is read or written on both clock edges * 16Mx64 Double Unbuffered DDR SO-DIMM based on 16Mx16 * DRAM DLL aligns DQ and DQS transitions with clock transitions. DDR SDRAM. * Address and control signals are fully synchronous to positive * Performance: clock edge * Programmable Operation: PC3200 PC2700 PC2100 -5/-5T -6K -75B 3 2.5 2.5 fCK Clock Frequency 200 166 133 MHz tCK Clock Cycle 5 6 7.5 ns 400 333 266 MHz fDQ DQ Burst Frequency - DIMM CAS Latency: 2, 2.5, 3 Unit Speed Sort DIMM CAS Latency - Burst Type: Sequential or Interleave - Burst Length: 2, 4, 8 - Operation: Burst Read and Write * Auto Refresh (CBR) and Self Refresh Modes * Automatic and controlled precharge commands * Intended for 133, 166 and 200 MHz applications * 13/9/1 Addressing (row/column/bank) * Inputs and outputs are SSTL-2 compatible * 7.8 s Max. Average Periodic Refresh Interval * VDD = VDDQ = 2.5V 0.2V (2.6V 0.1V for DDR400A/B) * Serial Presence Detect * SDRAMs have 4 internal banks for concurrent operation * Gold contacts * Module has one physical bank * SDRAMs in 66-pin TSOP Type II Package * Differential clock inputs Description NT128D64SH4BBGM is an unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Small Outline Dual In-Line Memory Module (SO-DIMM), organized as a single bank of 16Mx64 high-speed memory array. The module uses four 16Mx16 DDR SDRAMs in 400 mil TSOP II packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 2.66" long space-saving footprint. The DIMM is intended for use in applications operating up to 200 MHz clock speeds and achieves high-speed data transfer rates of up to 400 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. Ordering Information Part Number Speed Power Organization Leads 16Mx64 Gold 200MHz (5ns @ CL = 3) NT128D64SH4BBGM-5 DDR400A PC3200A 166MHz (6ns @ CL = 2.5) 133MHz (7.5ns @ CL = 2) NT128D64SH4BBGM-5T DDR400B PC3200B NT128D64SH4BBGM-6K DDR333 PC2700 NT128D64SH4BBGM-75B NT128D64SH4B0GM-75B REV 1.0 12/11/2003 DDR266B PC2100 2.6V 200MHz (5ns @ CL = 3) 166MHz (6ns @ CL = 2.5) 166MHz (6ns @ CL = 2.5) 133MHz (7.5ns @ CL = 2) 133MHz (7.5ns @ CL = 2.5) 2.5V 100MHz (10ns @ CL = 2) 1 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64SH4B0GM / NT128D64SH4BBGM 128MB : 16M x 64 PC3200 / PC2700 / PC2100 Unbuffered DDR SO-DIMM Pin Description CK0, CK1, CK2, CK0, CK1, CK2 CKE0, CKE1 Differential Clock Inputs. DQ0-DQ63 Data input/output Clock Enable DQS0-DQS7 Bidirectional data strobes RAS Row Address Strobe DM0-DM7 Input Data Mask CAS Column Address Strobe VDD Power WE Write Enable VDDQ Supply voltage for DQs S0, S1 Chip Selects VSS Ground A0-A9, A11, A12 Address Inputs NC No Connect A10/AP Address Input/Auto-precharge SCL Serial Presence Detect Clock Input BA0, BA1 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input/output VREF Ref. Voltage for SSTL_2 inputs SA0-2 Serial Presence Detect Address Inputs VDDID VDD Identification flag. VDDSPD Serial EEPROM positive power supply Pinout Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREF 2 3 VSS 4 VREF 51 VSS 52 VSS 101 A9 102 A8 151 DQ42 152 DQ46 VSS 53 DQ19 54 DQ23 103 VSS 104 VSS 153 DQ43 154 DQ47 5 DQ0 6 DQ4 55 DQ24 56 DQ28 105 A7 106 A6 155 VDD 156 VDD 7 9 DQ1 8 DQ5 57 VDD 58 VDD 107 A5 108 A4 157 VDD 158 CK1 VDD 10 VDD 59 DQ25 60 DQ29 109 A3 110 A2 159 VSS 160 CK1 11 DQS0 12 DM0 61 DQS3 62 DM3 111 A1 112 A0 161 VSS 162 VSS 13 DQ2 14 DQ6 63 VSS 64 VSS 113 VDD 114 VDD 163 DQ48 164 DQ52 15 VSS 16 VSS 65 DQ26 66 DQ30 115 A10/AP 116 BA1 165 DQ49 166 DQ53 17 DQ3 18 DQ7 67 DQ27 68 DQ31 117 BA0 118 RAS 167 VDD 168 VDD 19 DQ8 20 DQ12 69 VDD 70 VDD 119 WE 120 CAS 169 DQS6 170 DM6 21 VDD 22 VDD 71 NC 72 NC 121 S0 122 S1 171 DQ50 172 DQ54 23 DQ9 24 DQ13 73 NC 74 NC 123 DU 124 DU 173 VSS 174 VSS 25 DQS1 26 DM1 75 VSS 76 VSS 125 VSS 126 VSS 175 DQ51 176 DQ55 27 VSS 28 VSS 77 DQS8 78 NC 127 DQ32 128 DQ36 177 DQ56 178 DQ60 29 DQ10 30 DQ14 79 NC 80 NC 129 DQ33 130 DQ37 179 VDD 180 VDD 31 DQ11 32 DQ15 81 VDD 82 VDD 131 VDD 132 VDD 181 DQ57 182 DQ61 33 VDD 34 VDD 83 NC 84 NC 133 DQS4 134 DM4 183 DQS7 184 DM7 35 CK0 36 VDD 85 DU 86 DU 135 DQ34 136 DQ38 185 VSS 186 VSS 37 CK0 38 VSS 87 VSS 88 VSS 137 VSS 138 VSS 187 DQ58 188 DQ62 39 VSS 40 VSS 89 CK2 90 VSS 139 DQ35 140 DQ39 189 DQ59 190 DQ63 41 DQ16 42 DQ20 91 CK2 92 VDD 141 DQ40 142 DQ44 191 VDD 192 VDD 43 DQ17 44 DQ21 93 VDD 94 VDD 143 VDD 144 VDD 193 SDA 194 SA0 45 VDD 46 VDD 95 CKE1 96 CKE0 145 DQ41 146 DQ45 195 SCL 196 SA1 47 DQS2 48 DM2 97 DU 98 DU 147 DQS5 148 DM5 197 VDDSPD 198 SA2 49 DQ18 50 DQ22 99 A12 100 A11 149 VSS 150 VSS 199 VDDID 200 DU Note: All pin assignments are consistent for all 8-byte unbuffered versions. REV 1.0 12/11/2003 2 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64SH4B0GM / NT128D64SH4BBGM 128MB : 16M x 64 PC3200 / PC2700 / PC2100 Unbuffered DDR SO-DIMM Input/Output Functional Description Symbol CK0, CK1, CK2, CK0, CK1, CK2 CKE0, CKE1 Type (SSTL) (SSTL) Polarity Cross point Active High Function The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR SDRAM command decoder when low and disables the (SSTL) Active Low command decoder when high. When the command decoder is disabled, new commands are RAS, CAS, WE (SSTL) Active Low When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to VREF Supply S0, S1 ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is selected by S1. VDDQ Supply BA0, BA1 (SSTL) be executed by the SDRAM. Reference voltage for SSTL-2 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) A0 - A9 A10/AP A11, A12 when sampled at the rising clock edge. In addition to the column address, AP is used to (SSTL) - invoke auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high, auto-precharge is selected and BA0/BA1 defines the bank to be precharged. If AP is low, auto-precharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. DQ0 - DQ63 (SSTL) - DQS0 - DQS7 (SSTL) Active High DM0 - DM7 Input Active High VDD, VSS Supply SA0 - SA2 - SDA - SCL - VDDSPD REV 1.0 12/11/2003 Supply Data and Check Bit input/output pins operate in the same manner as on conventional DRAMs. Data strobes: Output with read data, input with write data. Edge aligned with read data, centered on write data. Used to capture write data. The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. Power and ground for the DDR SDRAM input buffers and core logic Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pull-up. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pull-up. Serial EEPROM positive power supply. 3 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64SH4B0GM / NT128D64SH4BBGM 128MB : 16M x 64 PC3200 / PC2700 / PC2100 Unbuffered DDR SO-DIMM Functional Block Diagram (1 Bank, 16Mx16 DDR SDRAMs) S0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQS DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UDQS LDQS DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 UDQS A0-A12 D0 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 BA0-BA1 CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D1 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 A0-A12 : SDRAMs D0-D3 RAS : SDRAMs D0-D3 CAS CAS : SDRAMs D0-D3 CKE0 CKE : SDRAMs D0-D3 CKE1 N.C. WE Notes : 1. 2. 3. 4. REV 1.0 12/11/2003 WE : SDRAMs D0-D3 LDQS DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 UDQS CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D2 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 LDQS DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 UDQS VDDSPD VDD/VDDQ VREF VSS VDDID BA0-BA1 : SDRAMs D0-D3 RAS DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 CS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D3 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 SPD D0-D3 D0-D3 D0-D3 CK0 CK0 CK1 CK1 Serial PD SCL WP DQ wiring may differ from that described in this drawing. DQ/DQS/DM/CKE/S relationships are maintained as shown. DQ/DQS/DM/DQS resistors are 22+/- 5% Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ. CK2 A0 A1 A2 SA0 SA1 SA2 SDA CK2 2 loads 2 loads 0 loads 4 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64SH4B0GM / NT128D64SH4BBGM 128MB : 16M x 64 PC3200 / PC2700 / PC2100 Unbuffered DDR SO-DIMM Serial Presence Detect (Part 1 of 2) Byte Description SPD Entry Value Serial PD Data Entry (Hexadecimal) 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type 3 Number of Row Addresses on Assembly SDRAM DDR 07 13 0D 4 Number of Column Addresses on Assembly 9 09 5 Number of DIMM Bank 1 01 6 Data Width of Assembly x64 40 7 Data Width of Assembly (cont') x64 00 8 Voltage Interface Level of this Assembly DDR SDRAM Device Cycle Time 9 DDR266B/333, CL=2.5 DDR400A/B, CL=3 DDR SDRAM Device Access Time from Clock 10 DDR266B/333, CL=2.5 DDR400A/B, CL=3 SSTL 2.5V 04 DDR266B 7.5ns 75 DDR333 6.0ns 60 5.0ns 50 DDR400A DDR400B DDR266B 0.75ns 75 DDR333 0.70ns 70 0.60ns 60 Non-Parity 00 SR/1x(7.8us) 82 DDR400A DDR400B 11 DIMM Configuration Type 12 Refresh Rate/Type 13 Primary DDR SDRAM Width x16 10 14 Error Checking DDR SDRAM Device Width N/A 00 15 DDR SDRAM Device Attr: Min CLK Delay, Random Col Access 16 DDR SDRAM Device Attributes: Burst Length Supported 17 DDR SDRAM Device Attributes: Number of Device Banks 18 19 DDR SDRAM Device Attributes: CAS Latencies Supported DDR SDRAM Device Attributes: WE Latency 21 DDR SDRAM Device Attributes: 22 DDR SDRAM Device Attributes: General Minimum Clock Cycle at CL=2.5 Maximum Data Access Time from Clock at 24 CL=2 (DDR266B/DDR333) CL=2.5 (DDR400A/DDR400B) 25 26 Minimum Clock Cycle Time at CL=1 Maximum Data Access Time from Clock at CL=1 REV 1.0 12/11/2003 0E 4 04 2/2.5 0C DDR333 2/2.5 0C DDR400A 2/2.5/3 1C DDR400B 2.5/3 18 0 01 1 02 Differential Clock 20 DDR266B/333 0.2V Tolerance DDR400A/B 0.1V Tolerance DDR266B 23 01 2,4,8 DDR266B DDR SDRAM Device Attributes: CS Latency 20 1 Clock Note 00 7.5ns 75 DDR333 10ns A0 DDR400A 5.0ns 50 DDR400B 6.0ns 60 DDR266B 0.70ns 70 DDR333 0.75ns 75 DDR400A 0.60ns 60 DDR400B 0.70ns 70 DDR266B N/A 00 DDR333 N/A 00 DDR400A N/A 00 DDR400B 7.5ns 75 DDR266B N/A 00 DDR333 N/A 00 DDR400A N/A 00 DDR400B 7.5ns 75 5 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64SH4B0GM / NT128D64SH4BBGM 128MB : 16M x 64 PC3200 / PC2700 / PC2100 Unbuffered DDR SO-DIMM Serial Presence Detect (Part 2 of 2) 27 28 29 30 31 32 33 34 35 36-40 41 Minimum Row Precharge Time (tRP) Minimum Row Active to Row Active delay (tRRD) Minimum RAS to CAS delay (tRCD) Minimum RAS Pulse Width (tRAS) DDR266B 18ns 48 DDR333 20ns 50 DDR400A 15ns 3C 3C DDR400B 15ns DDR266B 12ns 30 DDR333 15ns 3C DDR400A 10ns 28 DDR400B 10ns 28 DDR266B 18ns 48 DDR333 20ns 50 DDR400A 15ns 3C DDR400B 15ns 3C DDR266B 42ns 2A DDR333 45ns 2D DDR400A 40ns 28 DDR400B 40ns 28 128MB 20 Module Bank Density Address and Command Setup Time Before Clock Address and Command Hold Time After Clock Data Input Setup Time Before Clock Data Input Hold Time After Clock DDR266B 0.75ns 75 DDR333 0.90ns 90 DDR400A 0.60ns 60 DDR400B 0.60ns 60 DDR266B 0.75ns 75 DDR333 0.90ns 90 DDR400A 0.60ns 60 DDR400B 0.60ns 60 DDR266B 0.45ns 45 DDR333 0.50ns 50 DDR400A 0.40ns 40 DDR400B 0.40ns 40 DDR266B 0.45ns 45 DDR333 0.5ns 50 DDR400A 0.40ns 40 DDR400B 0.40ns 40 Reserved Minimum Active/Auto-refresh Time (tRC) Reserved 00 60ns 3C 42 Auto-refresh to Active/Auto-refresh Command Period (tRFC) 72ns 48 43 Max Cycle Time (tCK max) 12ns 30 44 Maximum DQS-DQ Skew Time (tDQSQ) 0.4ns 28 45 Maximum Read Data Hold Skew Factor (tQHS) 0.55ns 55 46-61 62 63 Reserved SPD Revision Checksum Data Reserved 00 Initial 00 DDR266B 3C DDR333 BD DDR400A 87 DDR400B 8D 64-71 Manufacturer's JEDEC ID Code NANYA 7F7F7F0B00000000 72 Module Manufacturing Location N/A 00 73-90 Module Part number N/A 00 91-92 Module Revision Code N/A 00 93-94 Module Manufacturing Data Year/Week Code yy/ww 95-98 Module Serial Number Serial Number 00 Reserved 00 99-255 Reserved 1. yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex) 2. ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex) REV 1.0 12/11/2003 1,2 6 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64SH4B0GM / NT128D64SH4BBGM 128MB : 16M x 64 PC3200 / PC2700 / PC2100 Unbuffered DDR SO-DIMM Absolute Maximum Ratings Symbol VIN, VOUT Parameter Voltage on I/O pins relative to VSS Rating Units -0.5 to VDDQ +0.5 V VIN Voltage on Input relative to VSS -0.5 to +3.6 V VDD Voltage on VDD supply relative to VSS -0.5 to +3.6 V VDDQ Voltage on VDDQ supply relative to VSS -0.5 to +3.6 V 0 to +70 C -55 to +150 C TA TSTG Operating Temperature (Ambient) Storage Temperature (Plastic) PD Power Dissipation 4 W IOUT Short Circuit Output Current 50 mA Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Capacitance Symbol Max. Units Notes Input Capacitance: CK0, CK0, CK1, CK1, CK2, CK2 CI1 12 pF 1 Input Capacitance: A0-A11, BA0, BA1, WE, RAS, CAS, CKE0, S0 CI2 30 pF 1 Input Capacitance: SA0-SA2, SCL CI4 9 pF 1 CIO1 7 pF 1, 2 Parameter Input/Output Capacitance DQ0-63; DQS0-7 CIO3 pF Input/Output Capacitance: SDA 11 1. VDDQ = VDD = 2.5V 0.2V, f = 100 MHz, TA = 25 C, VOUT (DC) = VDDQ /2, VOUT (Peak to Peak) = 0.2V. 2. DQS inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the board level. REV 1.0 12/11/2003 7 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64SH4B0GM / NT128D64SH4BBGM 128MB : 16M x 64 PC3200 / PC2700 / PC2100 Unbuffered DDR SO-DIMM DC Electrical Characteristics and Operating Conditions (TA = 0 C ~ 70 C; VDDQ = VDD = 2.5V 0.2V (DDR266B/DDR333); VDDQ = VDD = 2.6V 0.1V (DDR400A/B) ) Symbol VDD VDDQ VSS, VSSQ Parameter Min Supply Voltage I/O Supply Voltage Max Units Notes 2.7 V 1 2.7 V 1 0 0 V DDR266B/333 2.3 DDR400A/B 2.5 DDR266B/333 2.3 DDR400A/B 2.5 Supply Voltage, I/O Supply Voltage VREF I/O Reference Voltage 0.49 x VDDQ 0.51 x VDDQ V 1, 2 VTT I/O Termination Voltage (System) VREF - 0.04 VREF + 0.04 V 1, 3 VIH (DC) Input High (Logic1) Voltage VREF + 0.15 VDDQ + 0.3 V 1 VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.15 V 1 VIN (DC) Input Voltage Level, CK and CK Inputs -0.3 VDDQ + 0.3 V 1 VID (DC) Input Differential Voltage, CK and CK Inputs 0.30 VDDQ + 0.6 V 1, 4 -5 5 A 1 -5 5 A 1 -16.8 - mA 1 16.8 - mA 1 II IOZ IOH IOL Input Leakage Current Any input 0V VIN VDD; (All other pins not under test = 0V) Output Leakage Current (DQs are disabled; 0V Vout VDDQ Output High Current (VOUT = VDDQ -0.373V, min VREF, min VTT) Output Low Current (VOUT = 0.373, max VREF, max VTT) 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 4. VID is the magnitude of the difference between the input level on CK and the input level on CK. REV 1.0 12/11/2003 8 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64SH4B0GM / NT128D64SH4BBGM 128MB : 16M x 64 PC3200 / PC2700 / PC2100 Unbuffered DDR SO-DIMM AC Characteristics (Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC) unless otherwise specified. 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level. AC Output Load Circuits VTT 50 ohms Output Timing Reference Point VOUT 30 pF AC Operating Conditions (TA = 0 C ~ 70 C; VDDQ = VDD = 2.5V 0.2V (DDR266B/DDR333); VDDQ = VDD = 2.6V 0.1V (DDR400A/B) ) Symbol Parameter/Condition VIH (AC) Input High (Logic 1) Voltage. Min Max VREF + 0.31 VIL (AC) Input Low (Logic 0) Voltage. VID (AC) Input Differential Voltage, CK and CK Inputs VIX (AC) Input Differential Pair Cross Point Voltage, CK and CK Inputs Unit Notes V 1, 2 VREF - 0.31 V 1, 2 0.62 VDDQ + 0.6 V 1, 2, 3 (0.5* VDDQ) - 0.2 (0.5* VDDQ) + 0.2 V 1, 2, 4 1. Input slew rate = 1V/ ns. 2. Inputs are not recognized as valid until VREF stabilizes. 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. REV 1.0 12/11/2003 9 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64SH4B0GM / NT128D64SH4BBGM 128MB : 16M x 64 PC3200 / PC2700 / PC2100 Unbuffered DDR SO-DIMM Operating, Standby, and Refresh Currents (TA = 0 C ~ 70 C; VDDQ = VDD = 2.5V 0.2V (DDR266B/DDR333); VDDQ = VDD = 2.6V 0.1V (DDR400A/B) ) Symbol Parameter/Condition PC3200 PC2700 PC2100 (-5) (-6K) (-75B) Unit Notes 520 440 380 mA 1,2,4 650 620 540 mA 1,2,4 64 56 56 mA 1,2,4 170 150 130 mA 1,2,4 80 75 70 mA 1,2,4 310 270 240 mA 1,2,4 1400 1280 1140 mA 1,2,4 800 720 600 mA 1,2,4 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); IDD0 DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); IDD1 CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle IDD2P IDD2N IDD3P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH IDD3N (MIN) ; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; Burst = 2; reads; continuous burst; address IDD4R and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA Operating Current: one bank; Burst = 2; writes; continuous burst; address IDD4W and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 1,2,3, IDD5 Auto-Refresh Current: tRC = tRFC (MIN) 880 860 720 mA IDD6 Self-Refresh Current: CKE 0.2V 12 12 12 mA 1,2,4 1920 1640 1420 mA 1,2,4 4 Operating Current: four bank; four bank interleaving with BL = 4, address and IDD7 control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1. IDD specifications are tested after the device is properly initialized. 2. Input slew rate = 1V/ ns. 3. Current at 7.8 s is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 s. 4. Preliminary data for PC3200 (-5/-5T) REV 1.0 12/11/2003 10 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64SH4B0GM / NT128D64SH4BBGM 128MB : 16M x 64 PC3200 / PC2700 / PC2100 Unbuffered DDR SO-DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module (TA = 0 C ~ 70 C; VDDQ = VDD = 2.5V 0.2V (DDR266B/DDR333); VDDQ = VDD = 2.6V 0.1V (DDR400A/B) (Part 1 of 2) Symbol tAC tDQSCK -5/-5T Parameter DQ output access time from CK/CK -6K -75B Min. Max. Min. Max. Min. Max. -0.6 +0.6 -0.7 +0.7 -0.75 +0.75 Unit Notes ns 1-4 DQS output access time from CK/CK -0.5 +0.5 -0.7 +0.7 -0.75 +0.75 ns 1-4 tCH CK high-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK 1-4 tCL CK low-level width 0.45 0.55 0.45 0.55 0.45 0.55 tCK 1-4 5 8 ns 1-4 CL=3 tCK Clock cycle time CL=2.5 5/6 12 6 12 7.5 ns 1-4 CL=2 7.5/- 12/- 7.5 12 10 ns 1-4 1-4, tDH DQ and DM input hold time 0.4 0.45 0.5 ns tDS DQ and DM input setup time 0.4 0.45 0.5 ns tDIPW DQ and DM input pulse width (each input) 1.75 1.75 1.75 ns 1-4 tHZ Data-out high-impedance time from CK/CK -0.6 +0.6 -0.7 +0.7 -0.75 +0.75 ns 1-4, 5 tLZ Data-out low-impedance time from CK/CK -0.6 +0.6 -0.7 +0.7 -0.75 +0.75 ns 1-4, 5 0.5 ns 1-4 tCK 1-4 tCK 1-4 0.75 ns 1-4 1.25 tCK 1-4 tDQSQ tHP DQS-DQ skew (DQS & associated DQ signals) Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time tQH Data output hold time from DQS tQHS Data hold Skew Factor tDQSS Write command to 1st DQS latching transition tDQSL, DQS input low (high) pulse width tDQSH (write cycle) tDSS tDSH tMRD tWPRES 0.4 0.45 tCH or tCH or tCH or tCL tCL tCL tHP - tHP - tHP - tQHS tQHS tQHS 0.5 0.72 1.28 0.55 0.75 1.25 0.75 15, 16 1-4, 15, 16 0.35 0.35 0.35 tCK 1-4 0.2 0.2 0.2 tCK 1-4 0.2 0.2 0.2 tCK 1-4 Mode register set command cycle time 2 2 2 tCK 1-4 Write preamble setup time 0 0 0 ns 1-4, 7 DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) tWPST Write postamble 0.40 tCK 1-4, 6 tWPRE Write preamble 0.25 0.25 0.25 tCK 1-4 0.6 0.75 0.9 ns 0.6 0.75 0.9 ns 0.7 0.8 1.0 ns tIH tIS tIH REV 1.0 12/11/2003 Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) 0.60 0.40 0.60 0.40 0.60 2-4, 9, 11, 12 2-4, 9, 11, 12 2-4, Address and control input hold time (slow slew rate) 10, 11, 12, 14 11 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64SH4B0GM / NT128D64SH4BBGM 128MB : 16M x 64 PC3200 / PC2700 / PC2100 Unbuffered DDR SO-DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module (TA = 0 C ~ 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) (Part 2 of 2) Symbol tIS -5 Parameter Min. -6K Max. Min. -75B Max. Min. Unit Notes ns 10-12, ns 2-4, 12 Max. 2-4, Address and control input setup time 0.7 (slow slew rate) 0.8 1.0 14 tIPW Input pulse width 2.2 2.2 2.2 tRP RE Read preamble 0.9 1.1 0.9 1.1 0.9 1.1 tCK 1-4 tRP ST Read postamble 0.40 0.60 0.40 0.60 0.40 0.60 tCK 1-4 tRAS Active to Precharge command 42ns 120us 42ns 120us 45ns 120us tRC Active to Active/Auto-refresh command period 55 60 65 ns 1-4 tRFC Auto-refresh to Active/Auto-refresh command period 70 72 75 ns 1-4 tRCD Active to Read or Write delay 15 18 20 ns 1-4 tRAP Active to Read Command with Auto-precharge 15 18 20 ns 1-4 1-4 tRP Precharge command period 15 18 20 ns 1-4 tRRD Active bank A to Active bank B command 10 12 15 ns 1-4 tWR Write recovery time 15 (tWR/ tCK ) + (tRP / tCK ) 1-4 Auto-precharge write recovery + precharge time 15 (tWR/ tCK ) + (tRP / tCK ) ns tDAL 15 (tWR/ tCK ) + (tRP / tCK ) tCK 1-4, 13 tWTR Internal write to read command delay 2 1 1 tCK 1-4 tPDEX Power down exit time 5 6 7.5 ns 1-4 tXSNR Exit self-refresh to non-read command 75 75 75 ns 1-4 tXSRD Exit self-refresh to read command 200 200 200 tCK 1-4 tREFI Average Periodic Refresh Interval s 1-4, 8 REV 1.0 12/11/2003 7.8 7.8 7.8 12 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64SH4B0GM / NT128D64SH4BBGM 128MB : 16M x 64 PC3200 / PC2700 / PC2100 Unbuffered DDR SO-DIMM AC Timing Specification Notes 1. Input slew rate = 1V/ns. 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK is VREF. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to low at this time, depending on tDQSS. 8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device. 9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 11. CK/CK slew rates are >= 1.0 V/ns. 12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. 13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. For example, for PC2100 at CL= 2.5, tDAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5. 14. An input setup and hold time derating table is used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/ns. Input Slew Rate 1. 2. Delta (tIS) Delta (tIH) Unit Note 0.5 V/ns 0 0 ps 1, 2 0.4 V/ns +50 0 ps 1, 2 0.3 V/ns +100 0 ps 1, 2 Input slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising transitions. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 15. An input setup and hold time derating table is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. 1. 2. Input Slew Rate Delta (tDS) Delta (tDH) Unit 0.5 V/ns 0 0 ps 1, 2 0.4 V/ns +75 +75 ps 1, 2 0.3 V/ns +150 +150 ps 1, 2 Note I/O slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising transitions. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 16. An I/O Delta Rise, Fall Derating table is used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ. 1. 2. 3. 4. Delta Rise and Fall Rate Delta (tDS) Delta (tDH) Unit Note 0.0 ns/V 0 0 ps 1-4 0.25 ns/V +50 +50 ps 1-4 0.5 ns/V +100 +100 ps 1-4 Input slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising transitions. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V Using the table above, this would result in an increase in tDS and tDH of 100 ps. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. REV 1.0 12/11/2003 13 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64SH4B0GM / NT128D64SH4BBGM 128MB : 16M x 64 PC3200 / PC2700 / PC2100 Unbuffered DDR SO-DIMM Package Dimensions FRONT 67.60 (2X) 1.80 1 2.15 39 41 11.40 31.75 20.00 6.00 4.00 63.60 199 Detail A Detail B 4.20 47.40 2.45 1.80 BACK SIDE 3.00 MAX 2 40 42 200 1.00+/- 0.10 Detail A 0.45 0.60 1.00+/- 0.1 2.55 4.00+/-0.10 0.25 MAX Detail B Note: All dimensions are typical with tolerances of +/- 0.15 unless otherwise stated. Units: Millimeters (Inches) REV 1.0 12/11/2003 14 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT128D64SH4B0GM / NT128D64SH4BBGM 128MB : 16M x 64 PC3200 / PC2700 / PC2100 Unbuffered DDR SO-DIMM Revision Log Rev Date 0.1 Dec, 2003 1.0 Dec 11, 2003 Modification Preliminary Release Specification to cover 128MB DDR1 SODIMM speeds of 5/5T/6K/75B Official Release Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 Please visit our home page for more information and your nearest sales office: www.nanya.com Printed in Taiwan (c)2003 REV 1.0 12/11/2003 15 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.