P/N: TS4FCFSAR00ISI
TS8FCFSAR00ISI
TS16FCFSAR00ISI
Industrial CompactFlash
Description
Transcend’s industrial CF is a high speed
industrial Compact Flash Card with high quality
flash memory assembled on a printed circuit board.
Dimensions
RoHS compliant
Single Power Supply: 3.3V±5% or 5V±10%
Operating Temperature: -40oC to 85oC
Storage Temperature: -55oC to 100oC
Humidity (Non condensation): 0% to 95%
Built-in BCH ECC (Error Correction Code) functionality
and global wear-leveling algorithm to ensure data transfer
Operation Modes:
PC Card Memory Mode
PC Card IO Mode
True IDE Mode
True IDE Mode supports:
Ultra DMA Mode 0 to 5 (Ultra DMA mode 5 must
supply with 3.3V)
Multi-Word DMA Mode 0 to 4
PIO Mode 0 to 6
True IDE Mode: Fixed Disk (Default)
PC Card Mode: Fixed Disk (Default)
Durability of Connector: 10,000 times
MTBF: 3,000,000 hours (in 25 oC)
Support Global Wear-Leveling, Static Data Refresh,
Early Retirement, and Erase Count Monitor functions to
extend product life
Support S.M.A.R.T (Self-defined)
Support Security Command
Compliant with CompactFlash, PCMCIA, and ATA
standards
Intelligent Power Shield to prevent data loss in the event
of a sudden power outage (optional for 8G- 64G)
Ordering Information
Capacity
Interface
Transfer Mode
Disk Type
4GB~16GB
(optional 32G- 64G)
True IDE mode
Ultra DMA mode 0~5
Multi-Word DMA Mode 0~4
PIO Mode 0 ~ 6
Fixed Disk (Default)
PC Card mode (PCMCIA)
80ns, 100ns, 120ns, 250ns
Fixed Disk (Default)
C.H.S Table
Capacity
C
H
S
4GB
7899
16
63
8GB
15798
16
63
16GB
16383
15
63
*Note: FAT format for <4GB, FAT32 format for ≥4GB
Endurance
CAPACITY
Tera Byte Write
4GB
88 TBW
8GB
176 TBW
16GB
354 TBW
Performance
CAPACITY
Read (MB/s)
Write (MB/s)
Random Read (MB/s)
Random Write (MB/s)
4GB
78.62
40.60
14.20
1.751
8GB
84.60
64.91
14.3
1.762
16GB
83.04
64.49
11.27
2.053
Note : 25 oC, according to CF reader test on Q77H2, 4GB RAM * 1, Windows® 7 SP1, benchmark utility
CrystalDisk (version 3.0.1)
Note* : 25 oC, according to CF to IDE connector test on P5G41T, 1GB RAM * 2, IDE interface support
UDMA5, Windows® XP Version 2002 SP3, benchmark utility CrystalDisk (version 3.0)
Power Requirements (DC 5V, 3.3V @25℃)
Capacity & Input Voltage
Current Magnitude (mA)
Read
Write
4GB
3.3V 5%
185.5
131.1
8GB
3.3V 5%
189.5
155.5
16GB
3.3V 5%
199.1
177.3
1.
Read/Write operation is derived from benchmark utility Crystal DiskMark (version 3.0.1), copied file 1000MB.
2.
StandBy Current : 5V : 1.2mA 3.3V : 1.1mA
3.
All data above are maximum value of each measurement.
Regulations
Compliance
CE, FCC and BSMI
SHOCK & Vibration Test
Condition
Standard
Mechanical Shock Test
1500G, 0.5ms, 3 axes
IEC 60068-2-27
Vibration Test
20G (Peak-to-Peak)
20Hz to 2000Hz (Frequency)
IEC 60068-2-6
More Functions to extend product life
1.
Global Wear Leveling – Advanced algorithm to enhance the Wear-Leveling Efficiency
Global wear leveling ensures every block has an even erase count. By ensuring all spare blocks in the
SSD’s flash chips are managed in a single pool, each block can then have an even erase count. This helps
to extend the lifespan of a SSD and to provide the best possible endurance.
There are 3 main processes in global wear leveling:
(1)
Record the block erase count and save it in the wear-leveling table.
(2)
Find the static-block and save it in wear-leveling pointer.
(3)
Check the erase count when a block is pulled from the pool of spare blocks. If the erased block
count is larger than the Wear Count (WEARCNT), then the static blocks are leveraged against the
over-count blocks.
2.
StaticDataRefresh Technology – Keeping Data Healthy
Many variants may disturb the charge inside a Flash cell. These variants can be: time, read operations,
undesired charge, heat, etc. Each variant would create a charge loss, which slightly influences the charge
levels. In our everyday usage, more than 60% are repeated read operations, and the accumulated charge
loss would eventually result in the data loss. Normally, the ECC engine corrections take place without
affecting normal host operations. Over time, the number of bit errors accumulated in the read transaction
exceeds the correcting capacity of the ECC engine, which results in corrupted data being sent to the host.
To prevent this, the controller monitors the bit error levels during each read operation; when the number of
bit errors reaches the preset threshold value, the controller automatically performs a data refresh to
“restore” the correct charge levels in the cell. Implementation of StaticDataRefresh Technology reinstates
the data to its original, error-free state, and hence, lengths the data’s lifespan.
3.
EarlyRetirement – Avoiding Data Loss Due to Weak Block
The StaticDataRefresh feature functions well when the cells in a block are still healthy. As the block
ages over time, it cannot store charge reliably anymore, EarlyRetirement enters the scene.
EarlyRetirement works by moving the static data to another block (a health block) before the previously
used block becomes completely incapable of holding charges for data. When the charge loss error level
exceeds another threshold value (higher from that for StaticDataRefresh), the controller automatically
moves its data to another block. In addition, the original block is then marked as a bad block, which
prevents its further use, and thus the block enters the state of “EarlyRetirement.” Note that, through this
process, the incorrect data are detected and effectively corrected by the ECC engine, thus the data in the
new block is stored error-free.
4.
Intelligent Power Shield – Avoiding Data Loss during Power Failure
When a power failure takes place, the line voltage drops. When it reaches the first Logic-Freeze
Threshold, the core controller is held at a steady state. Here are some implications: Firstly, it ceases the
communication with the host. This prevents the host from sending in further address/instructions/data that
may be corrupted. During power disturbance, the host is likely experiencing a voltage drop, so the
transmission integrity cannot be guaranteed. Secondly, it stops sending the information to the Flash, which
prevents the controller from corrupting the address/data being transmitted to the Flash, and corrupting the
Flash contents inadvertently. Furthermore, Intelligent Power Shield cuts off the connection of host power
and turns off the controller to reserve most of the energy for NAND Flash to complete programming.
Transcend
Block Diagram
Suggest Power Sequence
Below figure illustrates the recommend Transcend CF power sequence.
1.
Input power ramp down time is below 2ms with monotonous falling edge.
2.
Power on interval is more than 2s.
3.
Input power ramp up time is below 2ms with monotonous rising edge.
*The actual value may vary depend on device capacity and system environment.
Pin Assignments and Pin Type
Note: 1) These signals are required only for 16 bit accesses and not required when installed in 8 bit
systems. Devices should allow for 3-state signals not to consume current.
2)
The signal should be grounded by the host.
3)
The signal should be tied to VCC by the host.
4)
The mode is required for CompactFlash Storage Cards.
5)
The -CSEL signal is ignored by the card in PC Card modes. However, because it is not
pulled upon the card in these modes, it should not be left floating by the host in PC Card
modes. In these modes, the pin should be connected by the host to PC Card A25 or
grounded by the host.
6)
If DMA operations are not used, the signal should be held high or tied to VCC by the host. For
proper operation in older hosts: while DMA operations are not active, the card shall ignore
this signal,including a floating condition
7)
Signal usage in True IDE Mode except when Ultra DMA mode protocol is active.
8)
Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Write is active.
9)
Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Read is active.
10)
Signal usage in PC Card I/O and Memory Mode when Ultra DMA mode protocol DMA Write is active.
11)
Signal usage in PC Card I/O and Memory Mode when Ultra DMA mode protocol DMA Read is active.
12) Signal usage in PC Card I/O and Memory Mode when Ultra DMA protocol is active.
Signal Description
Signal Name
Dir.
Pin
Description
A10 – A00
I
8,10,11,12,
These address lines along with the -REG signal are used to select the following:
(PC Card Memory Mode)
14,15,16,17,
The I/O port address registers within the CompactFlash Storage Card , the
18,19,20
memory mapped port address registers within the CompactFlash Storage Card,
a byte in the card's information structure and its configuration control and status
registers.
A10 – A00
This signal is the same as the PC Card Memory Mode signal.
(PC Card I/O Mode)
A02 - A00
I
18,19,20
In True IDE Mode, only A[02:00] are used to select the one of eight registers
(True IDE Mode)
in the Task File, the remaining address lines should be grounded by the host.
BVD1
(PC Card Memory Mode)
-STSCHG
(PC Card I/O Mode)
Status Changed
-PDIAG
(True IDE Mode)
I/O
46
This signal is asserted high, as BVD1 is not supported.
This signal is asserted low to alert the host to changes in the READY and Write
Protect states, while the I/O interface is configured. Its use is controlled by the
Card Config and Status Register.
In the True IDE Mode, this input / output is the Pass Diagnostic signal in the
Master / Slave handshake protocol.
BVD2
(PC Card Memory Mode)
-SPKR
(PC Card I/O Mode)
-DASP
(True IDE Mode)
I/O
45
This signal is asserted high, as BVD2 is not supported.
This line is the Binary Audio output from the card. If the Card does not support the
Binary Audio function, this line should be held negated.
In the True IDE Mode, this input/output is the Disk Active/Slave Present signal in
the Master/Slave handshake protocol.
-CD1, -CD2
(PC Card Memory Mode)
-CD1, -CD2
(PC Card I/O Mode)
-CD1, -CD2
(True IDE Mode)
O
26,25
These Card Detect pins are connected to ground on the CompactFlash Storage
Card. They are used by the host to determine that the CompactFlash Storage
Card is fully inserted into its socket.
This signal is the same for all modes.
This signal is the same for all modes.
Signal Name
Dir.
Pin
Description
-CE1, -CE2
(PC Card Memory Mode)
Card Enable
-CE1, -CE2
(PC Card I/O Mode)
Card Enable
-CS0, -CS1
(True IDE Mode)
I
7,32
These input signals are used both to select the card and to indicate to the card
whether a byte or a word operation is being performed. -CE2 always accesses
the odd byte of the word.-CE1 accesses the even byte or the Odd byte of the
word depending on A0 and -CE2. A multiplexing scheme based on A0,-CE1,
-CE2 allows 8 bit hosts to access all data on D0-D7. See Table 27, Table 29,
Table 31, Table 35, Table 36 and Table 37.
This signal is the same as the PC Card Memory Mode signal.
In the True IDE Mode, -CS0 is the address range select for the task file
registers while -CS1 is used to select the Alternate Status Register and the
Device Control Register.
While –DMACK is asserted, -CS0 and –CS1 shall be held negated and the
width of the transfers shall be 16 bits.
-CSEL
(PC Card Memory Mode)
-CSEL
(PC Card I/O Mode)
-CSEL
(True IDE Mode)
I
39
This signal is not used for this mode, but should be connected by the host to PC
Card A25 or grounded by the host.
This signal is not used for this mode, but should be connected by the host to PC
Card A25 or grounded by the host.
This internally pulled up signal is used to configure this device as a Master or a
Slave when configured in the True IDE Mode.
When this pin is grounded, this device is configured as a Master.
When the pin is open, this device is configured as a Slave.
D15 - D00
I/O
31,30,29,28,
These lines carry the Data, Commands and Status information between the host
(PC Card Memory Mode)
27,49,48,47,
6,5,4,3,2,
23, 22, 21
and the controller. D00 is the LSB of the Even Byte of the Word. D08 is the LSB of
the Odd Byte of the Word.
D15 - D00
This signal is the same as the PC Card Memory Mode signal.
(PC Card I/O Mode)
D15 - D00
(True IDE Mode)
In True IDE Mode, all Task File operations occur in byte mode on the low order
bus D[7:0] while all data transfers are 16 bit using D[15:0].
GND
(PC Card Memory Mode)
GND
(PC Card I/O Mode)
GND
(True IDE Mode)
--
1,50
Ground.
This signal is the same for all modes.
This signal is the same for all modes.
Signal Name
Dir.
Pin
Description
-INPACK
(PC Card Memory Mode)
-INPACK
(PC Card I/O Mode)
Input Acknowledge
DMARQ
(True IDE Mode)
O
43
This signal is not used in this mode.
The Input Acknowledge signal is asserted by the CompactFlash Storage Card
when the card is selected and responding to an I/O read cycle at the address that
is on the address bus. This signal is used by the host to control the enable of any
input data buffers between the CompactFlash Storage Card and the CPU.
This signal is a DMA Request that is used for DMA data transfers between host
and device. It shall be asserted by the device when it is ready to transfer data to
or from the host. For Multiword DMA transfers, the direction of data transfer is
controlled by -IORD and -IOWR. This signal is used in a handshake manner with
-DMACK, i.e., the device shall wait until the host asserts -DMACK before
negating DMARQ, and reasserting DMARQ if there is more data to transfer.
DMARQ shall not be driven when the device is not selected.
While a DMA operation is in progress, -CS0 and –CS1 shall be held negated and
the width of the transfers shall be 16 bits.
If there is no hardware support for DMA mode in the host, this output signal is not
used and should not be connected at the host. In this case, the BIOS must report
that DMA mode is not supported by the host so that device drivers will not attempt
DMA mode.
A host that does not support DMA mode and implements both PCMCIA and
True-IDE modes of operation need not alter the PCMCIA mode connections
while in True-IDE mode as long as this does not prevent proper operation in any
mode.
-IORD
(PC Card Memory Mode)
-IORD
(PC Card I/O Mode)
-IORD
(True IDE Mode – Except
Ultra DMA Protocol Active)
-HDMARDY
(True IDE Mode – In Ultra
DMA Protocol DMA Read)
HSTROBE
(True IDE Mode – In Ultra
DMA Protocol DMA Write)
I
34
This signal is not used in this mode.
This is an I/O Read strobe generated by the host. This signal gates I/O data onto
the bus from the CompactFlash Storage Card when the card is configured to use
the I/O interface.
In True IDE Mode, while Ultra DMA mode is not active, this signal has the same
function as in PC Card I/O Mode.
In True IDE Mode when Ultra DMA mode DMA Read is active, this signal is
asserted by the host to indicate that the host is read to receive Ultra DMA data-in
bursts. The host may negate -HDMARDY to pause an Ultra DMA transfer.
In True IDE Mode when Ultra DMA mode DMA Write is active, this signal is the
data out strobe generated by the host. Both the rising and falling edge of
HSTROBE cause data to be latched by the device. The host may stop generating
HSTROBE edges to pause an Ultra DMA data-out burst.
Signal Name
Dir.
Pin
Description
-IOWR
(PC Card Memory Mode)
-IOWR
(PC Card I/O Mode)
-IOWR
(True IDE Mode – Except
Ultra DMA Protocol Active)
STOP
(True IDE Mode – Ultra DMA
Protocol Active)
I
35
This signal is not used in this mode.
The I/O Write strobe pulse is used to clock I/O data on the Card Data bus into the
CompactFlash Storage Card controller registers when the CompactFlash
Storage Card is configured to use the I/O interface.
The clocking shall occur on the negative to positive edge of the signal (trailing
edge).
In True IDE Mode, while Ultra DMA mode protocol is not active, this signal has
the same function as in PC Card I/O Mode. When Ultra DMA mode protocol is
supported, this signal must be negated before entering Ultra DMA mode protocol.
In True IDE Mode, while Ultra DMA mode protocol is active, the assertion of this
signal causes the termination of the Ultra DMA burst.
-OE
(PC Card Memory Mode)
-OE
(PC Card I/O Mode)
-ATA SEL
(True IDE Mode)
I
9
This is an Output Enable strobe generated by the host interface. It is used to read
data from the CompactFlash Storage Card in Memory Mode and to read the CIS
and configuration registers.
In PC Card I/O Mode, this signal is used to read the CIS and configuration
registers.
To enable True IDE Mode this input should be grounded by the host.
READY
(PC Card Memory Mode)
-IREQ
(PC Card I/O Mode)
INTRQ
(True IDE Mode)
O
37
In Memory Mode, this signal is set high when the CompactFlash Storage Card is
ready to accept a new data transfer operation and is held low when the card is
busy.
At power up and at Reset, the READY signal is held low (busy) until the
CompactFlash Storage Card has completed its power up or reset function. No
access of any type should be made to the CompactFlash Storage Card during
this time.
Note, however, that when a card is powered up and used with RESET
continuously disconnected or asserted, the Reset function of the RESET pin is
disabled. Consequently, the continuous assertion of RESET from the application
of power shall not cause the READY signal to remain continuously in the busy
state.
I/O Operation – After the CompactFlash Storage Card Card has been configured
for I/O operation, this signal is used as -Interrupt Request. This line is strobed low
to generate a pulse mode interrupt or held low for a level mode interrupt.
In True IDE Mode signal is the active high Interrupt Request to the host.
Signal Name
Dir.
Pin
Description
-REG
(PC Card Memory Mode)
Attribute Memory Select
-REG
(PC Card I/O Mode)
I
44
This signal is used during Memory Cycles to distinguish between Common
Memory and Register (Attribute) Memory accesses. High for Common Memory,
Low for Attribute Memory.
The signal shall also be active (low) during I/O Cycles when the I/O address is on
the Bus.
-DMACK
(True IDE Mode)
This is a DMA Acknowledge signal that is asserted by the host in response to
DMARQ to initiate DMA transfers.
While DMA operations are not active, the card shall ignore the -DMACK signal,
including a floating condition.
If DMA operation is not supported by a True IDE Mode only host, this signal
should be driven high or connected to VCC by the host.
A host that does not support DMA mode and implements both PCMCIA and
True-IDE modes of operation need not alter the PCMCIA mode connections
while in True-IDE mode as long as this does not prevent proper operation all
modes.
RESET
(PC Card Memory Mode)
RESET
(PC Card I/O Mode)
-RESET
(True IDE Mode)
I
41
The CompactFlash Storage Card is Reset when the RESET pin is high with the
following important exception:
The host may leave the RESET pin open or keep it continually high from the
application of power without causing a continuous Reset of the card. Under either
of these conditions, the card shall emerge from power-up having completed an
initial Reset.
The CompactFlash Storage Card is also Reset when the Soft Reset bit in the
Card Configuration Option Register is set.
This signal is the same as the PC Card Memory Mode signal.
In the True IDE Mode, this input pin is the active low hardware reset from the
host.
VCC
(PC Card Memory Mode)
VCC
(PC Card I/O Mode)
VCC
(True IDE Mode)
--
13,38
+5 V, +3.3 V power.
This signal is the same for all modes.
This signal is the same for all modes.
Signal Name
Dir.
Pin
Description
-VS1
-VS2
(PC Card Memory Mode)
-VS1
-VS2
(PC Card I/O Mode)
-VS1
-VS2
(True IDE Mode)
O
33
40
Voltage Sense Signals. -VS1 is grounded on the Card and sensed by the Host so
that the CompactFlash Storage Card CIS can be read at 3.3 volts and -VS2 is
reserved by PCMCIA for a secondary voltage and is not connected on the Card.
This signal is the same for all modes.
This signal is the same for all modes.
-WAIT
(PC Card Memory Mode)
-WAIT
(PC Card I/O Mode)
IORDY
(True IDE Mode – Except
Ultra DMA Mode)
-DDMARDY
(True IDE Mode – Ultra DMA
Write Mode)
DSTROBE
(True IDE Mode – Ultra
DMA Read Mode)
O
42
The -WAIT signal is driven low by the CompactFlash Storage Card to signal the
host to delay completion of a memory or I/O cycle that is in progress.
This signal is the same as the PC Card Memory Mode signal.
In True IDE Mode, except in Ultra DMA modes, this output signal may be used as
IORDY.
In True IDE Mode, when Ultra DMA mode DMA Write is active, this signal is
asserted by the host to indicate that the device is read to receive Ultra DMA
data-in bursts. The device may negate -DDMARDY to pause an Ultra DMA
transfer.
In True IDE Mode, when Ultra DMA mode DMA Write is active, this signal is the
data out strobe generated by the device. Both the rising and falling edge of
DSTROBE cause data to be latched by the host. The device may stop generating
DSTROBE edges to pause an Ultra DMA data-out burst.
-WE
(PC Card Memory Mode)
-WE
(PC Card I/O Mode)
-WE
(True IDE Mode)
I
36
This is a signal driven by the host and used for strobing memory write data to the
registers of the CompactFlash Storage Card when the card is configured in the
memory interface mode. It is also used for writing the configuration registers.
In PC Card I/O Mode, this signal is used for writing the configuration registers.
In True IDE Mode, this input signal is not used and should be connected to VCC
by the host.
WP
(PC Card Memory Mode)
Write Protect
-IOIS16
(PC Card I/O Mode)
-IOCS16
(True IDE Mode)
O
24
Memory Mode – The CompactFlash Storage Card does not have a write protect
switch. This signal is held low after the completion of the reset initialization
sequence.
I/O Operation – When the CompactFlash Storage Card is configured for I/O
Operation Pin 24 is used for the -I/O Selected is 16 Bit Port (-IOIS16) function. A
Low signal indicates that a 16 bit or odd byte only operation can be performed at
the addressed port.
In True IDE Mode this output signal is asserted low when this device is expecting
a word data transfer cycle.
Electrical Specification
The following tables indicate all D.C. Characteristics for the CompactFlash Storage Card. Unless otherwise stated,
conditions are:
Vcc = 5V ±10%
Vcc = 3.3V ± 5%
Input Power
Input Leakage Current
Input Characteristics
CompactFlash interface I/O at 5.0V
Parameter
Symbol
Min.
Max.
Unit
Remark
Supply Voltage
VCC
4.5
5.5
V
High level output voltage
VOH
VCC-0.8
V
Low level output voltage
VOL
0.8
V
High level input voltage
VIH
4.0
V
Non-schmitt trigger
2.92
V
Schmitt trigger1
Low level input voltage
VIL
0.8
V
Non-schmitt trigger
1.70
V
Schmitt trigger1
Pull up resistance2
RPU
50.
73
kOhm
Pull down resistance
RPD
50
97
kOhm
CompactFlash interface I/O at 3.3V
Parameter
Symbol
Min.
Max.
Unit
Remark
Supply Voltage
VCC
2.97
3.63
V
High level output voltage
VOH
VCC-0.8
V
Low level output voltage
VOL
0.8
V
High level input voltage
VIH
2.4
V
Non-schmitt trigger
2.05
V
Schmitt trigger1
Low level input voltage
VIL
0.6
V
Non-schmitt trigger
1.25
V
Schmitt trigger1
Pull up resistance2
RPU
52.7
141
kOhm
Pull down resistance
RPD
47.5
172
kOhm
The I/O pins other than CompactFlash interface
Parameter
Symbol
Min.
Max.
Unit
Remark
Supply Voltage
VCC
2.7
3.6
V
High level output voltage
VOH
2.4
V
Low level output voltage
VOL
0.4
V
High level input voltage
VIH
2.0
V
Non-schmitt trigger
1.4
2.0
V
Schmitt trigger
Low level input voltage
VIL
0.8
V
Non-schmitt trigger
0.8
1.2
V
Schmitt trigger
Pull up resistance
RPU
40
kOhm
Pull down resistance
RPD
40
kOhm
1. Include CE1, CE2, HREG, HOE. HIOE, HWE, HIOW pins.
2. Include CE1, CE2, HREG, HOE. HIOE, HWE, HIOW, CSEL, PDIAG, DASP pins.
Output Drive Type
Output Drive Characteristics
Signal Interface
Notes: 1) Control Signals: each card shall present a load to the socket no larger than 50 pF 10 at a DC current of 700 μA
low state and 150 μA high state, including pull-resistor. The socket shall be able to drive at least the following
load 10 while meeting all AC timing requirements: (the number of sockets wired in parallel) multiplied by (50 pF
with DC current 700 μA low state and 150 μA high state per socket).
2) Resistor is optional.
3) Status Signals: the socket shall present a load to the card no larger than 50 pF 10 at a DC current of 400 μA low
state and 100 μA high state, including pull-up resistor. The card shall be able to drive at least the following load
10 while meeting all AC timing requirements: 50 pF at a DC current of 400 μA low state and 100 μA high state.
4) Status Signals: the socket shall present a load to the card no larger than 50 pF 10 at a DC current of 400 μA low
state and 100 μA high state, including pull-up resistor. The card shall be able to drive at least the following load
10 while meeting all AC timing requirements: 50 pF at a DC current of 400 μA low state and 100 μA high state.
5) Status Signals: the socket shall present a load to the card no larger than 50 pF 10 at a DC current of 400 μA low
state and 100 μA high state, including pull-up resistor. The card shall be able to drive at least the following load
10 while meeting all AC timing requirements: 50 pF at a DC current of 400 μA low state and 1100 μA high state.
6) BVD2 was not defined in the JEIDA 3.0 release. Systems fully supporting JEIDA release 3 SRAM cards shall
pull-up pin 45 (BVD2) to avoid sensing their batteries as “Low.”
7) Address Signals: each card shall present a load of no more than 100pF 10 at a DC current of 450μA low state and
150μA high state. The host shall be able to drive at least the following load 10 while meeting all AC timing
requirements: (the number of sockets wired in parallel) multiplied by (100pF with DC current 450μA low state
and 150μA high state per socket).
8) Data Signals: the host and each card shall present a load no larger than 50pF 10 at a DC current of 450μA and
150μA high state. The host and each card shall be able to drive at least the following load 10 while meeting all
AC timing requirements: 100pF with DC current 1.6mA low state and 300μA high state. This permits the host to
wire two sockets in parallel without derating the card access speeds.
9) Reset Signal: This signal is pulled up to prevent the input from floating when a CFA to PCMCIA adapter is used in
a PCMCIA revision 1 host. However, to minimize DC current drain through the pull-up resistor in normal
operation the pull-up should be turned off once the Reset signal has been actively driven low by the host.
Consequently, the input is specified as an I2Z because the resistor is not necessarily detectable in the input
current leakage test.
10) Host and card restrictions for CF Advanced Timing Modes and Ultra DMA modes: Additional Requirements for
CF Advanced Timing Modes and Ultra DMA Electrical Requirements for additional required limitations on the
implementation of CF Advanced Timing modes and Ultra DMA modes respectively.
Additional Requirements for CF Advanced Timing Modes
The CF Advanced Timing modes include PCMCIA I/O and Memory modes that are 100ns or faster and True
IDE PIO Modes 5,6 and Multiword DMA Modes 3,4.
When operating in CF Advanced timing modes, the host shall conform to the following requirements:
1) Only one CF device shall be attached to the CF Bus.
2) The host shall not present a load of more than 40pF to the device for all signals, including any cabling.
3) The maximum cable length is 0.15 m (6 in). The cable length is measured from the card connector to the host
controller. 0.46 m (18 in) cables are not supported.
4) The -WAIT and IORDY signals shall be ignored by the host.
Devices supporting CF Advanced timing modes shall also support slower timing modes, to ensure operability with
systems that do not support CF Advanced timing modes
Ultra DMA Electrical Requirements
Host and Card signal capacitance limits for Ultra DMA operation
The host interface signal capacitance at the host connector shall be a maximum of 25 pF for each signal as measured at
1 MHz. The card interface signal capacitance at the card connector shall be a maximum of 20 pF for each signal as
measured at 1 MHz.
Series termination required for Ultra DMA operation
Series termination resistors are required at both the host and the card for operation in any of the Ultra DMA modes. Table
13 describes typical values for series termination at the host.
Signal
Host Termination
-IORD ( -HDMARDY, HSTROBE)
22 ohm
-IOWR (STOP)
22 ohm
-CS0, -CS1
33 ohm
A00, A01, A02
33 ohm
-DMACK
22 ohm
D15 through D00
33 ohm
DMARQ
82 ohm
INTRQ
82 ohm
IORDY (-DDMARDY, DSTROBE)
82 ohm
-RESET
33 ohm
NOTE − Only those signals requiring termination are listed in this table. If a signal is
not listed, series termination is not required for operation in an Ultra DMA mode.
Below table show signals also requiring a pull-up or pull-down resistor at the host.
The actual termination values should be selected to compensate for transceiver and
trace impedance to match the characteristic cable impedance
Table: Typical Series Termination for Ultra DMA
Printed Circuit Board (PCB) Trace Requirements for Ultra DMA
On any PCB for a host or device supporting Ultra DMA:
The longest D[15:00] trace shall be no more than 0.5" longer than either STROBE trace as measured from the
IC pin to the connector.
The shortest D[15:00] trace shall be no more than 0.5" shorter than either STROBE trace as measured from
the IC pin to the connector.
Ultra DMA Mode Cabling Requirement
Operation in Ultra DMA mode requires a crosstalk suppressing cable. The cable shall have a grounded line
between each signal line.
For True IDE mode operation using a cable with IDE (ATA) type 40 pin connectors it is recommended that the
host sense the cable type using the method described in the ANSI INCITS 361-2002 AT Attachment - 6
standard, to prevent use of Ultra DMA with a 40 conductor cable.
Table: Ultra DMA Termination with Pull-up or Pull down Example
Attribute Memory Read Timing Specification
Configuration Register (Attribute Memory) Write Timing Specification
Common Memory Read Timing Specification
Common Memory Write Timing Specification
I/O Input (Read) Timing Specification
I/O Output (Write) Timing Specification
True IDE PIO Mode Read/Write Timing Specification
True IDE Ultra DMA Mode Read/Write Timing Specification
Table: Ultra DMA Data Burst Timing
Notes: 1) All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V.
2)
All signal transitions for a timing parameter shall be measured at the connector specified in the
measurement location column. For example, in the case of tRFS, both STROBE and –DMARDY
transitions are measured at the sender connector.
3)
The parameter tCYC shall be measured at the recipient’s connector farthest from the sender.
4)
The parameter tLI shall be measured at the connector of the sender or recipient that is
responding to an incoming transition from the recipient or sender respectively. Both the incoming
signal and the outgoing response shall be measured at the same connector.
5)
The parameter tAZ shall be measured at the connector of the sender or recipient that is driving
the bus but must release the bus to allow for a bus turnaround.
Notes: 1) The parameters tUI, tMLI : (Ultra DMA Data-In Burst Device Termination Timing and Ultra DMA
Data-In Burst Host Termination Timing), and tLI indicate sender-to-recipient or recipient-to-sender
interlocks, i.e., one agent (either sender or recipient) is waiting for the other agent to respond with a
signal before proceeding. tUI is an unlimited interlock that has no maximum time value. tMLI is a
limited time-out that has a defined minimum. tLI is a limited time-out that has a defined maximum.
2)
80-conductor cabling shall be required in order to meet setup (tDS, tCS) and hold (tDH, tCH) times
in modes greater than 2.
3)
Timing for tDVS, tDVH, tCVS and tCVH shall be met for lumped capacitive loads of 15 and 40 pF
at the connector where the Data and STROBE signals have the same capacitive load value. Due to
reflections on the cable, these timing measurements are not valid in a normally functioning system.
4)For all modes the parameter tZIORDY may be greater than tENV due to the fact that the host has a
pull-up on IORDY- giving it a known state when released.
5)
The parameters tDS, and tDH for mode 5 are defined for a recipient at the end of the cable only in
a configuration with a single device located at the end of the cable. This could result in the minimum
values for tDS and tDH for mode 5 at the middle connector being 3.0 and 3.9 ns respectively.
6)
The parameters are applied to True IDE mode operationonly.
Table: Ultra DMA Sender and Recipient IC Timing Requirements
Notes: 1) All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V.
2)
The correct data value shall be captured by the recipient given input data with a slew rate of 0.4
V/ns rising and falling and the input STROBE with a slew rate of 0.4 V/ns rising and falling at tDSIC
and tDHIC timing (as measured through 1.5 V).
3)
The parameters tDVSIC and tDVHIC shall be met for lumped capacitive loads of 15 and 40 pF at
the IC where all signals have the same capacitive load value. Noise that may couple onto the output
signals from external sources has not been included in these values.
Table: Ultra DMA Sender and Recipient IC Timing Requirements
Note: 1) The sender shall be tested while driving an 18 inch long, 80 conductor cable with PVC insulation
material. The signal under test shall be cut at a test point so that it has not trace, cable or recipient
loading after the test point. All other signals should remain connected through to the recipient. The
test point may be located at any point between the sender’s series termination resistor and one half
inch or less of conductor exiting the connector. If the test point is on a cable conductor rather than the
PCB, an adjacent ground conductor shall also be cut within one half inch of the connector.
The test load and test points should then be soldered directly to the exposed source side connectors.
The test loads consist of a 15 pF or a 40 pF, 5%, 0.08 inch by 0.05 inch surface mount or smaller size
capacitor from the test point to ground. Slew rates shall be met for both capacitor values.
Measurements shall be taken at the test point using a <1 pF, >100 Kohm, 1 Ghz or faster probe and
a 500 MHz or faster oscilloscope. The average rate shall be measured from 20% to 80% of the settled
VOH level with data transitions at least 120 nsec apart. The settled VOH level shall be measured as
the average output high level under the defined testing conditions from 100 nsec after 80% of a rising
edge until 20% of the subsequent falling edge.
The CompactFlash Storage Cards is identified by appropriate information in the Card Information Structure
(CIS). The following configuration registers are used to coordinate the I/O spaces and the Interrupt level of cards
that are located in the system. In addition, these registers provide a method for accessing status information
about the CompactFlash Storage Card that may be used to arbitrate between multiple interrupt sources on the
same interrupt level or to replace status information that appears on dedicated pins in memory cards that have
alternate use in I/O cards.
Multiple Function CompactFlash Storage Cards
Table: CompactFlash Storage Card Registers and Memory Space Decoding
Table: CompactFlash Storage Card Configuration Registers Decoding
Card Configuration
Attribute Memory Function
Attribute memory is a space where CompactFlash Storage Card identification and configuration information
are stored, and is limited to 8 bit wide accesses only at even addresses. The card configuration registers are
also located here. For CompactFlash Storage Cards, the base address of the card configuration registers is
200h.
Table 31: Attribute Memory Function
Configuration Option Register (Base + 00h in Attribute Memory)
Card Configuration and Status Register (Base + 02h in Attribute Memory)
Pin Replacement Register (Base + 04h in Attribute Memory)
Socket and Copy Register (Base + 06h in Attribute Memory)
I/O Transfer Function
The I/O transfer to or from the CompactFlash Storage can be either 8 or 16 bits. When a 16 bit accessible
port is addressed, the signal -IOIS16 is asserted by the CompactFlash Storage. Otherwise, the -IOIS16
signal is de-asserted. When a 16 bit transfer is attempted, and the -IOIS16 signal is not asserted by the
CompactFlash Storage, the system shall generate a pair of 8 bit references to access the word‘s even byte
and odd byte. The CompactFlash Storage Card permits both 8 and 16 bit accesses to all of its I/O addresses,
so -IOIS16 is asserted for all addresses to which the CompactFlash Storage responds. The CompactFlash
Storage Card may request the host to extend the length of an input cycle until data is ready by asserting the
-WAIT signal at the start of the cycle.
Table : PCMCIA Mode I/O Function
The Common Memory transfer to or from the CompactFlash Storage can be either 8 or 16 bits.
Table: Common Memory Function
Common Memory Transfer Function
The CompactFlash Storage Card can be configured in a True IDE Mode of operation. The CompactFlash Storage
Card is configured in this mode only when the -OE input signal is grounded by the host during the power off to
power on cycle. Optionally, CompactFlash Storage Cards may support the following optional detection methods:
1.
The card is permitted to monitor the –OE (-ATA SEL) signal at any time(s) and switch to PCMCIA mode upon
detecting a high level on the pin.
2.
The card is permitted to re-arbitrate the interface mode determination following a transition of the (-)RESET pin.
3.
The card is permitted to monitor the –OE (-ATA SEL) signal at any time(s) and switch to True IDE mode upon
detection of a continuous low level on pin for an extended period of time.
Table: True IDE Mode I/O Function defines the function of the operations for the True IDE Mode.
True IDE Mode I/O Transfer Function
The goal of the Metaformat is to describe the requirements and capabilities of the CompactFlash Storage Card as
thoroughly as possible. This includes describing the power requirements, IO requirements, memory requirements,
manufacturer information and details about the services provided.
Table: Sample Device Info Tuple Information for Extended Speeds
Note: The value “1” defined for D3 of the N+0 words indicates that no write-protect switch controls writing the ATA
registers. The value “0” defined for D7 in the N+2 words indicates that there is not more than a single speed
extension byte.
Metaformat Overview
The CompactFlash Storage Card can be configured as a high performance I/O device through:
a)
The standard PC-AT disk I/O address spaces 1F0h-1F7h, 3F6h-3F7h (primary) or 170h- 177h, 376h-377h
(secondary) with IRQ 14 (or other available IRQ).
b)
Any system decoded 16 byte I/O block using any available IRQ.
c)
Memory space.
The communication to or from the CompactFlash Storage Card is done using the Task File registers, which
provide all the necessary registers for control and status information related to the storage medium. The PCMCIA
interface connects peripherals to the host using four register mapping methods. Table 39 is a detailed description
of these methods:
CF-ATA Drive Register Set Definition and Protocol
I/O Primary and Secondary Address Configurations
Table: Primary and Secondary I/O Decoding
Contiguous I/O Mapped Addressing
When the system decodes a contiguous block of I/O registers to select the CompactFlash Storage Card, the
registers are accessed in the block of I/O space decoded by the system as follows:
Table: Contiguous I/O Decoding
Memory Mapped Addressing
When the CompactFlash Storage Card registers are accessed via memory references, the registers appear in the
common memory space window: 0-2K bytes as follows:
True IDE Mode Addressing
When
the CompactFlash Storage Card is configured in the True IDE Mode, the I/O decoding is as follows:
CF-ATA Registers
The following section describes the hardware registers used by the host software to issue commands to the
CompactFlash device. These registers are often collectively referred to as the “task file.”
Data Register (Address - 1F0h[170h];Offset 0,8,9)
The Data Register is a 16 bit register, and it is used to transfer data blocks between the CompactFlash
Storage Card data buffer and the Host. This register overlaps the Error Register.
Error Register (Address - 1F1h[171h]; Offset 1, 0Dh Read Only)
This register contains additional information about the source of an error when an error is indicated in bit 0
of the Status register.
This register is also accessed in PC Card Modes on data bits D15-D8 during a read operation to offset 0
with -CE2 low and -CE1 high.
Bit 7 (BBK/ICRC): this bit is set when a Bad Block is detected. This bit is also set when an interface CRC
error is detected in True IDE Ultra DMA modes of operation.
Bit 6 (UNC): this bit is set when an Uncorrectable Error is encountered.
Bit 5: this bit is 0.
Bit 4 (IDNF): the requested sector ID is in error or cannot be found.
Bit 3: this bit is 0.
Bit 2 (Abort) This bit is set if the command has been aborted because of a CompactFlash Storage Card
status condition: (Not Ready, Write Fault, etc.) or when an invalid command has been issued.
Bit 1 This bit is 0.
Bit 0 (AMNF) This bit is set in case of a general error.
This register provides information regarding features of the CompactFlash Storage Card that the host can
utilize. This register is also accessed in PC Card modes on data bits D15-D8 during a write operation to
Offset 0 with -CE2 low and -CE1 high.
Sector Count Register (Address - 1F2h[172h]; Offset 2)
This register contains the numbers of sectors of data requested to be transferred on a read or write
operation between the host and the CompactFlash Storage Card. If the value in this register is zero, a count
of 256 sectors is specified. If the command was successful, this register is zero at command completion. If
not successfully completed, the register contains the number of sectors that need to be transferred in order
to complete the request.
Sector Number (LBA 7-0) Register (Address - 1F3h[173h]; Offset 3)
This register contains the starting sector number or bits 7-0 of the Logical Block Address (LBA) for any
CompactFlash Storage Card data access for the subsequent command.
6.1.5.5 Cylinder Low (LBA 15-8) Register (Address - 1F4h[174h]; Offset 4)
This register contains the low order 8 bits of the starting cylinder address or bits 15-8 of the Logical Block
Address.
Cylinder High (LBA 23-16) Register (Address - 1F5h[175h]; Offset 5)
This register contains the high order bits of the starting cylinder address or bits 23-16 of the Logical Block
Address.
Drive/Head (LBA 27-24) Register (Address 1F6h[176h]; Offset 6)
The Drive/Head register is used to select the drive and head. It is also used to select LBA addressing
instead of cylinder/head/sector addressing.
Bit 7: this bit is specified as 1 for backward compatibility reasons. It is intended that this bit will become
obsolete in a future revision of the specification. This bit is ignored by some controllers in some
commands.
Bit 6: LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address Mode (LBA).
When LBA=0, Cylinder/Head/Sector mode is selected. When LBA=1, Logical Block Address is
selected. In Logical Block Mode, the Logical Block Address is interpreted as follows:
LBA7-LBA0: Sector Number Register D7-D0.
LBA15-LBA8: Cylinder Low Register D7-D0.
LBA23-LBA16: Cylinder High Register D7-D0.
LBA27-LBA24: Drive/Head Register bits HS3-HS0.
Bit 5: this bit is specified as 1 for backward compatibility reasons. It is intended that this bit will become
obsolete in a future revisions of the specification. This bit is ignored by some controllers in some
commands.
Bit 4 (DRV): DRV is the drive number. When DRV=0, drive (card) 0 is selected. When DRV=1, drive (card)
1 is selected. Setting this bit to 1 is obsolete in PCMCIA modes of operation. If the obsolete
functionality is support by a CF Storage Card, the CompactFlash Storage Card is set to be Card 0 or 1
using the copy field (Drive #) of the PCMCIA Socket & Copy configuration register.
Bit 3 (HS3): when operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number. It is Bit 27
in the Logical Block Address mode.
Feature Register (Address - 1F1h[171h]; Offset 1, 0Dh Write Only)
Bit 2 (HS2): when operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It is Bit 26
in the Logical Block Address mode.
Bit 1 (HS1): when operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It is Bit 25
in the Logical Block Address mode.
Bit 0 (HS0): when operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It is Bit 24
in the Logical Block Address mode.
Status & Alternate Status Registers (Address 1F7h[177h]&3F6h[376h]; Offsets 7 & Eh)
These registers return the CompactFlash Storage Card status when read by the host. Reading
the Status register does clear a pending interrupt while reading the Auxiliary Status register does
not. The status bits are described as follows:
Bit 7 (BUSY): the busy bit is set when the CompactFlash Storage Card has access to the command buffer
and registers and the host is locked out from accessing the command register and buffer. No other bits
in this register are valid when this bit is set to a 1. During the data transfer of DMA commands, the Card
shall not assert DMARQ unless either the BUSY bit, the DRQ bit, or both are set to one.
Bit 6 (RDY): RDY indicates whether the device is capable of performing CompactFlash Storage Card
operations. This bit is cleared at power up and remains cleared until the CompactFlash Storage Card is
ready to accept a command.
Bit 5 (DWF): This bit, if set, indicates a write fault has occurred.
Bit 4 (DSC): This bit is set when the CompactFlash Storage Card is ready.
Bit 3 (DRQ): The Data Request is set when the CompactFlash Storage Card requires that information be
transferred either to or from the host through the Data register. During the data transfer of DMA
commands, the Card shall not assert DMARQ unless either the BUSY bit, the DRQ bit, or both are set
to one.
Bit 2 (CORR): This bit is set when a Correctable data error has been encountered and the data has been
corrected. This condition does not terminate a multi-sector read operation.
Bit 1 (IDX): This bit is always set to 0.
Bit 0 (ERR): This bit is set when the previous command has ended in some type of error. The bits in the
Error register contain additional information describing the error. It is recommended that media access
commands (such as Read Sectors and Write Sectors) that end with an error condition should have the
address of the first sector in error in the command block registers.
This register is used to control the CompactFlash Storage Card interrupt request and to issue an ATA soft
reset to the card. This register can be written even if the device is BUSY. The bits are defined as follows:
Bit 7: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.
Bit 6: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.
Bit 5: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.
Bit 4: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.
Bit 3: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.
Bit 2 (SW Rst): this bit is set to 1 in order to force the CompactFlash Storage Card to perform an AT Disk
controller Soft Reset operation. This does not change the PCMCIA Card Configuration Registers as a
hardware Reset does. The Card remains in Reset until this bit is reset to ‘0.’
Bit 1 (-IEn): the Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1, interrupts from
the CompactFlash Storage Card are disabled. This bit also controls the Int bit in the Configuration and
Status Register. This bit is set to 0 at power on and Reset.
Bit 0: this bit is ignored by the CompactFlash Storage Card.
Device Control Register (Address - 3F6h[376h]; Offset Eh)
Card (Drive) Address Register (Address 3F7h[377h]; Offset Fh)
This register is provided for compatibility with the AT disk drive interface. It is recommended that this
register not be mapped into the host’s I/O space because of potential conflicts on Bit 7.
Bit 7: this bit is unknown.
Implementation Note:
Conflicts may occur on the host data bus when this bit is provided by a Floppy Disk Controller
operating at the same addresses as the CompactFlash Storage Card. Following are some possible
solutions to this problem for the PCMCIA implementation:
1)
Locate the CompactFlash Storage Card at a non-conflicting address, i.e. Secondary address
(377) or in an independently decoded Address Space when a Floppy Disk Controller is located at
the Primary addresses.
2)
Do not install a Floppy and a CompactFlash Storage Card in the system at the same time.
3)
Implement a socket adapter that can be programmed to (conditionally) tri-state D7 of I/0 address
3F7h/377h when a CompactFlash Storage Card is installed and conversely to tristate D6-D0 of
I/O address 3F7h/377h when a floppy controller is installed.
4)
Do not use the CompactFlash Storage Card’s Drive Address register. This may be accomplished
by either a) If possible, program the host adapter to enable only I/O addresses 1F0h-1F7h, 3F6h
(or 170h-177h, 176h) to the CompactFlash Storage Card or b) if provided use an additional
Primary / Secondary configuration in the CompactFlash Storage Card which does not respond to
accesses to I/O locations 3F7h and 377h. With either of these implementations, the host
software shall not attempt to use information in the Drive Address Register.
Bit 6 (-WTG): this bit is 0 when a write operation is in progress; otherwise, it is 1.
Bit 5 (-HS3): this bit is the negation of bit 3 in the Drive/Head register.
Bit 4 (-HS2): this bit is the negation of bit 2 in the Drive/Head register.
Bit 3 (-HS1): this bit is the negation of bit 1 in the Drive/Head register.
Bit 2 (-HS0): this bit is the negation of bit 0 in the Drive/Head register.
Bit 1 (-nDS1): this bit is 0 when drive 1 is active and selected.
Bit 0 (-nDS0): this bit is 0 when the drive 0 is active and selected.
CF-ATA Command Set
Request Sense - 03h
The extended error code is returned to the host in the Error Register.
Write Sector(s) without Erase - 38h
Erase Sector(s) - C0h
This command is used to pre-erase and condition data sectors in advance of a Write without Erase or Write
Multiple without Erase command. There is no data transfer associated with this command but a Write Fault error
status can occur.
Write Multiple without Erase – CDh
Translate Sector - 87h
Translate Sector Information
Set Features – EFh
Feature Supported
Feature
Operation
03h
Set transfer mode based on calue in Sector Count register
81h
Disable 8 bit data transfer
82h
Disable Write Cache
Execute Drive Diagnostic - 90h
When the diagnostic command is issued in a PCMCIA configuration mode, this command runs only on the
CompactFlash Storage Card that is addressed by the Drive/Head register. This is because PCMCIA card
interface does not allow for direct inter-drive communication (such as the ATA PDIAG and DASP signals). When
the diagnostic command is issued in the True IDE Mode, the Drive bit is ignored and the diagnostic command is
executed by both the Master and the Slave with the Master responding with status for both devices.
Diagnostic Codes are returned in the Error Register at the end of the command.
Flush Cache – E7h
This command causes the card to complete writing data from its cache. The card returns status with RDY=1 and
DSC=1 after the data in the write cache buffer is written to the media. If the Compact Flash Storage Card does not
support the Flush Cache command, the Compact Flash Storage Card shall return command aborted.
Identify Device – ECh
The Identify Device command enables the host to receive parameter information from the
CompactFlash Storage Card. This command has the same protocol as the Read Sector(s) command. The
parameter words in the buffer have the arrangement and meanings defined in Table as below. All reserved
bits or words are zero. Hosts should not depend on Obsolete words in Identify Device containing 0. Table
47 specifies each field in the data returned by the Identify Device Command. In Table as below, X indicates
a numeric nibble value specific to the card and aaaa indicates an ASCII string specific to the particular drive.
Read DMA – C8h
Read Multiple - C4h
Read Sector(s) - 20h or 21h
Read Verify Sector(s) - 40h or 41h
Set Multiple Mode - C6h
Write DMA – CAh
Write Multiple Command - C5h
Write Sector(s) - 30h or 31h
NOP - 00h
This command always fails with the CompactFlash Storage Card returning command aborted.
Read Buffer - E4h
The Read Buffer command enables the host to read the current contents of the CompactFlash Storage Card’s
sector buffer. This command has the same protocol as the Read Sector(s) command.
Write Buffer - E8h
Check Power Mode - 98h or E5h
If the CompactFlash Storage Card is in, going to, or recovering from the sleep mode, the CompactFlash Storage
Card sets BSY, sets the Sector Count Register to 00h, clears BSY and generates an interrupt.
If the CompactFlash Storage Card is in Idle mode, the CompactFlash Storage Card sets BSY, sets the Sector
Count Register to FFh, clears BSY and generates an interrupt.
Idle - 97h or E3h
This command causes the CompactFlash Storage Card to set BSY, enter the Idle mode, clear BSY and
generate an interrupt. If the sector count is non-zero, it is interpreted as a timer count with each count being 5
milliseconds and the automatic power down mode is enabled. If the sector count is zero, the automatic power
down mode is disabled. Note that this time base (5 msec) is different from the ATA specification.
Idle Immediate - 95h or E1h
This command causes the CompactFlash Storage Card to set BSY, enter the Idle mode, clear BSY and
generate an interrupt.
Set Sleep Mode- 99h or E6h
Standby - 96h or E2h
Standby Immediate - 94h or E0h
Security Set Password – F1h
Table
Security Unlock – F2h
Security Erase Prepare – F3h
Security Erase Unit – F4h
Security Freeze Lock – F5h
Security Freeze Lock – F6h
Format Track - 50h
This command writes the desired head and cylinder of the selected drive with a vendor unique data pattern
(typically FFh or 00h). To remain host backward compatible, the CompactFlash Storage Card expects a sector
buffer of data from the host to follow the command with the same protocol as the Write Sector(s) command
although the information in the buffer is not used by the CompactFlash Storage Card. If LBA=1 then the number of
sectors to format is taken from the Sec Cnt register (0=256). The use of this command is not recommended.
Initialize Drive Parameters - 91h
This command enables the host to set the number of sectors per track and the number of heads per cylinder.
Only the Sector Count and the Card/Drive/Head registers are used by this command.
Recalibrate - 1Xh
Seek - 7Xh
Wear Level - F5h
Write Verify - 3Ch
Error Posting
Error and Status Register summarizes the valid status and error value for all the CF-ATA Command set.
ID Table Information of True IDE Mode
Word
Address
Default
Value
Total
Bytes
Data Field Type Information
0
4A04h
2
General configuration - signature for the CompactFlash Storage Card
1
XXXXh
2
Default number of cylinders
2
0000h
2
Reserved
3
00XXh
2
Default number of heads
4
0000h
2
Obsolete
5
0000h
2
Obsolete
6
XXXXh
2
Default number of sectors per track
7-8
XXXXh
4
Number of sectors per card (Word 7 = MSW, Word 8 = LSW)
9
0000h
2
Obsolete
10-19
aaaa
20
Serial number in ASCII (Right Justified)
20
0002h
2
Obsolete
21
0002h
2
Obsolete
22
0004h
2
Number of ECC bytes passed on Read/Write Long Commands
23-26
aaaa
8
Firmware revision in ASCII. Big Endian Byte Order in Word
27-46
aaaa
40
Model number in ASCII (Left Justified) Big Endian Byte Order in Word
47
8001h
2
Maximum number of sectors on Read/Write Multiple command
48
0000h
2
Reserved
49
0F00h
2
Capabilities
50
0000h
2
Reserved
51
0200h
2
PIO data transfer cycle timing mode
52
0000h
2
Obsolete
53
0007h
2
Field Validity
54
XXXXh
2
Current numbers of cylinders
55
XXXXh
2
Current numbers of heads
56
XXXXh
2
Current sectors per track
57-58
XXXXh
4
Current capacity in sectors (LBAs)(Word 57 = LSW, Word 58 = MSW)
59
01XXh
2
Multiple sector setting
60-61
XXXXh
4
Total number of sectors addressable in LBA Mode
62
0000h
2
Reserved
63
0007h
2
Multiword DMA transfer. In PC Card modes this value shall be 0h
64
0003h
2
Advanced PIO modes supported
65
0078h
2
Minimum Multiword DMA transfer cycle time per word. In PC Card modes this
value shall be 0h
66
0078h
2
Recommended Multiword DMA transfer cycle time. In PC Card modes this
value shall be 0h
67
0078h
2
Minimum PIO transfer cycle time without flow control
68
0078h
2
Minimum PIO transfer cycle time with IORDY flow control
Word
Address
Default
Value
Total
Bytes
Data Field Type Information
69-79
0000h
20
Reserved
80-81
0000h
4
Reserved – CF cards do not return an ATA version
82
702Bh
2
Command sets supported 0
83
500Ch
2
Command sets supported 1
84
4000h
2
Command sets supported 2
85
0000h
2
Command sets enabled 0
86
0000h
2
Command sets enabled 1
87
0000h
2
Command sets enabled 2
88
003Fh
2
Ultra DMA Mode Supported and Selected
89
0001h
2
Time required for Security erase unit completion
90
0000h
2
Time required for Enhanced security erase unit completion
91
0000h
2
Current Advanced power management value
92
0000h
2
Master Password Revision Code
93
604Fh
6F00h
603Fh
2
- Hardware reset result (Master)
- Hardware reset result (Slave)
- Hardware reset result (Master w/ slave present)
94-127
0000h
68
Reserved
128
0001h
2
Security status
129-159
0000h
64
Vendor unique bytes
160
81F4h
2
Power requirement description
161
0000h
2
Reserved for assignment by the CFA
162
0000h
2
Key management schemes supported
163
0092h
2
CF Advanced True IDE Timing Mode Capability and Setting
164
0000h
2
CF Advanced PC Card I/O and Memory Timing Mode Capability
165-175
0000h
22
Reserved
176-255
0000h
160
Reserved
Word 0: General Configuration
This field indicates the general characteristics of the device. When Word 0 of the Identify drive information
is 848Ah then the device is a CompactFlash Storage Card and complies with the CFA specification and
CFA command set. It is recommended that PCMCIA modes of operation report only the 848Ah value as
they are always intended as removable devices.
Bits 15-0: CF Standard Configuration Value
Word 0 is 848Ah. This is the recommended value of Word 0.
Some operating systems require Bit 6 of Word 0 to be set to 1 (Non-removable device) to use the card as
the root storage device. The Card must be the root storage device when a host completely replaces
conventional disk storage with a CompactFlash Card in True IDE mode. To support this requirement and
provide capability for any future removable media Cards, alternatehandling of Word 0 is permitted.
Bits 15-0: CF Preferred Alternate Configuration Values
044Ah: This is the alternate value of Word 0 turns on ATA device and turns off Removable Media and
Removable Device while preserving all Retired bits in the word.
0040h: This is the alternate value of Word 0 turns on ATA device and turns off Removable Media and
Removable Device while zeroing all Retired bits in the word
Bit 15-12: Configuration Flag
If bits 15:12 are set to 8h then Word 0 shall be 848Ah.
If bits 15:12 are set to 0h then Bits 11:0 are set using the definitions below and the Card is required to
support for the CFA command set and report that in bit 2 of Word 83.
Bit 15:12 values other than 8h and 0h are prohibited.
Bits 11-8: Retired
These bits have retired ATA bit definitions. It is recommended that the value of these bits be either the
preferred value of 0h or the value of 4h that preserves the corresponding bits from the 848Ah CF signature
value.
Bit 7: Removable Media Device
If Bit 7 is set to 1, the Card contains media that can be removed during Card operation.
If Bit 7 is set to 0, the Card contains nonremovable media.
Bit 6: Not Removable Controller and/or Device
Alert! This bit will be considered for obsolescence in a future revision of this standard.
If Bit 6 is set to 1, the Card is intended to be nonremovable during operation.
If Bit 6 is set to 0, the Card is intended to be removable during operation.
Bits 5-0: Retired/Reserved
Alert! Bit 2 will be considered for definition in a future revision of this standard and shall be 0 at this
time.
Bits 5-1 have retired ATA bit definitions.
Bit 2 shall be 0.
Bit 0 is Reserved and shall be 0.
It is recommended that the value of bits 5-0 be either the preferred value of 00h or the value of 0Ah that
preserves the corresponding bits from the 848Ah CF signature value.
Word 1: Default Number of Cylinders
This field contains the number of translated cylinders in the default translation mode. This value will be the
same as the number of cylinders.
Word 3: Default Number of Heads
This field contains the number of translated heads in the default translation mode.
Word 6: Default Number of Sectors per Track
This field contains the number of sectors per track in the default translation mode.
Words 7-8: Number of Sectors per Card
This field contains the number of sectors per CompactFlash Storage Card. This double word
value is also the first invalid address in LBA translation mode.
Words 10-19: Serial Number
This field contains the serial number for this CompactFlash Storage Card and is right justified and padded
with spaces (20h).
Word 22: ECC Count
This field defines the number of ECC bytes used on each sector in the Read and Write Long commands.
This value shall be set to 0004h.
Words 23-26: Firmware Revision
This field contains the revision of the firmware for this product.
Words 27-46: Model Number
This field contains the model number for this product and is left justified and padded with spaces (20h).
Word 47: Read/Write Multiple Sector Count
Bits 15-8 shall be the recommended value of 80h or the permitted value of 00h. Bits 7-0 of this word define
the maximum number of sectors per block that the CompactFlash Storage Card supports for Read/Write
Multiple commands.
Word 49: Capabilities
Bit 13: Standby Timer
If bit 13 is set to 1 then the Standby timer is supported as defined by the IDLE command
If bit 13 is set to 0 then the Standby timer operation is defined by the vendor.
Bit 11: IORDY Supported
If bit 11 is set to 1 then this CompactFlash Storage Card supports IORDY operation.
If bit 11 is set to 0 then this CompactFlash Storage Card may support IORDY operation.
Bit 10: IORDY may be disabled
Bit 10 shall be set to 0, indicating that IORDY may not be disabled.
Bit 9: LBA supported
Bit 9 shall be set to 1, indicating that this CompactFlash Storage Card supports LBA mode addressing. CF
devices shall support LBA addressing.
Bit 8: DMA Supported If bit 8 is set to 1 then Read DMA and Write DMA commands are supported. Bit 8
shall be set to 0. Read/Write DMA commands are not currently permitted on CF cards.
PIO Data Transfer Cycle Timing Mode
The PIO transfer timing for each CompactFlash Storage Card falls into modes that have unique
parametric timing specifications. The value returned in Bits 15-8 shall be 00h for mode 0, 01h for mode 1,
or 02h for mode 2. Values 03h through FFh are reserved.
Translation Parameters Valid
Bit 0 shall be set to 1 indicating that words 54 to 58 are valid and reflect the current number of cylinders,
heads and sectors. If bit 1 of word 53 is set to 1, the values in words 64 through 70 are valid. If this bit is
cleared to 0, the values reported in words 64-70 are not valid. Any CompactFlash Storage Card that
supports PIO mode 3 or above shall set bit 1 of word 53 to one and support the fields contained in words
64 through 70.
Current Number of Cylinders, Heads, Sectors/Track
These fields contains the current number of user addressable Cylinders, Heads, and Sectors/Track in the
current translation mode.
Current Capacity
This field contains the product of the current cylinders times heads times sectors.
Multiple Sector Setting
Bits 15-9 are reserved and shall be set to 0.
Bit 8 shall be set to 1 indicating that the Multiple Sector Setting is valid.
Bits 7-0 are the current setting for the number of sectors that shall be transferred per interrupt on
Read/Write Multiple commands.
Total Sectors Addressable in LBA Mode
This field contains the total number of user addressable sectors for the CompactFlash Storage Card in
LBA mode only.
Multiword DMA transfer
Bits 15 through 8 of word 63 of the Identify Device parameter information is defined as the Multiword DMA
mode selected field. If this field is supported, bit 1 of word 53 shall be set to one. This field is bit significant.
Only one of bits may be set to one in this field by the CompactFlash Storage Card to indicate the multiword
DMA mode which is currently selected. Of these bits, bits 15 through 11 are reserved. Bit 8, if set to one,
indicates that Multiword DMA mode 0 has been selected. Bit 9, if set to one, indicates that Multiword DMA
mode 1 has been selected. Bit 10, if set to one, indicates that Multiword DMA mode 2 has been selected.
Selection of Multiword DMA modes 3 and above are specific to CompactFlash are reported in word 163,
Word 163: CF Advanced True IDE Timing Mode Capabilities and Settings.
Bits 7 through 0 of word 63 of the Identify Device parameter information is defined as the Multiword DMA
data transfer supported field. If this field is supported, bit 1 of word 53 shall be set to one. This field is bit
significant. Any number of bits may be set to one in this field by the CompactFlash Storage Card to
indicate the Multiword DMA modes it is capable of supporting.
Of these bits, bits 7 through 2 are reserved. Bit 0, if set to one, indicates that the CompactFlash Storage
Card supports Multiword DMA mode 0. Bit 1, if set to one, indicates that the CompactFlash Storage Card
supports Multiword DMA modes 1 and 0. Bit 2, if set to one, indicates that the CompactFlash Storage
Card supports Multiword DMA modes 2, 1 and 0. Support for Multiword DMA modes 3 and above are
specific to CompactFlash are reported in word 163, Word 163: CF Advanced True IDE Timing Mode
Capabilities and Settings.
Word 64: Advanced PIO transfer modes supported
Bits 7 through 0 of word 64 of the Identify Device parameter information is defined as the advanced PIO
data transfer supported field. If this field is supported, bit 1 of word 53 shall be set to one. This field is bit
significant. Any number of bits may be set to one in this field by the CompactFlash Storage Card to
indicate the advanced PIO modes it is capable of supporting.
Of these bits, bits 7 through 2 are reserved. Bit 0, if set to one, indicates that the CompactFlash Storage
Card supports PIO mode 3. Bit 1, if set to one, indicates that the CompactFlash StorageCard supports
PIO mode 4.
Support for PIO modes 5 and above are specific to CompactFlash are reported in word 163.
Word 65: Minimum Multiword DMA transfer cycle time
Word 65 of the parameter information of the Identify Device command is defined as the minimum
Multiword DMA transfer cycle time. This field defines, in nanoseconds, the minimum cycle time that, if
used by the host, the CompactFlash Storage Card guarantees data integrity during the transfer.
If this field is supported, bit 1 of word 53 shall be set to one. The value in word 65 shall not be less than the
minimum cycle time for the fastest DMA mode supported by the device. This field shall be supported by all
CompactFlash Storage Cards supporting DMA modes 1 and above. If bit 1 of word 53 is set to one, but
this field is not supported, the Card shall return a value of zero in this field.
Recommended Multiword DMA transfer cycle time
Word 66 of the parameter information of the Identify Device command is defined as the recommended
Multiword DMA transfer cycle time. This field defines, in nanoseconds, the cycle time that, if used by the
host, may optimize the data transfer from by reducing the probability that the CompactFlash Storage Card
will need to negate the DMARQ signal during the transfer of a sector.
If this field is supported, bit 1 of word 53 shall be set to one. The value in word 66 shall not be less than the
value in word 65. This field shall be supported by all CompactFlash Storage Cards supporting DMA
modes 1 and above. If bit 1 of word 53 is set to one, but this field is not supported, the Card shall return a
value of zero in this field.
Word 67: Minimum PIO transfer cycle time without flow control
Word 67 of the parameter information of the Identify Device command is defined as the minimum PIO
transfer without flow control cycle time. This field defines, in nanoseconds, the minimum cycle time that, if
used by the host, the CompactFlash Storage Card guarantees data integrity during the transfer without
utilization of flow control. If this field is supported, Bit 1 of word 53 shall be set to one. Any CompactFlash
Storage Card that supports PIO mode 3 or above shall support this field, and the value in word 67 shall not
be less than the value reported in word 68. If bit 1 of word 53 is set to one because a CompactFlash
Storage Card supports a field in words 64-70 other than this field and the CompactFlash Storage Card
does not support this field, the CompactFlash Storage Card shall return a value of zero in this field.
Word 68: Minimum PIO transfer cycle time with IORDY
Word 68 of the parameter information of the Identify Device command is defined as the minimum PIO
transfer with IORDY flow control cycle time. This field defines, in nanoseconds, the minimum cycle time
that the CompactFlash Storage Card supports while performing data transfers while utilizing IORDY flow
control. If this field is supported, Bit 1 of word 53 shall be set to one. Any CompactFlash Storage Card that
supports PIO mode 3 or above shall support this field, and the value in word 68 shall be the fastest defined
PIO mode supported by the CompactFlash Storage Card. If bit 1 of word 53 is set to one because a
CompactFlash Storage Card supports a field in words 64-70 other than this field and the CompactFlash
Storage Card does not support this field, the CompactFlash Storage Card shall return a value of zero in
this field.
Words 82-84: Features/command sets supported
Words 82, 83, and 84 shall indicate features/command sets supported. The value 0000h or FFFFh was
placed in each of these words by CompactFlash Storage Cards prior to ATA-3 and shall be interpreted by
the host as meaning that features/command sets supported are not indicated. Bits 1 through 13 of word
83 and bits 0 through 13 of word 84 are reserved. Bit 14 of word 83 and word 84 shall be set to one and bit
15 of word 83 and word 84 shall be cleared to zero to provide indication that the features/command sets
supported words are valid. The values in these words should not be depended on by host implementers.
Bit 0 of word 82 shall be set to zero; the SMART feature set is not supported.
If bit 1 of word 82 is set to one, the Security Mode feature set is supported.
Bit 2 of word 82 shall be set to zero; the Removable Media feature set is not supported.
Bit 3 of word 82 shall be set to one; the Power Management feature set is supported.
Bit 4 of word 82 shall be set to zero; the Packet Command feature set is not supported.
If bit 5 of word 82 is set to one, write cache is supported.
If bit 6 of word 82 is set to one, look-ahead is supported.
Bit 7 of word 82 shall be set to zero; release interrupt is not supported.
Bit 8 of word 82 shall be set to zero; Service interrupt is not supported.
Bit 9 of word 82 shall be set to zero; the Device Reset command is not supported.
Bit 10 of word 82 shall be set to zero; the Host Protected Area feature set is not supported.
Bit 11 of word 82 is obsolete.
Bit 12 of word 82 shall be set to one; the CompactFlash Storage Card supports the Write Buffer command.
Bit 13 of word 82 shall be set to one; the CompactFlash Storage Card supports the Read Buffer
command.
Bit 14 of word 82 shall be set to one; the CompactFlash Storage Card supports the NOP command.
Bit 15 of word 82 is obsolete.
Bit 0 of word 83 shall be set to zero; the CompactFlash Storage Card does not support the Download
Microcode command.
Bit 1 of word 83 shall be set to zero; the CompactFlash Storage Card does not support the Read DMA
Queued and Write DMA Queued commands.
Bit 2 of word 83 shall be set to one; the CompactFlash Storage Card supports the CFA feature set.
If bit 3 of word 83 is set to one, the CompactFlash Storage Card supports the Advanced Power
Management feature set.
Bit 4 of word 83 shall be set to zero; the CompactFlash Storage Card does not support the Removable
Media Status feature set.
Words 85-87: Features/command sets enabled
Words 85, 86, and 87 shall indicate features/command sets enabled. The value 0000h or FFFFh was
placed in each of these words by CompactFlash Storage Cards prior to ATA-4 and shall be interpreted by
the host as meaning that features/command sets enabled are not indicated. Bits 1 through 15 of word 86
are reserved. Bits 0-13 of word 87 are reserved. Bit 14 of word 87 shall be set to one and bit 15 of word 87
shall be cleared to zero to provide indication that the features/command sets enabled words are valid. The
values in these words should not be depended on by host implementers.
Bit 0 of word 85 shall be set to zero; the SMART feature set is not enabled.
If bit 1 of word 85 is set to one, the Security Mode feature set has been enabled via the Security Set
Password command.
Bit 2 of word 85 shall be set to zero; the Removable Media feature set is not supported.
Bit 3 of word 85 shall be set to one; the Power Management feature set is supported.
Bit 4 of word 85 shall be set to zero; the Packet Command feature set is not enabled.
If bit 5 of word 85 is set to one, write cache is enabled.
If bit 6 of word 85 is set to one, look-ahead is enabled.
Bit 7 of word 85 shall be set to zero; release interrupt is not enabled.
Bit 8 of word 85 shall be set to zero; Service interrupt is not enabled.
Bit 9 of word 85 shall be set to zero; the Device Reset command is not supported.
Bit 10 of word 85 shall be set to zero; the Host Protected Area feature set is not supported.
Bit 11 of word 85 is obsolete.
Bit 12 of word 85 shall be set to one; the CompactFlash Storage Card supports the Write Buffer command.
Bit 13 of word 85 shall be set to one; the CompactFlash Storage Card supports the Read Buffer
command.
Bit 14 of word 85 shall be set to one; the CompactFlash Storage Card supports the NOP command.
Bit 15 of word 85 is obsolete.
Bit 0 of word 86 shall be set to zero; the CompactFlash Storage Card does not support the Download
Microcode command.
Bit 1 of word 86 shall be set to zero; the CompactFlash Storage Card does not support the Read DMA
Queued and Write DMA Queued commands.
If bit 2 of word 86 shall be set to one, the CompactFlash Storage Card supports the CFA feature set.
If bit 3 of word 86 is set to one, the Advanced Power Management feature set has been enabled via the
Set Features command.
Bit 4 of word 86 shall be set to zero; the CompactFlash Storage Card does not support the Removable
Media Status feature set.
Word 88: Ultra DMA Modes Supported and Selected
Word 88 identifies the Ultra DMA transfer modes supported by the device and indicates the mode that is
currently selected. Only one DMA mode shall be selected at any given time. If an Ultra DMA mode is
selected, then no Multiword DMA mode shall be selected. If a Multiword DMA mode is selected, then no
Ultra DMA mode shall be selected. Support of this word is mandatory if Ultra DMA is supported.
Bits 15-13: Reserved
Bit 13: 1 = Ultra DMA mode 5 is selected 0 = Ultra DMA mode 5 is not selected
Bit 12: 1 = Ultra DMA mode 4 is selected 0 = Ultra DMA mode 4 is not selected
Bit 11: 1 = Ultra DMA mode 3 is selected 0 = Ultra DMA mode 3 is not selected
Bit 10: 1 = Ultra DMA mode 2 is selected 0 = Ultra DMA mode 2 is not selected
Bit 9: 1 = Ultra DMA mode 1 is selected 0 = Ultra DMA mode 1 is not selected
Bit 8: 1 = Ultra DMA mode 0 is selected 0 = Ultra DMA mode 0 is not selected
Bits 7-5: Reserved
Bit 5: 1 = Ultra DMA mode 5 and below are supported. Bits 0-4 Shall be set to 1
Bit 4: 1 = Ultra DMA mode 4 and below are supported. Bits 0-3 Shall be set to 1.
Bit 3: 1 = Ultra DMA mode 3 and below are supported, Bits 0-2 Shall be set to 1.
Bit 2: 1 = Ultra DMA mode 2 and below are supported. Bits 0-1 Shall be set to 1.
Bit 1: 1 = Ultra DMA mode 1 and below are supported. Bit 0 Shall be set to 1.
Bit 0: 1 = Ultra DMA mode 0 is supported
Word 89: Time required for Security erase unit completion
Word 89 specifies the time required for the Security Erase Unit command to complete. This command
shall be supported on CompactFlash Storage Cards that support security.
Value
Time
0
Value not specified
1-254
(Value * 2) minutes
255
>508 minutes
Word 90: Time required for Enhanced security erase unit completion
Word 90 specifies the time required for the Enhanced Security Erase Unit command to complete.
This command shall be supported on CompactFlash Storage Cards that support security.
Value
Time
0
Value not specified
1-254
(Value * 2) minutes
255
>508 minutes
Word 91: Advanced power management level value
Bits 7-0 of word 91 contain the current Advanced Power Management level setting.
Word 128: Security Status
Bit 8: Security Level
If set to 1, indicates that security mode is enabled and the security level is maximum.
If set to 0 and security mode is enabled, indicates that the security level is high.
Bit 5: Enhanced security erase unit feature supported
If set to 1, indicates that the Enhanced security erase unit feature set is supported.
Bit 4: Expire
If set to 1, indicates that the security count has expired and Security Unlock and Security Erase Unit are
command aborted until a power-on reset or hard reset.
Bit 3: Freeze
If set to 1, indicates that the security is Frozen.
Bit 2: Lock
If set to 1, indicates that the security is locked.
Bit 1: Enable/Disable
If set to 1, indicates that the security is enabled.
If set to 0, indicates that the security is disabled.
Bit 0: Capability
If set to 1, indicates that CompactFlash Storage Card supports security mode feature set.
If set to 0, indicates that CompactFlash Storage Card does not support security mode feature set.
Word 160: Power Requirement Description
This word is required for CompactFlash Storage Cards that support power mode 1.
Bit 15: VLD
If set to 1, indicates that this word contains a valid power requirement description.
If set to 0, indicates that this word does not contain a power requirement description.
Bit 14: RSV
This bit is reserved and shall be 0.
Bit 13: -XP
If set to 1, indicates that the CompactFlash Storage Card does not have Power Level 1 commands.
If set to 0, indicates that the CompactFlash Storage Card has Power Level 1 commands
Bit 12: -XE
If set to 1, indicates that Power Level 1 commands are disabled.
If set to 0, indicates that Power Level 1 commands are enabled.
Bit 0-11: Maximum current
This field contains the CompactFlash Storage Card’s maximum current in mA.
Word 162: Key Management Schemes Supported
Bit 0: CPRM support
If set to 1, the device supports CPRM Scheme (Content Protection for Recordable Media)
If set to 0, the device does not support CPRM.
Bits 1-15 are reserved for future additional Key Management schemes.
Word 163: CF Advanced True IDE Timing Mode Capabilities and Settings
This word describes the capabilities and current settings for CFA defined advanced timing modes using
the True IDE interface.
Notice! The use of True IDE PIO Modes 5 and above or of Multiword DMA Modes 3 and above
impose significant restrictions on the implementation of the host:
Additional Requirements for CF Advanced Timing Modes.
There are four separate fields defined that describe support and selection of Advanced PIO timing modes
and Advanced Multiword DMA timing modes. The older modes are reported in words 63 and 64.
Word 63: Multiword DMA transfer and 6.2.1.6.19: Word 64: Advanced PIO transfer modes supported.
Bits 2-0: Advanced True IDE PIO Mode Support Indicates the maximum True IDE PIO mode supported by
the card.
Value
Maximum PIO mode timing selected
0
Specified in word 64
1
PIO Mode 5
2
PIO Mode 6
3-7
Reserved
Bits 5-3: Advanced True IDE Multiword DMA Mode Support Indicates the maximum True IDE Multiword
DMA mode supported by the card.
Value
Maximum Multiword DMA timing mode supported
0
Specified in word 63
1
Multiword DMA Mode 3
2
Multiword DMA Mode 4
3-7
Reserved
Bits 8-6: Advanced True IDE PIO Mode Selected Indicates the current True IDE PIO mode selected on
the card.
Value
Current PIO timing mode selected
0
Specified in word 64
1
PIO Mode 5
2
PIO Mode 6
3-7
Reserved
Bits 11-9: Advanced True IDE Multiword DMA Mode Selected Indicates the current True IDE Multiword
DMA Mode Selected on the card.
Value
Current Multiword DMA timing mode selected
0
Specified in word 63
1
Multiword DMA Mode 3
2
Multiword DMA Mode 4
3-7
Reserved
Bits 15-12 are reserved.
Word 164: CF Advanced PCMCIA I/O and Memory Timing Modes Capabilities and Settings
This word describes the capabilities and current settings for CFA defined advanced timing modes using
the Memory and PCMCIA I/O interface.
Notice! The use of PCMCIA I/O or Memory modes that are 100ns or faster impose significant
restrictions on the implementation of the host:
Additional Requirements for CF Advanced Timing Modes.
Bits 2-0: Maximum Advanced PCMCIA I/O Mode Support Indicates the maximum I/O timing mode
supported by the card.
Value
Maximum PCMCIA IO timing mode Supported
0
255ns Cycle PCMCIA I/O Mode
1
120ns Cycle PCMCIA I/O Mode
2
100ns Cycle PCMCIA I/O Mode
3
80ns Cycle PCMCIA I/O Mode
4-7
Reserved
Bits 5-3: Maximum Memory timing mode supported
Indicates the Maximum Memory timing mode supported by the card.
Bits 15-6: Reserved.
Value
Maximum Memory timing mode Supported
0
250ns Cycle Memory Mode
1
120ns Cycle Memory Mode
2
100ns Cycle Memory Mode
3
80ns Cycle Memory Mode
4-7
Reserved
SMART Command Set
SMART Feature Register Values
D0h
Read Data
D5h
Read Log
D1h
Read Attribute Threshold
D6h
Write Log
D2h
Enable/Disable Autosave
D8h
Enable SMART Operations
D3h
Save Attribute Values
D9h
Disable SMART Operations
D4h
Execute OFF-LINE Immediate
DAh
Return Status
1.
If reserved size is below the Threshold, the status can be read from Cylinder register by Return Status command
(DAh).
SMART Data Structure
BYTE
F / V
Decription
0-1
X
Revision code
2-361
X
Vendor specific
362
V
Off-line data collection status
363
X
Self-test execution status byte
364-365
V
Total time in seconds to complete off-line data collection activity
366
X
Vendor specific
367
F
Off-line data collection capability
368-369
F
SMART capability
370
F
Error logging capability
7-1 Reserved
0 1=Device error logging supported
371
X
Vendor specific
372
F
Short self-test routine recommended polling time (in minutes)
373
F
Extended self-test routine recommended polling time (in minutes)
374
F
Conveyance self-test routine recommended polling time (in minutes)
375-385
R
Reserved
386-395
F
Firmware Version/Date Code
396-399
R
Reserved
400-406
V
‘SMI2236’
407-511
V
Reserved
F=the content of the byte is fixed and does not change.
V=the content of the byte is variable and may change depending on the state of the device or
The technical information above is based on CFA standard data and tested to be reliable. However, Transcend makes no
warranty, either expressed or implied, as to its accuracy and assumes no liability in connection with the use of this
product. Transcend reserves the right to make changes in specifications at any time without prior notice.
SMART Attributes
The table below shows the vendor specific data in byte 2 to 361 of the 512-byte SMART data
Attribute ID
(hex)
Raw Attribute Value
Attribute Name
01
MSB
00
00
00
00
00
Read Error Rate
05
LSB
MSB
00
00
00
00
Reallocated sectors count
0C
LSB
MSB
00
00
00
00
Power Cycle Count
A0
LSB
-
-
MSB
00
00
Uncorrectable sectors count when
read/write
A1
LSB
MSB
00
00
00
00
Number of valid spare blocks
A2
LSB
MSB
00
00
00
00
Number of Child pair
A3
LSB
MSB
00
00
00
00
Number of initial invalid blocks
A4
LSB
-
-
MSB
00
00
Total erase count
A5
LSB
-
-
MSB
00
00
Maximum erase count
A6
LSB
-
-
MSB
00
00
Minimum erase count
A7
LSB
-
-
MSB
00
00
Average erase count
C0
LSB
-
-
MSB
00
00
Power-off retract Count
C2
MSB
00
00
00
00
00
Controlled temperature
C3
LSB
-
-
MSB
00
00
Hardware ECC recovered
C4
LSB
-
-
MSB
00
00
Reallocation event count
C6
LSB
-
-
MSB
00
00
Reserved
C7
LSB
MSB
00
00
00
00
Ultra DMA CRC Error Count
F1
LSB
-
-
MSB
00
00
Total LBAs written (each write unit
= 32MB)
F2
LSB
-
-
MSB
00
00
Total LBAs read (each read unit =
32MB)
the commands executed by the device.
X=the content of the byte is vendor specific and may be fixed or variable.
R=the content of the byte is reserved and shall be zero.
* 4 Byte value : [MSB] [2] [1] [LSB]