MAX6965AEE - Maxim Integrated Products, Inc.

MAX6965

9-Output LED Driver with Intensity Control

and Hot-Insertion Protection

________________________________________________________________ Maxim Integrated Products 1

For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

General Description

The MAX6965 I2C™-compatible serial interfaced periph-

eral provides microprocessors with nine additional out-

put ports. Each output is an open-drain current-sinking

output rated to 50mA at 7V. All outputs are capable of

driving LEDs, or providing logic outputs with external

resistive pullup up to 7V.

Eight-bit PWM current control is also integrated. Four of

the bits are global control and apply to all LED outputs

to provide coarse adjustment of current from fully off to

fully on with 14 intensity steps. Additionally each output

then has an individual 4-bit control, which further

divides the globally set current into 16 more steps.

Alternatively, the current control can be configured as a

single 8-bit control that sets all outputs at once.

Each output has independent blink timing with two blink

phases. LEDs can be individually set to be either on or off

during either blink phase, or to ignore the blink control.

The blink period is controlled by an external clock (up to

1kHz) on BLINK or by a register. The BLINK input can also

be used as a logic control to turn the LEDs on and off, or

as a general-purpose input (GPI).

The MAX6965 supports hot insertion. The SDA, SCL,

RST, BLINK, and the slave address input AD0 remain

high impedance in power-down (V+ = 0V) with up to 6V

asserted upon them. The output ports remain high

impedance with up to 8V asserted upon them.

The MAX6965 is controlled through a 2-wire I2C serial

interface, and can be configured to one of four I2C

addresses.

Applications

LCD Backlights

LED Status Indication

Keypad Backlights

RGB LED Drivers

Features

♦400kbps, 2-Wire Serial Interface, 5.5V Tolerant

♦2V to 3.6V Operation

♦Overall 8-Bit PWM LED Intensity Control

Global 16-Step Intensity Control

Plus Individual 16-Step Intensity Controls

♦Two-Phase LED Blinking

♦High Port Output Current—Each Port 50mA (max)

♦RST Input Clears Serial Interface and Restores

Power-Up Default State

♦Supports Hot Insertion

♦Outputs are 7V-Rated Open Drain

♦Low Standby Current (1.2µA (typ), 3.3µA (max))

♦Tiny 3mm x 3mm, Thin QFN Package

♦-40°C to +125°C Temperature Range

MAX6965

V+

3.3V

µC

SDA

SCL

SDA

I/O

AD0

SCL

RELAY

GND

0.047µF

RST

BLINK

RELAY

Typical Application Circuit

19-3058; Rev 3; 3/05

Ordering Information

PART TEMP

RANGE

PIN-

PACKAGE

TOP

MARK

PKG

CODE

MAX6965ATE

-40°C to

+125°C

16 Thin QFN

3mm x 3mm

x 0.8mm

AAW

T1633-4

MAX6965AEE

-40°C to 16 QSOP ——

Pin Configurations appear at end of data sheet.

Purchase of I2C components of Maxim Integrated Products, Inc.,

or one of its sublicensed Associated Companies, conveys a

license under the Philips I2C Patent Rights to use these compo-

nents in an I2C system, provided that the system conforms to the

I2C Standard Specification as defined by Philips.

MAX6965

9-Output LED Driver with Intensity Control

and Hot-Insertion Protection

2_______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

Voltage (with respect to GND)

V+ .............................................................................-0.3V to +4V

SCL, SDA, AD0, BLINK, RST ...................................-0.3V to +6V

O0–O8 ......................................................................-0.3V to +8V

DC Current on O0 to O8 .....................................................55mA

DC Current on SDA.............................................................10mA

Maximum GND Current ....................................................190mA

Continuous Power Dissipation (TA= +70°C)

16-Pin QSOP (derate 8.3mW/°C over +70°C)..............666mW

16-Pin QFN (derate 14.7mW/°C over +70°C) ............1176mW

Operating Temperature Range (TMIN to TMAX)...-40°C to +125°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

ELECTRICAL CHARACTERISTICS

(Typical Operating Circuit, V+ = 2V to 3.6V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.)

(Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

Operating Supply Voltage V+

2.0 3.6

Output Load External Supply

Voltage VEXT 07V

TA = +25°C

1.2 2.3

TA = -40°C to +85°C 2.6

Standby Current

(Interface Idle, PWM Disabled)

I+

S C L and S D A at V + ; other

d i g i tal i np uts at V + or GN D ;

P WM i ntensi ty contr ol d i sab l ed

TA = TMIN to TMAX

3.3

µA

TA = +25°C 7

12.1

TA = -40°C to +85°C 13.3

Supply Current

(Interface Idle, PWM Enabled) I+

S C L and S D A at V + ; other

d i g i tal i np uts at V + or GN D ;

P WM i ntensi ty contr ol enab l ed

TA = TMIN to TMAX

14.4

µA

TA = +25°C 40 76

TA = -40°C to +85°C

Supply Current

(Interface Running, PWM

Disabled)

I+

fSCL = 400kHz; other digital

inputs at V+ or GND; PWM

intensity control disabled TA = TMIN to TMAX 80

µA

TA = +25°C 51

110

TA = -40°C to +85°C 117

Supply Current

(Interface Running, PWM

Enabled)

I+

fSCL = 400kHz; other digital

inputs at V+ or GND; PWM

intensity control enabled TA = TMIN to TMAX

122

µA

Input High Voltage

SDA, SCL, AD0, BLINK, RST VIH 0.7 x

V+

Input Low Voltage

SDA, SCL, AD0, BLINK, RST VIL 0.3 x

V+

Input Leakage Current

SDA, SCL, AD0, BLINK, RST

IIH, IIL

Input = GND or V+

-0.2 +0.2

µA

Input Capacitance

SDA, SCL, AD0, BLINK, RST 8pF

MAX6965

9-Output LED Driver with Intensity Control

and Hot-Insertion Protection

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(Typical Operating Circuit, V+ = 2V to 3.6V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at V+ = 3.3V, TA= + 25°C.)

(Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TA = +25°C

0.15 0.25

TA = -40°C to +85°C 0.29

V+ = 2V, ISINK = 20mA

TA = TMIN to TMAX

0.31

TA = +25°C

0.13 0.22

TA = -40°C to +85°C 0.25

V+ = 2.5V, ISINK = 20mA

TA = TMIN to TMAX

0.27

TA = +25°C

0.12 0.22

TA = -40°C to +85°C 0.23

Output Low Voltage

O0–O8 VOL

V+ = 3.3V, ISINK = 20mA

TA = TMIN to TMAX

0.25

Output Low-Voltage SDA

VOLSDA

ISINK = 6mA

0.4

PWM Clock Frequency fPWM 32

kHz

TIMING CHARACTERISTICS

(Typical Operating Circuit, V+ = 2V to 3.6V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.)

(Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

Serial Clock Frequency fSCL

400 kHz

Bus Free Time Between a STOP and a START

Condition tBUF

1.3

µs

Hold Time, Repeated START Condition

tHD

STA 0.6

µs

Repeated START Condition Setup Time

tSU

STA 0.6

µs

STOP Condition Setup Time

tSU

STO 0.6

µs

Data Hold Time

tHD

DAT

(Note 2)

0.9

µs

Data Setup Time

tSU

DAT 180

SCL Clock Low Period tLOW

1.3

µs

SCL Clock High Period tHIGH

0.7

µs

Rise Time of Both SDA and SCL Signals, Receiving

tR(Notes 3, 4) 20 +

0.1Cb300

Fall Time of Both SDA and SCL Signals, Receiving tF(Notes 3, 4) 20 +

0.1Cb300

Fall Time of SDA Transmitting tF.TX (Notes 3, 5) 20 +

0.1Cb250

Pulse Width of Spike Suppressed tSP (Note 6) 50 ns

Capacitive Load for Each Bus Line Cb(Note 3)

400

MAX6965

9-Output LED Driver with Intensity Control

and Hot-Insertion Protection

4_______________________________________________________________________________________

PORT OUTPUT LOW VOLTAGE WITH 50mA

LOAD CURRENT vs. TEMPERATURE

PORT OUTPUT LOW VOLTAGE VOL (V)

0.1

0.2

0.3

0.4

0.5

0.6

MAX6965 toc04

TEMPERATURE (°C)

1109565 80-10 5 20 35 50-25-40 125

V+ = 3.6V

V+ = 2.7V

V+ = 2V

PORT OUTPUT LOW VOLTAGE WITH 20mA

LOAD CURRENT vs. TEMPERATURE

MAX6965 toc05

TEMPERATURE (°C)

PORT OUTPUT LOW VOLTAGE VOL (V)

1109580655035205-10-25

0.1

0.2

0.3

0.4

0.5

0.6

-40 125

ALL OUTPUTS LOADED

V+ = 3.6V

V+ = 2.7V

V+ = 2V

PWM CLOCK FREQUENCY

vs. TEMPERATURE

MAX6965 toc06

TEMPERATURE (°C)

PWM CLOCK FREQUENCY

1109580655035205-10-25

0.925

0.950

0.975

1.000

1.025

1.050

0.900

-40 125

V+ = 3.6V

V+ = 2V

V+ = 2.7V

NORMALIZED TO V+ = 3.3V, TA = +25°C

STANDBY CURRENT vs. TEMPERATURE

MAX6965 toc01

TEMPERATURE (°C)

STANDBY CURRENT (µA)

1109565 80-10 520 35 50-25

-40 125

V+ = 3.6V

PWM ENABLED

V+ = 2.7V

PWM ENABLED

V+ = 2V

PWM DISABLED

V+ = 2.7V

PWM DISABLED

V+ = 3.6V

PWM

DISABLED

V+ = 2V

PWM ENABLED

SUPPLY CURRENT vs. TEMPERATURE

(PWM DISABLED; fSCL = 400kHz)

MAX6965 toc02

TEMPERATURE (°C)

SUPPLY CURRENT (µA)

1109565 80-10 5 20 35 50-25

-40 125

V+ = 3.6V

V+ = 2.7V

V+ = 2V

SUPPLY CURRENT vs. TEMPERATURE

(PWM ENABLED; fSCL = 400kHz)

MAX6965 toc03

TEMPERATURE (°C)

SUPPLY CURRENT (µA)

1109565 80-10 5 20 35 50-25-40 125

V+ = 3.6V

V+ = 2.7V

V+ = 2V

__________________________________________Typical Operating Characteristics

(TA = +25°C, unless otherwise noted.)

TIMING CHARACTERISTICS (continued)

(Typical Operating Circuit, V+ = 2V to 3.6V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.)

(Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

RST Pulse Width tW1µs

Output Data Valid tDV Figure 10 5 µs

Note 1: All parameters tested at TA= +25°C. Specifications over temperature are guaranteed by design.

Note 2: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge

the undefined region of SCL’s falling edge.

Note 3: Guaranteed by design.

Note 4: Cb= total capacitance of one bus line in pF. tRand tFmeasured between 0.3 x VDD and 0.7 x VDD.

Note 5: ISINK ≤6mA. Cb= total capacitance of one bus line in pF. tRand tFmeasured between 0.3 x VDD and 0.7 x VDD.

Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.

MAX6965

9-Output LED Driver with Intensity Control

and Hot-Insertion Protection

_______________________________________________________________________________________ 5

SCOPE SHOT OF TWO OUTPUT PORTS

MAX6965 toc07

2ms/div

OUTPUT 1

2V/div

OUTPUT 2

2V/div

MASTER INTENSITY SET TO 1/15

OUTPUT 1 INDIVIDUAL INTENSITY

SET TO 1/16

OUTPUT 2 INDIVIDUAL INTENSITY

SET TO 15/16

SCOPE SHOT OF TWO OUTPUT PORTS

MAX6965 toc08

2ms/div

OUTPUT 1

2V/div

OUTPUT 2

2V/div

OUTPUT 1 INDIVIDUAL INTENSITY

SET TO 1/16

MASTER INTENSITY SET TO 14/15

OUTPUT 2 INDIVIDUAL INTENSITY

SET TO 14/15

SINK CURRENT vs. VOL

MAX6965 toc09

SINK CURRENT (mA)

VOL (V)

45403530252015105

0.05

0.10

0.15

0.20

0.25

0.30

0.35

050

V+ = 3.3V

V+ = 3.6V

V+ = 2V

V+ = 2.7V

ONLY ONE OUTPUT LOADED

Typical Operating Characteristics (continued)

(TA = +25°C, unless otherwise noted.)

QSOP QFN NAME FUNCTION

115BLINK Input Port. Configurable as blink control or general-purpose input.

216RST Reset Input. Active low clears the 2-wire interface and puts the device in same

condition as power-up reset.

31AD0 Address Input. Sets device slave address. Connect to either GND, V+, SCL, or

SDA to give 4 logic combinations. See Table 1.

4–7, 9–13 2–5, 7–11 O0–O8 Output Ports. O0–O8 are open-drain outputs rated at 7V, 50mA.

86GND Ground. Do not sink more than 190mA into the GND pin.

14 12 SCL I2C-Compatible Serial Clock Input

15 13 SDA I2C-Compatible Serial Data I/O

16 14 V+

Positive Supply Voltage. Bypass V+ to GND with a 0.047µF ceramic capacitor

—PAD

Exposed Pad

Exposed pad on packaged underside. Connect to GND.

Pin Description

MAX6965

Functional Overview

The MAX6965 is a general-purpose output (GPO)

peripheral that provides nine output ports, O0–O8, con-

trolled through an I2C-compatible serial interface. All out-

puts sink loads up to 50mA connected to external

supplies up to 7V, independent of the MAX6965’s supply

voltage. The MAX6965 is rated for a ground current of

190mA, allowing all nine outputs to sink 20mA at the

same time. Figure 1 shows the output structure of the

MAX6965. The outputs default to logic high (high imped-

ance unless external pullup resistors are used) on

power-up.

Output Control and LED Blinking

The blink phase 0 register sets the output logic levels of

the 8 outputs O0–O7 (Table 6). This register controls

the port outputs if the blink function is disabled. A dupli-

cate register, the Blink Phase 1 register, is also used if

the blink function is enabled (Table 7). In blink mode,

the outputs can be flipped between using the blink

phase 0 register, and the blink phase 1 register using

hardware control (the BLINK input) and/or software

control (the blink flip flag in the configuration register)

(Table 4).

The 9th output, O8, is controlled through 2 bits in the

Configuration register, which provide the same static or

blink control as the other eight outputs (Table 4).

The logic level of the BLINK input may be read back

through the blink status bit in the configuration register

(Table 4). The BLINK input, therefore, may be used as

a general-purpose logic input (GPI port) if the blink

function is not required.

PWM Intensity Control

The MAX6965 includes an internal oscillator, nominally

32kHz, to generate PWM timing for LED intensity con-

trol. PWM intensity control can be enabled on an out-

put-by-output basis, allowing the MAX6965 to provide

any mix of PWM LED drives and glitch-free logic out-

puts (Table 8). PWM can be disabled entirely, in which

case all outputs are static and the MAX6965 operating

current is lowest because the internal oscillator is

turned off.

PWM intensity control uses a 4-bit master control and 4

bits of individual control per output (Tables 11 and 12).

The 4-bit master control provides 16 levels of overall

intensity control, which applies to all PWM-enabled out-

puts. The master control sets the maximum pulse width

from 1/15 to 15/15 of the PWM time period. The individ-

ual settings comprise a 4-bit number, further reducing

the duty cycle to be from 1/16 to 15/16 of the time win-

dow set by the master control.

For applications requiring the same PWM setting for all

output ports, a single global PWM control can be used

instead of all the individual controls to simplify the con-

trol software and provide 240 steps of intensity control

(Tables 8 and 11).

9-Output LED Driver with Intensity Control

and Hot-Insertion Protection

6_______________________________________________________________________________________

Figure 1. Simplified Schematic of I/O Ports

DATA FROM

SHIFT REGISTER

WRITE PULSE

OUTPUT

PORT

I/O PIN

GND

OUTPUT PORT

Figure 2. 2-Wire Serial Interface Timing Details

SCL

SDA

tRtF

tBUF

START

CONDITION

STOP

CONDITION

REPEATED START CONDITION

START CONDITION

tSU,STO

tHD,STA

tSU,STA

tHD,DAT

tSU,DAT

tLOW

tHIGH

tHD,STA

User RAM

The MAX6965 includes a register byte, which is avail-

able as general-user RAM (Table 2). This byte is reset

to the value 0xFF on power-up and when the RST input

is taken low (Table 3).

Standby Mode

When the serial interface is idle and the PWM intensity

control is unused, the MAX6965 automatically enters

standby mode. If the PWM intensity control is used, the

operating current is slightly higher because the internal

PWM oscillator is running. When the serial interface is

active, the operating current also increases because

the MAX6965, like all I2C slaves, has to monitor every

transmission.

Serial Interface

Serial Addressing

The MAX6965 operates as a slave that sends and

receives data through an I2C-compatible 2-wire inter-

face. The interface uses a serial data line (SDA) and a

serial clock line (SCL) to achieve bidirectional commu-

nication between master(s) and slave(s). A master (typ-

ically a microcontroller) initiates all data transfers to and

from the MAX6965 and generates the SCL clock that

synchronizes the data transfer (Figure 2).

The MAX6965 SDA line operates as both an input and

an open-drain output. A pullup resistor, typically 4.7kΩ,

is required on SDA. The MAX6965 SCL line operates

only as an input. A pullup resistor, typically 4.7kΩ, is

required on SCL if there are multiple masters on the 2-

wire interface, or if the master in a single-master system

has an open-drain SCL output.

Each transmission consists of a START condition

(Figure 3) sent by a master, followed by the MAX6965

7-bit slave address plus R/Wbit, a register address

byte, one or more data bytes, and finally a STOP condi-

tion (Figure 3).

Start and Stop Conditions

Both SCL and SDA remain high when the interface is

not busy. A master signals the beginning of a transmis-

sion with a START (S) condition by transitioning SDA

from high to low while SCL is high. When the master

has finished communicating with the slave, it issues a

STOP (P) condition by transitioning SDA from low to

high while SCL is high. The bus is then free for another

transmission (Figure 3).

Bit Transfer

One data bit is transferred during each clock pulse.

The data on SDA must remain stable while SCL is high

(Figure 4).

Acknowledge

The acknowledge bit is a clocked 9th bit that the recipi-

ent uses to handshake receipt of each byte of data

(Figure 5). Thus, each byte transferred effectively

requires 9 bits. The master generates the 9th clock

pulse, and the recipient pulls down SDA during the

acknowledge clock pulse so the SDA line is stable low

MAX6965

9-Output LED Driver with Intensity Control

and Hot-Insertion Protection

_______________________________________________________________________________________ 7

Figure 3. Start and Stop Conditions

SDA

SCL

START

CONDITION

STOP

CONDITION

Figure 4. Bit Transfer

SDA

SCL

DATA LINE STABLE;

DATA VALID

CHANGE OF DATA

ALLOWED

Figure 5. Acknowledge

SCL

SDA BY

TRANSMITTER

CLOCK PULSE

FOR ACKNOWLEDGE

START

CONDITION

SDA BY

RECEIVER

12 89

Figure 6. Slave Address

SDA

SCL

MSB LSB

ACK00A6 0 0A2 R/W

MAX6965

during the high period of the clock pulse. When the

master is transmitting to the MAX6965, the device gen-

erates the acknowledge bit because the MAX6965 is

the recipient. When the MAX6965 is transmitting to the

master, the master generates the acknowledge bit

because the master is the recipient.

Slave Address

The MAX6965 has a 7-bit long slave address (Figure 6).

The eighth bit following the 7-bit slave address is the

R/Wbit. The R/Wbit is low for a write command, high

for a read command.

The second (A5), third (A4), fourth (A3), sixth (A1), and

last (A0) bits of the MAX6965 slave address are always

1, 0, 0, 0, and 0. Slave address bits A6 and A2 are

selected by the address input AD0. AD0 can be con-

nected to GND, V+, SDA, or SCL. The MAX6965 has

four possible slave addresses (Table 1), and therefore

a maximum of four MAX6965 devices can be controlled

independently from the same interface.

Message Format for Writing the MAX6965

A write to the MAX6965 comprises the transmission of

the MAX6965’s slave address with the R/Wbit set to

zero, followed by at least 1 byte of information. The first

byte of information is the command byte. The command

byte determines which register of the MAX6965 is to be

written to by the next byte, if received (Table 2). If a

STOP condition is detected after the command byte is

received, then the MAX6965 takes no further action

beyond storing the command byte.

Any bytes received after the command byte are data

bytes. The first data byte goes into the internal register of

the MAX6965 selected by the command byte (Figure 8).

If multiple data bytes are transmitted before a STOP con-

dition is detected, these bytes are generally stored in

subsequent MAX6965 internal registers because the

command byte address autoincrements (Table 2). A

diagram of a write to the output ports registers (blink

phase 0 register or blink phase 1 register) is given in

Figure 10.

9-Output LED Driver with Intensity Control

and Hot-Insertion Protection

8_______________________________________________________________________________________

Table 1. MAX6965 I2C Slave Address Map

DEVICE ADDRESS

PIN AD0 A6 A5 A4 A3 A2 A1 A0

SCL 1 1 00000

SDA 1 1 00100

GND 0 1 00000

V+ 0 1 00100

Table 2. Register Address Map

(hex)

AUTOINCREMENT

ADDRESS

Blink phase 0 outputs 0x01 0x01 (no change)

User RAM 0x03 0x03 (no change)

Blink phase 1 outputs 0x09 0x09 (no change)

Master, O8 intensity 0x0E 0x0E (no change)

Configuration 0x0F 0x0F (no change)

Outputs intensity O1, O0 0x10 0x11

Outputs intensity O3, O2 0x11 0x12

Outputs intensity O5, O4 0x12 0x13

Outputs intensity O7, O6 0x13 0x10

Message Format for Reading

The MAX6965 is read using the MAX6965’s internally

stored command byte as an address pointer the same

way the stored command byte is used as an address

pointer for a write. The pointer autoincrements after

each data byte is read using the same rules as for a

write (Table 2). Thus, a read is initiated by first configur-

ing the MAX6965’s command byte by performing a

write (Figure 7). The master can now read n consecu-

tive bytes from the MAX6965 with the first data byte

being read from the register addressed by the initial-

ized command byte. When performing read-after-write

verification, remember to reset the command byte’s

address because the stored command byte address

has been autoincremented after the write (Table 2).

MAX6965

9-Output LED Driver with Intensity Control

and Hot-Insertion Protection

_______________________________________________________________________________________ 9

Figure 8. Command and Single Data Byte Received

SAAAP0SLAVE ADDRESS COMMAND BYTE DATA BYTE

BYTE

AUTOINCREMENT MEMORY ADDRESS

D15 D14 D13 D12 D11 D10 D9 D8 D1 D0D3 D2D5 D4D7 D6

ACKNOWLEDGE FROM MAX6965 ACKNOWLEDGE FROM MAX6965

ACKNOWLEDGE FROM MAX6965

HOW COMMAND BYTE AND DATA BYTE MAP INTO

MAX6965's REGISTERS

R/W

Figure 9. n Data Bytes Received

SAAAP0SLAVE ADDRESS COMMAND BYTE DATA BYTE

BYTES

D15 D14 D13 D12 D11 D10 D9 D8 D1 D0D3 D2D5 D4D7 D6

ACKNOWLEDGE FROM MAX6965 ACKNOWLEDGE FROM MAX6965

ACKNOWLEDGE FROM MAX6965

HOW COMMAND BYTE AND DATA BYTE MAP INTO

MAX6965's REGISTERS

R/W

AUTOINCREMENT MEMORY ADDRESS

Figure 7. Command Byte Received

SAA

0SLAVE ADDRESS COMMAND BYTE

ACKNOWLEDGE FROM MAX6965

D15 D14 D13 D12 D11 D10 D9 D8

COMMAND BYTE IS STORED ON RECEIPT OF

STOP CONDITION

ACKNOWLEDGE FROM MAX6965

R/W

Figure 10. Write Timing Diagram

SLAVE ADDRESS

123456789

SA6A5 A4A3A2A1A0 0 A 0 000000

COMMAND BYTE

1A A AP

START CONDITION ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM SLAVE STOP

CONDITION

O7–O0 DATA1 VALID DATA2 VALID

tDV tDV

SCL

SDA

WRITE TO OUTPUT PORTS REGISTERS (BLINK PHASE 0 REGISTERS/BLINK PHASE 1 REGISTERS)

R/W

MSB LSBDATA1 MSB LSBDATA2

MAX6965

9-Output LED Driver with Intensity Control

and Hot-Insertion Protection

10 ______________________________________________________________________________________

Operation with Multiple Masters

If the MAX6965 is operated on a 2-wire interface with

multiple masters, a master reading the MAX6965 should

use a repeated start between the write, which sets the

MAX6965’s address pointer, and the read(s) that takes

the data from the location(s) (Table 2). This is because it

is possible for master 2 to take over the bus after master

1 has set up the MAX6965’s address pointer but before

master 1 has read the data. If master 2 subsequently

changes the MAX6965’s address pointer, then master

1’s delayed read can be from an unexpected location.

Command Address Autoincrementing

The command address stored in the MAX6965 circu-

lates around grouped register functions after each data

byte is written or read (Table 2).

Device Reset

The reset input RST is an active-low input. When taken

low, RST clears any transaction to or from the MAX6965

on the serial interface and configures the internal regis-

ters to the same state as a power-up reset (Table 3).

The MAX6965 then waits for a START condition on the

serial interface.

Detailed Description

Initial Power-Up

On power-up, and whenever the RST input is pulled

low, all control registers are reset and the MAX6965

enters standby mode (Table 3). Power-up status makes

all outputs logic high (high impedance if external pullup

resistors are not fitted) and disables both the PWM

oscillator and blink functionality. The RST input can be

used as a hardware shutdown input, which effectively

turns off any LED (or other) loads and puts the device

into its lowest power condition.

Configuration Register

The configuration register is used to configure the PWM

intensity mode and blink behavior, operate the O8 out-

put, and read back the BLINK input logic level (Table 4).

Blink Mode

In blink mode, the outputs can be flipped between

using either the blink phase 0 register or the blink

phase 1 register. Flip control is both hardware (the

BLINK input) and software control (the blink flip flag B

in the configuration register) (Table 4).

The blink function can be used for LED effects by pro-

gramming different display patterns in the two sets of

output port registers, and using the software or hard-

ware controls to flip between the patterns.

If the blink phase 1 register is written with 0xFF, then

the BLINK input can be used as a hardware disable to,

for example, instantly turn off an LED pattern pro-

grammed into the blink phase 0 register. This tech-

nique can be further extended by driving the BLINK

input with a PWM signal to modulate the LED current to

provide fading effects.

The blink mode is enabled by setting the blink enable

flag E in the configuration register (Table 4). When blink

mode is enabled, the state of the blink flip flag and

BLINK input are EXOR’ed to set the phase, and the out-

puts are set by either the blink phase 0 registers or the

blink phase 1 registers (Figure 11, Table 5).

The blink mode is disabled by clearing the blink enable

flag E in the configuration register (Table 4). When blink

mode is disabled, the state of the blink flip flag is

ignored, and the blink phase 0 registers alone control

the outputs.

The logic status of BLINK is made available as the read-

only blink status flag blink in the configuration register

(Table 4). This flag allows BLINK to be used as an extra

general-purpose input (GPI) in applications not using the

blink function. When BLINK is going to be used as a GPI,

blink mode should be disabled by clearing the blink

enable flag E in the configuration register (Table 4).

Blink Phase Register

When the blink function is disabled, the blink phase

0 register sets the logic levels of the eight outputs

(O0 through O7) (Table 6). A duplicate register called

the blink phase 1 register is also used if the blink func-

tion is enabled (Table 7). A logic high sets the appro-

priate output high impedance, while a logic low makes

the port go low.

Reading a blink phase register reads the value stored

in the register, not the actual port condition. The port

output itself may or may not be at a valid logic level,

depending on the external load connected.

The 9th output, O8, is controlled through 2 bits in the

configuration register, which provide the same static or

blink control as the other eight output ports.

MAX6965

9-Output LED Driver with Intensity Control

and Hot-Insertion Protection

______________________________________________________________________________________ 11

Table 3. Power-Up Configuration

ADDRESS

CODE

(HEX)

D7 D6 D5 D4 D3 D2 D1

Blink phase 0 outputs High-impedance outputs 0x01

1111111

User RAM 0xFF 0x03

1111111

Blink phase 1 outputs High-impedance outputs 0x09

1111111

Master, O8 intensity PWM oscillator is disabled;

O8 is static logic output 0x0E

0000111

Configuration

O8 is high-impedance output;

blink is disabled;

global intensity is enabled

0x0F

0011010

Outputs intensity O1, O0

O1, O0 are static logic outputs

0x10

1111111

Outputs Intensity O3, O2

O3, O2 are static logic outputs

0x11

1111111

Outputs intensity O5, O4

O5, O4 are static logic outputs

0x12

1111111

Outputs intensity O7, O6

O7, O6 are static logic outputs

0x13

1111111

Table 4. Configuration Register

ADDRESS

CODE

(HEX) D7 D6 D5 D4 D3 D2 D1 D0

CONFIGURATION

R/W

—

BLINK

STATUS

OUTPUT

—

GLOBAL

INTENSITY

BLINK FLIP

BLINK

ENABLE

Write device configuration

Read-back device configuration

BLINK O1

O0 0GBE

Disable blink

—

XXXXXXX0

Enable blink

—

XXXXXXX1

—

XXXXXX01

Flip blink register (see text)

—

XXXXXX11

Disable global intensity control—intensity is

set by registers 0x10–0x13 for ports O0

through O7 when configured as outputs,

and by D3–D0 of register 0x0E for output O8

—

XXXXX0XX

Enable global intensity control—intensity

for all ports configured as outputs is set by

D3–D0 of register 0x0E

—

0x0F

XXXXX1XX

X = Don’t care.

MAX6965

9-Output LED Driver with Intensity Control

and Hot-Insertion Protection

12 ______________________________________________________________________________________

Table 4. Configuration Register (continued)

ADDRESS

CODE

(HEX) D7 D6 D5 D4 D3 D2 D1 D0

CONFIGURATION

R/W

—

BLINK

STATUS

OUTPUT

—

GLOBAL

INTENSITY

BLINK FLIP

BLINK

ENABLE

Write device configuration

Read-back device configuration

BLINK O1

O0 0GBE

O8 output is low (blink is disabled)

—

XXX00XX0

O8 output is high impedance

(blink is disabled)

—

XXX10XX0

O 8 outp ut i s l ow d ur i ng b l i nk p hase 0

—

0x0F

XXX00XX1

O8 output is high impedance during

blink phase 0

—

XXX10XX1

O 8 outp ut i s l ow d ur i ng b l i nk p hase 1

—

XX0X0XX1

O8 output is high impedance during

blink phase 1

—

XX1X0XX1

Read-back BLINK input pin status;

input is low

X0XXXXXX

Read-back BLINK input pin status;

input is high

X1XXXXXX

Table 5. Blink Controls

BLINK ENABLE

FLAG

BLINK FLIP

FLAG

BLINK INPUT

BLINK FLIP FLAG

EXOR

BLINK INPUT PIN

BLINK

FUNCTION

OUTPUT REGISTERS

USED

0XXXDisabled Blink phase 0

00 0 Blink phase 0

01 1 Blink phase 1

10 1 Blink phase 1

11 0

Enabled

Blink phase 0

X = Don’t care.

MAX6965

9-Output LED Driver with Intensity Control

and Hot-Insertion Protection

______________________________________________________________________________________ 13

Table 6. Blink Phase 0 Register

R/W

ADDRESS

CODE

(hex) D7 D6 D5 D4 D3 D2 D1 D0

Write outputs phase 0

Read-back outputs phase 0

0x01

OP7 OP6 OP5 OP4 OP3 OP2 OP1

OP0

Table 7. Blink Phase 1 Register

R/W

ADDRESS

CODE

(hex) D7 D6 D5 D4 D3 D2 D1 D0

Write outputs phase 1

Read-back outputs phase 1

0x09

OP7 OP6 OP5 OP4 OP3 OP2 OP1

OP0

Table 8. PWM Application Scenarios

APPLICATION RECOMMENDED CONFIGURATION

All outputs static without PWM

Set the master, O8 intensity register 0x0E to any value from 0x00 to 0x0F.

The global intensity G bit in the configuration register is don't care.

The output intensity registers 0x10 through 0x13 are don't care.

A mix of static and PWM outputs, with PWM

outputs using different PWM settings

Set the master, O8 intensity register 0x0E to any value from 0x10 to 0xFF.

Clear global intensity G bit to 0 in the configuration register to disable global intensity

control.

For the static outputs, set the output intensity value to 0xF.

For the PWM outputs, set the output intensity value in the range 0x0 to 0xE.

A mix of static and PWM outputs, with PWM

outputs all using the same PWM setting

As above. Global intensity control cannot be used with a mix of static and PWM

outputs, so write the individual intensity registers with the same PWM value.

All outputs PWM using the same PWM

setting

Set the master, O8 intensity register 0x0E to any value from 0x10 to 0xFF.

Set global intensity G bit to 1 in the configuration register to enable global intensity

control.

The master, O8 intensity register 0x0E is the only intensity register used.

The output intensity registers 0x10 through 0x13 are don't care.

MAX6965

9-Output LED Driver with Intensity Control

and Hot-Insertion Protection

14 ______________________________________________________________________________________

PWM Intensity Control

The MAX6965 includes an internal oscillator, nominally

32kHz, to generate PWM timing for LED intensity control

or other applications such as PWM trim DACs. PWM can

be disabled entirely for all the outputs. In this case, all

outputs are static and the MAX6965 operating current is

lowest because the internal PWM oscillator is turned off.

The MAX6965 can be configured to provide any combi-

nation of PWM outputs and glitch-free logic outputs.

Each PWM output has an individual 4-bit intensity con-

trol (Table 12). When all outputs are to be used with the

same PWM setting, the outputs can be controlled

together instead of using the global intensity control

(Table 11). Table 8 shows how to set up the MAX6965

to suit a particular application.

PWM Timing

The PWM control uses a 240-step PWM period, divided

into 15 master intensity timeslots. Each master intensity

timeslot is divided further into 16 PWM cycles (Figure 12).

The master intensity operates as a gate, allowing the indi-

vidual output settings to be enabled from 1 to 15 timeslots

per PWM period (Figures 13, 14, and 15) (Table 11).

Each output’s individual 4-bit intensity control only

operates during the number of timeslots gated by the

master intensity. The individual controls provide 16

intensity settings from 1/16 through 16/16 (Table 12).

Figures 16, 17, and 18 show examples of individual

intensity control settings. The highest value an individ-

ual or global setting can be set to is 16/16. This setting

forces the output to ignore the master control, and fol-

low the logic level set by the appropriate blink phase

put with no PWM.

Using PWM Intensity Controls with Blink Disabled

When blink is disabled (Table 5), the blink phase 0 regis-

ter specifies each output’s logic level during the PWM on-

time (Table 6). The effect of setting an output’s blink

phase 0 register bit to 0 or 1 is shown in Table 9. With its

output bit set to zero, an LED can be controlled with 16

intensity settings from 1/16th duty through fully on, but

cannot be turned fully off using the PWM intensity control.

With its output bit set to 1, an LED can be controlled with

16 intensity settings from fully off through 15/16th duty.

Using PWM Intensity Controls with Blink Enabled

When blink is enabled (Table 5), the blink phase 0 regis-

ter and blink phase 1 register specify each output’s logic

level during the PWM on-time during the respective blink

phases (Tables 6 and 7). The effect of setting an output’s

blink phase register bit to 0 or 1 is shown in Table 10.

LEDs can be flipped between either directly on and off,

or between a variety of high/low PWM intensities.

Figure 12. PWM Timing

ONE PWM PERIOD IS 240 CYCLES OF THE 32kHz PWM

OSCILLATOR. A PWM PERIOD CONTAINS 15 MASTER

INTENSITY TIMESLOTS

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 14 15 1 2

EACH MASTER INTENSITY

TIMESLOT CONTAINS 16

PWM CYCLES

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 15 16 12

Figure 11. BLINK Logic

BLINK ENABLE FLAG E

BLINK FLIP FLAG B

BLINK INPUT

BLINK PHASE

REGISTERS

MAX6965

9-Output LED Driver with Intensity Control

and Hot-Insertion Protection

______________________________________________________________________________________ 15

Global/O8 Intensity Control

The 4 bits used for output O8’s PWM individual intensity

setting also double as the global intensity control

(Table 11). Global intensity simplifies the PWM settings

when the application requires them all to be the same,

such as for backlight applications, by replacing the

nine individual settings with one setting. Global intensi-

ty is enabled with the global intensity flag G in the con-

figuration register (Table 4). When global PWM control

is used, the 4 bits of master intensity and 4 bits of O8

intensity effectively combine to provide an 8-bit, 240-

step intensity control applying to all outputs.

It is not possible to apply global PWM control to a sub-

set of the ports, and use the others as logic outputs. To

mix static logic outputs and PWM outputs, individual

PWM control must be selected (Table 8).

Applications Information

Hot Insertion

The RST input, BLINK input, and serial interface SDA,

SCL, AD0 remain high impedance with up to 6V assert-

ed on them when the MAX6965 is powered down (V+ =

0V). Output ports O0–O8 remain high impedance with

up to 8V asserted on them. The MAX6965 can therefore

be used in hot-swap applications.

Output Level Translation

The open-drain output architecture allows the ports to

level translate the outputs to higher or lower voltages

than the MAX6965 supply. An external pullup resistor

can be used on any output to convert the high-imped-

ance logic-high condition to a positive voltage level.

The resistor can be connected to any voltage up to 7V.

For interfacing CMOS inputs, a pullup resistor value of

220kΩis a good starting point. Use a lower resistance

to improve noise immunity, in applications where power

consumption is less critical, or where a faster rise time

is needed for a given capacitive load.

Driving LED Loads

When driving LEDs, a resistor in series with the LED

must be used to limit the LED current to no more than

50mA. Choose the resistor value according to the fol-

lowing formula:

RLED = (VSUPPLY - VLED - VOL) / ILED

where:

RLED is the resistance of the resistor in series with the

LED (Ω).

Figure 15. Master Set to 15/15

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 14 15 2 1

Figure 14. Master Set to 14/15

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 14 15 2 1

Figure 13. Master Set to 1/15

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 14 15 2 1

Figure 17. Individual (or Global) Set to 15/16

MASTER INTENSITY TIMESLOT

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

NEXT MASTER INTENSITY TIMESLOT

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Figure 16. Individual (or Global) Set to 1/16

MASTER INTENSITY TIMESLOT

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

NEXT MASTER INTENSITY TIMESLOT

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Figure 18. Individual (or Global) Set to 16/16

MASTER INTENSITY TIMESLOT CONTROL IS IGNORED

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

VSUPPLY is the supply voltage used to drive the LED (V).

VLED is the forward voltage of the LED (V).

VOL is the output low voltage of the MAX6964 when

sinking ILED (V).

ILED is the desired operating current of the LED (A).

For example, to operate a 2.2V red LED at 14mA from a

5V supply, RLED = (5 - 2.2 - 0.25) / 0.014 = 182Ω.

Driving Load Currents Higher than 50mA

The MAX6965 can be used to drive loads drawing more

than 50mA, like relays and high-current white LEDs, by

paralleling outputs. Use at least one output per 50mA of

load current; for example, a 6V 330mW relay draws

55mA and needs two paralleled outputs to drive it.

Ensure that the paralleled outputs chosen are controlled

by the same blink phase register, i.e., select outputs from

the O0 through O7 range. This way, the paralleled out-

puts are turned on and off together. Do not use output

O8 as part of a load-sharing design. O8 cannot be

switched at the same time as any of the other outputs

because it is controlled by a different register.

MAX6965

9-Output LED Driver with Intensity Control

and Hot-Insertion Protection

16 ______________________________________________________________________________________

Table 9. PWM Intensity Settings (Blink Disabled)

PWM DUTY CYCLE

OUTPUT BLINK PHASE 0

PWM DUTY CYCLE

OUTPUT BLINK PHASE 0

OUTPUT

(OR

GLOBAL)

INTENSITY

SETTING

LOW TIME HIGH TIME

LED BEHAVIOR WHEN

OUTPUT BLINK PHASE 0

(LED IS ON WHEN

OUTPUT IS LOW)

LOW TIME HIGH TIME

LED BEHAVIOR WHEN

OUTPUT BLINK PHASE 0

(LED IS ON WHEN

OUTPUT IS LOW)

0x0 1/16 15/16 Lowest PWM intensity 15/16 1/16 Highest PWM intensity

0x1 2/16 14/16 14/16 2/16

0x2 3/16 13/16 13/16 3/16

0x3 4/16 12/16 12/16 4/16

0x4 5/16 11/16 11/16 5/16

0x5 6/16 10/16 10/16 6/16

0x6 7/16 9/16 9/16 7/16

0x7 8/16 8/16 8/16 8/16

0x8 9/16 7/16 7/16 9/16

0x9 10/16 6/16 6/16 10/16

0xA 11/16 5/16 5/16 11/16

0xB 12/16 4/16 4/16 12/16

0xC 13/16 3/16 3/16 13/16

0xD 14/16 2/16

 Increasing PWM intensity

2/16 14/16

Increasing PWM intensity 

0xE 15/16 1/16 Highest PWM intensity 1/16 15/16 Lowest PWM intensity

0xF

Static low Static low

Full intensity, no PWM

(LED on continuously)

Static high

impedance

Static high

impedance

LED off continuously

Figure 19. Diode-Protected Switching Inductive Load

MAX6965

V+

2V TO 3.6V

µC

SDA

SCL

BLINK

SDA

I/O

AD0

SCL

I/O

GND

0.047µF

RST

BAS16

MAX6965

9-Output LED Driver with Intensity Control

and Hot-Insertion Protection

______________________________________________________________________________________ 17

Table 10. PWM Intensity Settings (Blink Enabled)

EXAMPLES OF LED BLINK BEHAVIOR

(LED IS ON WHEN OUTPUT IS LOW)

PWM DUTY

CYCLE OUTPUT

BLINK PHASE X

BIT = 0

PWM DUTY

CYCLE OUTPUT

BLINK PHASE X

BIT = 1

OUTPUT

(OR

GLOBAL)

INTENSITY

SETTING

LOW

TIME

HIGH

TIME

LOW

TIME

HIGH

TIME

B L I N K PH A SE 0 R EG IST ER B IT = 0

B L I N K PH A SE 1 R EG IST ER B IT = 1

B L I N K PH A SE 0 R EG IST ER B IT = 1

B L I N K PH A SE 1 R EG IST ER B IT = 0

0x0 1/16

15/16

15/16 1/16

0x1 2/16

14/16

14/16 2/16

0x2 3/16

13/16

13/16 3/16

0x3 4/16

12/16

12/16 4/16

0x4 5/16

11/16

11/16 5/16

0x5 6/16

10/16

10/16 6/16

0x6 7/16

9/16

9/16 7/16

P hase 0: LE D on at l ow i ntensi ty

P hase 1: LE D on at hi g h i ntensi ty

P hase 0: LE D on at hi g h i ntensi ty

P hase 1: LE D on at l ow i ntensi ty

0x7 8/16

8/16

8/16 8/16 Output is half intensity during both blink phases

0x8 9/16

7/16

7/16 9/16

0x9

10/16 6/16

6/16 10/16

0xA

11/16 5/16

5/16 11/16

0xB

12/16 4/16

4/16 12/16

0xC

13/16 3/16

3/16 13/16

0xD

14/16 2/16

2/16 14/16

0xE

15/16 1/16

1/16 15/16

P hase 0: LE D on at hi g h i ntensi ty

P hase 1: LE D on at l ow i ntensi ty

P hase 0: LE D on at l ow i ntensi ty

P hase 1: LE D on at hi g h i ntensi ty

0xF Static

low

Static

low

Static high

impedance

Static high

impedance

Phase 0: LED on continuously

Phase 1: LED off continuously

Phase 0: LED off continuously

Phase 1: LED on continuously

The MAX6965 must be protected from the negative

voltage transient generated when switching off induc-

tive loads, such as relays, by connecting a reverse-

biased diode across the inductive load (Figure 19). The

peak current through the diode is the inductive load’s

operating current.

Power-Supply Considerations

The MAX6965 operates with a power-supply voltage of

2V to 3.6V. Bypass the power supply to GND with at

least 0.047µF as close to the device as possible.

For the QFN version, connect to the underside exposed

pad to GND.

MAX6965

9-Output LED Driver with Intensity Control

and Hot-Insertion Protection

18 ______________________________________________________________________________________

Table 11. Master, O8 Intensity Register

ADDRESS

CODE

(HEX) D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB MSB

LSB

MASTER AND GLOBAL INTENSITY

R/W

MASTER INTENSITY O8 INTENSITY

Write master and global intensity

Read-back master and global intensity

1M3

M1 M0 G3 G2 G1

Master intensity duty cycle is 0/15 (off);

internal oscillator is disabled;

all outputs will be static with no PWM

—

0000————

Master intensity duty cycle is 1/15

—

0001————

Master intensity duty cycle is 2/15

—

0010————

Master intensity duty cycle is 3/15

—

0011————

—

————————

Master intensity duty cycle is 13/15

—

1101————

Master intensity duty cycle is 14/15

—

1110————

Master intensity duty cycle is 15/15 (full)

—

1111————

O8 intensity duty cycle is 1/16

—

———— 0 0 0 0

O8 intensity duty cycle is 2/16

—

———— 0 0 0 1

O8 intensity duty cycle is 3/16

—

———— 0 0 1 0

—

————————

O8 intensity duty cycle is 14/16

—

———— 1 1 0 1

O8 intensity duty cycle is 15/16

—

———— 1 1 1 0

O8 intensity duty cycle is 16/16

(static output, no PWM)

—

0X0E

———— 1 1 1 1

MAX6965

9-Output LED Driver with Intensity Control

and Hot-Insertion Protection

______________________________________________________________________________________ 19

Table 12. Output Intensity Registers

ADDRESS

CODE

(HEX) D7 D6 D5 D4 D3 D2 D1

MSB LSB MSB

LSB

OUTPUTS O1, O0 INTENSITY

R/W

OUTPUT O1 INTENSITY OUTPUT O0 INTENSITY

Write output O1, O0 intensity

Read-back output O1, O0 intensity

1O1I3 O1I2 O1I1 O1I0 O0I3 O0I2 O0I1

O0I0

Output O1 intensity duty cycle is 1/16

—

0000————

Output O1 intensity duty cycle is 2/16

—

0001————

Output O1 intensity duty cycle is 3/16

—

0010————

—

————————

Output O1 intensity duty cycle is 14/16

—

1101————

Output O1 intensity duty cycle is 15/16

—

1110————

Output O1 intensity duty cycle is 16/16

(static logic level, no PWM)

—

1111————

Output O0 intensity duty cycle is 1/16

—

———— 0 0 0 0

Output O0 intensity duty cycle is 2/16

—

———— 0 0 0 1

Output O0 intensity duty cycle is 3/16

—

———— 0 0 1 0

—

————————

Output O0 intensity duty cycle is 14/16

—

———— 1 1 0 1

Output O0 intensity duty cycle is 15/16

—

———— 1 1 1 0

Output O0 intensity duty cycle is 16/16

(static logic level, no PWM)

—

0X10

———— 1 1 1 1

MSB LSB MSB

LSB

OUTPUTS O3, O2 INTENSITY OUTPUT O3 INTENSITY OUTPUT O2 INTENSITY

Write output O3, O2 intensity

Read-back output O3, O2 intensity

0x11

O3I3 O3I2 O3I1 O3I0 O2I3 O2I2 O2I1

O2I0

MSB LSB MSB

LSB

OUTPUTS O5, O4 INTENSITY OUTPUT O5 INTENSITY OUTPUT O4 INTENSITY

Write output O5, O4 intensity

Read-back output O5, O4 intensity

0x12

O5I3 O5I2 O5I1 O5I0 O4I3 O4I2 O4I1

O4I0

MSB LSB MSB

LSB

OUTPUTS O7, O6 INTENSITY OUTPUT O7 INTENSITY OUTPUT O6 INTENSITY

Write output O7, O6 intensity

Read-back output O7, O6 intensity

0x13

O7I3 O7I2 O7I1 O7I0 O6I3 O6I2 O6I1

O6I0

OUTPUT O8 INTENSITY See master, O8 intensity register (Table 11).

MAX6965

9-Output LED Driver with Intensity Control

and Hot-Insertion Protection

20 ______________________________________________________________________________________

V+

SDA

SCL

08O0

ADO

RST

TOP VIEW

04GND

QSOP

MAX6965AEE

BLINK

Chip Information

TRANSISTOR COUNT: 17,611

PROCESS: BiCMOS

11 10 9

1234

GND

SCL

V+

BLINK

RST

SDA

AD0

TOP VIEW

MAX6965ATE

THIN QFN

Pin Configurations

MAX6965

9-Output LED Driver with Intensity Control

and Hot-Insertion Protection

______________________________________________________________________________________ 21

QSOP.EPS

21-0055

PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to www.maxim-ic.com/packages.)

MAX6965

9-Output LED Driver with Intensity Control

and Hot-Insertion Protection

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to www.maxim-ic.com/packages.)

12x16L QFN THIN.EPS

0.10 C0.08 C

0.10 M C A B

D/2

E/2

E2/2

(ND - 1) X e

(NE - 1) X e

D2/2

21-0136

PACKAGE OUTLINE

12, 16L, THIN QFN, 3x3x0.8mm

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

EXPOSED PAD VARIATIONS

1.10

T1633-1 0.95

CODES

PKG.

T1233-1

MIN.

0.95

NOM.

1.10

1.25

1.10

0.95

1.25

NOM.

1.10

MAX.

1.25

MIN.

0.95

MAX.

1.25

0.25

0.20 REF

0.02

0.05

0.45

2.90

0.20

2.90

0.70

0.50 BSC.

0.55

3.00

0.65

3.10

0.25

3.00

0.75

0.30

3.10

0.80

0.20 REF

0.25 -

0.02

0.05

0.50 BSC.

0.30

2.90

0.40

3.00

0.20

2.90

0.70

0.25

3.00

0.75

3.10

0.50

0.80

3.10

0.30

PKG

REF. MIN.

12L 3x3

NOM. MAX. NOM.

16L 3x3

MIN. MAX.

0.35 x 45∞

PIN ID JEDEC

WEED-1

0.35 x 45∞WEED-2

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

3. N IS THE TOTAL NUMBER OF TERMINALS.

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO

JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED

WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR

MARKED FEATURE.

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm

FROM TERMINAL TIP.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.

NOTES:

21-0136

PACKAGE OUTLINE

12, 16L, THIN QFN, 3x3x0.8mm

T1233-3 1.10 1.25 0.95 1.10 0.35 x 45∞1.25 WEED-1

0.95

T1633F-3 0.65

T1633-4 0.95

0.80 0.95 0.65 0.80

1.10 1.25 0.95 1.10

0.225 x 45∞

0.95 WEED-2

0.35 x 45∞

1.25 WEED-2

T1633-2 0.95 1.10 1.25 0.95 1.10 0.35 x 45∞

1.25 WEED-2

DOWN

BONDS

ALLOWED

YES

N/A