FE175D480x033FP-00
AC Front End
Complete AC-DC PCB-Mounted Solution
AC Front End Rev 2.1
Page 1 of 23 03/2019
S
NRTL
CUS
CUS
®
Features & Benefits
• Complete AC-DC PCB-mounted solution
• Active Power Factor Correction (PFC)
• Rectification
• Filtering
• Transient protection
• Low-profile package, 9.55mm height above board
• Power density: 121W/in3, 330W in 7.2in2 footprint
• Consistent high efficiency over
world-wide AC mains (85 – 264VAC)
• Secondary-side energy storage
• SELV 48V Output
Efficient power distribution to PoL converters
• 3,000VAC / 4,242VDC isolation
• PFC (THD) exceeds EN61000-3-2 requirements
• Conducted emissions EN55022, Class B
(with a few external components)
• Surge immunity EN61000-4-5
• ZVS high-frequency (MHz) switching
• Low-profile, high-density filtering
• 100ºC baseplate operation
Typical Applications
• LED – Lighting, display, signage
• Telecom (WiMAX, Power Amplifiers, Optical Switches)
• Automatic Test Equipment (ATE)
• High-Efficiency Server Power
• Office Equipment (Printers, Copiers, Projectors)
• Industrial Equipment
(Process Controllers, Material Handling,
Factory Automation)
Product Description
The AC Front End is an AC-to-DC converter, operating from
a universal AC input to generate an isolated and regulated
48VDC output with power factor correction. The module
incorporates rectification, transient and surge suppression and
AC to DC conversion to provide a complete AC to DC solution
in a thin-profile package. With its ZVS high-frequency Adaptive
Cell™ topology, the AC Front End module consistently delivers
high efficiency across worldwide AC mains. Downstream DC-DC
converters support secondary-side energy storage and efficient
power distribution, providing superior power system performance
and connectivity from the wall plug to the point-of-load.
Product Ratings
VIN = 85 – 264VAC POUT = 330W
VOUT = 48VDC (Isolated)
Part Ordering Information
Part Number Temperature Grade Revision
FE175D480C033FP-00 C = –20 to 100°C
00
FE175D480T033FP-00 T = –40 to 100°C
AC Front End Rev 2.1
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FE175D480x033FP-00
85 – 264VAC 12V
Load
+OUT
+OUT
–OUT
–OUT
AC (L)
AC (N)
DCM™
MOV
AC Front End
Hold-Up Capacitor
Gnd
Gnd
FUSE
Typical Application
Vicor recommends the following PRM™ modules: PRM48JF480T500A00, PRM48JH480T250A00, PR036A480x012xP, PR045A480X040xP
AC Front End Rev 2.1
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FE175D480x033FP-00
GNDGND AC (N)
–IN
RSV3
AC Front End
Top View
RSV1
EN
AC (L)
DC+
OUT
DC–
OUT
DC–
OUT
DC+
OUT
Pin Configuration
Pin Descriptions
Signal Name Type Description
GND PE Ground Protective Earth Ground; two pins plus six grounded standoffs between PCB and baseplate
AC (N) AC Power Input AC Neutral Input
AC (L) AC Power Input AC Line Input
EN Signal Input Open drain with internal pullup. Leave open to enable, pull to –IN to disable
–IN Signal Reference EN pin reference pin
RSV3 No Connect Do not connect to this pin
RSV1 No Connect Do not connect to this pin
DC +OUT Power Output +48V Output
DC –OUT Power Return +48V Return Pin
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FE175D480x033FP-00
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to device.
Electrical specifications do not apply when operating beyond rated operating conditions. Positive pin current represents current flowing out of the pin
Electrical Specifications
Specifications apply over all line and load conditions, 50Hz and 60Hz line frequencies, TC = 25°C, unless otherwise noted.
Boldface specifications apply over the temperature range of the specified Product Grade. COUT is 6800µF ±20% unless otherwise specified.
Parameter Comments Min Max Unit
Input voltage AC (L) to AC (N) Continuous 275 VAC
Input voltage AC (L) to AC (N) 1ms 0 600 VPK
RSV1 to –IN Do not connect to this pin –0.3 5.3 VDC
EN to –IN 5V tolerant 3.3V logic –0.3 5.3 VDC
RSV3 to –IN Do not connect to this pin –0.3 5.3 VDC
Output voltage (+OUT to –OUT) –0.3 57.0 VDC
Output Current 0.0 10.2 A
Operating Temperature
C-Grade; baseplate –20 100
ºC
T-Grade; baseplate –40 100
M-Grade; baseplate –55 100
Storage Temperature
C-Grade –40 125
ºC
T-Grade –40 125
M-Grade –65 125
Dielectric Withstand
Input – Output 3000
VRMS
Input – Base 1500
Output – Base 1500
Attribute Symbol Conditions / Notes Min Typ Max Unit
Power Input Specification
Input Voltage Range VIN Continuous operation 85 264 VRMS
Input Voltage Cell Reconfiguration
Low-to-High Threshold VIN-CR+ 145 148 VRMS
Input Voltage Cell Reconfiguration
High-to-Low Threshold VIN-CR– 132 135 VRMS
Input Current (Peak) IINRP 12 A
Source Line Frequency Range FLINE 47 63 Hz
Power Factor PF Input power >100W 0.9 –
Input Inductance (External) LIN
Differential-mode inductance; common-mode
inductance may be higher; see “Source Inductance
Considerations” on page 19
1 mH
No-Load Specification
Input Power – No Load, Maximum PNL EN floating, see Figure 3 1.1 1.5 W
Input Power – Disabled, Maximum PQEN pulled low, see Figure 4 1.6 W
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FE175D480x033FP-00
Attribute Symbol Conditions / Notes Min Typ Max Unit
Power Output Specification
Output Voltage Set Point VOUT VIN = 230VRMS, 10% load 47.5 49 50.5 V
Output Voltage, No Load VOUT-NL Over all operating stead-state line conditions 46 51.5 55 V
Output Voltage Range (Transient) VOUT Non-faulting abnormal line and load
transient conditions 30 55 V
Output Power POUT See Figure 1, safe operating area 330 W
Efficiency η
VIN = 230V, full load 91 94
%85V < VIN < 264V, full load, see Figure 2 88.5
85V < VIN < 264V, 75% load 89
Output Voltage Ripple,
Switching Frequency VOUT-PP-HF Over all opearting steady-state line and load
conditions, 20MHz BW, measured at C3, Figure 28 100 300 mV
Output Voltage Ripple,
Line Frequency VOUT-PP-LF Over all opearting steady-state line and load
conditions, 20MHz BW 3.8 5 V
Output Capacitance (External) COUT-EXT 6000 12,000 µF
Output Turn-On Delay tON
From VIN applied, EN floating 400 1000 ms
From EN pin release, VIN applied
Start-Up Set-Point Acquisition Time tSS Full load 400 500 ms
Cell Reconfiguration Response Time tCR Full load 5.5 11 ms
Voltage Deviation (Load Transient) %VOUT-TRANS COUT = max 8 %
Recovery Time tTRANS 250 500 ms
Line Regulation %VOUT-LINE Full load 0.5 1 %
Load Regulation %VOUT-LOAD 10 – 100% load 0.5 1 %
Output Current (Continuous) IOUT See Figure 1, SOA 6.9 A
Output Current (Transient) IOUT-PK 20ms duration, max 10.2 A
Output Switching Cycle Charge QTOT 13.5 µC
Output Inductance (Parasitic) LOUT-PAR Frequency at 1MHz 1 nH
Output Capacitance (Internal) COUT-INT Effective value at nominal output voltage 7 µF
Output Cpacitance (Internal ESR) RCOUT 0.5 mΩ
Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, 50Hz and 60Hz line frequencies, TCASE = 25°C, unless otherwise noted.
Boldface specifications apply over the temperature range of the specified Product Grade. COUT is 6800µF ±20% unless otherwise specified.
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FE175D480x033FP-00
Figure 1 — DC output safe opearating area Figure 2 — Full-load efficiency vs. line voltage
0
60
120
180
240
300
360
420
0
1
2
3
4
5
6
7
80 100 120 140 160 180 200 220 240 260
Output Power (W)
Output Current (A)
Current Power
Input Voltage (VRMS)
DC Output Safe Operating Area
Efficiency (%)
Input Voltage (V)
Full Load Efficiency vs. Line Voltage 25°C Case
85 100 115 130 145 160 175 190 205 220 235 250 265
88%
89%
90%
91%
92%
93%
94%
95%
Attribute Symbol Conditions / Notes Min Typ Max Unit
Powertrain Protections
Input Undervoltage Turn-On VIN-UVLO+ See timing diagram 74 83 VRMS
Intput Undervoltage Turn-Off VIN-UVLO– 65 71 VRMS
Input Overvoltage Turn-On VIN-OVLO+ See timing diagram 265 270 VRMS
Input Overvoltage Turn-Off VIN-OVLO– 273 283 VRMS
Output Overvoltage Threshold VOUT-OVLO+ Instantaneous, latched shut down 55.3 56.6 59.0 V
Upper Start/Restart Temperature
Threshold (Case) TCASE-OTP– 100 ºC
Overtemperature Shut-Down
Threshold (Junction) TJ-OTP+ 130 ºC
Overtemperature Shut-Down
Threshold (Case) TCASE-OTP+ 110 ºC
Undertemperature Shut-Down
Threshold (Case) TCASE-UTP– C-Grade –25 ºC
Lower Start/Restart Temperature
Threshold (Case) TCASE-UTP+ C-Grade –20 ºC
Overcurrent Blanking Time tOC Based on line frequency 400 460 550 ms
Input Overvoltage Response Time tPOVP 6µs
Input Undervoltage Response Time tUVLO Based on line frequency 27 39 51 ms
Output Overvoltage Response Time tSOVP Powertrain on 60 120 180 µs
Short-Circuit Response Time tSC Powertrain on, operational state 60 120 µs
Fault Retry Delay Time tOFF See timing diagram 10 s
Output Power Limit PPROT 330 W
Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, 50Hz and 60Hz line frequencies, TCASE = 25°C, unless otherwise noted.
Boldface specifications apply over the temperature range of the specified Product Grade. COUT is 6800µF ±20% unless otherwise specified.
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FE175D480x033FP-00
Signal Characteristics
Specifications apply over all line and load conditions, 50Hz and 60Hz line frequencies, TCASE = 25°C, unless otherwise noted.
Boldface specifications apply over the temperature range of the specified Product Grade.
Enable: EN
• The EN pin enables and disables the AC Front End; when held below 0.8V the unit will be disabled.
• The EN pin can reset the AC Front End after a latching OVP event.
• The EN pin voltage is 3.3V during normal operation.
• The EN pin is referenced to the –IN pin of the module.
Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit
Digital
Input
Start Up En Enable Threshold VEN_EN 2.00 V
Standby
En Disable Time tEN_DIS From any point in line cycle 9 16 ms
En Disable Threshold VEN_DIS 0.80 V
En Resistance To Disable REN_EXT Max allowable resistance to –IN required to
disable the moducle 14 kΩ
Reserved: RSV1, RSV3
• No connections are required to these pins. In noisy environments, it is beneficial to add a 0.1µF capacitor between each reserved pin and –IN.
–IN
• Warning: –IN and N are not at the same potential and must not be connected together.
• The –IN pin is the signal reference ground for the EN pin.
• The –IN pin also serves as an access point for the common mode bypass filter to comply with EN55022 Class B for Conducted Emissions.
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FE175D480x033FP-00
High-Level Functional State Diagram
Conditions that cause state transitions are shown along arrows. Sub-sequence activities are listed inside the state bubbles.
OPERATIONAL
VOUT Ramp Up (tss)
Regulates VOUT
Powertrain: Active
RNG: Auto
PFC: Auto
STANDBY
Powertrain: Stopped
RNG: High
Application of
VIN EN = True
and
No Faults
LATCHED
FAULT
Powertrain: Stopped
RNG: High
VIN > VIN-UVLO+
STARTUP
SEQUENCE
Line Frequency
Acquisition
Powertrain: Stopped
RNG: Auto
tON Expiry
EN = False
or
VIN Out of Range EN = False
or
VIN Out of Range
NON LATCHED
FAULT
tOFF delay
Powertrain: Stopped
RNG: High
Overtemp,
Output Short,
or Overload
Output OVP
No Faults
EN Falling Edge
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Functional Block Diagram
Module inputs are shown in blue; module outputs are shown in brown.
Note: Negative current is externally forced and shown for the purpose of OVP protection scenario.
VIN-RMS
EN
VOUT
ILOAD
VIN-OVLO+
1
Input Power
On & UV
Turn-on
3
Full
Load
Applied
4
EN
Forced
Low
5
EN
High
6
Range
Change
LO to HI
9
Range
Change
HI to LO
7
Input
OV
Turn-off
8
Input
OV
Turn-on
10
Load
Dump
11
Load
Step
12
Input Power
Off & UV
Turn-off
Input
Output
tCR
tON
VIN-UVLO+
≈30VRMS
2
10%
Load
Applied
tCR
tTRANS
(2 places)
VIN-OVLO-
VIN-UVLO-
VIN-CR+ VIN-CR-
VOUT-NL VOUT
tON tON
tPOVP tUVLO
tEN-DIS
tSS
tSS
VIN-RMS
VOUT
ILOAD
tON
VIN-UVLO+
tOC
tOFF+tON tOFF+tON
tOC
≥tOFF+tON
VOUT-OVLO+
tSOVP
tON
tSS
VIN-UVLO-
tSC
tOFF+tON
tOFF+tON
EN
tOC
))
))
))
))
))
))
13
Input Power
ON & UV
Turn-on
14
Output OC
Fault
15
Output
OC
Recovery
16
Output
OVP
Fault
17
Toggle EN
(Output
OVP
Recovery)
18
Output
OVP
Fault
19
Recycle
Input
Power
(Output
OVP
Recovery)
20
Output
SC
Fault
21
Output
SC
Recovery
22
OT Fault
&
Recovery
23
Line
Drop-Out
24
Input
Power
Off & UV
Turn-off
Input
Output
tON
VIN-UVLO+
))))
))))
))))
**
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FE175D480x033FP-00
Application Characteristics
The following figures present typical performance at TCASE = 25ºC, unless otherwise noted. See associated figures for general trend data.
No Load Power Dissipation vs. Line,
Module Enabled - Nominal VOUT
Input Voltage (V)
Power Dissipation (W)
-55°C 100°C
T :
CASE
0.00
0.50
1.00
1.50
2.00
2.50
3.00
85 100 115 130 145 160 175 190 205 220 235 250 265
25°C
85 100 115 130 145 160 175 190 205 220 235 250 265
No Load Power Dissipation vs. Line,
Module Disabled, EN Low
Input Voltage (V)
Power Dissipation (W)
0.460
0.660
0.860
1.060
1.260
1.460
1.660
Figure 3 — Typical no-load power dissipation vs. VIN,
module enabled
Figure 4 — No-load power dissipation trend vs. VIN,
module disabled
Figure 5 — Typical switching frequency output voltage ripple
waveform, TCASE = 30ºC, VIN = 230V, IOUT = 6.9A, no
external ceramic capacitance
Figure 7 — Typical output voltage transient response,
TCASE = 30ºC, VIN = 230V, IOUT = 6.9A, COUT = 6,800µF
Figure 8 — Typical start-up waveform, application of VIN ,
RLOAD = 7.1Ω, COUT = 6,800µF
Figure 6 — Typical line frequency output voltage ripple waveform,
TCASE = 30ºC, VIN = 230V, IOUT = 6.9A, COUT = 6,800µF.
Measured at C3, Figure 25
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Figure 9 — Typical start-up waveform, EN pin release, VIN = 230V,
RLOAD = 7.1Ω, COUT = 6,800µF
Figure 11 — Line drop out, 50Hz, 90° phase, VIN = 230V,
PLOAD = 330W, COUT = 6,800µF
Figure 10 — Line drop out, 50Hz, 0° phase,
PLOAD = 330W, COUT = 6,800µF
Figure 12 — Typical EMI spectrum, quasi-peak scan, 90% load,
230VIN, COUT = 6,800µF; test circuit – Figure 25
Figure 14 — Typical EMI spectrum, quasi-peak scan, 90% load,
115VIN, COUT = 6,800µF; test circuit – Figure 25
Figure 13 — Typical EMI spectrum, average scan, 90% load,
230VIN, COUT = 6,800µF; test circuit – Figure 28
Report No. TRFE175D480C033FP082912AR1
Compliance Engineering
8/29/2012 Page 7 of 7
Input: 230V/50Hz Output: 90% Load (297W)
Average Scan Red Lead (L1)
SGL
150 kHz
30 M Hz
Unit
dB
V
ResB W
9 k Hz
Meas T
20 ms
Det
QP/A V
Att
20 dB
INPUT 2
Trd
5502 2RED
2AV
29.Aug 2012 11:02
1 MH z
10 M Hz
30
40
50
60
70
80
90
20
10 0
22AVB
22AVA
Date : 29.AUG. 2012 11: 02:41
Average Scan Black Lead (L2/N)
SGL
150 kHz
30 M Hz
Unit
dB
V
Trd
5502 2BLK
ResB W
9 k Hz
Meas T
20 ms
Det
QP/A V
Att
20 dB
INPUT 2
2AV
29.Aug 2012 12:58
1 MH z
10 M Hz
30
40
50
60
70
80
90
20
10 0
22AVB
22AVA
Date : 29 .AUG. 2012 12: 58:13
Report No. TRFE175D480C033FP082912AR1
Compliance Engineering
8/29/2012 Page 6 of 7
Input: 230V/50Hz Output: 90% Load (297W)
Quasi-Peak Scan Red Lead (L1)
SGL
1QP
150 kHz
30 M Hz
Unit
dB
V
ResB W
9 k Hz
Meas T
20 ms
Det
QP/A V
Att
20 dB
INPU T 2
29.Aug 2012 11:01
Trd
5502 2RED
1 MH z
10 M Hz
30
40
50
60
70
80
90
20
10 0
22QP A
22QPB
Date : 29.AUG. 2012 11: 01:40
Quasi-Peak Scan Black Lead (L2/N)
SGL
1QP
150 kHz
30 M Hz
Unit
dB
V
Trd
5502 2BLK
ResB W
9 k Hz
Meas T
20 ms
Det
QP/A V
Att
20 dB
INPU T 2
29.Aug 2012 12:57
1 MH z
10 M Hz
30
40
50
60
70
80
90
20
10 0
22QP A
22QPB
Date : 29.AUG. 2012 12: 57:35
Application Characteristics (Cont.)
The following figures present typical performance at TCASE = 25ºC, unless otherwise noted. See associated figures for general trend data.
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Figure 17 — Typical input current harmonics, full load vs. VIN
Figure 19 — VIN to VOUT efficiency and power dissipation vs.
VIN and IOUT, TCASE = –55ºC
Figure 16 — Typical line current waveform, 60Hz, VIN = 120V,
PLOAD = 330W; COUT = 6,800µF
Figure 15 — Typical EMI spectrum, average scan, 90% load,
115VIN, COUT = 6,800µF; test circuit – Figure 25
Figure 18 — Typical power factor vs. VIN and IOUT
Figure 20 — VIN to VOUT efficiency and power dissipation vs.
VIN and IOUT, TCASE = 25ºC
Report No. TRFE175D480C033FPR1
Compliance Engineering
7/27/2012 Page 17 of 17
Input : 115V/60Hz Output: 90% Load (297W)
Average Scan Red Lead (L1)
SGL
150 kHz
30 M Hz
Unit
dB
V
Trd
55022RED
ResB W
9 kHz
Meas T
1 s
Det
MA/A V
Att
20 dB
INPUT 2
26.Jul 2012 16:36
2AV
1 MH z
10 M Hz
30
40
50
60
70
80
90
20
10 0
22AVB
22AVA
Date : 26.JUL. 2012 16: 36:57
Average Scan Black Lead (L2/N)
SGL
150 kHz
30 M Hz
Unit
dB
V
Trd
55022BLK
ResB W
9 kHz
Meas T
1 s
Det
MA/A V
Att
20 dB
INPUT 2
2AV
26.Jul 2012 16:47
1 MH z
10 M Hz
30
40
50
60
70
80
90
20
10 0
22AVB
22AVA
Date : 26.JUL. 2012 16: 47:25
Current [mA]
Input Current Harmonics
0
100
200
300
400
500
600
700
800
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
230 V, 50 Hz 1/3x EN61000-3-2, Class A EN61000-3-2, Class D
Efficiency & Power Dissipation -55°C Case
Efficiency (%)
Load Current (A)
100 V Power Diss 115 V Power Diss 240 V Power Diss
V :
IN 100 V Eff 115 V Eff 240 V Eff
0
4
8
12
16
20
24
28
32
36
40
44
48
76%
78%
80%
82%
84%
86%
88%
90%
92%
94%
96%
0.69 1.38 2.07 2.76 3.45 4.14 4.83 5.18 5.52 6.21 6.90
Power Dissipation (W)
Load Current (A)
Power Factor
Power Factor vs. Load and VIN at 25°C
V :
IN 100 V 115 V 240 V
.750
.800
.850
.900
.950
1.000
0 1 2 3 4 5 6 7
Efficiency & Power Dissipation 25°C Case
Efficiency (%)
Load Current (A)
100 V Power Diss 115 V Power Diss 240 V Power Diss
V :
IN 100 V Eff 115 V Eff 240 V Eff
0
4
8
12
16
20
24
28
32
36
40
44
48
76%
78%
80%
82%
84%
86%
88%
90%
92%
94%
96%
0.69 1.38 2.07 2.76 3.45 4.14 4.83 5.18 5.52 6.21 6.90
Power Dissipation (W)
Application Characteristics (Cont.)
The following figures present typical performance at TCASE = 25ºC, unless otherwise noted. See associated figures for general trend data.
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Figure 21 — VIN to VOUT efficiency and power dissipation vs.
VIN and IOUT, TCASE = 100ºC
Efficiency & Power Dissipation 100°C Case
Efficiency (%)
Power Dissipation (W)
0
4
8
12
16
20
24
28
32
36
40
44
48
76%
78%
80%
82%
84%
86%
88%
90%
92%
94%
96%
0.69 1.38 2.07 2.76 3.45 4.14 4.83 5.52 6.21 6.90
Load Current (A)
100 V Power Diss 115 V Power Diss 240 V Power Diss
V :
IN 100 V Eff 115 V Eff 240 V Eff
Figure 22 — Baseplate-to-air thermal resistance; Insulated: minimal
thermal dissipation through pins to PCB;
Uninsulated: thermal dissipation to typical PCB
0
1
2
3
4
5
6
0 200 400 600 800 1000
Thermal Resistance (°C/W)
Air Flow (LFM)
Thermal Resistance (Baseplate to Air)
vs. Air Flow
INSULATED UNINSULATED
Application Characteristics (Cont.)
The following figures present typical performance at TCASE = 25ºC, unless otherwise noted. See associated figures for general trend data.
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FE175D480x033FP-00
General Characteristics
Specifications apply over all line and load conditions, 50Hz and 60Hz line frequencies, TC = 25°C, unless otherwise noted.
Boldface specifications apply over the temperature range of the specified product grade.
Attribute Symbol Conditions / Notes Min Typ Max Unit
Mechanical
Length L 95.3 [3.75] mm [in]
Width W 48.6 [1.91] mm [in]
Height H 9.55 [0.38] mm [in]
Volume Vol 44.2 [2.69] cm3 [in3]
Weight W 111 [3.9] g [oz]
Pin Material C10200 copper, full hard
Underplate Nickel 100 150
μin
Pin Finish Pure matte tin,
whisker-resistant chemistry 200 300
Thermal
Operating Baseplate
(Case) Temperature TCAny operating
condition
C-Grade –20 100
°CT-Grade –40 100
M-Grade –55 100
Thermal Resistance
Baseplate-to-sink, flat greased surface 0.13
°C / W
Baseplate-to-sink, thermal pad
(PN 36967) 0.17
Thermal Capacity 84.5 Ws / °C
Assembly
ESD Rating
ESDHBM Human Body Model,
(JEDEC JESD 22-A114C.01) 1000
V
ESDMM Machine Model,
(JEDEC JESD 22-A115B) N/A
ESDCDM Charged Device Model,
(JEDEC JESD 22-C101D) 200
Soldering
See Application Note: Soldering Methods and Procedure for Vicor Power Modules
Safety & Reliability
Touch Current
Measured in accordance with
IEC 60990 using measuring network
Figure 28
0.56 0.68 mA
Agency Approvals / Standards
cURus UL/CSA 60950-1
cTÜVus EN 60950-1
CE, Low Voltage Directive 2006/95/EC
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General Characteristics (Cont.)
Specifications apply over all line and load conditions, 50Hz and 60Hz line frequencies, TC = 25°C, unless otherwise noted.
Boldface specifications apply over the temperature range of the specified product grade.
Attribute Symbol Conditions / Notes
EMI/EMC Compliance
FCC Part 15, EN55022,
CISPR22: 2006 + A1: 2007,
Conducted Emissions
Class B Limits – with components connected as shown in Figure 28
EN61000-3-2: 2009,
Harmonic Current Emissions Class A
EN61000-3-3: 2005,
Voltage Changes & Flicker
PST < 1.0; PLT < 0.65;
dc < 3.3%; dmax < 6%
EN61000-4-4: 2004,
Electrical Fast Transients Level 2, Performance criteria A
EN61000-4-5: 2006,
Surge Immunity Level 3, Immunity Criteria B, external TMOV required
EN61000-4-6: 2009,
Conducted RF Immunity Level 2, 130dBµV (3.0VRMS)
EN61000-4-8: 1993 + A1 2001,
Power Frequency H-Field 10A/m,
continuous field
Level 3, Performance Criteria A
EN61000-4-11: 2004,
Voltage Dips & Interrupts
Class 2,
Performance Criteria A Dips,
Performance Criteria B Interrupts
AC Front End Rev 2.1
Page 16 of 23 03/2019
FE175D480x033FP-00
Product Details and Design Guidelines
Building Blocks and System Designs
The AC Front End is a high efficiency AC-to-DC converter,
operating from a universal AC input to generate an isolated SELV
48VDC output bus with power factor correction. It is the key
component of an AC-to-DC power supply system such as the one
shown in Figure 23 above.
The input to the AC Front End is a sinusoidal AC source with
a power factor maintained by the module with harmonics
conforming to IEC61000-3-2. Internal filtering enables compliance
with the standards relevant to the application (Surge, EMI, etc.).
See EMI/EMC Compliance standards on page 16.
The module uses secondary-side energy storage (at the SELV
48V bus) and optional PRM™ regulators to maintain output hold
up through line dropouts and brownouts. Downstream regulators
also provide tighter voltage regulation, if required.
The FE175D480C033FP-00 is designed for standalone operation;
however, it may be part of a system that is paralleled by
downstream DC-DC converters. Contact Vicor Sales or refer to
our www.vicorpower.com, regarding new models that can be
paralleled directly for higher power applications.
Traditional PFC Topology
To cope with input voltages across worldwide AC mains
(85 – 264VAC), traditional AC-DC power supplies (Figure 24)
use two power conversion stages: 1) a PFC boost stage to step
up from a rectified input as low as 85VAC to ~380VDC; and 2) a
DC-DC down converter from 380VDC to a 12V bus. The efficiency
of the boost stage and of traditional power supplies is significantly
compromised operating from worldwide AC lines as low as 85VAC.
Adaptive Cell™ Topology
With its single-stage Adaptive Cell topology, the AC Front End
enables consistently high-efficiency conversion from worldwide AC
mains to a 48V bus and efficient secondary-side power distribution.
Power Factor Correction
The module provides power factor correction over worldwide AC
mains. For most static loads, PFC approaches unity, see Figure 18.
Load transients that approach the line frequency should be filtered
or avoided as these may reduce PFC.
Input Fuse Selection
The AC Front End is not internally fused in order to provide
flexibility in configuring power systems. Input line fusing is
recommended at system level, in order to provide thermal
protection in case of catastrophic failure. The fuse shall be selected
by closely matching system requirements with the following
characteristics:
Recommended fuse: 5A, 216 Series Littelfuse
Current rating
(usually greater than the AC Front End maximum current)
Maximum voltage rating
(usually greater than the maximum possible input voltage)
Ambient temperature
Breaking capacity per application requirements
Nominal melting I2t
Fault Handling
Input Undervoltage (UV) Fault Protection
The AC Front End’s input voltage is monitored by the
microcontroller to detect an input undervoltage condition. When
the input voltage is less than the VIN-UVLO–, a fault is detected, the
fault latch and reset logic disables the modulator, the modulator
stops powertrain switching, and the output voltage of the unit
falls. After a time tUVLO, the unit shuts down. Faults lasting less
than tUVLO may not be detected. Such a fault does not go through
an auto-restart cycle. Once the input voltage rises above VIN-UVLO+,
the unit recovers from the input UV fault, the powertrain resumes
normal switching after a time tON and the output voltage of the
unit reaches the set-point voltage within a time tSS.
Overcurrent (OC) Fault Protection
The unit’s output current, determined by VEAO, VIN-B and
the primary-side-sensed output voltage is monitored by the
microcontroller to detect an output OC condition. If the output
current exceeds its current limit, a fault is detected, the reset logic
disables the modulator, the modulator stops powertrain switching,
and the output voltage of the module falls after a time tOC. As
long as the fault persists, the module goes through an auto-restart
cycle with off time equal to tOFF+tON and on time equal to tOC.
Faults shorter than a time tOC may not be detected. Once the
fault is cleared, the module follows its normal start up sequence
after a time tOFF.
Short Circuit (SC) Fault Protection
The microcontroller determines a short circuit on the output of
the unit by measuring its primary sensed output voltage. Most
commonly, a drop in the primary-sensed output voltage triggers
a short circuit event. The module responds to a short circuit event
within a time tSC. The module then goes through an auto restart
cycle, with an off time equal to tOFF+tON and an on time equal to
tSC, for as long as the short circuit fault condition persists. Once the
fault is cleared, the unit follows its normal start up sequence after a
time toff. Faults shorter than a time tSC may not be detected.
85 – 264VAC
Approximately
48VDC
DC-DC
Converter
LOAD
(Optional)
AC Front End
Hold-Up Capacitor
MOV*
+OUT
+OUT
–OUT
–OUT
AC (L)
AC (N)
Full-Wave
Rectifier
EMI/TVS
Filter
Isolated
DC-DC
Converter
12V Bus
Figure 23 — 300W universal AC-to-DC supply
Figure 24 — Traditional PFC AC-to-DC supply
AC Front End Rev 2.1
Page 17 of 23 03/2019
FE175D480x033FP-00
Temperature Fault Protection
The microcontroller monitors the temperature within the
AC Front End. If this temperature exceeds TJ-OTP+, an
overtemperature fault is detected, the reset logic block disables
the modulator, the modulator stops the powertrain switching
and the output voltage of the AC Front End falls. Once the case
temperature falls below TCASE-OTP–, after a time greater than or
equal to toff, the converter recovers and undergoes a normal
restart. For the C-Grade version of the converter, this temperature
is 75°C. Faults shorter than a time totp may not be detected. If
the temperature falls below TCASE-UTP–, an undertemperature fault
is detected, the reset logic disables the modulator, the modulator
stops powertrain switching and the output voltage of the unit
falls. Once the case temperature rises above TCASE-UTP, after a time
greater than or equal to tOFF, the unit recovers and undergoes a
normal restart.
Output Overvoltage Protection (OVP)
The microcontroller monitors the primary sensed output voltage to
detect output OVP. If the primary sensed output voltage exceeds
VOUT-OVLO+, a fault is latched, the logic disables the modulator, the
modulator stops powertrain switching, and the output voltage
of the module falls after a time tsovp. Faults shorter than a time
tSOVP may not be detected. This type of fault is a latched fault and
requires that 1) the EN pin be toggled or 2) the input power be
recycled to recover from the fault.
Hold-Up Capacitance
The AC Front End uses secondary-side energy storage (at the
SELV 48V bus) and optional PRM™ regulators to maintain output
hold up through line dropouts and brownouts. The module’s
output bulk capacitance can be sized to achieve the required hold
up functionality.
Hold-up time depends upon the output power drawn from the
AC-Front-End-based AC-to-DC front end and the input voltage
range of downstream DC-to-DC converters.
The following formula can be used to calculate hold-up capacitance
for a system comprised of AC Front End and a PRM regulator:
Where:
C = AC Front End’s output bulk capacitance in farads
td = Hold-up time in seconds
POUT = AC Front End’s output power in watts
V2 = Output voltage of AC Front end’s converter in volts
V1 = PRM regulator undervoltage turn off (volts)
or
POUT/IOUT-PK, whichever is greater
Output Filtering
The AC Front End module requires an output bulk capacitor
in the range of 6,000 – 12,000µF for proper operation of
the PFC front end.
The output voltage has the following two components of
voltage ripple:
1) Line frequency voltage ripple: 2 • fLINE Hz component
2) Switching frequency voltage ripple: 1MHz module switching
frequency component
Where, in the schematic:
C1 = 2.2nF (Murata GA355DR7GF222KW01L)
C2 = 4.7nF (Murata GA355DR7GF472KW01L)
C3 = 3.3µF (TDK C4532X7R1H335MT)
C4 = 6800µF 63V (Panasonic UVR1J682MRD)
C5 = 100µF 63V (Nichicon UVY1J101MPD)
F1 = 5A, 216 Series Littlefuse
L1 = 15µH (TDK MLF2012C150KT)
L2 = 600µH (Vicor 37052-601)
MOV = 300V, 10kA, 20mm dia (Littlefuse TMOV20RP300E)
R1 = 6.8Ω
R2 = 2.2Ω
Line Frequency Filtering
Output line frequency ripple depends upon output bulk
capacitance. Output bulk capacitor values should be calculated
based on line frequency voltage ripple. High-grade electrolytic
capacitors with adequate ripple current ratings, low ESR and a
minimum voltage rating of 63V are recommended.
C3
C5
L2
R2
C2
C4
85 – 264VAC
+OUT
+OUT
–OUT
–OUT
GND
AC (L)
AC (N)
GND
AC Front End
R1C1
L1
+OUT
–OUT
MOV
RSV1
EN
RSV3
–IN
F1
CM
lPK
lPK/2
loutDC
lfLINE
(1)C = 2 • POUT •
(
0.005 + t
d
)
(
V2
2 – V1
2
)
Figure 25 — Typical application for EN55022 Class B EMI
Figure 26 — Output current waveform
AC Front End Rev 2.1
Page 18 of 23 03/2019
FE175D480x033FP-00
Based on the output current waveform, as seen in Figure 26, the
following formula can be used to determine peak-to-peak line
frequency output voltage ripple:
Where:
VPPLINE = Output voltage ripple peak-to-peak line frequency
POUT = Average output power
VOUT = Output voltage set point, nominally 48V
fLINE = Frequency of line voltage
C = Output bulk capacitance
IDC = Maximum average output current
IPK = Peak-to-peak line frequency output current ripple
In certain applications, the choice of bulk capacitance may be
determined by hold-up requirements and low frequency output
voltage filtering requirements. Such applications may use the
greater capacitance value determined from these requirements.
The ripple current rating for the bulk capacitors can be determined
from the following equation:
Switching Frequency Filtering
Some applications require the output filtering shown in Figure 25
to meet radiated emissions limits. In such a situation, the output
switching ripple shown in Figure 5 should be expected at the
output of the filter. In cases where other means are used to control
radiated emissions, and more ripple can be tolerated, the output
filter can be simplified by removal of the common mode inductor,
and C5, which is used to reduce the Q of the LC resonant tank.
Output switching frequency voltage ripple is the function of the
output bypass ceramic capacitor. Output bypass ceramic capacitor
values should be calculated based on switching frequency voltage
ripple. Normally bypass capacitors with low ESR are used with a
sufficient voltage rating.
Output bypass ceramic capacitor value for allowable peak-to-peak
switching frequency voltage ripple can be determined by:
Where:
VOUT-PP-HF = Allowable peak-to-peak output switching
frequency voltage ripple in volts
QTOT = The total output charge per switching cycle at full
load, maximum 13.5μC
COUT-INT = The module internal effective capacitance
C3 = Required output bypass ceramic capacitor
EMI Filtering and Transient Voltage Suppression
EMI Filtering
The AC Front End with PFC is designed such that it will comply with
EN55022 Class B for Conducted Emissions with the filter connected
across –IN and GND as shown in Figure 25. The emissions spectrum
is shown in Figures 12 – 15. If one of the outputs is connected to
earth ground, a small (single turn) output common mode choke
is also required.
EMI performance is subject to a wide variety of external influences
such as PCB construction, circuit layout etc. As such, external
components in addition to those listed herein may be required in
specific instances to gain full compliance to the standards specified.
Transient Voltage Suppression
The AC Front End contains line transient suppression circuitry to
meet specifications for surge (i.e., EN61000-4-5) and fast transient
conditions (i.e., EN61000-4-4 fast transient/“burst”).
Thermal Design
Thermal management of internally dissipated heat should maximize
heat removed from the baseplate surface, since the baseplate
represents the lowest aggregate thermal impedance to internal
components. The baseplate temperature should be maintained
below 100°C. Cooling of the system PCB should be provided
to keep the leads below 100°C, and to control maximum PCB
temperatures in the area of the module.
Powering a Constant Power Load
When the output voltage of the AC Front End module is applied
to the input of the PRM™ regulator, the regulator turns on and
acts as a constant-power load. When the module’s output voltage
reaches the input undervoltage turn on of the regulator, the
regulator will attempt to start. However, the current demand of the
PRM regulator at the undervoltage turn-on point and the hold-up
capacitor charging current may force the AC Front End into current
limit. In this case, the unit may shut down and restart repeatedly.
In order to prevent this multiple restart scenario, it is necessary to
delay enabling a constant-power load when powered up by the
upstream AC to 48V front end until after the output set point of
the AC Front End is reached.
This can be achieved by
1) Keeping the downstream constant-power load off during
power up sequence
and
2) Turning the downstream constant-power load on after the
output voltage of the module reaches 48V steady state.
After the initial start up, the output of the AC Front End can be
allowed to fall to 30V during a line dropout at full load. In this
case, the circuit should not disable the PRM regulator if the input
voltage falls after it is turned on; therefore, some form of hysteresis
or latching is needed on the enable signal for the constant power
load. The output capacitance of the AC Front End should also be
sized appropriately for a constant power load to prevent collapse
of the output voltage of the module during line dropout (see
Hold-Up Capacitance on page 18). A constant-power load can be
turned off after completion of the required hold up time during
the power-down sequence or can be allowed to turn off when it
reaches its own undervoltage shut-down point.
(2)VPPLINE = 0.2 •
P
OUT
(
VOUT • fLINE • C
)
(3)IRIPPLE ≈ 0.8 •
P
OUT
V
OUT
(4)
(4)
C3 = QTOT
VOUT-PP-HF – COUT-INT
C3 = – COUT-INT
Q
TOT
V
OUT-PP-HF
AC Front End Rev 2.1
Page 19 of 23 03/2019
FE175D480x033FP-00
The timing diagram in Figure 27 shows the output voltage of
the AC Front End module and the PRM™ PC pin voltage and
output voltage of the PRM regulator for the power up and power
down sequence. It is recommended to keep the time delay
approximately 10 – 20ms.
Special care should be taken when enabling the constant-power
load near the auto-ranger threshold, especially with an inductive
source upstream of the AC Front End. A load current spike
may cause a large input voltage transient, resulting in a range
change which could temporarily reduce the available power
(see Adaptive Cell™ Topology below).
Adaptive Cell™ Topology
The Adaptive Cell topology utilizes magnetically coupled “top”
and “bottom” primary cells that are adaptively configured in series
or parallel by a configuration controller comprised of an array of
switches. A microcontroller monitors operating conditions and
defines the configuration of the top and bottom cells through a
range control signal.
A comparator inside the microcontroller monitors the line voltage
and compares it to an internal voltage reference.
If the input voltage of the AC Front End crosses above the positive
going cell reconfiguration threshold voltage, the output of the
comparator transitions, causing switches S1 and S2 to open and
switch S3 to close (see Functional Block Diagram on page 8). With
the top cell and bottom cell configured in series, the unit operates
in “high” range and input capacitances CIN-T and CIN-B are in series.
If the peak of input voltage of the unit falls below the
negative-going range threshold voltage for two line cycles, the cell
configuration controller opens switch S3 and closes switches S1 and
S2. With the top cell and bottom cells configured in parallel, the
unit operates in “low” range and input capacitances CIN-T and CIN-B
are in parallel.
Power processing is held off while transitioning between ranges
and the output voltage of the unit may temporarily droop. External
output hold up capacitance should be sized to support power
delivery to the load during cell reconfiguration. The minimum
specified external output capacitance of 6,000µF is sufficient to
provide adequate ride-through during cell reconfiguration for
typical applications.
Source Inductance Considerations
The AC Front End powertrain uses a unique Adaptive Cell Topology
that dynamically matches the powertrain architecture to the AC
line voltage. In addition the AC Front End uses a unique control
algorithm to reduce the AC line harmonics yet still achieve rapid
response to dynamic load conditions presented to it at the DC
output terminals. Given these unique power processing features,
the AC Front End can expose deficiencies in the AC line source
impedance that may result in unstable operation if ignored.
It is recommended that for a single AC Front End, the line source
inductance should be no greater than 1mH for a universal AC
input of 100 – 240V. If the AC Front End will be operated at 240V
nominal only, the source impedance may be increased to 2mH.
For either of the preceding operating conditions it is best to be
conservative and stay below the maximum source inductance
values. When multiple AC Front End’s are used on a single AC line,
the inductance should be no greater than 1mH/N, where N is the
number of AC Front End’s on the AC branch circuit, or 2mH/N
for 240VAC operation. It is important to consider all potential
sources of series inductance including and not limited to, AC
power distribution transformers, structure wiring inductance, AC
line reactors, and additional line filters. Non-linear behavior of
power distribution devices ahead of the AC Front End may further
reduce the maximum inductance and require testing to ensure
optimal performance.
If the AC Front End is to be utilized in large arrays, the AC Front
Ends should be spread across multiple phases or sources thereby
minimizing the source inductance requirements, or be operated
at a line voltage close to 240VAC. Vicor Applications should be
contacted to assist in the review of the application when multiple
devices are to be used in arrays.
AC Front End
PRM™
Regulator
PRM UV
Turn on
49V – 3%
PRM™
Regulator
VOUT
tDELAY
tHOLD-UP
VOUT
PC
Figure 27 — PRM enable hold-off waveforms
AC Front End Rev 2.1
Page 20 of 23 03/2019
FE175D480x033FP-00
Product outline drawings are available in .pdf and .dxf formats. 3D mechanical models are available in .pdf and .step formats.
See the AC Front End family page for more details.
95.3
3.75
48.6
1.91
47.63
1.875
2.0
.080
44.55
1.754
9.3
.364
26.05
1.026
17.28
.680
8.78
.345
2.86
.113
50.25
1.978
80.25
3.159
37.26
1.467
74.52
2.934
9.8
.386
3.18
(6) PL.
.125
7.03
.277
4.00
.157
8.00
.315
12.00
.472
24.30
.957
IWI
IWI
IWI
IWI
5.8
.227
37.1
1.46
5.2
.204
38.2
1.505
2.54
.100
7.01
.276
13.54
±.64
.533
±.025
9.55
±.25
.376
±.010
3.99
.157
.6
.022
94.1
3.706
2.06
.081
(12) PL.
SEATING
PLANE
NOTES:
1- RoHS COMPLIANT PER CST-0001 LATEST REVISION.
2- PLATED THROUGH HOLES SHALL BE USED WITH VIBRICK
STANDOFF KITS TO GROUND THE BASEPLATE TO THE
CUSTOMERS PCB AND/OR COLD PLATE.
Product Outline Drawing – Top View
AC Front End Rev 2.1
Page 21 of 23 03/2019
FE175D480x033FP-00
24.30
.957
48.6
1.91
47.63
1.875
95.3
3.75
3.81
±.08
PLATED THRU
1.02 [.040] ANNULAR RING
(Ø5.84 [.230])
(4) PL.
SEE NOTE 2
.150
±.003
3.81
±.08
PLATED THRU
.06 [.023] ANNULAR RING
(Ø5.00 [.197])
(2) PL.
SEE NOTE 2
.150
±.003
2.36
±.08
PLATED THRU
.54 [.021] ANNULAR RING
(Ø3.43 [.135])
(4) PL.
.093
±.003
2.36
±.08
PLATED THRU
.73 [.029] ANNULAR RING
(Ø3.81 [.150])
(8) PL.
.093
±.003
R4.64
.182
(3) PL.
.00
.000
4.25
±.08
.167
±.003
13.03
±.08
.513
±.003
22.28
±.08
.877
±.003
4.25
±.08
.167
±.003
13.03
±.08
.513
±.003
22.28
±.08
.877
±.003
.00
.000
6.00
±.08
.236
±.003
2.00
±.08
.079
±.003
2.00
±.08
.079
±.003
6.00
±.08
.236
±.003
0
.000
.00
.000
10.13
±.08
.399
±.003
37.26
±.08
1.467
±.003
37.26
±.08
1.467
±.003
40.13
±.08
1.580
±.003
40.13
±.08
1.580
±.003
3.86
±.08
.152
±.003
15.39
±.08
.606
±.003
18.28
±.08
.720
±.003
7.74
±.08
.305
±.003
yljvttluklkGwjiGwh{{lyu
(COMPONENT SIDE SHOWN)
DC+
OUT
DC+
OUT
DC-
OUT
DC-
OUT
RSV1
EN
RSV3
-IN
GND
AC(L)
AC(N)
GND
TOP LAYER
COPPER KEEP
OUT AREA
Recommended PCB Footprint
Product outline drawings are available in .pdf and .dxf formats. 3D mechanical models are available in .pdf and .step formats.
See the AC Front End family page for more details.
AC Front End Rev 2.1
Page 22 of 23 03/2019
FE175D480x033FP-00
Revision History
Revision Date Description Page Number(s)
2.1 03/19/19 First release with updated formatting n/a
AC Front End Rev 2.1
Page 23 of 23 03/2019
FE175D480x033FP-00
Contact Us: http://www.vicorpower.com/contact-us
Vicor Corporation
25 Frontage Road
Andover, MA, USA 01810
Tel: 800-735-6200
Fax: 978-475-6715
www.vicorpower.com
email
Customer Service: custserv@vicorpower.com
Technical Support: apps@vicorpower.com
©2019 Vicor Corporation. All rights reserved. The Vicor name is a registered trademark of Vicor Corporation.
All other trademarks, product names, logos and brands are property of their respective owners.
Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and
accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom
power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor
makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves
the right to make changes to any products, specifications, and product descriptions at any time without notice. Information published by
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Testing and other quality controls are used to the extent Vicor deems necessary to support Vicor’s product warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
Specifications are subject to change without notice.
Visit http://www.vicorpower.com/ac-dc/converters/ac-front-end-module for the latest product information.
Vicor’s Standard Terms and Conditions and Product Warranty
All sales are subject to Vicor’s Standard Terms and Conditions of Sale, and Product Warranty which are available on Vicor’s webpage
(http://www.vicorpower.com/termsconditionswarranty) or upon request.
Life Support Policy
VICOR’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF VICOR CORPORATION. As used
herein, life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and
whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to
result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform
can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Per Vicor Terms
and Conditions of Sale, the user of Vicor products and components in life support applications assumes all risks of such use and indemnifies
Vicor against all liability and damages.
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Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the
products described in this data sheet. No license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property
rights is granted by this document. Interested parties should contact Vicor’s Intellectual Property Department.
The products described on this data sheet are protected by the following U.S. Patents Numbers:
5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,909; 7,038,917;
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