A65H73361/A65H83181 Series
128K x 36 & 256K x 18 Late Write Synchronous
Preliminary Fast SRAM with Pipelined Data Output
PRELIMINARY (February, 1999, Version 2.0) AMIC Technology, Inc.
Document Title
128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output
Revision History
Rev. No. History Issue Date Remark
2.0 Add JTAG standard February 12, 1999 Preliminary
A65H73361/A65H83181 Series
128K x 36 & 256K x 18 Late Write Synchronous
Preliminary Fast SRAM with Pipelined Data Output
PRELIMINARY (February, 1999, Version 2.0) 1AMIC Technology, Inc.
Features
nFast access times: 2.5/3.0/3.5ns
n128k x 36 or 256k x 18 organizations
nCMOS technology
nRegister to register synchronous operation with self-
timed late write
nSingle +3.3V ±5% power supply
nIndividual byte write and global write
nHSTL input & output levels
nBoundary scan(JTAG) IEEE 1149.1 compatible
nAsynchronous output enable
nSleep mode (ZZ)
nProgrammable impedance output drivers
nJEDEC Standard pinout and boundary scan order
n 7 x 17 bump plastic ball grid array (PBGA) package
General Description
The A65H73361 and A65H83181 are 128k words by 36
bits and 256k words by 18 bits late write synchronous
4Mb SRAMS built using high performance CMOS
process.
The differential clock are used to control the timing of
read/write operation and all internal operations are self-
timed. The positive edge triggered CK clock input
controls all addresses write-enables and Synchronous
select and data ins are registered.
The data outs are controlled by the output registers off
the next positive clock edge to be updated.
The internal write buffer enables write data to be
accepted on the rising edge of the clock one cycle after
address and control signals.
The SRAM uses HSTL I/O interfaces with programmable
impedance output drivers allowing the outputs to match
the impedance of the circuit traces which reduces signal
reflections.
A65H73361/A65H83181 Series
PRELIMINARY (February, 1999, Version 2.0) 2AMIC Technology, Inc.
Pin Configuration
A65H73361
V
DDQ
SA
7
NC SA
16
SA
14
V
DDQ
1 2 3 4 5 6 7
NC NC SA
8
NC SA
11
NC NC
NC SA
6
SA
9
V
DD
SA
10
SA
15
NC
DQ
18
DQ
27
V
SS
NC M
1
V
DD
NC
NC ZZ
V
DDQ
TMS TDI TCK TDO NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
UV
DDQ
NC NC
M
2
V
SS
SA
5
DQ
19
SA
4
SA
12
SA
3
SA
2
SA
13
SA
1
DQ
1
DQ
0
DQ
3
DQ
2
V
DDQ
SW V
SS
DQ
4
V
DDQ
DQ
32
DQ
33
SBW
d
CK SBW
a
DQ
6
DQ
5
DQ
34
DQ
35
V
SS
CK V
SS
DQ
8
DQ
7
V
DDQ
V
DD
V
ref
V
DD
V
ref
V
DD
V
DDQ
DQ
25
DQ
26
NC V
SS
DQ
17
DQ
16
DQ
23
DQ
24
SBW
C
NC SBW
b
DQ
15
DQ
14
V
DDQ
DQ
22
V
SS
GV
SS
DQ
13
V
DDQ
DQ
20
DQ
21
V
SS
SS V
SS
DQ
12
DQ
11
V
SS
ZQ V
SS
DQ
10
DQ
9
DQ
31
DQ
30
DQ
25
V
SS
DQ
29
V
SS
V
SS
SA
0
A65H83181
V
DDQ
SA
7
NC SA
16
SA
14
V
DDQ
1 2 3 4 5 6 7
NC NC SA
8
NC SA
11
NC NC
NC SA
6
SA
9
V
DD
SA
10
SA
15
NC
DQ
9
NC V
SS
NC M
1
V
DD
NC
ZZ
V
DDQ
TMS TDI TCK TDO NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
UV
DDQ
NC
M
2
V
SS
SA
5
NC
SA
4
SA
13
SA
3
NC SA
17
SA
1
NC DQ
0
DQ
3
NC
V
DDQ
SW V
SS
NC V
DDQ
DQ
14
NC CK SBW
a
DQ
6
NC
NC DQ
17
V
SS
CK V
SS
NC DQ
7
V
DDQ
V
DD
V
ref
V
DD
V
ref
V
DD
V
DDQ
DQ
16
NC NC V
SS
DQ
8
NC
NC DQ
15
SBW
b
NC NC DQ
5
V
DDQ
NC V
SS
GV
SS
DQ
4
V
DDQ
NC DQ
12
V
SS
SS V
SS
NC DQ
2
V
SS
ZQ V
SS
DQ
1
NC
DQ
13
NC
DQ
10
V
SS
DQ
11
V
SS
V
SS
SA
0
V
SS
V
SS
V
SS
SA
2
SA
12
V
SS
A65H73361/A65H83181 Series
PRELIMINARY (February, 1999, Version 2.0) 3AMIC Technology, Inc.
Block Diagram
128Kx36
or
256Kx18
Array
DQ0 - DQ35
Column Decoder
Read/Write Amp
Row Decoder
Write
Buffer
2:1 MUX
2:1 MUX Match
WR Add
Register
Data Out
Registor
RD Add
Register
SW
Register
SBW
Register
SW
Register
SBW
Register
SA0-SA17
CK
LatchSS
ZZ
SW
SBW Latch
SS
Register
SS
Register
G
Pin Description
SA0-SA17 Address input
(X18 : SA0 - SA17, X36 : SA0 - SA16) GAsynchronous output enable
DQ0-DQ35 Data I/O
(X18 : DQ0 - DQ17, X36 : DQ0 - DQ35)
SS
Synchronous select
CK ,CK Differential input register clocks M1, M2 For boundary scan purpose
SW
Write enable. Global VREP(2) HSTL input reference voltage
SBWa
Write enable. Byte a (DQ0-DQ8) VDD Power supply (+3.3V)
SBWb
Write enable. Byte b (DQ9-DQ17) VSS Ground
SBWc
Write enable. Byte c (DQ18-DQ26) VDDQ Output power supply
SBWd
Write enable. Byte d (DQ27-DQ35) ZZ Asynchronous sleep mode
TMS, TDI, TCK IEEE 1149.1 test inputs(LVTTL levels) ZQ Output driver impedance control
TDO IEEE 1149.1 test output(LVTTL level) NC No connect
A65H73361/A65H83181 Series
PRELIMINARY (February, 1999, Version 2.0) 4AMIC Technology, Inc.
Clock Truth Table
KZZ
SS
SW
SBWa
SBWb
SBWc
SBWd
DQ(n) DQ(n+1) MODE
LÕHL L HXXXXXDOUT 0-35 Read Cycle ALL Bytes
LÕHLLLLHHHXDIN 0-8 Write Cycle 1st Byte
LÕHLLLHLH H XDIN 9-17 Write Cycle 2nd Byte
LÕHLLLH H LHXDIN 18-26 Write Cycle 3rd Byte
LÕHLLLHHHLXDIN 27-35 Write Cycle 4th Byte
LÕHLLLLLLLXDIN 0-35 Write Cycle ALL Byte
LÕHLLLHHHHXHigh-Z Abort Write Cycle
LÕHLHXXXXXXHigh-Z Deselect Cycle
XHXXXXXXHigh-Z High-Z Sleep Mode
Clock Truth Table
Operation
G
DQ
Read LDOUT 0-35
Read HHigh-Z
Sleep(ZZ=H) XHigh-Z
Write(
SW
=L) XDIN
Deselect(
SS
=H) XHigh-Z
A65H73361/A65H83181 Series
PRELIMINARY (February, 1999, Version 2.0) 5AMIC Technology, Inc.
Absolute Maximum Ratings*
Power Supply Voltage(VDD) . . . . . . . . . . -0.5V to +4.6V
Voltage Relative to GND for any Pin Except VDD(VIN,
VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V
Power Dissipation (PD) . . . . . . . . .. . . . . . . . . . .. . .1.0W
Operating Temperature (Topr). . . . . . . . .. . 0°C to 70°C
Storage Temperature (Tbias) . . . . . . .. .. . -10°C to 85°C
Storage Temperature(Tstg). . . . . . . . . . .-55°C to 125°C
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied and exposure the absolute maximum
rating conditions for extended periods may affect device
reliability.
Recommended DC Operating Conditions (TJ = 0 to 110°C)
Parameter Symbol Min. Typ. Max. Units Notes
Supply Voltage VDD 3.15 3.3 3.47 V1
Output Driver Supply Voltage VDDQ 1.4 1.5 1.6 V1
Input High Voltage VIH VREF+0.1 -VDDQ+0.3 V1, 2
Input Low Voltage VIL -0.3 -VREF-0.1 V1, 3
Input reference Voltage VREF 0.68 0.75 0.90 V1, 6
Clocks Signal Voltage VIN-CLK -0.3 -VDDQ+0.3 V1, 4
Differential Clocks Signal Voltage VDIF-CLK 0.1 -VDDQ+0.6 V1, 5
Clocks Common Mode Voltage VCM-CLK 0.55 -0.90 V1
Output Current IOUT -5 8 mA
1.All voltage reference to VSS. All VDD VDDQ and VSS pins must be connected.
2.VIH(Max)DC = VDD + 0.3V, VIH(Max)AC = VDD + 1.5V (pulse width ≤ 4.0ns).
3.VIL(Min)DC = -0.3V, VIL(Min)AC = -1.5 V (pulse width ≤ 4.0ns).
4.VIN-CLK specifies the maximum allowable DC excursions of each differential clock (CK , CK ).
5.VDIF-CLK specifies the minimum clock differential voltage required for switching.
6.Peak to Peak AC component superimposed on VREF may not exceed 5% of VREF.
A65H73361/A65H83181 Series
PRELIMINARY (February, 1999, Version 2.0) 6AMIC Technology, Inc.
DC Electrical Characteristics (TJ = 0 to +110°C, VDD = 3.3V ± 5%)
Parameter Symbol Min. Max. Units Notes
Average Power Supply Operating Current-X36
(IOUT = 0, VIN = VIH or VIL, ZZ & SS = VIL)lDD5
lDD6
lDD7
-
-TBD mA 1
Average Power Supply Operating Current-X18
(IOUT = 0, VIN = VIH or VIL, ZZ & SS = VIL)lDD5
lDD6
lDD7
-
-TBD mA 1
Power Supply Standby Current
(ZZ = VIH, All other inputs = VIH or VIL, Iout =0)
(
SS
= VIH, ZZ = VIL. All their inputs = VIH or VIL, lOUT = 0 )
Lsbzz
lSBss
-
-TBD mA
mA
1
1
Input Leakage Current
(VIN = VSS or VDD)lLI - ±1.0 µA
Output Leakage Current
(VOUT = VSS or VDD, DQ in High = Z) lLO - ±1.0 µA
Output High Level Voltage(lOH = -6mA @ VDDQ/2+0.3)VOH VDDQ-.4 VDDQ V2
Output Low Level Voltage(lOL = +6mA @ VDDQ/2-0.3)VOL VSS VSS+.4 V2
1. lOUT = Chip Output Current.
2.Minimum Impedance Output Driver.
A65H73361/A65H83181 Series
PRELIMINARY (February, 1999, Version 2.0) 7AMIC Technology, Inc.
Capacitance (TJ = 0 to +110°C, VDD = 3.3V ± 5%, f = 1MHz)
Parameter Symbol Test Condition Max. Units
Input Capacitance CIN VIN = 0V 3pF
Data I/O Capacitance (DQ0-DQ35) COUT VOUT= 0V 4pF
AC Input Characteristics
Item Symbol Min. Max. Notes
AC Input Logic High VIN (ac) TBD 3
AC Input Logic Low VIL (ac) TBD 3
Clock Input Differential Voltage VDIF (ac) TBD 2
VREF Peak to Peak ac Voltage VREF (ac) 5% VREF (dc) 1
1.The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
2.Performance is a function on VIH and VIL levels to clock inputs.
3.See AC input Definition figure on page 7.
AC Input Definition
VIH(ac)
VREF
VIL(ac)
A65H73361/A65H83181 Series
PRELIMINARY (February, 1999, Version 2.0) 8AMIC Technology, Inc.
Programmable Impedance Output Driver DC Electrical Characteristics
(TJ = 0 to +110°C, VDD = 3.3V ± 5%)
Parameter Symbol Min. Max. Units Notes
Output High Level Voltage VOH VDDQ/2 VDDQ V1
Output Low Level Voltage VOL VSS VDDQ/2 V2
1.lOH = (VDDQ/2)/(RQ/5) 7.5% @ VOH = VDDQ/2 For :150Ω ≤ RQ ≤350Ω
2.lOL = (VDDQ/2)/(RQ/5) 7.5% @ VOL = VDDQ/2 For :150Ω ≤RQ ≤ 350Ω
AC Test Conditions (TJ = 0 to +110°C, VDD = 3.3V ± 5%, VDDQ = 1.5V)
Parameter Symbol Conditions units Notes
Output High Level Voltage VIH 1.25 V
Output Low Level Voltage VIL 0.25 V
Input Reference Voltage VREF 0.75 V
Differential Clocks Voltage VDIF-CLK 0.75 V
Input Rise Time TR0.5 ns
Input Fall Time TF0.5 ns
I/O Signals Reference Level 0.75 V
Clocks Reference level Differential Cross Point V
Output Load Conditions 1
1.See AC Test Loading figure on page 8.
AC Test Loading
50
Ω
250
Ω
50
Ω
V
DDO
/2
DEVICE
UNDER
TEST
0.75V
V
REF
ZQ
A65H73361/A65H83181 Series
PRELIMINARY (February, 1999, Version 2.0) 9AMIC Technology, Inc.
AC Characteristics (TJ = 0 to +110°C, VDD = 3.3V ± 5%)
Parameter Symbol -5 -6 -7 Units Notes
Min. Max. Min. Max. Min. Max.
Cycle Time tKHKH 5-6.0 -7.0 -ns
Clock High Pulse Width tKHKL 1.5 -1.5 -1.5 -ns
Clock Low Pulse Width tKLKH 1.5 -1.5 -1.5 -ns
Clock to Output Valid tKHQV -2.5 3.0 -3.5 ns 1
Address Setup Time tAVKH 0.5 -0.5 -0.5 -ns 4
Address Hold Time tKHAX 1.0 -1.0 -1.0 -ns 4
Sync Select Setup Time tSVKH 0.5 -0.5 -0.5 -ns 4
Sync Select Hold Time tKHSX 1.0 -1.0 -1.0 -ns 4
Write Enables Setup Time tWVKH 0.5 -0.5 -0.5 -ns 4
Write Enables Hold Time tKHWX 1.0 -1.0 -1.0 -ns 4
Data In Setup Time tDVKH 0.5 -0.5 -0.5 -ns 4
Data In Hold Time tKHDX 1.0 -1.0 -1.0 -ns 4
Data Out Hold Time tKHQX 0.5 -0.5 -0.5 -ns 1
Clock High to Output High-z tKHQZ -2.5 -3.0 -3.5 ns 1, 2
Clock high to Output Active tXHQX4 1.0 -1.0 -1.0 -ns 1, 2
Output Enable to High-z tGHQZ -2.5 3.0 -3.5 ns 1, 2
Output Enable to Low-z tGLQX 0.5 -0.5 -0.5 -ns 1, 2
Output Enable to Output Valid tGLQV -2.5 -3.0 -3.5 ns 1
Output Enable Setup Time tGHKH 0.5 -0.5 -0.5 -ns 1, 3
Output Enable Hold Time tKHGX 1.5 -1.5 -1.5 -ns 1, 3
Sleep Mode Recovery Time tZZR 5-6-7-ns
Sleep Mode Enable Time tZZE -5-6-7ns
1.See AC Test Loading figure on page 8.
2.Transitions are measured ± 200mV from steady state voltage.
3.Output Driver Impedance update specifications for G induced updates. Write and Deselect cycles will also induce
Output Driver Updates during High-z.
4.Inuse conditions VIH, VIL, Trise, Tfall of inputs must be withim 20% of VIH, VIL, Trise, Tfall of Clock.
A65H73361/A65H83181 Series
PRELIMINARY (February, 1999, Version 2.0) 10 AMIC Technology, Inc.
Timing Diagram (Read and Deselect Cycles)
t
KHAX
t
KLKH
t
KHKL
t
KHKH
CK
SA
SS
SW
G
DQ
t
AVKH
A1 A2 A3 A4
t
KHSX
t
SVKH
t
WVKH
t
GHQZ
Q1 Q2 Q3
A3
Q4
t
GLQV
t
GLQX
t
KHQV
t
KHQX
t
KHQZ
t
KHQX4
t
KHQV
t
KHWX
A65H73361/A65H83181 Series
PRELIMINARY (February, 1999, Version 2.0) 11 AMIC Technology, Inc.
Timing Diagram (Read Write Cycles)
t
KHAX
t
KLKH
t
KHKL
t
KHKH
CK
SA
SS
SW
G
DQ
t
AVKH
A1 A2 A3 A4
t
KHSX
t
SVKH
Q3
A2
t
KHQV
t
KHQZ
t
KHQX4
t
KHDX
t
KHWX
t
XHWX
t
WVKH
SBW
t
WVKH
t
WVKH
t
KHWX
t
WVKH
t
XHWX
t
GHQZ
Q2
t
DVKH
t
KHDX
t
KHQV
t
DVKH
D4Q1 D2
NOTES:
1.D2 is the input data write in memory location A2.
2.Q2 is output data read from the write buffer, as a result of address A2 being a match from the last write cycle address.
A65H73361/A65H83181 Series
PRELIMINARY (February, 1999, Version 2.0) 12 AMIC Technology, Inc.
Timing Diagram (Sleep Mode)
t
ZZE
t
KHKH
t
ZZR
CK
zz
DQ
A65H73361/A65H83181 Series
PRELIMINARY (February, 1999, Version 2.0) 13 AMIC Technology, Inc.
IEEE 1149.1 TAP AND BOUNDARY SCAN
The SRAM provides a limited set of JTAG functions intended to test the interconnection between SRAM I/Os and printed
circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM core.
In conformance with IEEE std. 1149.1, the SRAM contains a TAP controller, Instruction register, Boundary Scan register,
Bypass register and ID register.
The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not
required.
Signal List
l TCK : Test Clock
l TMS : Test Mode Select
l TDI : Test Data In
l TDO : Test Data Out
Caution: TCK, TMS, TDI must be tied down, even if JTAG is not used.
JTAG Recommended DC Operating Conditions (TJ = 0 to 110 °C)
Parameter Symbol Min. Typ. Max. Units Notes
JTAG Input High Voltage VIH1 2.2 -VDD + 0.3 V1
JTAG Input Low Voltage VIL1 -03 -0.8 V1
JTAG Output High Level VOH1 2.4 - - V1,2
JTAG Output Low Level VOL1 - - 0.4 V1,3
1. All JTAG Inputs/Outputs are LVTTL Compatible only.
2. IOH1 = -8mA at 2.4V.
3. IOL1 = +8mA at 0.4V.
JTAG Recommended DC Operating Conditions (TJ = 0 to 110 °C)
Parameter Symbol Conditions Units Notes
Input Pulse High Level VIH1 3.0 V
Input Pulse Low Level VIL1 0.0 V
Input Rise Time TR1 2.0 ns
Input Fall Time TF1 2.0 ns
Input and Output Timing Reference Level 1.5 V1
1. See AC Test Loading on page 8.
A65H73361/A65H83181 Series
PRELIMINARY (February, 1999, Version 2.0) 14 AMIC Technology, Inc.
JTAG AC Characteristics (TJ = 0 to 110 °C, VDD = 3.3V ± 5%)
Parameter Symbol Min. Max. Units Notes
TCK Cycle Time tTHTH 20 -ns
TCK High Pulse Width tTHTL 7-ns
TCK Low Pulse Width tTLTH 7-ns
TMS Setup tMVTH 4-ns
TMS Hold tTHMX 4-ns
TDI Setup tDVTH 4-ns
TDI Hold tTHDX 4-ns
TCK Low to Valid Data tTLOV -7ns 1
1. See AC Test Loading on page 8.
JTAG Timing Diagram
t
THTL
t
TLTH
t
THTH
t
THMX
t
MVTH
t
THDX
t
DVTH
t
TLOV
TCK
TMS
TDI
TDO
A65H73361/A65H83181 Series
PRELIMINARY (February, 1999, Version 2.0) 15 AMIC Technology, Inc.
Scan Register Definition
Bit Size X18
Bit Size X 36
Instruction
3
3
Bypass 1 1
ID 32 32
Boundary Scan* 51 70
* The Boundary Scan chain consists of the following bits :
• 36 or 18 bits for Data Inputs Depending on X 18 or X 36 Configuration
• 15 bits for SA0 - SA14 for X 36, 16 bits for SA0 - SA15 for X 18
• 4 bits for SBWa - SBWd in X 36, 2 bits for SBWa and SBWb X 18
• 9 bits for CK, CK , ZQ, SS, G, SW , ZZ, M1 and M2
• 6 bits for Place Holders
* CK and CK clocks connect to a differential receiver that generates a single-ended clock signal. This signal and its
inverted value are used for Boundary Scan sampling.
ID Register Definition
Field Bit Number and Description
Part Revision Number
(31 : 28)
Device Density
and Configuration
(27 : 18)
Vender Definition
(17 : 12) Manufacture JEDEC
Code (11 : 1) Start
Bit (0)
256K X 18
0001
100 000 0110
000001
000 101 111 11
1
128K X 36 0001 011 100 1101 100001 000 101 111 11 1
Instruction Set
Code
Instruction
Notes
000
SAMPLE-Z
1
001 IDCODE 1
010 SAMPLE-Z 1
011 PRIVATE 3
100 SAMPLE 4
101 PRIVATE 3
110 PRIVATE 3
111 BYPASS 3
1. Places DQs in High-Z in order to sample all input data regardless of the other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data.
3. BYPASS register is initiated to Vss when BYPASS instruction is invoked. The BYPASS register also holds the last
serially loaded TDI when exiting the Shift DR state.
4. SAMPLE instruction does not place DQs in High-Z
List of IEEE 1149.1 standard violations :
• 7.2.1.b,e
• 7.7.1.a-f
• 10.1.1.b,e
• 10.7.1.a-d
• 6.1.1.d
A65H73361/A65H83181 Series
PRELIMINARY (February, 1999, Version 2.0) 16 AMIC Technology, Inc.
Boundary Scan Order (X 36)
Exit Order Signal Bump # Exit Order Signal Bump # Exit Order Signal Bump #
1M2 5R 25 DQ13 6F 49 DQ26 2H
2SA1 4P 26 DQ11 7E 50 DQ25 1H
3SA2 4T 27 DQ12 6E 51
SBWc
3G
4SA12 6R 28 DQ9 7D 52 ZQ 4D
5SA13 5T 29 DQ10 6D 53 SS 4E
6ZZ 7T 30 SA14 6A 54 NC 4G
7DQ1 6P 31 SA15 6C 55 NC 4H
8DQ0 7P 32 SA10 5C 56 SW 4M
9DQ3 6N 33 SA16 5A 57 SBWd 3L
10 DQ2 7N 34 NC 6B 58 DQ34 1K
11 DQ4 6M 35 SA11 5B 59 DQ35 2K
12 DQ6 6L 36 SA8 3B 60 DQ32 1L
13 DQ5 7L 37 NC 2B 61 DQ33 2L
14 DQ8 6K 38 SA7 3A 62 DQ31 2M
15 DQ7 7K 39 SA9 3C 63 DQ29 1N
16 SBWa 5L 40 SA6 2C 64 DQ30 2N
17 CK 4L 41 SA5 2A 65 DQ27 1P
18 CK 4K 42 DQ19 2D 66 DQ28 2P
19 G4F 43 DQ18 1D 67 SA3 3T
20 SBWb 5G 44 DQ21 2E 68 SA4 2R
21 DQ16 7H 45 DQ20 1E 69 SA0 4N
22 DQ17 6H 46 DQ22 2F 70 M1 3R
23 DQ14 7G 47 DQ24 2G
24 DQ15 6G 48 DQ23 1G
A65H73361/A65H83181 Series
PRELIMINARY (February, 1999, Version 2.0) 17 AMIC Technology, Inc.
Boundary Scan Order (X 18)
Exit Order Signal Bump # Exit Order Signal Bump #
1M2 5R 27 NC 2B
2SA12 6T 28 SA7 3A
3SA1 4P 29 SA9 3C
4SA13 6R 30 SA6 2C
5SA17 5T 31 SA5 2A
6ZZ 7T 32 DQ9 1D
7DQ0 7P 33 DQ12 2E
8DQ3 6N 43 DQ15 2G
9DQ6 6L 35 DQ16 1H
10 DQ7 7K 36 SBWb 3G
11 SBWa 5L 37 ZQ 4D
12 CK 4L 38
SS
4E
13 CK 4K 39 NC 4G
14 G4F 40 NC 4H
15 DQ8 6H 41
SW
4M
16 DQ5 7G 42 DQ17 2K
17 DQ4 6F 43 DQ14 1L
18 DQ2 7E 44 DQ13 2M
19 DQ1 6D 45 DQ11 1N
20 SA14 6A 46 DQ10 2P
21 SA15 6C 47 SA3 3T
22 SA10 5C 48 SA4 2R
23 SA16 5A 49 SA0 4N
24 NC 6B 50 SA2 2T
25 SA11 5B 51 M1 3R
26 SA8 3B
A65H73361/A65H83181 Series
PRELIMINARY (February, 1999, Version 2.0) 18 AMIC Technology, Inc.
TAP Controller State Machine
Test Logic Reset
Run Test Idle Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
1
0
01
1
0
0
1
0
1
1
0
1
0
0
0
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
0
1
0
1
1
0
0
0
0
0
1
11
1 1
A65H73361/A65H83181 Series
PRELIMINARY (February, 1999, Version 2.0) 19 AMIC Technology, Inc.
Ordering Information
Part Number Organization Speed Package
A65H83181P-5 256K x 18 2.5ns Access / 5 ns Cycle 7 x 17 PBGA
A65H83181P-6 256K x 18 3.0ns Access / 6 ns Cycle 7 x 17 PBGA
A65H83181P-7 256K x 18 3.5ns Access / 7 ns Cycle 7 x 17 PBGA
A65H73361P-5 128K x 36 2.5ns Access / 5 ns Cycle 7 x 17 PBGA
A65H73361P-6 128K x 36 3.0ns Access / 6 ns Cycle 7 x 17 PBGA
A65H73361P-7 128K x 36 3.5ns Access / 7 ns Cycle 7 x 17 PBGA
A65H73361/A65H83181 Series
PRELIMINARY (February, 1999, Version 2.0) 20 AMIC Technology, Inc.
Package Information
14.00
±
0.10
22.00±0.10
20.00±0.05
PIN #1 1.96 (Min)
2.36 (Max)
30°
±
2
1.00
±
0.05
0.60
±
0.10
20.32±0.10
-A-
-B- 7.62
±
0.10
7654321
0.30 SC A S B S
0.10 SC
12.00
±
0.05
1.56
0.56
1.270 TYP.
-C-
0.15 C
D
SEATING PLANE NOTE:
1. ALL DIMENSIONS ARE MILLIMETERS.
2. DETAILS OF MOLDED PLASTIC BODY MAY VARY FROM THAT SHOWN.
1.27 TYP.
119X
φ
0.80
±
0.1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U