R10DS0209EJ0200 Rev.2.00 Page 1 of 20
May 12, 2016
Data Sheet
R1EV5801MB Series
1M EEPROM (128-Kword × 8-bit)Ready/
Busy and RES function
Description
Renesas Electronics’ R1EV5801MB is an electrically erasable and programmable ROM organized as 131072-word 8-
bit. It has realized high speed, low power consumption and high reliability by employing advanced MONOS memory
technology and CMOS process and circuitry technology. It also has a 128-byte page programming function to make the
write operations faster.
Features
Single voltage supply: 2.7 V to 5.5 V
Access time:
150 ns (max) at Vcc=4.5 V to 5.5 V
250 ns (max) at Vcc=2.7 V to 5.5 V
Power dissipation
Active: 20 mW/MHz, (typ)
Standby: 110 W (max)
On-chip latches: address, data, CE, OE, WE
Automatic byte write: 10 ms (max)
Automatic page write (128 bytes): 10 ms (max)
Data polling and RDY/Busy
Data protection circuit on power on/off
Conforms to JEDEC byte-wide standard
Reliable CMOS with MONOS cell technology
104 or more erase/write cycles
10 or more years data retention
Software data protection
Write protection by RES pin
Temperature range: 40 to +85C
There are lead free products.
R10DS0209EJ0200
Rev.2.00
May 12, 2016
R1EV5801MB Series
R10DS0209EJ0200 Rev.2.00 Page 2 of 20
May 12, 2016
Ordering Information
Orderable Part Name Access time Package Shipping Container Quality
R1EV5801MBSDRDI#B0 150ns/250ns
525mil 32-pin plastic SOP
PRSP0032DC-A (FP-32DV)
Tube Max. 22 pcs/tube
Max. 880 pcs/inner box
R1EV5801MBTDRDI#B0 150ns/250ns
32-pin plastic TSOP
PTSA0032KD-A (TFP-32DAV)
Tray Max. 60 pcs/reel
Max. 600 pcs/inner box
Pin Arrangement
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
OE
A4
A5
A6
A7
A12
A14
A16
RDY/Busy
VCC
A15
RES
WE
A13
A8
A9
A11
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
RES
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
RDY/Busy
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
(Top view)
R1EV5801MBTDR Series
R1EV5801MBSDR Series
Pin Description
Pin name Function
A0 to A16 Address input
I/O0 to I/O7 Data input/output
OE Output enable
CE Chip enable
WE Write enable
VCC Power supply
VSS Ground
RDY/Busy Ready busy
RE
S
Reset
R1EV5801MB Series
R10DS0209EJ0200 Rev.2.00 Page 3 of 20
May 12, 2016
Block Diagram
V
V
OE
CE
A6
A0
A7
A16
WE
CC
SS
I/O0 I/O7
High voltage generator
Control logic and timing
Y decoder
X decoder
Address
buer and
latch
I/O buer
and
input latch
Y gating
Memory array
Data latch
RES
RDY/Bus
y
RES
to
to
to
Voltage detector
Operation Table
Operation CE OE WE RES RDY/Busy I/O
Read VIL V
IL V
IH V
H*1 High-Z Dout
Standby VIH *2 High-Z High-Z
Write VIL V
IH V
IL V
H High-Z to VOL Din
Deselect VIL V
IH V
IH V
H High-Z High-Z
Write Inhibit V
IH
V
IL 
Dat
a
Polling VIL V
IL V
IH V
H V
OL Dout (I/O7)
Program reset V
IL High-Z High-Z
Notes: 1. Refer to the recommended DC operating conditions.
2. : Don’t care
Absolute Maximum Ratings
Parameter Symbol Value Unit
Supply voltage relative to VSS V
CC 0.6 to +7.0 V
Input voltage relative to VSS Vin 0.5*1 to +7.0 V
Operating temperature range*2 Topr –40 to +85 C
Storage temperature range Tstg –55 to +125 C
Notes: 1. Vin min = 3.0 V for pulse width 50 ns
2. Including electrical characteristics and data retention
R1EV5801MB Series
R10DS0209EJ0200 Rev.2.00 Page 4 of 20
May 12, 2016
Recommended DC Operating Conditions
Parameter Symbol Min Typ Max Unit
Supply voltage VCC 2.7 3.0 5.5 V
V
SS 0 0 0 V
Input voltage*3 V
IL 0.3*1 0.8 V
VIH 1.9*2 V
CC + 0.3 V
V
H V
CC 0.5 V
CC + 1.0 V
Operating temperature Topr –40 +85 C
Notes: 1. VIL (min): 1.0 V for pulse width 50 ns
2. VIH (min): 2.2 V for VCC = 3.6 to 5.5 V
3. Refer to the recommended AC test condition during read and write operation.
DC Characteristics (Ta = -40 to +85C, VCC = 2.7 V to 5.5 V)
Parameter Symbol Min Typ Max Unit Test conditions
Input leakage current ILI 2*1 A VCC = 5.5 V, Vin =5.5 V
Output leakage current ILO 2 A VCC = 5.5 V, Vout = 5.5/0.4 V
Standby VCC current ICC1 20 A CE = VCC
ICC2 1 mA CE = VIH
Operating VCC current ICC3 15 mA
Iout = 0 mA, Duty = 100%,
Cycle = 1 µs, VCC = 5.5 V
  6 mA
Iout = 0 mA, Duty = 100%,
Cycle = 1 µs, VCC = 3.3 V
50 mA
Iout = 0 mA, Duty = 100%,
Cycle = 150 ns, VCC = 5.5 V
  15 mA
Iout = 0 mA, Duty = 100%,
Cycle = 250 ns, VCC = 3.3 V
Output low voltage VOL 0.4 V IOL = 2.1 mA
Output high voltage VOH V
CC 0.8 V IOH = 400 A
Notes: 1. ILI on RES: 100 A (max)
Capacitance (Ta = +25C, f = 1 MHz)
Parameter Symbol Min Typ Max Unit Test conditions
Input capacitance*1 Cin 6 pF Vin = 0 V
Output capacitance*1 Cout 12 pF Vout = 0 V
Note: 1. This parameter is periodically sampled and not 100 tested.
R1EV5801MB Series
R10DS0209EJ0200 Rev.2.00 Page 5 of 20
May 12, 2016
AC Characteristics
(Ta = -40 to +85C, VCC = 4.5 V to 5.5 V)
Test Conditions
Input pulse levels: 0.4 V to 2.4 V, 0 V to VCC (RES pin)
Input rise and fall time: 20 ns
Output load: 1TTL Gate +100 pF
Reference levels for measuring timing: 0.8 V, 2.0 V
Read Cycle
Parameter Symbol Min Max Unit Test conditions
Address to output delay tACC  150 ns CE = OE = VIL, WE = VIH
CE to output delay tCE  150 ns OE = VIL, WE = VIH
OE to output delay tOE 10 75 ns CE = VIL, WE = VIH
Address to output hold tOH 0  ns CE = OE = VIL, WE = VIH
OE (CE) high to output float*1 t
DF 0 50 ns CE = VIL, WE = VIH
RE
S
low to output float*1 tDFR 0 350 ns CE = OE = VIL, WE = VIH
RE
S
to output delay tRR 0 450 ns CE = OE = VIL, WE = VIH
Write Cycle
Parameter Symbol Min*2 Typ Max Unit Test conditions
Address setup time tAS 0   ns
Address hold time tAH 150   ns
CE to write setup time (WE controlled) tCS 0   ns
CE hold time (WE controlled) tCH 0   ns
WE to write setup time (CE controlled) tWS 0   ns
WE hold time (CE controlled) tWH 0   ns
OE to write setup time tOES 0   ns
OE hold time tOEH 0   ns
Data setup time tDS 100   ns
Data hold time tDH 10   ns
WE pulse width (WE controlled) tWP 0.250  30 µs
CE pulse width (CE controlled) tCW 0.250  30 µs
Data latch time tDL 300   ns
Byte load cycle tBLC 0.55  30 µs
Byte load window tBL 100   µs
Write cycle time tWC —  10*3 ms
Time to device busy tDB 120   ns
Write start time tDW 150*4   ns
Reset protect time tRP 100   µs
Reset high time*5 t
RES 1   µs
Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer
driven.
2. Use this device in longer cycle than this value.
3. tWC must be longer than this value unless polling techniques or RDY/Busy are used. This device automatically
completes the internal write operation within this value.
4. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy are used.
5. This parameter is sampled and not 100 tested.
6. A7 through A16 are page addresses and these addresses are latched at the first falling edge of WE.
7. A7 through A16 are page addresses and these addresses are latched at the first falling edge of CE.
8. See AC read characteristics.
R1EV5801MB Series
R10DS0209EJ0200 Rev.2.00 Page 6 of 20
May 12, 2016
AC Characteristics
(Ta = -40 to +85C, VCC = 2.7 V to 5.5 V)
Test Conditions
Input pulse levels: 0.4 V to 2.4 V, 0 V to VCC (RES pin)
Input rise and fall time: 20 ns
Output load: 1TTL Gate +100 pF
Reference levels for measuring timing: 0.8 V, 2.0 V
Read Cycle
Parameter Symbol Min Max Unit Test conditions
Address to output delay tACC 250 ns CE = OE = VIL, WE = VIH
CE to output delay tCE 250 ns OE = VIL, WE = VIH
OE to output delay tOE 10 120 ns CE = VIL, WE = VIH
Address to output hold tOH 0 ns CE = OE = VIL, WE = VIH
OE (CE) high to output float*1 t
DF 0 50 ns CE = VIL, WE = VIH
RE
S
low to output float*1 tDFR 0 350 ns CE = OE = VIL, WE = VIH
RE
S
to output delay tRR 0 600 ns CE = OE = VIL, WE = VIH
Write Cycle
Parameter Symbol Min*2 Typ Max Unit Test conditions
Address setup time tAS 0 ns
Address hold time tAH 150 ns
CE to write setup time (WE controlled) tCS 0 ns
CE hold time (WE controlled) tCH 0 ns
WE to write setup time (CE controlled) tWS 0 ns
WE hold time (CE controlled) tWH 0 ns
OE to write setup time tOES 0 ns
OE hold time tOEH 0 ns
Data setup time tDS 100 ns
Data hold time tDH 10 ns
WE pulse width (WE controlled) tWP 0.250 30 µs
CE pulse width (CE controlled) tCW 0.250 30 µs
Data latch time tDL 750 ns
Byte load cycle tBLC 1.0 30 s
Byte load window tBL 100 s
Write cycle time tWC 10*3 ms
Time to device busy tDB 120 ns
Write start time tDW 250*4 ns
Reset protect time tRP 100 s
Reset high time*5 t
RES 1 s
Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer
driven.
2. Use this device in longer cycle than this value.
3. tWC must be longer than this value unless polling techniques or RDY/Busy are used. This device automatically
completes the internal write operation within this value.
4. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy are used.
5. This parameter is sampled and not 100 tested.
6. A7 through A16 are page addresses and these addresses are latched at the first falling edge of WE.
7. A7 through A16 are page addresses and these addresses are latched at the first falling edge of CE.
8. See AC read characteristics.
R1EV5801MB Series
R10DS0209EJ0200 Rev.2.00 Page 7 of 20
May 12, 2016
Timing Waveforms
Read Timing Waveform
Address
CE
OE
WE
Data Out
High
Data out valid
t
ACC
t
CE
t
OE
t
OH
t
DF
t
RR
t
DFR
RES
R1EV5801MB Series
R10DS0209EJ0200 Rev.2.00 Page 8 of 20
May 12, 2016
Byte Write Timing Waveform (1) (WE Controlled)
Address
CE
WE
OE
Din
RDY/Busy
t
WC
t
CH
t
AH
t
CS
t
AS
t
WP
t
OEH
t
BL
t
OES
t
DS
t
DH
t
DB
t
RP
RES
V
CC
t
RES
High-Z High-Z
t
DW
R1EV5801MB Series
R10DS0209EJ0200 Rev.2.00 Page 9 of 20
May 12, 2016
Byte Write Timing Waveform (2) (CE Controlled)
Address
CE
WE
OE
Din
RDY/Busy
tWC
tAH
tWS
tAS
tOEH
tWH
tOES
tDS tDH
tDB
tRP
RES
VCC
tCW
tBL
tDW
tRES
High-Z High-Z
R1EV5801MB Series
R10DS0209EJ0200 Rev.2.00 Page 10 of 20
May 12, 2016
Page Write Timing Waveform (1) (WE Controlled)
Address
A0 to A16
WE
CE
OE
Din
RDY/Busy
t
AS
t
AH
t
BL
t
WC
t
OEH
t
DH
t
DB
t
OES
t
RP
t
RES
RES
V
CC
t
CH
t
CS
t
WP
t
DL
t
BLC
t
DS
t
DW
High-Z High-Z
*6
R1EV5801MB Series
R10DS0209EJ0200 Rev.2.00 Page 11 of 20
May 12, 2016
Page Write Timing Waveform (2) (CE Controlled)
Address
A0 to A16
WE
CE
OE
Din
RDY/Busy
t
AS
t
AH
t
BL
t
WC
t
OEH
t
DH
t
DB
t
OES
t
RP
t
RES
RES
V
CC
t
WH
t
WS
t
CW
t
DL
t
BLC
t
DS
t
DW
High-Z High-Z
*6
R1EV5801MB Series
R10DS0209EJ0200 Rev.2.00 Page 12 of 20
May 12, 2016
Data Polling Timing Waveform
t
CE
t
OEH
t
WC
t
DW
t
OES
Address
CE
WE
OE
I/O7
t
OE
Din X
An An
Dout XDout X
*8
*8
R1EV5801MB Series
R10DS0209EJ0200 Rev.2.00 Page 13 of 20
May 12, 2016
Toggle bit
This device provide another function to determine the internal programming cycle. If the EEPROM is set to read mode
during the internal programming cycle, I/O6 will charge from “1” to “0” (toggling) for each read. When the internal
programming cycle is finished, toggling of I/O6 will stop and the device can be accessible for next read or program.
Notes: 1. I/O6 beginning state is “1”.
2. I/O6 ending state will vary.
3. See AC read characteristics.
4. Any location can be used, but the address must be fixed.
Toggle bit Waveform
WE
t
OES
OE
CE
Dout
I/O6 Dout Dout Dout
Next mode
t
OE
t
CE
t
DW
t
WC
t
OEH
*1 *2 *2
Address
*3
*3
*4
Din
R1EV5801MB Series
R10DS0209EJ0200 Rev.2.00 Page 14 of 20
May 12, 2016
Software Data Protection Timing Waveform (1) (in protection mode)
V
CE
WE
Address
Data
5555
AA
AAAA or
2AAA
55
5555
A0
tBLC tWC
CC
Write address
Write data
Software Data Protection Timing Waveform (2) (in non-protection mode)
V
CE
WE
Address
Data
t
WC
CC
Normal active
mode
5555
AA
AAAA
or
2AAA
55
5555
80
5555
AA
AAAA
or
2AAA
55
5555
20
R1EV5801MB Series
R10DS0209EJ0200 Rev.2.00 Page 15 of 20
May 12, 2016
Functional Description
Automatic Page Write
Page-mode write feature allows 1 to 128 bytes of data to be written into the EEPROM in a single write cycle.
Following the initial byte cycle, an additional 1 to 127 bytes can be written in the same manner. Each additional byte
load cycle must be started within 30 µs from the preceding falling edge of WE or CE. When CE or WE is kept high for
100 µs after data input, the EEPROM enters write mode automatically and the input data are written into the EEPROM.
Data Polling
Data polling allows the status of the EEPROM to be determined. If EEPROM is set to read mode during a write cycle,
an inversion of the last byte of data to be loaded outputs from I/O7 to indicate that the EEPROM is performing a write
operation.
RDY/Busy Signal
RDY/Busy signal also allows status of the EEPROM to be determined. The RDY/Busy signal has high impedance
except in write cycle and is lowered to VOL after the first write signal. At the end of write cycle, the RDY/Busy signal
changes state to high impedance.
RES Signal
When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping RES low
when VCC is switched. RES should be high during read and programming because it doesn’t provide a latch function.
V
Program inhibit
CC
RES
Program inhibit
Read inhibit Read inhibit
WE, CE Pin Operation
During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising edge of
WE or CE.
Write/Erase Endurance and Data Retention Time
The endurance is 104 cycles (1% cumulative failure rate). The data retention time is more than 10 years.
R1EV5801MB Series
R10DS0209EJ0200 Rev.2.00 Page 16 of 20
May 12, 2016
Data Protection
To prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 20 ns or less in
program mode.
1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation
During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to programming
mode by mistake. Be careful not to allow noise of a width of more than 20 ns on the control pins.
WE
CE
OE
V
0 V
V
0 V
20 ns max
IH
IH
R1EV5801MB Series
R10DS0209EJ0200 Rev.2.00 Page 17 of 20
May 12, 2016
2. Data Protection at VCC On/Off
When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as a trigger
and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the EEPROM
must be kept in an unprogrammable state while the CPU is in an unstable state.
Note: The EEPROM should be kept in unprogrammable state during VCC on/off by using CPU RESET signal.
VCC
CPU
RESET
Unprogrammable Unprogrammable
**
2.1 Protection by RES
The unprogrammable state can be realized by that the CPU’s reset signal inputs directly to the EEPROM’s RES
pin. RES should be kept VSS level during VCC on/off.
The EEPROM brakes off programming operation when RES becomes low, programming operation doesn’t
finish correctly in case that RES falls low during programming operation. RES should be kept high for 10 ms
after the last data input.
VCC
RES
WE
or CE 100 µs min 10 ms min
1 µs min
Program inhibit Program inhibit
R1EV5801MB Series
R10DS0209EJ0200 Rev.2.00 Page 18 of 20
May 12, 2016
3. Software data protection
To prevent unintentional programming, this device has the software data protection (SDP) mode. The SDP is
enabled by inputting the following 3 bytes code and write data. SDP is not enabled if only the 3 bytes code is input.
To program data in the SDP enable mode, 3 bytes code must be input before write data.
Data
AA
↓
55
↓
A0
↓
Write data }
Address
5555
↓
AAAA or 2AAA
↓
5555
↓
Write address Normal data input
The SDP mode is disabled by inputting the following 6 bytes code. Note that, if data is input in the SDP disable
cycle, data can not be written.
Data
AA
↓
55
↓
80
↓
AA
↓
55
↓
20
Address
5555
↓
AAAA or 2AAA
↓
5555
↓
5555
↓
AAAA or 2AAA
↓
5555
The software data protection is not enabled at the shipment.
Note: There are some differences between Renesas Electronics’ and other company’s for enable/disable sequence of
software data protection. If there are any questions , please contact with Rnesas Electronics’ sales offices.
R1EV5801MB Series
R10DS0209EJ0200 Rev.2.00 Page 19 of 20
May 12, 2016
Orderable part Number Guide
R1EV58 01MB SD R I #B0
Parallel EEPROM
Memory density
01MB : 1Mbit
256B : 256Kbit
064B : 64Kbit
Package type
DA : DiLP-28pin
SD : SOP-32pin
SC : SOP-28pin
TD : TSOP-32pin
TC : TSOP-28pin
Function
R : Reset function suported
N : Reset function not suported
Quality grade
I :
–40 to +85 deg C (Industry)
D
Packaging, Environmental
#S0 :
#B0 :
Embossed tape (Pb free)
Tray or Tube (Pb free)
Orderable part Number Guide of Parallel EEPROM
Access time
D : 150ns/250ns
B : 85/100/120ns
R1EV5801MB Series
R10DS0209EJ0200 Rev.2.00 Page 20 of 20
May 12, 2016
Package Dimensions
R1EV5801MBSD Series (PRSP0032DC-A / Previous code: FP-32DV)
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
1.00
0.10
1.27
13.84 14.44
0.400.32
20.95
MaxNom
Min
Dimension in Millimeters
Symbol
Reference
3.00
1.000.800.60
0.20
11.30
0.270.150.05
0.48
0.38
0.270.220.17
14.14
8°0°
0.15
1.42
20.45
Previous Code
JEITA Package Code RENESAS Code
PRSP0032DC-A FP-32D/FP-32DV
MASS[Typ.]
1.3gP-SOP32-11.3x20.45-1.27
Terminal cross section
c
Detail F
L
S
S
y
F
*1
*2
*3
Mx
1
Index mark
16
1732
A
Ze
E
D
e
HE
L
A
D
E
A2
A1
bp
b1
c
x
y
Z
L1
c1
θ
θ
L1
b1
c1
bp
A1
bp
HE
R1EV5801MBTD Series (PTSA0032KD-A / Previous Code: TFP-32DAV)
F
Detail F
Terminal cross section
NOTE)
1. DIMENSION"*1"AND"*2(Nom)"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
Dimension in Millimeters
A
1
L
1
L
θ
A
1
L
1
b
p
b
1
c
1
c
L
θ
A
*1
D
H
D
*2
E
b
p
M
S
y
x
e
S
Z
*3
17
32
1
16
Min Nom Max
Reference
Symbol
12.40
8.00 8.20
0.18
1.20
0.13
0.20
0.08
0.300.220.14
0.220.17
0.125
0.50
0.12
14.2014.0013.80
0.60
0.45
0.10
0.08
0.50
0.80
0.40
50
L1
Z
c1
θ
b1
A1
A2
A
bp
HD
E
D
L
y
x
e
c
Index mark
0.26g
MASS[Typ.]
Previous Code
TFP-32DA/TFP-32DAV
RENESAS Code
JEITA Package Code
P-TSOP(1)32-8x12.4-0.50 PTSA0032KD-A
All trademarks and registered trademarks are the property of their respective owners.
C - 1
Revision History R1EV5801MB Series Data Sheet
Rev. Date
Description
Page Summary
0.01 Oct 17, 2013 Initial issue
0.02 Oct 18, 2013 19 Orderable part Number Guide: Deletion of A and C for access time.
1.00 Jun 09, 2014 — Delete preliminary
2.00 May 12, 2016 4 DC Operating Conditions: Addition of Note 3.
5 AC Characteristics: Addition of Max. 30us for WE pulse width (tWP)
AC Characteristics: Addition of Max. 30us for CE pulse width (tCW)
6 AC Characteristics: Addition of Max. 30us for WE pulse width (tWP)
AC Characteristics: Addition of Max. 30us for CE pulse width (tCW)
Notice
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