FN3658 Rev.8.00 Page 1 of 19
Dec 11, 2019
FN3658
Rev.8.00
Dec 11, 2019
HIP4080A
80V/2.5A Peak, High Frequency Full Bridge FET Driver
DATASHEET
The HIP4080A is a high frequency, medium voltage Full
Bridge N-Channel FET driver IC, available in 20 lead plastic
SOIC and DIP packages. The HIP4080A includes an input
comparator, used to facilitate the “hysteresis” and PWM
modes of operation. Its HEN (high enable) lead can force
current to freewheel in the bottom two external power
MOSFETs, maintaining the upper power MOSFETs off.
Since it can switch at frequencies up to 1MHz, the HIP4080A
is well suited for driving Voice Coil Motors, switching power
amplifiers and power supplies.
HIP4080A can also drive medium voltage brush motors, and
two HIP4080As can be used to drive high performance
stepper motors, since the short minimum “on-time” can
provide fine micro-stepping capability.
Short propagation delays of approximately 55ns maximize
control loop crossover frequencies and dead-times which
can be adjusted to near zero to minimize distortion, resulting
in precise control of the driven load.
The similar HIP4081A IC allows independent control of all 4
FETs in a Full Bridge configuration.
The Application Note for the HIP4080A is AN9404.
Features
Drives N-Channel FET Full Bridge Including High Side
Chop Capability
Bootstrap Supply Max Voltage to 95VDC
Drives 1000pF Load at 1MHz in Free Air at +50°C with
Rise and Fall Times of Typically 10ns
User-Programmable Dead Time
Charge-Pump and Bootstrap Maintain Upper Bias
Supplies
DIS (Disable) Pin Pulls Gates Low
Input Logic Thresholds Compatible with 5V to 15V Logic
Levels
Very Low Power Consumption
Undervoltage Protection
Pb-Free (RoHS Compliant)
Applications
Medium/Large Voice Coil Motors
Full Bridge Power Supplies
Switching Power Amplifiers
High Performance Motor Controls
Noise Cancellation Systems
Battery Powered Vehicles
Peripherals
U.P.S.
Pinout
HIP4080A
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART
NUMBER
TEMPERATURE
RANGE (°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
HIP4080AIPZ
(Note 1)
-40 to +85 20 Ld PDIP E20.3
HIP4080AIBZ
(Note 1)
-40 to +85 20 Ld SOIC M20.3
NOTES:
1. Intersil Pb-Free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which is compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-Free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-
free requirements of IPC/JEDEC J Std-020B.
2. Add “T” suffix for Tape and Reel packing option. HIP4080AIP not
available in Tape and Reel.
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
BHB
HEN
DIS
VSS
OUT
IN+
HDEL
IN-
LDEL
AHB
BHO
BLO
BLS
VDD
BHS
VCC
ALS
ALO
AHS
AHO
HIP4080A
FN3658 Rev.8.00 Page 2 of 19
Dec 11, 2019
Application Block Diagram
Functional Block Diagram (1/2 HIP4080A)
80V
GND
HIP4080A
GND
12V
LOAD
BHO
BHS
BLO
ALO
AHS
AHO
IN-
IN+
DIS
HEN
CHARGE
PUMP
VDD
HEN
DIS
OUT
IN+
IN_
HDEL
LDEL
VSS
TURN-ON
DELAY
+
-
TURN-ON
DELAY
DRIVER
DRIVER
AHB
AHO
AHS
VCC
ALO
ALS CBF
TO VDD (PIN 16)
CBS
DBS
HIGH VOLTAGE BUS 80VDC
+12VDC
LEVEL SHIFT
AND LATCH
14
10
11
12
15
13
16
2
3
5
6
7
8
9
4
BIAS
SUPPLY
UNDER-
VOLTAGE
HIP4080A
FN3658 Rev.8.00 Page 3 of 19
Dec 11, 2019
Typical Application (Hysteresis Mode Switching)
6V
80V
12V
12V
DIS
IN
GND
6V
GND
+
-
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1BHB
HEN
DIS
VSS
OUT
IN+
HDEL
IN-
LDEL
AHB
BHO
BLO
BLS
VDD
BHS
VCC
ALS
ALO
AHS
AHO
LOAD
HIP4080A/HIP4080
HIP4080A
FN3658 Rev.8.00 Page 4 of 19
Dec 11, 2019
Absolute Maximum Ratings Thermal Information
Supply Voltage, VDD and VCC. . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
Voltage on AHS, BHS . . . -6.0V (Transient) to 80V (25°C to 125°C)
Voltage on AHS, BHS . . . -6.0V (Transient) to 70V (-55°C to 125°C)
Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient)
Voltage on AHB, BHB . . . . . . VAHS, BHS -0.3V to VAHS, BHS +VDD
Voltage on ALO, BLO. . . . . . . . . . . . VALS, BLS -0.3V to VCC +0.3V
Voltage on AHO, BHO . . . . . . VAHS, BHS -0.3V to VAHB, BHB +0.3V
Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA
Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns
All Voltages relative to VSS, unless otherwise specified.
Operating Conditions
Supply Voltage, VDD and VCC. . . . . . . . . . . . . . . . . . +9.5V to +15V
Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V
Voltage on AHB, BHB . . . . . . . VAHS, BHS +5V to VAHS, BHS +15V
Input Current, HDEL and LDEL . . . . . . . . . . . . . . . .-500µA to -50µA
Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C
Thermal Resistance (Typical, Note 3) JA (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Maximum Power Dissipation at +85°C
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .470mW
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530mW
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Max. Junction Temperature. . . . . . . . . . . . . . . . . . +125°C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300°C
(For SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and
TA = +25°C, Unless Otherwise Specified
PARAMETERS SYMBOL TEST CONDITIONS
TJ = +25°C
TJ = - 40°C
TO +125°C
UNITSMIN TYP MAX MIN MAX
SUPPLY CURRENTS AND CHARGE PUMPS
VDD Quiescent Current IDD IN- = 2.5V, Other Inputs = 0V 8 11 14 7 14 mA
VDD Operating Current IDDO Outputs switching f = 500kHz, No Load 9 12 15 8 15 mA
VCC Quiescent Current ICC IN- = 2.5V, Other Inputs = 0V,
IALO = IBLO = 0
- 25 80 - 100 A
VCC Operating Current ICCO f = 500kHz, No Load 1 1.25 2.0 0.8 3 mA
AHB, BHB Quiescent Current -
Qpump Output Current
IAHB, IBHB IN- = 2.5V, Other Inputs = 0V,
IAHO =I
BHO = 0,
VDD = VCC =VAHB = VBHB = 10V
-50 -25 -11 -60 -10 A
AHB, BHB Operating Current IAHBO,
IBHBO
f = 500kHz, No Load 0.62 1.2 1.5 0.5 1.9 mA
AHS, BHS, AHB, BHB Leakage Current IHLK VBHS = VAHS = 80V,
VAHB = VBHB = 93V
- 0.02 1.0 - 10 A
AHB-AHS, BHB-BHS Qpump
Output Voltage
VAHB -
VAHS
VBHB -
VBHS
IAHB = IAHB = 0, No Load 11.5 12.6 14.0 10.5 14.5 V
INPUT COMPARATOR PINS: IN+, IN-, OUT
Offset Voltage VOS Over Common Mode Voltage Range -10 0 +10 -15 +15 mV
Input Bias Current IIB 00.52 0 4 A
Input Offset Current IOS -1 0 +1-2+2A
Input Common Mode Voltage Range CMVR 1 - VDD
-1.5
1V
DD
-1.5
V
HIP4080A
FN3658 Rev.8.00 Page 5 of 19
Dec 11, 2019
Voltage Gain AVOL 10 25 - 10 - V/mV
OUT High Level Output Voltage VOH IN+ > IN-, IOH = -250AV
DD
-0.4
--V
DD
- 0.5
-V
OUT Low Level Output Voltage VOL IN+ < IN-, IOL = +250A - -0.4-0.5V
Low Level Output Current IOL VOUT = 6V 6.5 14 19 6 20 mA
High Level Output Current IOH VOUT = 6V -17 -10 -3 -20 -2.5 mA
INPUT PINS: DIS
Low Level Input Voltage VIL Full Operating Conditions - - 1.0 - 0.8 V
High Level Input Voltage VIH Full Operating Conditions 2.5 - - 2.7 - V
Input Voltage Hysteresis -35- - -mV
Low Level Input Current IIL VIN = 0V, Full Operating Conditions -130 -100 -75 -135 -65 A
High Level Input Current IIH VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 A
INPUT PINS: HEN
Low Level Input Voltage VIL Full Operating Conditions - - 1.0 - 0.8 V
High Level Input Voltage VIH Full Operating Conditions 2.5 - - 2.7 - V
Input Voltage Hysteresis -35- - -mV
Low Level Input Current IIL VIN = 0V, Full Operating Conditions -260 -200 -150 -270 -130 A
High Level Input Current IIH VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 A
TURN-ON DELAY PINS: LDEL AND HDEL
LDEL, HDEL Voltage VHDEL,VI
HDEL = ILDEL = -100A 4.9 5.1 5.3 4.8 5.4 V
GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO
Low Level Output Voltage VOL IOUT = 100mA 0.7 0.85 1.0 0.5 1.1 V
High Level Output Voltage VCC - VOH IOUT = -100mA 0.8 0.95 1.1 0.5 1.2 V
Peak Pullup Current IO+V
OUT = 0V 1.7 2.6 3.8 1.4 4.1 A
Peak Pulldown Current IO-V
OUT = 12V 1.7 2.4 3.3 1.3 3.6 A
Under Voltage, Rising Threshold UV+ 8.1 8.8 9.4 8.0 9.5 V
Under Voltage, Falling Threshold UV- 7.6 8.3 8.9 7.5 9.0 V
Under Voltage, Hysteresis HYS 0.25 0.4 0.65 0.2 0.7 V
Electrical Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and
TA = +25°C, Unless Otherwise Specified (Continued)
PARAMETERS SYMBOL TEST CONDITIONS
TJ = +25°C
TJ = - 40°C
TO +125°C
UNITSMIN TYP MAX MIN MAX
HIP4080A
FN3658 Rev.8.00 Page 6 of 19
Dec 11, 2019
Switching Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K,
CL = 1000pF, and TA = +25°C, Unless Otherwise Specified
PARAMETERS SYMBOL TEST CONDITIONS
TJ = +25°C
TJ = - 40°C
TO +125°C
UNITSMIN TYP MAX MIN MAX
Lower Turn-off Propagation Delay (IN+/IN- to ALO/BLO) TLPHL - 40 70 - 90 ns
Upper Turn-off Propagation Delay (IN+/IN- to AHO/BHO) THPHL -5080-110ns
Lower Turn-on Propagation Delay (IN+/IN- to ALO/BLO) TLPLH - 40 70 - 90 ns
Upper Turn-on Propagation Delay (IN+/IN- to AHO/BHO) THPLH - 70 110 - 140 ns
Rise Time TR- 10 25 - 35 ns
Fall Time TF- 10 25 - 35 ns
Turn-on Input Pulse Width TPWIN-ON 50 - - 50 - ns
Turn-off Input Pulse Width TPWIN-OFF 40 - - 40 - ns
Disable Turn-off Propagation Delay
(DIS - Lower Outputs)
TDISLOW - 45 75 - 95 ns
Disable Turn-off Propagation Delay
(DIS - Upper Outputs)
TDISHIGH -5585-105ns
Disable to Lower Turn-on Propagation Delay
(DIS - ALO and BLO)
TDLPLH - 45 70 - 90 ns
Refresh Pulse Width (ALO and BLO) TREF-PW 240 380 500 200 600 ns
Disable to Upper Enable (DIS - AHO and BHO) TUEN - 480 630 - 750 ns
HEN-AHO, BHO Turn-off, Propagation Delay THEN-PHL RHDEL = RLDEL = 10K - 40 70 - 90 ns
HEN-AHO, BHO Turn-on, Propagation Delay THEN-PLH RHDEL = RLDEL = 10K - 60 90 - 110 ns
TRUTH TABLE
INPUT OUTPUT
IN+ > IN- HEN U/V DIS ALO AHO BLO BHO
X XX10000
0 0001000
1 1000110
0 1001001
1 0000010
X X1X0000
HIP4080A
FN3658 Rev.8.00 Page 7 of 19
Dec 11, 2019
Pin Descriptions
PIN
NUMBER SYMBOL DESCRIPTION
1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap
diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30A out of this pin to
maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
2 HEN High-side Enable input. Logic level input that when low overrides IN+/IN- (Pins 6 and 7) to put AHO and BHO drivers
(Pins 11 and 20) in low output state. When HEN is high AHO and BHO are controlled by IN+/IN- inputs. The pin can
be driven by signal levels of 0V to 15V (no greater than VDD).
3 DIS DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs.
When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to
15V (no greater than VDD).
4V
SS Chip negative supply, generally will be ground.
5 OUT OUTput of the input control comparator. This output can be used for feedback and hysteresis.
6 IN+ Noninverting input of control comparator. If IN+ is greater than IN- (Pin 7) then ALO and BHO are low level outputs
and BLO and AHO are high level outputs. If IN+ is less than IN- then ALO and BHO are high level outputs and BLO
and AHO are low level outputs. DIS (Pin 3) high level will override IN+/IN- control for all outputs. HEN (Pin 2) low level
will override IN+/IN- control of AHO and BHO. When switching in four quadrant mode, dead time in a half bridge leg
is controlled by HDEL and LDEL (Pins 8 and 9).
7 IN- Inverting input of control comparator. See IN+ (Pin 6) description.
8 HDEL High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of
both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no
shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V.
9 LDEL Low-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of
both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no
shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V.
10 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap
diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30A out of this pin to
maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
11 AHO A High-side Output. Connect to gate of A High-side power MOSFET.
12 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET.
14 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET.
15 VCC Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap diodes.
16 VDD Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4).
17 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET.
18 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET.
19 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of
bootstrap capacitor to this pin.
20 BHO B High-side Output. Connect to gate of B High-side power MOSFET.
HIP4080A
FN3658 Rev.8.00 Page 8 of 19
Dec 11, 2019
Timing Diagrams
FIGURE 1. BISTATE MODE
FIGURE 2. HIGH SIDE CHOP MODE
FIGURE 3. DISABLE FUNCTION
0
HEN
ALO
AHO
BLO
TLPHL
THPLH
TR
(10% - 90%)
TF
(90% - 10%)
TDT
U/V = DIS
THPHL TLPLH
TDT
1
IN+ > IN-
BHO
0
HEN
ALO
AHO
BLO
U/V = DIS
THEN-PLH
THEN-PHL
IN+ > IN-
BHO
HEN
AHO
BLO
U/V or DIS
TREF-PW
TDLPLH
IN+ > IN-
BHO
TDIS
TUEN
ALO
HIP4080A
FN3658 Rev.8.00 Page 9 of 19
Dec 11, 2019
Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL =
100K, and TA = +25°C, Unless Otherwise Specified
FIGURE 4. QUIESCENT IDD SUPPLY CURRENT vs VDD
SUPPLY VOLTAGE
FIGURE 5. IDDO NO-LOAD IDD SUPPLY CURRENT vs
FREQUENCY (kHz)
FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs
FREQUENCY (LOAD = 1000pF)
FIGURE 7. ICCO, NO-LOAD ICC SUPPLY CURRENT vs
FREQUENCY (kHz) TEMPERATURE
FIGURE 8. IAHB, IBHB NO-LOAD FLOATING SUPPLY BIAS
CURRENT vs FREQUENCY
FIGURE 9. COMPARATOR INPUT CURRENT IL vs
TEMPERATURE AT VCM = 5V
810 12 14
2.0
4.0
6.0
8.0
10.0
12.0
14.0
IDD SUPPLY CURRENT (mA)
VDD SUPPLY VOLTAGE (V)
13
12.5
12.0
11.5
11.0
10.5
10 200 400 600 800 1000
IDD SUPPLY CURRENT (mA)
SWITCHING FREQUENCY (kHz)
0100 200 300 400 500 600 700 800 900 1000
0.0
5.0
10.0
15.0
20.0
FLOATING SUPPLY BIAS CURRENT (mA)
SWITCHING FREQUENCY (kHz)
0 100 200 300 400 500 600 700 800 900 1000
0.0
1.0
2.0
3.0
4.0
5.0
ICC SUPPLY CURRENT (mA)
SWITCHING FREQUENCY (kHz)
+75°C
+25°C
+125°C
-40°C
0°C
0.5
1
1.5
2
2.5
200
600 800 1000
0 400
FLOATING SUPPLY BIAS CURRENT (mA)
SWITCHING FREQUENCY (kHz)
-40 -20 020 40 60 80 100 120
0.5
1.0
COMPARATOR INPUT CURRENT (A)
JUNCTION TEMPERATURE (°C)
HIP4080A
FN3658 Rev.8.00 Page 10 of 19
Dec 11, 2019
FIGURE 10. DIS LOW LEVEL INPUT CURRENT IIL vs
TEMPERATURE
FIGURE 11. HEN LOW LEVEL INPUT CURRENT IIL vs
TEMPERATURE
FIGURE 12. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP
VOLTAGE vs TEMPERATURE
FIGURE 13. UPPER DISABLE TURN-OFF PROPAGATION
DELAY TDISHIGH vs TEMPERATURE
FIGURE 14. DISABLE TO UPPER ENABLE TUEN
PROPAGATION DELAY vs TEMPERATURE
FIGURE 15. LOWER DISABLE TURN-OFF PROPAGATION
DELAY TDISLOW vs TEMPERATURE
Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL =
100K, and TA = +25°C, Unless Otherwise Specified (Continued)
-50 -25 025 50 75 100 125
-120
-110
-100
-90
LOW LEVEL INPUT CURRENT (A)
JUNCTION TEMPERATURE (°C)
-40 -20 020 40 60 80 100 120
-230
-220
-210
-200
-190
-180
LOW LEVEL INPUT CURRENT (A)
JUNCTION TEMPERATURE (°C)
-40 -20 020 40 60 80 100 120
10.0
11.0
12.0
13.0
14.0
15.0
NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
-40 -20 020 40 60 80 100 120
30
40
50
60
70
80
PROPAGATION DELAY (ns)
JUNCTION TEMPERATURE (°C)
425
450
475
500
525
-50 -25 025 50 75 100 125 150
JUNCTION TEMPERATURE (°C)
PROPAGATION DELAY (ns)
-40 -20 020 40 60 80 100 120
30
40
50
60
70
80
PROPAGATION DELAY (ns)
JUNCTION TEMPERATURE (°C)
HIP4080A
FN3658 Rev.8.00 Page 11 of 19
Dec 11, 2019
Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL =
10K, and TA = +25°C, Unless Otherwise Specified
FIGURE 16. TREF-PW REFRESH PULSE WIDTH vs
TEMPERATURE
FIGURE 17. DISABLE TO LOWER ENABLE TDLPLH
PROPAGATION DELAY vs TEMPERATURE
FIGURE 18. UPPER TURN-OFF PROPAGATION DELAY THPHL
vs TEMPERATURE
FIGURE 19. UPPER TURN-ON PROPAGATION DELAY THPLH
vs TEMPERATURE
FIGURE 20. LOWER TURN-OFF PROPAGATION DELAY TLPHL
vs TEMPERATURE
FIGURE 21. LOWER TURN-ON PROPAGATION DELAY TLPLH
vs TEMPERATURE
350
375
400
425
450
-50 -25 025 50 75 100 125 150
REFRESH PULSE WIDTH (ns)
JUNCTION TEMPERATURE (°C)
-40 -20 020 40 60 80 100 120
20
30
40
50
60
70
80
PROPAGATION DELAY (ns)
JUNCTION TEMPERATURE (°C)
-40 -20 020 40 60 80 100 120
40.0
50.0
60.0
70.0
80.0
90.0
PROPAGATION DELAY (ns)
JUNCTION TEMPERATURE (°C)
-40 -20 020 40 60 80 100 120
40.0
50.0
60.0
70.0
80.0
90.0
PROPAGATION DELAY (ns)
JUNCTION TEMPERATURE (°C)
-40 -20 020 40 60 80 100 120
40.0
50.0
60.0
70.0
80.0
90.0
PROPAGATION DELAY (ns)
JUNCTION TEMPERATURE (°C)
-40 -20 020 40 60 80 100 120
40.0
50.0
60.0
70.0
80.0
90.0
PROPAGATION DELAY (ns)
JUNCTION TEMPERATURE (°C)
HIP4080A
FN3658 Rev.8.00 Page 12 of 19
Dec 11, 2019
Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL =
100K, and TA = +25°C, Unless Otherwise Specified
FIGURE 22. GATE DRIVE FALL TIME TF vs TEMPERATURE FIGURE 23. GATE DRIVE RISE TIME TR vs TEMPERATURE
FIGURE 24. VLDEL, VHDEL VOLTAGE vs TEMPERATURE FIGURE 25. HIGH LEVEL OUTPUT VOLTAGE, VCC - VOH vs
BIAS SUPPLY AND TEMPERATURE AT 100A
FIGURE 26. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS
SUPPLY AND TEMPERATURE AT 100A
FIGURE 27. PEAK PULLDOWN CURRENT IO- BIAS SUPPLY
VOLTAGE
-40 -20 020 40 60 80 100 120
8.5
9.5
10.5
11.5
12.5
13.5
GATE DRIVE FALL TIME (ns)
JUNCTION TEMPERATURE (°C)
-40 -20 020 40 60 80 100 120
8.5
9.5
10.5
11.5
12.5
13.5
TURN-ON RISE TIME (ns)
JUNCTION TEMPERATURE (°C)
-40 -20 020 40 60 80 100 120
4.0
4.5
5.0
5.5
6.0
HDEL, LDEL INPUT VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
10 12 14
0
250
500
750
1000
1250
1500
VCC - VOH (mV)
BIAS SUPPLY VOLTAGE (V)
+75°C
+25°C
+125°C
-40°C
0°C
12 14
0
250
500
750
1000
1250
1500
VOL (mV)
BIAS SUPPLY VOLTAGE (V)
10
+75°C
+25°C
+125°C
-40°C
0°C
6 7 8 9 10 11 12 13 14 15 16
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
GATE DRIVE SINK CURRENT (A)
VCC, VDD, VAHG, VBHB (V)
HIP4080A
FN3658 Rev.8.00 Page 13 of 19
Dec 11, 2019
FIGURE 28. PEAK PULLUP CURRENT IO+ vs SUPPLY
VOLTAGE
FIGURE 29. LOW VOLTAGE BIAS CURRENT IDD AND ICC
(LESS QUIESCENT COMPONENT) vs
FREQUENCY AND GATE LOAD CAPACITANCE
FIGURE 30. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs
FREQUENCY AND BUS VOLTAGE
FIGURE 31. UNDERVOLTAGE LOCKOUT vs TEMPERATURE
FIGURE 32. MINIMUM DEAD-TIME vs DEL RESISTANCE
Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL =
100K, and TA = +25°C, Unless Otherwise Specified (Continued)
6 7 8 9 10 11 12 13 14 15 16
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
GATE DRIVE SINK CURRENT (A)
VCC, VDD, VABH, VBHB (V)
110 100 10002 5 20 50 500200
0.1
1
10
100
500
50
5
0.5
200
20
2
0.2
LOW VOLTAGE BIAS CURRENT (mA)
SWITCHING FREQUENCY (kHz)
3,000
1,000
10,000
100
10 100 100020 50 200 500
10
100
1000
20
50
200
500
LEVEL-SHIFT CURRENT (A)
SWITCHING FREQUENCY (kHz)
8.2
8.4
8.6
8.8
9
50 25 025 50 75 100 125 150
UV+
UV-
TEMPERATURE (°C)
BIAS SUPPLY VOLTAGE, VDD (V)
10 50 100 150 200 250
0
30
60
90
120
150
HDEL/LDEL RESISTANCE (k)
DEAD-TIME (ns)
FN3658 Rev.8.00 Page 14 of 19
Dec 11, 2019
HIP4080A
FN3658 Rev.8.00 Page 15 of 19
Dec 11, 2019
HIP4080A
HIP4080A
FN3658 Rev.8.00 Page 16 of 19
Dec 11, 2019
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make
sure you have the latest revision.
DATE REVISION CHANGE
Dec 11, 2019 FN3658.8 Removed retired parts.
Added Revision History section.
Updated POD M20.3 to the latest revision. Changes are as follows:
Rev 2. - Removed “u” symbol from drawing (overlaps the “a” on Side View).
Rev 3. - Top View:
Corrected "7.50 BSC" to "7.60/7.40" (no change from rev 2; error was introduced in conversion)
Changed "10.30 BSC" to "10.65/10.00" (no change from rev 2; error was introduced in conversion)
Side View:
Changed "12.80 BSC" to "13.00/12.60" (no change from rev 2; error was introduced in conversion)
Changed "2.65 max" to "2.65/2.35" (no change from rev 2; error was introduced in conversion)
Changed Note 1 from "ANSI Y14.5M-1982." to "ASME Y14.5M-1994"
Updated to new POD format by moving dimensions from table onto drawing and adding land pattern
Updated disclaimer.
HIP4080A
FN3658 Rev.8.00 Page 17 of 19
Dec 11, 2019
Package Outline Drawings
NOTES:
3. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
4. Dimensioning and tolerancing per ANSI Y14.5M-1982.
5. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.
6. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
7. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
8. E and are measured with the leads constrained to be perpen-
dicular to datum .
9. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
10. B1 maximum dimensions do not include dambar protrusions. Dam-
bar protrusions shall not exceed 0.010 inch (0.25mm).
11. N is the maximum number of terminal positions.
12. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA
-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E20.3 (JEDEC MS-001-AD ISSUE D)
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE (PDIP)
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.55 1.77 8
C 0.008 0.014 0.204 0.355 -
D 0.980 1.060 24.89 26.9 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N20 209
Rev. 0 12/93
HIP4080A
FN3658 Rev.8.00 Page 18 of 19
Dec 11, 2019
M20.3
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC)
Rev 3, 2/11
7. The lead width as measured 0.36mm (0.14 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
13.00
0.75
0.25 x 45°
0.32
0.23
MAX
1.27
0.40
10.65
10.00
7.60
7.40
20
123
INDEX
AREA
2.65
2.35
0.30
MAX
BSC
1.27
0.35
0.49
0.25 (0.10) MC SBMA 0.10 (0.004)
0.25 (0.10) MB
M
12
1.27 BSC
(9.40mm)
SEATING PLANE
(0.60)
(2.00)
2
20
3
3
5
7
NOTES:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension does not include mold flash, protrusions or gate
3. Dimension does not include interlead lash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
5. Dimension is the length of terminal for soldering to a substrate.
6. Terminal numbers are shown for reference only.
8. Controlling dimension: MILLIMETER.
9. Dimensions in ( ) for reference only.
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
(0.024 inch)
10. JEDEC reference drawing number: MS-013-AC.
12.60
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