DATASHEET HIP4080A FN3658 Rev.8.00 Dec 11, 2019 80V/2.5A Peak, High Frequency Full Bridge FET Driver The HIP4080A is a high frequency, medium voltage Full Bridge N-Channel FET driver IC, available in 20 lead plastic SOIC and DIP packages. The HIP4080A includes an input comparator, used to facilitate the "hysteresis" and PWM modes of operation. Its HEN (high enable) lead can force current to freewheel in the bottom two external power MOSFETs, maintaining the upper power MOSFETs off. Since it can switch at frequencies up to 1MHz, the HIP4080A is well suited for driving Voice Coil Motors, switching power amplifiers and power supplies. HIP4080A can also drive medium voltage brush motors, and two HIP4080As can be used to drive high performance stepper motors, since the short minimum "on-time" can provide fine micro-stepping capability. Features * Drives N-Channel FET Full Bridge Including High Side Chop Capability * Bootstrap Supply Max Voltage to 95VDC * Drives 1000pF Load at 1MHz in Free Air at +50C with Rise and Fall Times of Typically 10ns * User-Programmable Dead Time * Charge-Pump and Bootstrap Maintain Upper Bias Supplies * DIS (Disable) Pin Pulls Gates Low * Input Logic Thresholds Compatible with 5V to 15V Logic Levels Short propagation delays of approximately 55ns maximize control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in precise control of the driven load. * Very Low Power Consumption The similar HIP4081A IC allows independent control of all 4 FETs in a Full Bridge configuration. Applications * Full Bridge Power Supplies Ordering Information TEMPERATURE RANGE (C) HIP4080AIPZ (Note 1) -40 to +85 HIP4080AIBZ (Note 1) -40 to +85 * Pb-Free (RoHS Compliant) * Medium/Large Voice Coil Motors The Application Note for the HIP4080A is AN9404. PART NUMBER * Undervoltage Protection * Switching Power Amplifiers PACKAGE PKG. (RoHS Compliant) DWG. # 20 Ld PDIP E20.3 * High Performance Motor Controls * Noise Cancellation Systems * Battery Powered Vehicles 20 Ld SOIC M20.3 NOTES: 1. Intersil Pb-Free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-Free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pbfree requirements of IPC/JEDEC J Std-020B. 2. Add "T" suffix for Tape and Reel packing option. HIP4080AIP not available in Tape and Reel. FN3658 Rev.8.00 Dec 11, 2019 * Peripherals * U.P.S. Pinout HIP4080A (PDIP, SOIC) TOP VIEW BHB 1 HEN 2 19 BHS DIS 3 18 BLO 20 BHO VSS 4 17 BLS OUT 5 16 VDD IN+ 6 15 VCC IN- 7 14 ALS HDEL 8 13 ALO LDEL 9 12 AHS AHB 10 11 AHO Page 1 of 19 HIP4080A Application Block Diagram 80V 12V BHO BHS HEN LOAD BLO DIS HIP4080A IN+ ALO AHS IN- AHO GND Functional Block Diagram GND (1/2 HIP4080A) HIGH VOLTAGE BUS 80VDC AHB 10 UNDERVOLTAGE CHARGE PUMP LEVEL SHIFT AND LATCH DRIVER 11 CBS AHS VDD 16 HEN AHO 12 2 TURN-ON DELAY DBS DIS 3 15 OUT 5 IN+ 6 IN_ 7 HDEL 8 LDEL 9 DRIVER + - TURN-ON DELAY TO VDD (PIN 16) VCC ALO 13 ALS CBF +12VDC BIAS SUPPLY 14 VSS 4 FN3658 Rev.8.00 Dec 11, 2019 Page 2 of 19 HIP4080A Typical Application (Hysteresis Mode Switching) 80V BHO 20 2 HEN BHS 19 DIS 3 DIS BLO 18 4 VSS 5 OUT 6 IN+ 6V 7 ININ 8 HDEL HIP4080A/HIP4080 1 BHB 12V 9 LDEL LOAD BLS 17 VDD 16 VCC 15 12V ALS 14 ALO 13 AHS 12 10 AHB AHO 11 GND + 6V GND FN3658 Rev.8.00 Dec 11, 2019 Page 3 of 19 HIP4080A Absolute Maximum Ratings Thermal Information Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on AHS, BHS . . . -6.0V (Transient) to 80V (25C to 125C) Voltage on AHS, BHS . . . -6.0V (Transient) to 70V (-55C to 125C) Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient) Voltage on AHB, BHB . . . . . . VAHS, BHS -0.3V to VAHS, BHS +VDD Voltage on ALO, BLO. . . . . . . . . . . . VALS, BLS -0.3V to VCC +0.3V Voltage on AHO, BHO . . . . . . VAHS, BHS -0.3V to VAHB, BHB +0.3V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns All Voltages relative to VSS, unless otherwise specified. Thermal Resistance (Typical, Note 3) JA (C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Power Dissipation at +85C SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .470mW PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .530mW Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Operating Max. Junction Temperature. . . . . . . . . . . . . . . . . . +125C Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300C (For SOIC - Lead Tips Only) Operating Conditions Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . +9.5V to +15V Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V Voltage on AHB, BHB . . . . . . . VAHS, BHS +5V to VAHS, BHS +15V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . -500A to -50A Operating Ambient Temperature Range . . . . . . . . . .-40C to +85C CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and TA = +25C, Unless Otherwise Specified TJ = - 40C TO +125C TJ = +25C PARAMETERS MIN TYP MAX MIN MAX UNITS IN- = 2.5V, Other Inputs = 0V 8 11 14 7 14 mA Outputs switching f = 500kHz, No Load 9 12 15 8 15 mA IN- = 2.5V, Other Inputs = 0V, IALO = IBLO = 0 - 25 80 - 100 A f = 500kHz, No Load 1 1.25 2.0 0.8 3 mA IN- = 2.5V, Other Inputs = 0V, IAHO = IBHO = 0, VDD = VCC =VAHB = VBHB = 10V -50 -25 -11 -60 -10 A IAHBO, IBHBO f = 500kHz, No Load 0.62 1.2 1.5 0.5 1.9 mA IHLK VBHS = VAHS = 80V, VAHB = VBHB = 93V - 0.02 1.0 - 10 A IAHB = IAHB = 0, No Load 11.5 12.6 14.0 10.5 14.5 V Over Common Mode Voltage Range -10 0 +10 -15 +15 mV IIB 0 0.5 2 0 4 A IOS -1 0 +1 -2 +2 A CMVR 1 - VDD -1.5 1 VDD -1.5 V SYMBOL TEST CONDITIONS SUPPLY CURRENTS AND CHARGE PUMPS VDD Quiescent Current IDD VDD Operating Current IDDO VCC Quiescent Current ICC VCC Operating Current ICCO AHB, BHB Quiescent Current Qpump Output Current AHB, BHB Operating Current IAHB, IBHB AHS, BHS, AHB, BHB Leakage Current AHB-AHS, BHB-BHS Qpump Output Voltage VAHB VAHS VBHB VBHS INPUT COMPARATOR PINS: IN+, IN-, OUT Offset Voltage Input Bias Current Input Offset Current Input Common Mode Voltage Range FN3658 Rev.8.00 Dec 11, 2019 VOS Page 4 of 19 HIP4080A Electrical Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and TA = +25C, Unless Otherwise Specified (Continued) TJ = - 40C TO +125C TJ = +25C PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS 10 25 - 10 - V/mV Voltage Gain AVOL OUT High Level Output Voltage VOH IN+ > IN-, IOH = -250A VDD -0.4 - - VDD - 0.5 - V OUT Low Level Output Voltage VOL IN+ < IN-, IOL = +250A - - 0.4 - 0.5 V Low Level Output Current IOL VOUT = 6V 6.5 14 19 6 20 mA High Level Output Current IOH VOUT = 6V -17 -10 -3 -20 -2.5 mA Low Level Input Voltage VIL Full Operating Conditions - - 1.0 - 0.8 V High Level Input Voltage VIH Full Operating Conditions 2.5 - - 2.7 - V - 35 - - - mV INPUT PINS: DIS Input Voltage Hysteresis Low Level Input Current IIL VIN = 0V, Full Operating Conditions -130 -100 -75 -135 -65 A High Level Input Current IIH VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 A Low Level Input Voltage VIL Full Operating Conditions - - 1.0 - 0.8 V High Level Input Voltage VIH Full Operating Conditions 2.5 - - 2.7 - V - 35 - - - mV INPUT PINS: HEN Input Voltage Hysteresis Low Level Input Current IIL VIN = 0V, Full Operating Conditions -260 -200 -150 -270 -130 A High Level Input Current IIH VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 A IHDEL = ILDEL = -100A 4.9 5.1 5.3 4.8 5.4 V TURN-ON DELAY PINS: LDEL AND HDEL LDEL, HDEL Voltage VHDEL,V GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO Low Level Output Voltage VOL IOUT = 100mA 0.7 0.85 1.0 0.5 1.1 V High Level Output Voltage VCC - VOH IOUT = -100mA 0.8 0.95 1.1 0.5 1.2 V Peak Pullup Current IO+ VOUT = 0V 1.7 2.6 3.8 1.4 4.1 A Peak Pulldown Current IO- VOUT = 12V 1.7 2.4 3.3 1.3 3.6 A Under Voltage, Rising Threshold UV+ 8.1 8.8 9.4 8.0 9.5 V Under Voltage, Falling Threshold UV- 7.6 8.3 8.9 7.5 9.0 V Under Voltage, Hysteresis HYS 0.25 0.4 0.65 0.2 0.7 V FN3658 Rev.8.00 Dec 11, 2019 Page 5 of 19 HIP4080A Switching Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K, CL = 1000pF, and TA = +25C, Unless Otherwise Specified TJ = - 40C TO +125C TJ = +25C PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Lower Turn-off Propagation Delay (IN+/IN- to ALO/BLO) TLPHL - 40 70 - 90 ns Upper Turn-off Propagation Delay (IN+/IN- to AHO/BHO) THPHL - 50 80 - 110 ns Lower Turn-on Propagation Delay (IN+/IN- to ALO/BLO) TLPLH - 40 70 - 90 ns Upper Turn-on Propagation Delay (IN+/IN- to AHO/BHO) THPLH - 70 110 - 140 ns Rise Time TR - 10 25 - 35 ns Fall Time TF - 10 25 - 35 ns Turn-on Input Pulse Width TPWIN-ON 50 - - 50 - ns Turn-off Input Pulse Width TPWIN-OFF 40 - - 40 - ns Disable Turn-off Propagation Delay (DIS - Lower Outputs) TDISLOW - 45 75 - 95 ns Disable Turn-off Propagation Delay (DIS - Upper Outputs) TDISHIGH - 55 85 - 105 ns TDLPLH - 45 70 - 90 ns TREF-PW 240 380 500 200 600 ns TUEN - 480 630 - 750 ns Disable to Lower Turn-on Propagation Delay (DIS - ALO and BLO) Refresh Pulse Width (ALO and BLO) Disable to Upper Enable (DIS - AHO and BHO) HEN-AHO, BHO Turn-off, Propagation Delay THEN-PHL RHDEL = RLDEL = 10K - 40 70 - 90 ns HEN-AHO, BHO Turn-on, Propagation Delay THEN-PLH RHDEL = RLDEL = 10K - 60 90 - 110 ns TRUTH TABLE INPUT OUTPUT IN+ > IN- HEN U/V DIS ALO AHO BLO BHO X X X 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 1 1 0 0 0 0 0 1 0 X X 1 X 0 0 0 0 FN3658 Rev.8.00 Dec 11, 2019 Page 6 of 19 HIP4080A Pin Descriptions PIN NUMBER SYMBOL 1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. 2 HEN High-side Enable input. Logic level input that when low overrides IN+/IN- (Pins 6 and 7) to put AHO and BHO drivers (Pins 11 and 20) in low output state. When HEN is high AHO and BHO are controlled by IN+/IN- inputs. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). 3 DIS DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). 4 VSS Chip negative supply, generally will be ground. 5 OUT OUTput of the input control comparator. This output can be used for feedback and hysteresis. 6 IN+ Noninverting input of control comparator. If IN+ is greater than IN- (Pin 7) then ALO and BHO are low level outputs and BLO and AHO are high level outputs. If IN+ is less than IN- then ALO and BHO are high level outputs and BLO and AHO are low level outputs. DIS (Pin 3) high level will override IN+/IN- control for all outputs. HEN (Pin 2) low level will override IN+/IN- control of AHO and BHO. When switching in four quadrant mode, dead time in a half bridge leg is controlled by HDEL and LDEL (Pins 8 and 9). 7 IN- Inverting input of control comparator. See IN+ (Pin 6) description. 8 HDEL High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V. 9 LDEL Low-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V. 10 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. 11 AHO A High-side Output. Connect to gate of A High-side power MOSFET. 12 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET. 14 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET. 15 VCC Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap diodes. 16 VDD Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4). 17 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET. 18 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET. 19 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 20 BHO B High-side Output. Connect to gate of B High-side power MOSFET. FN3658 Rev.8.00 Dec 11, 2019 DESCRIPTION Page 7 of 19 HIP4080A Timing Diagrams THPHL TDT TLPLH U/V = DIS 0 HEN 1 IN+ > INALO AHO BLO BHO TLPHL THPLH TR TF (10% - 90%) (90% - 10%) TDT FIGURE 1. BISTATE MODE THEN-PHL THEN-PLH U/V = DIS 0 HEN IN+ > INALO AHO BLO BHO FIGURE 2. HIGH SIDE CHOP MODE TDLPLH TDIS TREF-PW U/V or DIS HEN IN+ > INALO AHO BLO BHO TUEN FIGURE 3. DISABLE FUNCTION FN3658 Rev.8.00 Dec 11, 2019 Page 8 of 19 HIP4080A Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and TA = +25C, Unless Otherwise Specified 13 14.0 IDD SUPPLY CURRENT (mA) IDD SUPPLY CURRENT (mA) 12.5 12.0 10.0 8.0 6.0 4.0 12.0 11.5 11.0 10.5 2.0 8 10 12 10 14 200 400 600 800 SWITCHING FREQUENCY (kHz) VDD SUPPLY VOLTAGE (V) FIGURE 4. QUIESCENT IDD SUPPLY CURRENT vs VDD SUPPLY VOLTAGE 1000 FIGURE 5. IDDO NO-LOAD IDD SUPPLY CURRENT vs FREQUENCY (kHz) +125C 20.0 ICC SUPPLY CURRENT (mA) FLOATING SUPPLY BIAS CURRENT (mA) 5.0 15.0 10.0 5.0 0.0 +75C 4.0 +25C 0C 3.0 -40C 2.0 1.0 0.0 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 SWITCHING FREQUENCY (kHz) FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs FREQUENCY (LOAD = 1000pF) 400 500 600 700 800 900 1000 FIGURE 7. ICCO, NO-LOAD ICC SUPPLY CURRENT vs FREQUENCY (kHz) TEMPERATURE 2.5 COMPARATOR INPUT CURRENT (A) FLOATING SUPPLY BIAS CURRENT (mA) 300 SWITCHING FREQUENCY (kHz) 2 1.5 1 0.5 0 200 400 600 800 SWITCHING FREQUENCY (kHz) 1000 FIGURE 8. IAHB, IBHB NO-LOAD FLOATING SUPPLY BIAS CURRENT vs FREQUENCY FN3658 Rev.8.00 Dec 11, 2019 1.0 0.5 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (C) FIGURE 9. COMPARATOR INPUT CURRENT IL vs TEMPERATURE AT VCM = 5V Page 9 of 19 HIP4080A Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and TA = +25C, Unless Otherwise Specified (Continued) -180 LOW LEVEL INPUT CURRENT (A) LOW LEVEL INPUT CURRENT (A) -90 -100 -110 -120 -50 -25 0 25 50 75 100 -190 -200 -210 -220 -230 -40 125 -20 0 JUNCTION TEMPERATURE (C) 40 60 80 100 120 FIGURE 11. HEN LOW LEVEL INPUT CURRENT IIL vs TEMPERATURE 80 15.0 PROPAGATION DELAY (ns) NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V) FIGURE 10. DIS LOW LEVEL INPUT CURRENT IIL vs TEMPERATURE 14.0 13.0 12.0 11.0 70 60 50 40 30 10.0 -40 -20 0 20 40 60 80 100 -40 120 -20 JUNCTION TEMPERATURE (C) 20 40 60 80 100 120 FIGURE 13. UPPER DISABLE TURN-OFF PROPAGATION DELAY TDISHIGH vs TEMPERATURE 80 PROPAGATION DELAY (ns) 525 500 475 450 425 -50 0 JUNCTION TEMPERATURE (C) FIGURE 12. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP VOLTAGE vs TEMPERATURE PROPAGATION DELAY (ns) 20 JUNCTION TEMPERATURE (C) 70 60 50 40 30 -25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE (C) FIGURE 14. DISABLE TO UPPER ENABLE TUEN PROPAGATION DELAY vs TEMPERATURE FN3658 Rev.8.00 Dec 11, 2019 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (C) FIGURE 15. LOWER DISABLE TURN-OFF PROPAGATION DELAY TDISLOW vs TEMPERATURE Page 10 of 19 HIP4080A Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K, and TA = +25C, Unless Otherwise Specified 80 70 PROPAGATION DELAY (ns) REFRESH PULSE WIDTH (ns) 450 425 400 375 60 50 40 30 350 -50 -25 0 25 50 75 100 20 -40 125 150 -20 JUNCTION TEMPERATURE (C) 40 60 80 100 120 FIGURE 17. DISABLE TO LOWER ENABLE TDLPLH PROPAGATION DELAY vs TEMPERATURE 90.0 PROPAGATION DELAY (ns) 90.0 PROPAGATION DELAY (ns) 20 JUNCTION TEMPERATURE (C) FIGURE 16. TREF-PW REFRESH PULSE WIDTH vs TEMPERATURE 80.0 70.0 60.0 50.0 80.0 70.0 60.0 50.0 40.0 40.0 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (C) -40 120 0 20 40 60 80 100 120 FIGURE 19. UPPER TURN-ON PROPAGATION DELAY THPLH vs TEMPERATURE 90.0 PROPAGATION DELAY (ns) 90.0 80.0 70.0 60.0 50.0 80.0 70.0 60.0 50.0 40.0 40.0 -40 -20 JUNCTION TEMPERATURE (C) FIGURE 18. UPPER TURN-OFF PROPAGATION DELAY THPHL vs TEMPERATURE PROPAGATION DELAY (ns) 0 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (C) 120 FIGURE 20. LOWER TURN-OFF PROPAGATION DELAY TLPHL vs TEMPERATURE FN3658 Rev.8.00 Dec 11, 2019 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (C) 120 FIGURE 21. LOWER TURN-ON PROPAGATION DELAY TLPLH vs TEMPERATURE Page 11 of 19 HIP4080A Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 13.5 13.5 12.5 12.5 TURN-ON RISE TIME (ns) GATE DRIVE FALL TIME (ns) 100K, and TA = +25C, Unless Otherwise Specified 11.5 10.5 9.5 8.5 -40 -20 0 20 40 60 80 100 11.5 10.5 9.5 8.5 -40 120 -20 0 JUNCTION TEMPERATURE (C) FIGURE 22. GATE DRIVE FALL TIME TF vs TEMPERATURE 60 80 100 120 1500 1250 5.5 VCC - VOH (mV) HDEL, LDEL INPUT VOLTAGE (V) 40 FIGURE 23. GATE DRIVE RISE TIME TR vs TEMPERATURE 6.0 5.0 1000 750 -40C 0C 500 4.5 +25C 250 4.0 -40 -20 0 20 40 60 80 100 +75C +125C 0 10 120 12 JUNCTION TEMPERATURE (C) FIGURE 25. HIGH LEVEL OUTPUT VOLTAGE, VCC - VOH vs BIAS SUPPLY AND TEMPERATURE AT 100A 3.5 GATE DRIVE SINK CURRENT (A) 1500 1250 1000 750 -40C 500 0C +25C 250 0 14 BIAS SUPPLY VOLTAGE (V) FIGURE 24. VLDEL, VHDEL VOLTAGE vs TEMPERATURE VOL (mV) 20 JUNCTION TEMPERATURE (C) +75C +125C 10 2.5 2.0 1.5 1.0 0.5 0.0 12 BIAS SUPPLY VOLTAGE (V) 14 FIGURE 26. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS SUPPLY AND TEMPERATURE AT 100A FN3658 Rev.8.00 Dec 11, 2019 3.0 6 7 8 9 10 11 12 13 14 15 16 VCC, VDD, VAHG, VBHB (V) FIGURE 27. PEAK PULLDOWN CURRENT IO- BIAS SUPPLY VOLTAGE Page 12 of 19 HIP4080A Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and TA = +25C, Unless Otherwise Specified (Continued) 500 LOW VOLTAGE BIAS CURRENT (mA) GATE DRIVE SINK CURRENT (A) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 6 7 8 9 10 11 12 13 14 15 200 100 10,000 50 3,000 20 1,000 10 100 5 2 1 0.5 0.2 0.1 16 1 2 VCC, VDD, VABH, VBHB (V) FIGURE 28. PEAK PULLUP CURRENT IO+ vs SUPPLY VOLTAGE 10 20 50 100 200 500 1000 FIGURE 29. LOW VOLTAGE BIAS CURRENT IDD AND ICC (LESS QUIESCENT COMPONENT) vs FREQUENCY AND GATE LOAD CAPACITANCE 9 BIAS SUPPLY VOLTAGE, VDD (V) 1000 500 LEVEL-SHIFT CURRENT (A) 5 SWITCHING FREQUENCY (kHz) 200 100 50 20 UV+ 8.8 8.6 UV8.4 8.2 10 10 20 50 100 200 500 1000 50 25 0 25 SWITCHING FREQUENCY (kHz) 50 75 100 125 FIGURE 30. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCY AND BUS VOLTAGE FIGURE 31. UNDERVOLTAGE LOCKOUT vs TEMPERATURE 150 DEAD-TIME (ns) 120 90 60 30 0 10 50 100 150 200 HDEL/LDEL RESISTANCE (k) 250 FIGURE 32. MINIMUM DEAD-TIME vs DEL RESISTANCE FN3658 Rev.8.00 Dec 11, 2019 150 TEMPERATURE (C) Page 13 of 19 HIP4080A FN3658 Rev.8.00 Dec 11, 2019 IN2 IN1 POWER SECTION +12V B+ 1 U2 2 2 R29 JMPR1 + C6 JMPR5 CONTROL LOGIC SECTION HIP4080A/81A U1 OUT/BLI U2 12 JMPR2 4 V SS 5 OUT/BLI IN+/ALI U2 6 JMPR3 HEN/BHI CD4069UB 11 U2 JMPR4 3 IN-/AHI 3 2 2 CW CD4069UB 9 LDEL 10 AHB R34 R33 10 CR2 1 C8 Q1 3 C4 2 R22 1 BLS 17 16 V DD 1 CW 1 AHS AHO Q3 3 L1 AO 2 +12V R23 6 IN+/ALI V 15 CC 7 IN-/AHI ALS 14 8 HDEL ALO 13 CD4069UB 5 R21 1 BHB BHO 20 2 HEN/BHI BHS 19 3 DIS BLO 18 CD4069UB 13 DRIVER SECTION 1 Q2 L2 C1 BO C2 3 2 12 R24 11 1 CR1 Q4 3 C3 CX CY R30 R31 C5 COM ALS BLS NOTES: 1. DEVICE CD4069UB PIN 7 = COM. PIN 14 = +12V. Page 14 of 19 2. COMPONENTS L1, L2, C1, C2, CX, CY, R30, R31, ARE NOT SUPPLIED. REFER TO APPLICATION NOTE FOR HELP IN DETERMINING JMPR1 - JMPR4 JUMPER LOCATIONS. FIGURE 33. HIP4080A EVALUATION PC BOARD SCHEMATIC C1 R26 COM C8 C6 R28 R27 B+ + CR2 R32 + JMPR5 R29 C7 +12V HIP4080A FN3658 Rev.8.00 Dec 11, 2019 GND AO Q1 C4 BHO U1 Q3 1 R22 1 JMPR1 JMPR2 JMPR3 JMPR4 I O IN2 ALS ALO C2 Q2 R23 Q4 1 1 R21 CY CX FIGURE 33. HIP4080A EVALUATION BOARD SILKSCREEN R31 R34 R30 CR1 R33 BLS C3 C5 ALS AHO LDEL HDEL O L2 BLO BLS L1 IN1 HIP4080/81 R24 DIS U2 BO Page 15 of 19 HIP4080A Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure you have the latest revision. DATE REVISION CHANGE Dec 11, 2019 FN3658.8 Removed retired parts. Added Revision History section. Updated POD M20.3 to the latest revision. Changes are as follows: Rev 2. - Removed "u" symbol from drawing (overlaps the "a" on Side View). Rev 3. - Top View: Corrected "7.50 BSC" to "7.60/7.40" (no change from rev 2; error was introduced in conversion) Changed "10.30 BSC" to "10.65/10.00" (no change from rev 2; error was introduced in conversion) Side View: Changed "12.80 BSC" to "13.00/12.60" (no change from rev 2; error was introduced in conversion) Changed "2.65 max" to "2.65/2.35" (no change from rev 2; error was introduced in conversion) Changed Note 1 from "ANSI Y14.5M-1982." to "ASME Y14.5M-1994" Updated to new POD format by moving dimensions from table onto drawing and adding land pattern Updated disclaimer. FN3658 Rev.8.00 Dec 11, 2019 Page 16 of 19 HIP4080A Package Outline Drawings E20.3 (JEDEC MS-001-AD ISSUE D) N 20 LEAD DUAL-IN-LINE PLASTIC PACKAGE (PDIP) E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- SEATING PLANE A2 A L D1 e B1 D1 B 0.010 (0.25) M A1 eC C A B S MILLIMETERS SYMBOL MIN MAX MIN A - 0.210 - MAX NOTES 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.55 1.77 8 eA C 0.008 0.014 C D 0.980 1.060 24.89 eB NOTES: 3. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 0.355 - 26.9 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC eA 0.300 BSC 4. Dimensioning and tolerancing per ANSI Y14.5M-1982. eB - 5. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. L 0.115 N 6. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 0.204 0.430 0.150 20 2.54 BSC 7.62 BSC - 6 10.92 7 3.81 4 2.93 20 9 Rev. 0 12/93 7. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 8. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 9. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 10. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 11. N is the maximum number of terminal positions. 12. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN3658 Rev.8.00 Dec 11, 2019 Page 17 of 19 HIP4080A M20.3 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC) Rev 3, 2/11 20 INDEX AREA 7.60 7.40 1 2 10.65 10.00 0.25 (0.10) M B M 3 3 TOP VIEW 13.00 12.60 SEATING PLANE 2 2.65 2.35 5 0.75 1.27 BSC 0.49 0.35 7 0.25 (0.10) M 0.25 0.30 MAX C A M B S 1.27 0.40 x 45 8 MAX 0.10 (0.004) SIDE VIEW 0.32 0.23 DETAIL "X" NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. (0.60) 1.27 BSC 2. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 20 (2.00) 3. Dimension does not include interlead lash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. (9.40mm) 5. Dimension is the length of terminal for soldering to a substrate. 6. Terminal numbers are shown for reference only. 7. The lead width as measured 0.36mm (0.14 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 8. Controlling dimension: MILLIMETER. 1 2 3 TYPICAL RECOMMENDED LAND PATTERN FN3658 Rev.8.00 Dec 11, 2019 9. Dimensions in ( ) for reference only. 10. JEDEC reference drawing number: MS-013-AC. Page 18 of 19 1RWLFH 'HVFULSWLRQVRIFLUFXLWVVRIWZDUHDQGRWKHUUHODWHGLQIRUPDWLRQLQWKLVGRFXPHQWDUHSURYLGHGRQO\WRLOOXVWUDWHWKHRSHUDWLRQRIVHPLFRQGXFWRUSURGXFWV DQGDSSOLFDWLRQH[DPSOHV<RXDUHIXOO\UHVSRQVLEOHIRUWKHLQFRUSRUDWLRQRUDQ\RWKHUXVHRIWKHFLUFXLWVVRIWZDUHDQGLQIRUPDWLRQLQWKHGHVLJQRI\RXU SURGXFWRUV\VWHP5HQHVDV(OHFWURQLFVGLVFODLPVDQ\DQGDOOOLDELOLW\IRUDQ\ORVVHVDQGGDPDJHVLQFXUUHGE\\RXRUWKLUGSDUWLHVDULVLQJIURPWKHXVHRI WKHVHFLUFXLWVVRIWZDUHRULQIRUPDWLRQ 5HQHVDV(OHFWURQLFVKHUHE\H[SUHVVO\GLVFODLPVDQ\ZDUUDQWLHVDJDLQVWDQGOLDELOLW\IRULQIULQJHPHQWRUDQ\RWKHUFODLPVLQYROYLQJSDWHQWVFRS\ULJKWVRU RWKHULQWHOOHFWXDOSURSHUW\ULJKWVRIWKLUGSDUWLHVE\RUDULVLQJIURPWKHXVHRI5HQHVDV(OHFWURQLFVSURGXFWVRUWHFKQLFDOLQIRUPDWLRQGHVFULEHGLQWKLV GRFXPHQWLQFOXGLQJEXWQRWOLPLWHGWRWKHSURGXFWGDWDGUDZLQJVFKDUWVSURJUDPVDOJRULWKPVDQGDSSOLFDWLRQH[DPSOHV 1ROLFHQVHH[SUHVVLPSOLHGRURWKHUZLVHLVJUDQWHGKHUHE\XQGHUDQ\SDWHQWVFRS\ULJKWVRURWKHULQWHOOHFWXDOSURSHUW\ULJKWVRI5HQHVDV(OHFWURQLFVRU RWKHUV <RXVKDOOQRWDOWHUPRGLI\FRS\RUUHYHUVHHQJLQHHUDQ\5HQHVDV(OHFWURQLFVSURGXFWZKHWKHULQZKROHRULQSDUW5HQHVDV(OHFWURQLFVGLVFODLPVDQ\ DQGDOOOLDELOLW\IRUDQ\ORVVHVRUGDPDJHVLQFXUUHGE\\RXRUWKLUGSDUWLHVDULVLQJIURPVXFKDOWHUDWLRQPRGLILFDWLRQFRS\LQJRUUHYHUVHHQJLQHHULQJ 5HQHVDV(OHFWURQLFVSURGXFWVDUHFODVVLILHGDFFRUGLQJWRWKHIROORZLQJWZRTXDOLW\JUDGHV6WDQGDUGDQG+LJK4XDOLW\7KHLQWHQGHGDSSOLFDWLRQVIRU HDFK5HQHVDV(OHFWURQLFVSURGXFWGHSHQGVRQWKHSURGXFW VTXDOLW\JUDGHDVLQGLFDWHGEHORZ 6WDQGDUG &RPSXWHUVRIILFHHTXLSPHQWFRPPXQLFDWLRQVHTXLSPHQWWHVWDQGPHDVXUHPHQWHTXLSPHQWDXGLRDQGYLVXDOHTXLSPHQWKRPH HOHFWURQLFDSSOLDQFHVPDFKLQHWRROVSHUVRQDOHOHFWURQLFHTXLSPHQWLQGXVWULDOURERWVHWF +LJK4XDOLW\ 7UDQVSRUWDWLRQHTXLSPHQWDXWRPRELOHVWUDLQVVKLSVHWF WUDIILFFRQWUROWUDIILFOLJKWV ODUJHVFDOHFRPPXQLFDWLRQHTXLSPHQWNH\ ILQDQFLDOWHUPLQDOV\VWHPVVDIHW\FRQWUROHTXLSPHQWHWF 8QOHVVH[SUHVVO\GHVLJQDWHGDVDKLJKUHOLDELOLW\SURGXFWRUDSURGXFWIRUKDUVKHQYLURQPHQWVLQD5HQHVDV(OHFWURQLFVGDWDVKHHWRURWKHU5HQHVDV (OHFWURQLFVGRFXPHQW5HQHVDV(OHFWURQLFVSURGXFWVDUHQRWLQWHQGHGRUDXWKRUL]HGIRUXVHLQSURGXFWVRUV\VWHPVWKDWPD\SRVHDGLUHFWWKUHDWWR KXPDQOLIHRUERGLO\LQMXU\DUWLILFLDOOLIHVXSSRUWGHYLFHVRUV\VWHPVVXUJLFDOLPSODQWDWLRQVHWF RUPD\FDXVHVHULRXVSURSHUW\GDPDJHVSDFHV\VWHP XQGHUVHDUHSHDWHUVQXFOHDUSRZHUFRQWUROV\VWHPVDLUFUDIWFRQWUROV\VWHPVNH\SODQWV\VWHPVPLOLWDU\HTXLSPHQWHWF 5HQHVDV(OHFWURQLFVGLVFODLPV DQ\DQGDOOOLDELOLW\IRUDQ\GDPDJHVRUORVVHVLQFXUUHGE\\RXRUDQ\WKLUGSDUWLHVDULVLQJIURPWKHXVHRIDQ\5HQHVDV(OHFWURQLFVSURGXFWWKDWLV LQFRQVLVWHQWZLWKDQ\5HQHVDV(OHFWURQLFVGDWDVKHHWXVHU VPDQXDORURWKHU5HQHVDV(OHFWURQLFVGRFXPHQW :KHQXVLQJ5HQHVDV(OHFWURQLFVSURGXFWVUHIHUWRWKHODWHVWSURGXFWLQIRUPDWLRQGDWDVKHHWVXVHU VPDQXDOVDSSOLFDWLRQQRWHV*HQHUDO1RWHVIRU +DQGOLQJDQG8VLQJ6HPLFRQGXFWRU'HYLFHVLQWKHUHOLDELOLW\KDQGERRNHWF DQGHQVXUHWKDWXVDJHFRQGLWLRQVDUHZLWKLQWKHUDQJHVVSHFLILHGE\ 5HQHVDV(OHFWURQLFVZLWKUHVSHFWWRPD[LPXPUDWLQJVRSHUDWLQJSRZHUVXSSO\YROWDJHUDQJHKHDWGLVVLSDWLRQFKDUDFWHULVWLFVLQVWDOODWLRQHWF5HQHVDV (OHFWURQLFVGLVFODLPVDQ\DQGDOOOLDELOLW\IRUDQ\PDOIXQFWLRQVIDLOXUHRUDFFLGHQWDULVLQJRXWRIWKHXVHRI5HQHVDV(OHFWURQLFVSURGXFWVRXWVLGHRIVXFK VSHFLILHGUDQJHV $OWKRXJK5HQHVDV(OHFWURQLFVHQGHDYRUVWRLPSURYHWKHTXDOLW\DQGUHOLDELOLW\RI5HQHVDV(OHFWURQLFVSURGXFWVVHPLFRQGXFWRUSURGXFWVKDYHVSHFLILF FKDUDFWHULVWLFVVXFKDVWKHRFFXUUHQFHRIIDLOXUHDWDFHUWDLQUDWHDQGPDOIXQFWLRQVXQGHUFHUWDLQXVHFRQGLWLRQV8QOHVVGHVLJQDWHGDVDKLJKUHOLDELOLW\ SURGXFWRUDSURGXFWIRUKDUVKHQYLURQPHQWVLQD5HQHVDV(OHFWURQLFVGDWDVKHHWRURWKHU5HQHVDV(OHFWURQLFVGRFXPHQW5HQHVDV(OHFWURQLFVSURGXFWV DUHQRWVXEMHFWWRUDGLDWLRQUHVLVWDQFHGHVLJQ<RXDUHUHVSRQVLEOHIRULPSOHPHQWLQJVDIHW\PHDVXUHVWRJXDUGDJDLQVWWKHSRVVLELOLW\RIERGLO\LQMXU\ LQMXU\RUGDPDJHFDXVHGE\ILUHDQGRUGDQJHUWRWKHSXEOLFLQWKHHYHQWRIDIDLOXUHRUPDOIXQFWLRQRI5HQHVDV(OHFWURQLFVSURGXFWVVXFKDVVDIHW\ GHVLJQIRUKDUGZDUHDQGVRIWZDUHLQFOXGLQJEXWQRWOLPLWHGWRUHGXQGDQF\ILUHFRQWURODQGPDOIXQFWLRQSUHYHQWLRQDSSURSULDWHWUHDWPHQWIRUDJLQJ GHJUDGDWLRQRUDQ\RWKHUDSSURSULDWHPHDVXUHV%HFDXVHWKHHYDOXDWLRQRIPLFURFRPSXWHUVRIWZDUHDORQHLVYHU\GLIILFXOWDQGLPSUDFWLFDO\RXDUH UHVSRQVLEOHIRUHYDOXDWLQJWKHVDIHW\RIWKHILQDOSURGXFWVRUV\VWHPVPDQXIDFWXUHGE\\RX 3OHDVHFRQWDFWD5HQHVDV(OHFWURQLFVVDOHVRIILFHIRUGHWDLOVDVWRHQYLURQPHQWDOPDWWHUVVXFKDVWKHHQYLURQPHQWDOFRPSDWLELOLW\RIHDFK5HQHVDV (OHFWURQLFVSURGXFW<RXDUHUHVSRQVLEOHIRUFDUHIXOO\DQGVXIILFLHQWO\LQYHVWLJDWLQJDSSOLFDEOHODZVDQGUHJXODWLRQVWKDWUHJXODWHWKHLQFOXVLRQRUXVHRI FRQWUROOHGVXEVWDQFHVLQFOXGLQJZLWKRXWOLPLWDWLRQWKH(85R+6'LUHFWLYHDQGXVLQJ5HQHVDV(OHFWURQLFVSURGXFWVLQFRPSOLDQFHZLWKDOOWKHVH DSSOLFDEOHODZVDQGUHJXODWLRQV5HQHVDV(OHFWURQLFVGLVFODLPVDQ\DQGDOOOLDELOLW\IRUGDPDJHVRUORVVHVRFFXUULQJDVDUHVXOWRI\RXUQRQFRPSOLDQFH ZLWKDSSOLFDEOHODZVDQGUHJXODWLRQV 5HQHVDV(OHFWURQLFVSURGXFWVDQGWHFKQRORJLHVVKDOOQRWEHXVHGIRURULQFRUSRUDWHGLQWRDQ\SURGXFWVRUV\VWHPVZKRVHPDQXIDFWXUHXVHRUVDOHLV SURKLELWHGXQGHUDQ\DSSOLFDEOHGRPHVWLFRUIRUHLJQODZVRUUHJXODWLRQV<RXVKDOOFRPSO\ZLWKDQ\DSSOLFDEOHH[SRUWFRQWUROODZVDQGUHJXODWLRQV SURPXOJDWHGDQGDGPLQLVWHUHGE\WKHJRYHUQPHQWVRIDQ\FRXQWULHVDVVHUWLQJMXULVGLFWLRQRYHUWKHSDUWLHVRUWUDQVDFWLRQV ,WLVWKHUHVSRQVLELOLW\RIWKHEX\HURUGLVWULEXWRURI5HQHVDV(OHFWURQLFVSURGXFWVRUDQ\RWKHUSDUW\ZKRGLVWULEXWHVGLVSRVHVRIRURWKHUZLVHVHOOVRU WUDQVIHUVWKHSURGXFWWRDWKLUGSDUW\WRQRWLI\VXFKWKLUGSDUW\LQDGYDQFHRIWKHFRQWHQWVDQGFRQGLWLRQVVHWIRUWKLQWKLVGRFXPHQW 7KLVGRFXPHQWVKDOOQRWEHUHSULQWHGUHSURGXFHGRUGXSOLFDWHGLQDQ\IRUPLQZKROHRULQSDUWZLWKRXWSULRUZULWWHQFRQVHQWRI5HQHVDV(OHFWURQLFV 3OHDVHFRQWDFWD5HQHVDV(OHFWURQLFVVDOHVRIILFHLI\RXKDYHDQ\TXHVWLRQVUHJDUGLQJWKHLQIRUPDWLRQFRQWDLQHGLQWKLVGRFXPHQWRU5HQHVDV (OHFWURQLFVSURGXFWV 1RWH 1RWH 5HQHVDV(OHFWURQLFVDVXVHGLQWKLVGRFXPHQWPHDQV5HQHVDV(OHFWURQLFV&RUSRUDWLRQDQGDOVRLQFOXGHVLWVGLUHFWO\RULQGLUHFWO\FRQWUROOHG VXEVLGLDULHV 5HQHVDV(OHFWURQLFVSURGXFWV PHDQVDQ\SURGXFWGHYHORSHGRUPDQXIDFWXUHGE\RUIRU5HQHVDV(OHFWURQLFV 5HY1RYHPEHU &RUSRUDWH+HDGTXDUWHUV &RQWDFW,QIRUPDWLRQ 72<268)25(6,$7R\RVX )RUIXUWKHULQIRUPDWLRQRQDSURGXFWWHFKQRORJ\WKHPRVWXSWRGDWH YHUVLRQRIDGRFXPHQWRU\RXUQHDUHVWVDOHVRIILFHSOHDVHYLVLW Corporate Headquarters .RWRNX7RN\R-DSDQ TOYOSU FORESIA, 3-2-24 Toyosu, ZZZUHQHVDVFRP Koto-ku, Tokyo 135-0061, Japan www.renesas.com Contact Information For further information on a product, technology, the most up-to-date ZZZUHQHVDVFRPFRQWDFW version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ 7UDGHPDUNV Trademarks 5HQHVDVDQGWKH5HQHVDVORJRDUHWUDGHPDUNVRI5HQHVDV(OHFWURQLFV &RUSRUDWLRQ$OOWUDGHPDUNVDQGUHJLVWHUHGWUDGHPDUNVDUHWKHSURSHUW\ Renesas and the Renesas logo are trademarks of Renesas Electronics RIWKHLUUHVSHFWLYHRZQHUV Corporation. All trademarks and registered trademarks are the property of their respective owners. 5HQHVDV(OHFWURQLFV&RUSRUDWLRQ$OOULJKWVUHVHUYHG