2M (128K x 16) Static RAM
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05201 Rev. *C Revised August 23, 2002
137CV25/3
Features
•Very High Speed: 55 ns and 70 ns
•Volt a ge range :
—CY62137CV25: 2.2V–2.7V
—CY62137CV30: 2.7V–3.3V
—CY62137CV33: 3.0V–3.6V
—CY62137CV: 2.7V–3.6V
•Pin Compatible with the CY62137V
•Ultra-low active power
—Typical active current: 1.5 mA @ f = 1 MHz
—Typical active current: 7 mA @ f = fmax (70 ns speed)
•Low and Ultra low st an dby pow er
•Easy memory expansion with CE and OE featu res
•Automatic power-down when deselected
•CMOS for optimum speed/power
•Packages offered in a 48-ball FBGA
Functional Description[1]
The CY62137CV25/30/33 and CY62137CV are high-perfor-
mance CMOS static RAMs organized as 128K words by 16
bits . These dev ices fea ture advanced circuit de sign to pro vide
ultra-low active current. This is ideal for providing More Battery
Life™ (MoBL®) in portable applications such as cellular tele-
phones. The devices also has an automatic power-down fea-
ture that significantly reduces power consumption by 80%
when addresses are not toggling. The device can also be put
into st andby m ode reduci ng power c onsumpt ion by mor e than
99% when deselected (CE HIGH or both BLE and BHE are
HIGH). The input/output pins (I/O0 through I/O15) are placed
in a high-impedance state when: deselected (CE HIGH), out-
puts are disabled (O E HIGH), both Byte High Enable and Byte
Low E nab l e a r e d is a bl ed ( B HE , BLE HIGH), or during a write
operation (CE LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then d ata f rom mem ory will appear on I/O8 to I/O 15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Note:
1. For best prac tice rec omm en da ti ons , ple ase ref er to the Cypress applica tion note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
128K x 16
RAM Array I/O0 – I/O7
ROW DECODER
A8
A7
A6
A5
A2
COLUMN DECODER
A11
A12
A13
A14
A15
2048 x 1024
SENSE AM PS
DATA IN DRIVERS
OE
A4
A3I/O8 – I/O15
CE
WE
BLE
BHE
A16
A0
A1
A9
Power-Down
Circuit BHE
BLE
CE
A10
10
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Document #: 38-05201 Rev. *C Page 2 of 14
Pin Configuration[2, 3]
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tes ted .)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential...–0.5V to Vccmax + 0.5V
DC Voltage Applied to Outputs
in High Z State[4] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[4]....................................−0.5V to VCC + 0.5V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Notes:
2. NC pins are not connected to the die.
3. E3 (DNU) can be left as NC or VSS to ensure proper application.
4. VIL(min.) = –2.0V for pulse durations less than 20 ns.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
WE
A11
A10
A6
A0
A3CE
I/O10
I/O8
I/O9
A4
A5
I/O11
I/O13
I/O12
I/O14
I/O15
VSS
A9
A8
OE
VSS
A7
I/O0
BHE
NC
A2
A1
BLE
VCC
I/O2
I/O1
I/O3
I/O4
I/O5I/O6
I/O7
A15
A14
A13
A12
NC
NC NC
3
265
4
1
D
E
B
A
C
F
G
H
FBGA (Top View)
A16
DNU
VCC
NC
Operating Range
Device Range Ambient
Temperature TAVCC
CY62137CV25 Industrial –40°C to +85°C 2.2V to 2.7V
CY62137CV30 2.7V to 3.3V
CY62137CV33 3.0V to 3.6V
CY62137CV 2.7 V to 3. 6V
Product Portfol io
Product
VCC Range (V) Speed
(ns)
Power Dissipation
Operating, ICC (mA)
Standby, ISB2 (µA)f = 1 MHz f = fmax
VCC(min.) VCC(typ.)[5] VCC(max.) Typ.[5] Max. Typ.[5] Max. Typ.[5] Max.
CY62137CV25LL 2.2 2.5 2.7 55 1.5 3 12 25 2 10
70 1.5 3 7 15
CY62137CV30LL 2.7 3.0 3.3 55 1.5 3 12 25 2 10
70 1.5 3 7 15
CY62137CV33LL 3.0 3.3 3.6 55 1.5 3 12 25 5 15
70 1.5 3 7 15
CY62137CVLL 2.7V 3.3 3.6 70 1.5 3 7 15 5 15
CY62137CVSL 2.7V 3.3 3.6 70 1.5 3 7 15 1 5
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Document #: 38-05201 Rev. *C Page 3 of 14
Electrical Characteristics Over the Operating Ran ge
Parameter Description Test Conditions
CY62137CV25-55 CY62137CV25-70
Min. Typ.[5] Max. Min. Typ.[5] Max. Unit
VOH Output HI GH Voltage IOH = –0.1 mA VCC = 2.2V 2.0 2.0 V
VOL Output LO W Voltage IOL = 0.1 mA VCC = 2.2V 0.4 0.4 V
VIH Input HIGH Voltage 1.8 VCC +
0.3V 1.8 VCC +
0.3V V
VIL Input LOW Voltage –0.3 0.6 –0.3 0.6 V
IIX Input Leaka ge Current GND < V I < VCC –1+1 –1+1 µA
IOZ Output Lea ka ge
Current GND < VO < VCC, Output Disabled –1+1 –1+1 µA
ICC VCC Operating Supply
Current f = fMAX = 1/tRC VCC = 2.7V
IOUT = 0 mA
CMOS Levels
12 25 715 mA
f = 1 MHz 1.5 31.5 3
ISB1 Automatic CE
Power-Down Cur-
rent— CMOS Inputs
CE > VCC – 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = fmax (Address and Data Only),
f=0 (OE, WE, BHE, and BLE)
210 210 µA
ISB2 Automatic CE
Power-Down Cur-
rent— CMOS Inputs
CE > VCC – 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 2.7V
Parameter Description Test Conditions
CY62137CV30-55 CY62137CV30-70
UnitMin. Typ.[5] Max. Min. Typ.[5] Max.
VOH Output HIGH Voltage IOH = –1.0 mA VCC = 2.7V 2.4 2.4 V
VOL Output LOW Voltage IOL = 2.1 mA VCC = 2.7V 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC +
0.3V 2.2 VCC +
0.3V V
VIL Input LOW Voltage –0.3 0.8 –0.3 0.8 V
IIX Input Leak age Curre nt GND < VI < VCC –1+1 –1+1 µA
IOZ Output Leakage
Current GND < VO < VCC, Output Disabled –1+1 –1+1 µA
ICC VCC Operating Supply
Current f = fMAX = 1/tRC VCC = 3.3V
IOUT = 0 mA
CMOS Levels
12 25 715 mA
f = 1 MHz 1.5 31.5 3
ISB1 Automatic CE
Power-Down Cur-
rent— CMOS Inputs
CE > VCC – 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = fmax (Address an d Dat a Only ),
f=0 (OE, WE, BHE, and BLE)
210 210 µA
ISB2 Automatic CE
Power-Down Cur-
rent— CMOS Inputs
CE > VCC – 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0 , VCC = 3.3V
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Document #: 38-05201 Rev. *C Page 4 of 14
.
Electrical Characteristics Over the Operating Ran ge (con tin ued )
Parameter Description Test Conditions
CY62137CV33-55 CY62137CV33-70
CY62137CV-70
UnitMin. Typ.[5] Max. Min. Typ.[5] Max.
VOH Output HIGH Vo ltage IOH = –1.0 mA VCC = 3.0V 2.4 2.4 V
VCC = 2.7V 2.4 V
VOL Output LOW Voltage IOL = 2.1 mA VCC = 3.0V 0.4 0.4 V
VCC = 2.7V 0.4 V
VIH Input HIGH Voltage 2.2 VCC +
0.3V 2.2 VCC +
0.3V V
VIL Input LOW Voltage –0.3 0.8 –0.3 0.8 V
IIX Input Leak age Curren t GND < VI < VCC –1+1 –1+1 µA
IOZ Output Leakage
Current GND < VO < VCC, Output Disabled –1+1 –1+1 µA
ICC VCC Operating Supply
Current f = fMAX = 1/tRC VCC = 3.6V
IOUT = 0 mA
CMOS Lev-
els
12 25 715 mA
f = 1 MHz 1.5 31.5 3
ISB1 Automatic CE
Power-Down Current
—CMOS Inputs
CE > VCC – 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = fmax (Address and Data Only),
f=0 (OE, WE, BHE, and BLE)
515 515 µA
ISB2 Automatic CE
Power-Down Current
—CMOS Inputs
CE > VCC – 0.2V
VIN > VCC – 0.2V or VIN < 0.2V ,
f = 0, VCC = 3.6V
LL 515 515
SL 1 5
Capacitance[6]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 2 5°C, f = 1 MHz,
VCC = VCC(typ.) 6pF
COUT Output Capacitance 8pF
Thermal Resistance
Description Test Conditions Symbol BGA Unit
Thermal Resistance
(Juncti on to Ambi ent )[6] Still Air, soldered on a 3 x 4.5 inch, two-layer printed
circuit board ΘJA 55 °C/W
Thermal Resistance
(Juncti on to Ca se)[6] ΘJC 16 °C/W
Note:
6. Tested initially and after any design or process changes that may affect these parameters.
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Document #: 38-05201 Rev. *C Page 5 of 14
AC Test Loads and Waveforms
VCC Typ
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
OUTPUT VTH
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Rise TIme: 1 V/ns Fall Time: 1 V/ns
Parameters 2.5V 3.0V 3.3V Unit
R1 16600 1105 1216 Ω
R2 15400 1550 1374 Ω
RTH 8000 645 645 Ω
VTH 1.20 1.75 1.75 V
Data Retenti on Characteristi cs (Over the Operating Range)
Parameter Description Conditions Min. Typ.[5] Max. Unit
VDR VCC for Data Re tention 1.5 Vccmax V
ICCDR Data Retention Current VCC= 1.5V
CE > VCC – 0.2V ,
VIN > VCC – 0.2V or VIN < 0. 2V 1 6 µA
tCDR[6] Chip Deselect to Data
Retention Time 0ns
tR[7] Operati on R eco ve ry Time tRC ns
Data Retenti on Waveform[8]
Notes:
7. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.
8. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
VCC(min.)
VCC(min.)
tCDR
VDR >1.5 V
DATA RETENTION MODE
tR
CE or
VCC
BHE.BLE
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Document #: 38-05201 Rev. *C Page 6 of 14
Switching Characteristics Over the Operating Range[9]
Parameter Description
55 ns 70 ns
UnitMin Max Min Max
Read Cycle
tRC Read Cycle Time 55 70 ns
tAA Address to Data Valid 55 70 ns
tOHA Data Hold from Address Change 10 10 ns
tACE CE LOW to Data Valid 55 70 ns
tDOE OE LOW to Data Valid 25 35 ns
tLZOE OE LOW to Low Z[10] 5 5 ns
tHZOE OE HIGH to High Z[10, 12] 20 25 ns
tLZCE CE LOW to Low Z[10] 10 10 ns
tHZCE CE HIGH to High Z[10, 12] 20 25 ns
tPU CE LOW to Power-Up 0 0 ns
tPD CE HIGH to Power-Down 55 70 ns
tDBE BHE/BLE LOW to Data Valid 55 70 ns
tLZBE[11] BHE/BLE LOW to Low Z[10] 5 5 ns
tHZBE BHE/BLE HIGH to High Z[10, 12] 20 25 ns
Write Cycle[13]
tWC Write Cycle Time 55 70 ns
tSCE CE LOW to Write End 45 60 ns
tAW Address Set-Up to W rit e End 45 60 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Set-U p to W rit e Start 0 0 ns
tPWE WE Pulse Width 40 45 ns
tBW BHE/BLE Pulse Width 50 60 ns
tSD Data Set-Up to Write End 25 30 ns
tHD Data Hold from Write End 0 0 ns
tHZWE WE LOW to High Z[10, 12] 20 25 ns
tLZWE WE HIGH to Low Z[10] 510 ns
Notes:
9. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30-pF load capacitance.
10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for
any given device.
11. If both byte enables are toggled together this value is 10 ns.
12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
13. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BH E and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Document #: 38-05201 Rev. *C Page 7 of 14
Switching Waveforms
Notes:
14. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL.
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE, BHE, BLE transiti on LOW.
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
Read Cycle No. 1 (Address Transition Controlled)[14, 15 ]
Read Cycle No. 2 (OE Controlled)[15, 16]
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
DATA OUT HIGH IMPEDANCE IMPEDANCE
I
CC
I
SB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
CC
SUPPLY
CURRENT
t
HZBE
BHE/BLE t
LZOE
ADDRESS
t
DOE
t
LZOE
t
DBE
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Document #: 38-05201 Rev. *C Page 8 of 14
Notes:
17. Data I/O is high-impedance if OE = VIH.
18. If CE goe s HIGH simult aneously with WE HIGH, the out put r emains i n a hi gh-impedan ce st ate .
19. During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 19
Write Cy cle No. 1(WE Controlled)
BHE/BLE tBW
[13, 17, 18]
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 19
Write Cycle No. 2 (C E Controlled)
BHE/BLE tBW
[13, 17, 18 ]
tSA
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Document #: 38-05201 Rev. *C Page 9 of 14
Switching Waveforms (continued)
DATAIN VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATAI/O NOTE 19
Write Cycle No. 3 (WE Controlled, OE LOW)
tBW
BHE/BLE
[18]
DATA I/O
ADDRESS
t
HD
t
SD
t
SA
t
HA
t
AW
tWC
CE
WE
DATA
IN
VALID
Write Cycle No. 4 (BHE/BLE Cont roll ed, OE LOW)[18]
NOTE 19
t
BW
BHE/BLE
tSCE
t
PWE
.
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Document #: 38-05201 Rev. *C Page 10 of 14
Typical DC and AC Parameters
12.0
10.0
6.0
4.0
0
8.0
ISB (µA)
12.0
10.0
6.0
4.0
2.0
2.2
0.0
8.0
ICC (mA)
SUPP LY VO LTAG E (V)
SUPPLY VO LTAGE (V)
MoBL
MoBL
2.2
2.0
(f = fmax,
(f = 1MHz)
14.0
2.5 2.7
2.5 2.7
12.0
10.0
6.0
4.0
2.0
2.7 3.3
0.0
8.0
ICC (mA)
SUPP LY VO LTAG E (V)
MoBL
(f = 1MHz)
14.0
3.0
12.0
10.0
6.0
4.0
2.0
3.0 3.6
0.0
8.0
ICC (mA)
SUPP LY VOLT AG E (V)
14.0
3.3
MoBL
12.0
10.0
6.0
4.0
2.7
0
8.0
SUPPLY VOLTAGE (V)
3.6
2.0
3.3
12.0
10.0
6.0
4.0
3.0
0
8.0
ISB (µA)
Standby Current vs. Supply Voltage
SUPP LY VOLTAGE (V)
MoBL
2.0
2.7 3.3
50
30
20
10
3.0 3.6
SUPPLY VOLTAGE (V )
0
40
TAA (ns)
60
3.3
50
30
20
10
2.2
0
40
TAA (ns)
60
2.5 2.7
50
30
20
10
SUPPLY VOLTAG E (V)
Access Time vs. Supply Voltage
0
40
TAA (ns)
60
3.0
2.7 3.3
MoBL
Operating Current vs. Supply Voltage
MoBL MoBL MoBL
(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C)
50
30
20
10
2.7 3.6
SUPPL Y VOLTAG E (V )
0
40
TAA (ns)
60
3.3
MoBL
SUPPLY VOLTAGE (V)
(f = 1MHz)
ISB (µA)
12.0
10.0
6.0
4.0
3.0
0
8.0
SUPPLY VO LTAGE (V)
3.6
2.0
3.3
MoBL
ISB (µA)
55 ns)
(f = fmax,
70 ns) (f = fmax,
70 ns)
(f = fmax,
55 ns)
(f = fmax,
70 ns)
(f = fmax,
55 ns) 12.0
10.0
6.0
4.0
2.0
2.7 3.6
0.0
8.0
ICC (mA)
SUPP LY VOLT AG E (V)
14.0
3.3
MoBL
(f = 1MHz)
(f = fmax,
70 ns)
LL
SL
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Document #: 38-05201 Rev. *C Page 11 of 14
Truth Table
CE WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High Z Deselect/Power-Down Standby (ISB)
X X X H H High Z Deselect/Power-Down Standby (ISB)
L H L L L Data Out (I/OO–I/O15)Read Active (ICC)
L H L H L Data Out (I/OO–I/O7);
I/O8–I/O15 in High Z Read Active (ICC)
L H L L H Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z Read Active (ICC)
L H H L L High Z Output Disabled Active (ICC)
L H H H L High Z Output Disabled Active (ICC)
L H H L H High Z Output Disabled Active (ICC)
L L X L L Data In (I/OO–I/O15)Write Active (ICC)
L L X H L Data In (I/OO–I/O7);
I/O8–I/O15 in High Z Write Active (ICC)
L L X L H Data In (I/O8–I/O15);
I/O0–I/O7 in High Z Write Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Voltage
Range (V) Package
Name Package Type Operating
Range
70 CY62137CV25LL-70BAI 2.2–2.7 BA48A 48-Ball Fine Pitch BGA ( 7 mm x 7 mm x 1.2 mm) Industrial
CY62137CV25LL-70BVI 2.2–2.7 BV48A 48-B all Fi ne Pitch BGA (6 mm x 8 mm x 1 mm)
CY62137CV30LL-70BAI 2.7–3.3 BA48A 48-Ball Fine Pitch BGA ( 7 mm x 7 mm x 1.2 mm)
CY62137CV30LL-70BVI 2.7–3.3 BV48A 48-B all Fi ne Pitch BGA (6 mm x 8 mm x 1 mm)
CY62137CV33LL-70BAI 3.0–3.6 BA48A 48-Ball Fine Pitch BGA ( 7 mm x 7 mm x 1.2 mm)
CY62137CV33LL-70BVI 3.0–3.6 BV48A 48-B all Fi ne Pitch BGA (6 mm x 8 mm x 1 mm)
CY62137CVLL-70BAI 2.7–3.6 BA48A 48-Bal l Fine Pitch BGA ( 7 mm x 7 mm x 1.2 mm)
CY62137CVLL-70BVI 2.7–3.6 BV48A 48-Ball Fine Pit ch BGA (6 mm x 8 mm x 1 mm)
CY62137CVSL-70BAI 2.7–3.6 BA48A 48-Ball Fine Pitch BGA ( 7 mm x 7 mm x 1.2 mm)
CY62137CVSL-70BVI 2.7–3.6 BV48A 48-B all Fi ne Pitch BGA (6 mm x 8 mm x 1 mm)
55 CY62137CV25LL-55BAI 2.2–2.7 BA48A 48-Ball Fine Pitch BGA ( 7 mm x 7 mm x 1.2 mm)
CY62137CV25LL-55BVI 2.2–2.7 BV48A 48-B all Fi ne Pitch BGA (6 mm x 8 mm x 1 mm)
CY62137CV30LL-55BAI 2.7–3.3 BA48A 48-Ball Fine Pitch BGA ( 7 mm x 7 mm x 1.2 mm)
CY62137CV30LL-55BVI 2.7–3.3 BV48A 48-B all Fi ne Pitch BGA (6 mm x 8 mm x 1 mm)
CY62137CV33LL-55BAI 3.0–3.6 BA48A 48-Ball Fine Pitch BGA ( 7 mm x 7 mm x 1.2 mm)
CY62137CV33LL-55BVI 3.0–3.6 BV48A 48-B all Fi ne Pitch BGA (6 mm x 8 mm x 1 mm)
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Document #: 38-05201 Rev. *C Page 12 of 14
Package Diagrams
48-Ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48A
51-85096-*E
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Document #: 38-05201 Rev. *C Page 13 of 14
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. Cy press Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
MoBL is a re gister ed tradem ark and Mo re Batt ery Life is a tra demar k of Cypres s Semico nducto r Corpo ration. All produc t and
company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams (continued)
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*A
CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Document #: 38-05201 Rev. *C Page 14 of 14
Document T itl e: CY62 13 7CV25 / 30/ 33 MoBL® and CY621 37CV MoBL® 2M (128K x 16) Static RAM
Document Numbe r: 38-052 01
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 112393 02/19/02 GAV New data sheet-Advance information
*A 1 14015 04/25/02 JUI Add BV package diagram. Change from Advance Information to Preliminary
*B 117064 07/12/0 2 MG N Change from Prelimina ry to Fina l
*C 118122 09/10/02 MGN Add new part number - CY62137CV with wider voltage (2.7V - 3.6V). Add
new SL power bin fo r new part #. Fo r T AA = 55 ns , improved tPWE Min from
45 ns to 40 ns. For TAA = 70 ns, improved tPWE Min from 50 ns to 45 ns.
For TAA = 70 ns, improved tLZWE Min from 5 ns to 10 ns.
