240pin DDR3 SDRAM Unbuffered DIMMs DDR3 SDRAM Unbuffered DIMMs Based on 1Gb A version HMT164U6AFP(R)6C HMT112U6AFP(R)8C HMT112U7AFP(R)8C HMT125U6AFP(R)8C HMT125U7AFP(R)8C ** Contents are subject to change without prior notice. Rev. 0.1 / Dec 2008 1 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Revision History Revision No. History Draft Date Remark 0.01 Initial draft for internal review Nov. 2007 Preliminary 0.02 Added IDD & Halogen-free products Mar. 2008 Preliminary 0.1 Initial Specification Release. Corrected typo on package ball feature. Dec 2008 Rev. 0.1 / Dec 2008 2 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Table of Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.2 Speed Grade & Key Parameters 1.3 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1 512MB, 64Mx64 Module(1Rank of x16) 3.2 1GB, 128Mx64 Module(1Rank of x8) 3.3 1GB, 128Mx72 ECC Module(1Rank of x8) 3.4 2GB, 256Mx64 Module(2Rank of x8) 3.5 2GB, 256Mx72 ECC Module(2Rank of x8) 4. Address Mirroring Feature 4.1 DRAM Pin Wiring for Mirroring 5. Absolute Maximum Ratings 5.1 Absolute Maximum DC Ratings 5.2 Operating Temperature Range 6. AC & DC Operating Conditions 6.1 Recommended DC Operating Conditions 6.2 DC & AC Logic Input Levels 6.2.1 For Single-ended Signals 6.2.2 For Differential Signals 6.2.3 Differential Input Cross Point 6.3 Slew Rate Definition 6.3.1 For Ended Input Signals 6.3.2 For Differential Input Signals 6.4 DC & AC Output Buffer Levels 6.4.1 Single Ended DC & AC Output Levels 6.4.2 Differential DC & AC Output Levels 6.4.3 Single Ended Output Slew Rate 6.4.4 Differential Ended Output Slew Rate 6.5 Overshoot/Undershoot Specification 6.6 Input/Output Capacitance & AC Parametrics 6.7 IDD Specifications & Measurement Conditions 7. Electrical Characteristics and AC Timing 7.1 Refresh Parameters by Device Density 7.2 DDR3 Standard speed bins and AC para 8. DIMM Outline Diagram 8.1 512MB, 64Mx64 Module(1Rankx16) 8.2 1GB, 128Mx64 Module(1Rank of x8) 8.3 1GB, 128Mx72 ECC Module(1Rank of x8) 8.4 2GB, 256Mx64 Module(2Rank of x8) 8.5 2GB, 256Mx72 ECC Module(2Rank of x8) Rev. 0.1 / Dec 2008 3 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 1. Description This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 1Gb A version. DDR3 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240 pin glass-epoxy substrate. This DDR3 Unbuffered DIMM series based on 1Gb A ver. provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition. 1.1 Device Features & Ordering Information 1.1.1 Features * VDD=VDDQ=1.5V * VDDSPD=3.3V to 3.6V * Fully differential clock inputs (CK, /CK) operation * Differential Data Strobe (DQS, /DQS) * On chip DLL align DQ, DQS and /DQS transition with CK transition * DM masks write data-in at the both rising and falling edges of the data strobe * All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock * Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11) supported * Programmable burst length 4/8 with both nibble sequential and interleave mode * BL switch on the fly * 8banks * 8K refresh cycles /64ms * DDR3 SDRAM Package: JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16) with support balls * Driver strength selected by EMRS * Dynamic On Die Termination supported * Asynchronous RESET pin supported * ZQ calibration supported * TDQS (Termination Data Strobe) supported (x8 only) * Programmable additive latency 0, CL-1, and CL-2 sup ported * Write Levelization supported * Programmable CAS Write latency (CWL) = 5, 6, 7, 8 * On Die Thermal Sensor supported (JEDEC optional) Rev. 0.1 / Dec 2008 * Auto Self Refresh supported 4 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 1.1.2 Ordering Information Part Name # of # of DRAMs ranks Density Org. HMT164U6AFP6C-S6/S5/G8/G7/H9/H8 512MB 64Mx64 4 1 HMT164U6AFR6C-S6/S5/G8/G7/H9/H8 512MB 64Mx64 4 1 HMT112U6AFP8C-S6/S5/G8/G7/H9/H8 1GB 128Mx64 8 1 HMT112U6AFR8C-S6/S5/G8/G7/H9/H8 1GB 128Mx64 8 1 HMT112U7AFP8C-S6/S5/G8/G7/H9/H8 1GB 128Mx72 9 1 Lead free ECC Yes HMT112U7AFR8C-S6/S5/G8/G7/H9/H8 1GB 128Mx72 9 1 Halogen-free ECC Yes HMT125U6AFP8C-S6/S5/G8/G7/H9/H8 2GB 256Mx64 16 2 Lead free None No HMT125U6AFR8C-S6/S5/G8/G7/H9/H8 2GB 256Mx64 16 2 Halogen-free None No HMT125U7AFP8C-S6/S5/G8/G7/H9/H8 2GB 256Mx72 18 2 Lead free ECC Yes HMT125U7AFR8C-S6/S5/G8/G7/H9/H8 2GB 256Mx72 18 2 Halogen-free ECC Yes Rev. 0.1 / Dec 2008 Materials ECC TS Lead-free None No Halogen-free None No Lead free None No Halogen-free None No 5 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 1.2 Speed Grade & Key Parameters MT/S DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Unit Grade -S6 tCK(min) -S5 -G8 -G7 2.5 -H9 1.875 -H8 -P1 1.5 -P9 1.25 ns CAS Latency 6 5 8 7 9 8 10 9 tCK tRCD(min) 15 12.5 15 13.125 13.5 12 12.5 11.25 ns tRP(min) 15 12.5 15 13.125 13.5 12 12.5 11.25 ns tRAS(min) 37.5 37.5 37.5 37.5 36 36 35 35 ns tRC(min) 52.5 50 52.5 50.625 49.5 48 47.25 46.25 ns CL-tRCD-tRP 6-6-6 5-5-5 8-8-8 7-7-7 9-9-9 8-8-8 10-10-10 9-9-9 tCK 1.3 Address Table 512MB 1GB 1GB 2GB 2GB Organization 64M x 64 128M x 64 128M x 72 256M x 64 256M x 72 Refresh Method 8K/64ms 8K/64ms 8K/64ms 8K/64ms 8K/64ms Row Address A0-A12 A0-A13 A0-A13 A0-A13 A0-A13 Column Address A0-A9 A0-A9 A0-A9 A0-A9 A0-A9 Bank Address BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2 Page Size 2KB 1KB 1KB 1KB 1KB # of Rank 1 1 1 2 2 # of Device 4 8 9 16 18 Rev. 0.1 / Dec 2008 6 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 2. Pin Architecture 2.1 Pin Definition Pin Name Description Pin Name Description I2C serial bus clock for EEPROM A0-A13 SDRAM address bus SCL BA0-BA2 SDRAM bank select SDA I2C serial bus data line for EEPROM SA0-SA2 I2C slave address select for EEPROM RAS SDRAM row address strobe CAS SDRAM column address strobe WE SDRAM write enable VDDQ* DIMM Rank Select Lines VREFDQ SDRAM I/O reference supply VREFCA SDRAM command/address reference supply S0-S1 CKE0-CKE1 SDRAM clock enable lines ODT0-ODT1 On-die termination control lines DQ0-DQ63 CB0-CB7 DIMM memory data bus DIMM ECC check bits VDD* VSS VDDSPD NC SDRAM core power supply SDRAM I/O Driver power supply Power supply return (ground) Serial EEPROM positive power supply Spare pins (no connect) DQS0-DQS8 SDRAM data strobes (positive line of differential pair) TEST Memory bus analysis tools (unused on memory DIMMS) DQS0-DQS8 SDRAM data strobes (negative line of differential pair) RESET Set DRAMs to Known State DM0-DM8 SDRAM data masks/high data strobes (x8-based x72 DIMMs) VTT SDRAM I/O termination supply CK0-CK1 SDRAM clocks (positive line of differential pair) RFU Reserved for future use CK0-CK1 SDRAM clocks (negative line of differential pair) - - *The VDD and VDDQ pins are tied common to a single power-plane on these designs Rev. 0.1 / Dec 2008 7 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 2.2 Input/Output Functional Description Symbol Type Polarity Function CK0-CK1 CK0-CK1 SSTL Differential crossing CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of crossing). CKE0-CKE1 SSTL Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. S0-S1 SSTL Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. This signal provides for external rank selection on systems with multiple ranks. RAS, CAS, WE SSTL Active Low RAS, CAS, and WE (ALONG WITH S) define the command being entered. ODT0-ODT1 SSTL Active High When high, termination resistance is enabled for all DQ, DQS, DQS and DM pins, assuming this function is enabled in the Mode Register 1 (MR1). VREFDQ Supply Reference voltage for SSTL15 I/O inputs. VREFCA Supply Reference voltage for SSTL 15 command/address inputs. VDDQ Supply Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity. For all current DDR3 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins. BA0-BA2 SSTL -- Selects which SDRAM bank of eight is activated. During a Bank Activate command cycle, Address input defines the row address (RA0-RA15). A0-A13 SSTL -- DQ0-DQ63, CB0-CB7 SSTL -- DM0-DM8 SSTL VDD, VSS Supply Rev. 0.1 / Dec 2008 Active High During a Read or Write command cycle, Address input defines the column address. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used to define which bank to precharge. A12(BC) is sampled during READ and WRITE commands to determine if burst chop (on-the-fly) will be performed (HIGH, no burst chop; LOW, burst chopped). Data and Check Bit Input/Output pins. DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Power and ground for the DDR3 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/VDDQ planes on these modules. 8 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Symbol Type Polarity DQS0-DQS8 DQS0-DQS8 SSTL Differential crossing Function Data strobe for input and output data. SA0-SA2 -- These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. SDA -- This bidirectional pin is used to transfer data into or out of the SPD EEPROM. An external resistor may be connected from the SDA bus line to VDDSPD to act as a pullup on the system board. SCL -- This signal is used to clock data into and out of the SPD EEPROM. An external resistor may be connected from the SCL bus time to VDDSPD to act as a pullup on the system board. VDDSPD Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM supply is operable from 3.0V to 3.6V. Supply 2.3 Pin Assignment Front Side(left 1-60) Pin x64 # Non-ECC x72 ECC Back Side(right 121-180) Front Side(left 61-120) Back Side(right 181-240) Pin x64 # Non-ECC x72 ECC Pin # x64 Non-ECC x72 ECC Pin # x64 Non-ECC x72 ECC VSS VSS 61 A2 A2 181 A1 A1 1 VREFDQ 2 VSS VSS 122 DQ4 DQ4 62 VDD VDD 182 VDD VDD 3 DQ0 DQ0 123 DQ5 DQ5 63 CK1 CK1 183 VDD VDD 4 DQ1 DQ1 124 VSS VSS 64 CK1 CK1 184 CK0 CK0 5 VSS VSS 125 DM0 DM0 65 VDD VDD 185 CK0 CK0 6 DQS0 DQS0 126 NC NC 66 VDD VDD 186 VDD VDD 7 DQS0 DQS0 127 VSS VSS 67 VREFCA VREFCA 187 NC NC 8 VSS VSS 128 DQ6 DQ6 68 NC NC 188 A0 A0 9 DQ2 DQ2 129 DQ7 DQ7 69 VDD VDD 189 VDD VDD BA12 VREFDQ 121 10 DQ3 DQ3 130 VSS VSS 70 A10 A10 190 BA12 11 VSS VSS 131 DQ12 DQ12 71 BA02 BA02 191 VDD VDD 12 DQ8 DQ8 132 DQ13 DQ13 72 VDD VDD 192 RAS RAS 13 DQ9 DQ9 133 VSS VSS 73 WE WE 193 S0 S0 14 VSS VSS 134 DM1 DM1 74 CAS CAS 194 VDD VDD 15 DQS1 DQS1 135 NC NC 75 VDD VDD 195 ODT0 ODT0 16 DQS1 DQS1 136 VSS VSS 76 S1 S1 196 A13 A13 NC = No Connect; RFU = Reserved Future Use 1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group. 2. Address pins A3-A8 and BA0 and BA1 can be mirrored or not mirrored. Please refer to Section 4.1 for more information on mirrored addresses. Rev. 0.1 / Dec 2008 9 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Front Side(left 1-60) Back Side(right 121-180) Front Side(left 61-120) Back Side(right 181-240) Pin x64 # Non-ECC x72 ECC Pin x64 # Non-ECC x72 ECC Pin # x64 Non-ECC x72 ECC Pin # x64 Non-ECC x72 ECC 17 VSS VSS 137 DQ14 DQ14 77 ODT1 ODT1 197 VDD VDD 18 DQ10 DQ10 138 DQ15 DQ15 78 VDD VDD 198 NC NC 19 DQ11 DQ11 139 VSS VSS 79 NC NC 199 VSS VSS 20 VSS VSS 140 DQ20 DQ20 80 VSS VSS 200 DQ36 DQ36 21 DQ16 DQ16 141 DQ21 DQ21 81 DQ32 DQ32 201 DQ37 DQ37 22 DQ17 DQ17 142 VSS VSS 82 DQ33 DQ33 202 VSS VSS 23 VSS VSS 143 DM2 DM2 83 VSS VSS 203 DM4 DM4 24 DQS2 DQS2 144 NC NC 84 DQS4 DQS4 204 NC NC 25 DQS2 DQS2 145 VSS VSS 85 DQS4 DQS4 205 VSS VSS 26 VSS VSS 146 DQ22 DQ22 86 VSS VSS 206 DQ38 DQ38 27 DQ18 DQ18 147 DQ23 DQ23 87 DQ34 DQ34 207 DQ39 DQ39 28 DQ19 DQ19 148 VSS VSS 88 DQ35 DQ35 208 VSS VSS 29 VSS VSS 149 DQ28 DQ28 89 VSS VSS 209 DQ44 DQ44 30 DQ24 DQ24 150 DQ29 DQ29 90 DQ40 DQ40 210 DQ45 DQ45 31 DQ25 DQ25 151 VSS VSS 91 DQ41 DQ41 211 VSS VSS 32 VSS VSS 152 DM3 DM3 92 VSS VSS 212 DM5 DM5 33 DQS3 DQS3 153 NC NC 93 DQS5 DQS5 213 NC NC 34 DQS3 DQS3 154 VSS VSS 94 DQS5 DQS5 214 VSS VSS 35 VSS VSS 155 DQ30 DQ30 95 VSS VSS 215 DQ46 DQ46 36 DQ26 DQ26 156 DQ31 DQ31 96 DQ42 DQ42 216 DQ47 DQ47 37 DQ27 DQ27 157 VSS VSS 97 DQ43 DQ43 217 VSS VSS 38 VSS VSS 158 NC CB4 98 VSS VSS 218 DQ52 DQ52 39 NC CB0 159 NC CB5 99 DQ48 DQ48 219 DQ53 DQ53 40 NC CB1 160 VSS VSS 100 DQ49 DQ49 220 VSS VSS 41 VSS VSS 161 DM8 DM8 101 VSS VSS 221 DM6 DM6 42 NC DQS8 162 NC NC 102 DQS6 DQS6 222 NC NC 43 NC DQS8 163 VSS VSS 103 DQS6 DQS6 223 VSS VSS 44 VSS VSS 164 NC CB6 104 VSS VSS 224 DQ54 DQ54 45 NC CB2 165 NC CB7 105 DQ50 DQ50 225 DQ55 DQ55 46 NC CB3 166 VSS VSS 106 DQ51 DQ51 226 VSS VSS 47 VSS VSS 167 NC NC 107 VSS VSS 227 DQ60 DQ60 NC = No Connect; RFU = Reserved Future Use 1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group. 2. Address pins A3-A8 and BA0 and BA1 can be mirrored or not mirrored. Please refer to Section 4.1 for more information on mirrored addresses. Rev. 0.1 / Dec 2008 10 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Front Side(left 1-60) Pin x64 # Non-ECC 48 x72 ECC NC NC Back Side(right 121-180) Front Side(left 61-120) Back Side(right 181-240) Pin x64 # Non-ECC x72 ECC Pin # x64 Non-ECC x72 ECC Pin # x64 Non-ECC x72 ECC 168 Reset 108 DQ56 DQ56 228 DQ61 DQ61 109 DQ57 DQ57 229 VSS VSS Reset KEY KEY 49 NC NC 169 CKE1/NC CKE1/NC 110 VSS VSS 230 DM7 DM7 50 CKE0 CKE0 170 VDD VDD 111 DQS7 DQS7 231 NC NC 51 VDD VDD 171 NC NC 112 DQS7 DQS7 232 VSS VSS 52 BA2 BA2 172 NC NC 113 VSS VSS 233 DQ62 DQ62 53 NC NC 173 VDD VDD 114 DQ58 DQ58 234 DQ63 DQ63 54 VDD VDD 174 A12 A12 115 DQ59 DQ59 235 VSS VSS 55 All All 175 A9 A9 116 VSS VSS 236 VDDSPD VDDSPD 56 A72 A72 176 VDD VDD 117 SA0 SA0 237 SA1 SA1 57 VDD VDD 177 A82 A82 118 SCL SCL 238 SDA SDA 58 A52 A52 178 A62 A62 119 SA2 SA2 239 VSS VSS 59 A42 A42 179 VDD VDD 120 VTT VTT 240 VTT VTT 60 VDD VDD 180 A32 A32 NC = No Connect; RFU = Reserved Future Use 1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group. 2. Address pins A3-A8 and BA0 and BA1 can be mirrored or not mirrored. Please refer to Section 4.1 for more information on mirrored addresses. Rev. 0.1 / Dec 2008 11 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 3. Functional Block Diagram 3.1 512MB, 64Mx64 Module(1Rank of x16) S0 DQS0 DQS0 DM0 DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQS3 DQS3 DM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS4 DQS4 DM4 CS D0 DQS5 DQS5 DM5 ZQ DQS6 DQS6 DM6 CS CSD1 DQS7 DQS7 DM7 CS ZQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 Serial PD SCL BA0-BA2 A0-A14 BA0-BA2: SDRAMs D0-D3 A0-A14: SDRAMs D0-D3 RAS RAS: SDRAMs D0-D3 CAS CAS: SDRAMs D0-D3 CKE0 CKE: SDRAMs D0-D3 WE ODT0 WE: SDRAMs D0-D3 CK0 CK0 RESET ODT: SDRAMs D0-D3 CK: SDRAMs D0-D3 CK: SDRAMs D0-D3 RESET:SDRAMs D0-D3 Rev. 0.1 / Dec 2008 VDDSPD VDD/VDDQ SDA WP A0 A1 A2 SA0 SA1 SA2 SPD D0-D3 VREFDQ D0-D3 VSS D0-D3 VREFCA D0-D3 CS D2 ZQ CS CSD3 CS ZQ Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ,DM,DQS,DQS resistors;Refer to associated topology diagram. 4. Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document. 5. The pair CK1 and CK1# is terminated in 75ohm but is not used on the module. 6. A15 is not routed on the module. 7. For each DRAM, a unique ZQ resistor is connected to ground.The ZQ resistor is 240ohm+-1% 8. One SPD exists per module. 12 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 3.2 1GB, 128Mx64 Module(1Rank of x8) S0 DQS0 DQS0 DM0 DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQS3 DQS3 DM3 DQS4 DQS4 DM4 DM CS DQS DQS 0 1 D0 2 3 4 5 6 ZQ 7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O I/O I/O I/O I/O I/O I/O I/O DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS DQS DQS I/O 0 I/O 1 D1 I/O 2 I/O 3 I/O 4 I/O 5 ZQ I/O 6 I/O 7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O I/O I/O I/O I/O I/O I/O I/O DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS DQS DQS I/O 0 I/O 1 D3 I/O 2 I/O 3 I/O 4 I/O 5 ZQ I/O 6 I/O 7 DQS5 DQS5 DM5 DQS6 DQS6 DM6 DM CS DQS DQS 0 1 D2 2 3 4 5 6 7 ZQ DQS7 DQS7 DM7 A0-A15 BA0-BA2: SDRAMs D0-D7 A0-A15: SDRAMs D0-D7 RAS RAS: SDRAMs D0-D7 CAS CAS: SDRAMs D0-D7 CKE0 CKE: SDRAMs D0-D7 WE ODT0 WE: SDRAMs D0-D7 CK0 CK0 CK: SDRAMs D0-D7 CK: SDRAMs D0-D7 RESET ODT: SDRAMs D0-D7 RESET:SDRAMs D0-D7 Rev. 0.1 / Dec 2008 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS Serial PD SCL BA0-BA2 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 VDDSPD VDD/VDDQ SDA WP A0 A1 A2 SA0 SA1 SA2 SPD D0-D7 VREFDQ D0-D7 VSS D0-D7 VREFCA D0-D7 D4 ZQ D5 ZQ D6 ZQ D7 ZQ Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ,DM,DQS/DQS resistors;Refer to associated topology diagram. 4. Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document. 5. Refer to Section 3.1 of this document for details on address mirroring. 6. For each DRAM, a unique ZQ resistor is connected to ground.The ZQ resistor is 240ohm+-1% 7. One SPD exists per module. 13 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 3.3 1GB, 128Mx72 Module(1Rank of x8) S0 DQS0 DQS0 DM0 DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQS3 DQS3 DM3 DQS8 DQS8 DM8 BA0-BA2 A0-A15 RAS CAS CKE0 WE ODT0 CK0 CK0 RESET DQS4 DQS4 DM4 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D0 ZQ DQS5 DQS5 DM5 DQS DQS D1 ZQ DQS6 DQS6 DM6 DQS DQS D2 ZQ DQS7 DQS7 DM7 DQS DQS D3 ZQ D8 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS SPD(TS integrated) SCL EVENT ZQ BA0-BA2: SDRAMs D0-D8 A0-A15: SDRAMs D0-D8 VDDSPD RAS: SDRAMs D0-D8 VDD/VDDQ CAS: SDRAMs D0-D8 CKE: SDRAMs D0-D8 VREFDQ WE: SDRAMs D0-D8 VSS ODT: SDRAMs D0-D8 CK: SDRAMs D0-D8 V REFCA CK: SDRAMs D0-D8 RESET:SDRAMs D0-D8 Rev. 0.1 / Dec 2008 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 EVENT SDA A0 A1 A2 SA0 SA1 SA2 SPD D0-D8 D0-D8 D0-D8 D0-D8 DQS DQS D4 ZQ D5 ZQ DQS DQS D6 ZQ DQS DQS D7 ZQ Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ,CB,DM,DQS/DQS resistors;Refer to associated topology diagram. 4. Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document. 5. For each DRAM, a unique ZQ resistor is connected to ground.The ZQ resistor is 240ohm+-1% 6. One SPD exists per module. 14 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 3.4 2GB, 256Mx64 Module(2Rank of x8) S1 S0 DQS0 DQS0 DM0 DQS4 DQS4 DM4 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQS DQS D0 ZQ DQS1 DQS1 DM1 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 D1 ZQ DQS2 DQS2 DM2 DQS3 DQS3 DM3 DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D2 ZQ CS DQS DQS D3 ZQ DM CS DQS DQS I/O 0 I/O 1 D8 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 ZQ I/O 7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS DQS DQS I/O 0 I/O 1 D4 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 D12 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS DQS DQS I/O 0 I/O 1 D5 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 D13 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS DQS DQS I/O 0 I/O 1 D6 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 D14 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS DQS DQS I/O 0 I/O 1 D7 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 D15 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS5 DQS5 DM5 DM CS DQS DQS I/O 0 I/O 1 D9 I/O 2 I/O 3 I/O 4 I/O 5 ZQ I/O 6 I/O 7 DQS6 DQS6 DM6 DM CS DQS DQS I/O 0 I/O 1 D10 I/O 2 I/O 3 I/O 4 I/O 5 ZQ I/O 6 I/O 7 RESET ZQ ZQ ZQ DQS7 DQS7 DM7 DM CS DQS DQS I/O 0 I/O 1 D11 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 ZQ I/O 7 Serial PD BA0-BA2 A0-A15 CKE1 CKE0 RAS CAS WE ODT0 ODT1 CK0 CK0 CK1 CK1 ZQ BA0-BA2: SDRAMs D0-D15 SCL A0-A15: SDRAMs D0-D15 WP CKE: SDRAMs D8-D15 A0 CKE: SDRAMs D0-D7 SA0 RAS: SDRAMs D0-D15 CAS: SDRAMs D0-D15 VDDSPD WE: SDRAMs D0-D15 VDD/VDDQ ODT: SDRAMs D0-D7 VREFDQ ODT: SDRAMs D8-D15 CK: SDRAMs D0-D7 VSS CK: SDRAMs D0-D7 VREFCA CK: SDRAMs D8-D15 CK: SDRAMs D8-D15 SDA A1 A2 SA1 SA2 SPD D0-D15 D0-D15 D0-D15 D0-D15 ZQ ZQ Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ,DM,DQS,DQS resistors;Refer to associated topology diagram. 4. Refer to Section 3.1 of this document for details on address mirroring. 5. For each DRAM, a unique ZQ resistor is connected to ground.The ZQ resistor is 240ohm+-1% 6. One SPD exists per module. RESET:SDRAMs D0-D3 Rev. 0.1 / Dec 2008 15 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 3.5 2GB, 256Mx72 Module(2Rank of x8) DQS1 DQS1 DM1 S1 S0 DQS0 DQS0 DM0 DQS4 DQS4 DM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS DQS DQS I/O 0 I/O 1 D0 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM CS DQS DQS I/O 0 I/O 1 D2 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS DQS DQS I/O 0 I/O 1 D3 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS2 DQS2 DM2 DQS3 DQS3 DM3 D1 ZQ ZQ DQS5 DQS5 DM5 D10 ZQ DQS6 DQS6 DM6 D11 ZQ DQS7 DQS7 DM7 ZQ DQS8 DQS8 DM8 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS DQS DQS I/O 0 I/O 1 D5 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DM CS DQS DQS I/O 0 I/O 1 D6 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS DQS DQS I/O 0 I/O 1 D7 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS CS DQS DQS D12 ZQ ZQ ZQ VDDSPD SPD(TS integrated) DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ BA0-BA2: SDRAMs D0-D17 A0-A15: SDRAMs D0-D17 CKE: SDRAMs D0-D8 CKE: SDRAMs D9-D17 RAS: SDRAMs D0-D17 CAS: SDRAMs D0-D17 WE: SDRAMs D0-D17 Rev. 0.1 / Dec 2008 CS DQS DQS ODT0 ODT1 CK0 CK0 CK1 CK1 RESET D17 EVENT EVENT A0 SA0 SA1 A2 SA2 ZQ ODT: SDRAMs D0-D8 ODT: SDRAMs D9-D17 CK: SDRAMs D0-D8 CK: SDRAMs D0-D8 CK: SDRAMs D9-D17 CK: SDRAMs D9-D17 RESET:SDRAMs D0-D17 ZQ D14 ZQ D15 ZQ D16 ZQ SPD D0-D17 VREFDQ D0-D17 Vss D0-D17 VREFCA D0-D17 SDA A1 D13 VDD/VDDQ SCL DM CS DQS DQS I/O 0 I/O 1 D8 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 BA0-BA2 A0-A15 CKE0 CKE1 RAS CAS WE CS DQS DQS D9 DM CS DQS DQS I/O 0 I/O 1 D4 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. DQ,CB,DM/DQS/DQS resistors;Refer to associated topology diagram. 4. Refer to Section 3.1 of this document for details on address mirroring. 5. For each DRAM, a unique ZQ resistor is connected to ground.The ZQ resistor is 240ohm+-1% 6. One SPD exists per module. 16 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 4. Address Mirroring Feature There is a via grid located under the SDRAMs for wiring the CA signals (address, bank address, command, and control lines) to the SDRAM pins. The length of the traces from the via to the SDRAMs places limitations on the bandwidth of the module. The shorter these traces, the higher the bandwidth. To extend the bandwidth of the CA bus for DDR3 modules, a scheme was defined to reduce the length of these traces.The pins on the SDRAM are defined in a manner that allows for these short trace lengths. The CA bus pins in Columns 2 and 8, ignoring the mechanical support pins, do not have any special functions (secondary functions). This allows the most flexibility with these pins. These are address pins A3, A4, A5, A6, A7, A8 and bank address pins BA0 and BA1. Refer to Table . Rank 0 SDRAM pins are wired straight, with no mismatch between the connector pin assignment and the SDRAM pin assignment. Some of the Rank 1 SDRAM pins are cross wired as defined in the table. Pins not listed in the table are wired straight. 4.1 DRAM Pin Wiring for Mirroring Connector Pin SDRAM Pin Rank 0 Rank 1 A3 A3 A4 A4 A4 A3 A5 A5 A6 A6 A6 A5 A7 A7 A8 A8 A8 A7 BA0 BA0 BA1 BA1 BA1 BA0 <Table 4.1: SDRAM Pin Wiring for Mirroring > The table 4.1 illustrates the wiring in both the mirrored and non-mirrored case. The lengths of the traces to the SDRAM pins, is obviously shorter. The via grid is smaller as well. Rev. 0.1 / Dec 2008 17 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C No Mirroring Mirroring < Figure 4.1: Wiring Differences for Mirrored and Non-Mirrored Addresses > Since the cross-wired pins have no secondary functions, there is no problem in normal operation. Any data written is read the same way. There are limitations however. When writing to the internal registers with a "load mode" operation, the specific address is required. This requires the controller to know if the rank is mirrored or not. This requires a few rules. Mirroring is done on 2 rank modules and can only be done on the second rank. There is not a requirement that the second rank be mirrored. There is a bit assignment in the SPD that indicates whether the module has been designed with the mirrored feature or not. See the DDR3 UDIMM SPD specification for these details. The controller must read the SPD and have the capability of de-mirroring the address when accessing the second rank. Rev. 0.1 / Dec 2008 18 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 5. ABSOLUTE MAXIMUM RATINGS 5.1 Absolute Maximum DC Ratings Symbol Parameter VDD VDDQ VIN, VOUT TSTG Rating Units Notes Voltage on VDD pin relative to Vss - 0.4 V ~ 1.975 V V ,3 Voltage on VDDQ pin relative to Vss - 0.4 V ~ 1.975 V V ,3 Voltage on any pin relative to Vss - 0.4 V ~ 1.975 V V -55 to +100 Storage Temperature ,2 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times;and VREF must be not greater than 0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. 5.2 DRAM Component Operating Temperature Range Symbol TOPER Parameter Rating Units Notes Normal Temperature Range 0 to 85 ,2 Extended Temperature Range 85 to 95 1,3 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85... and 95... case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 s. (This double refresh requirement may not apply for some devices.) It is also possible to specify a component with 1X refresh (tREFI to 7.8s) in the Extended Temperature Range. Please refer to supplier data sheet and/ or the DIMM SPD for option avail ability. b) If Self-Refresh operation is required in the Extended Temperature Range, than it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0band MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). Rev. 0.1 / Dec 2008 19 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 6. AC & DC Operating Conditions 6.1 Recommended DC Operating Conditions Symbol Parameter VDD VDDQ Rating Units Notes 1.575 V 1,2 1.575 V 1,2 Min. Typ. Max. Supply Voltage 1.425 1.500 Supply Voltage for Output 1.425 1.500 1. Under all conditions, VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD abd VDDQ tied together. 6.2 DC & AC Logic Input Levels 6.2.1 DC & AC Logic Input Levels for Single-Ended Signals DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600 Symbol Parameter Unit Notes - V 1, 2 Vref - 0.100 V 1, 2 - V 1, 2 Vref - 0.175 V 1, 2 Min Max Vref + 0.100 VIH(DC) DC input logic high VIL(DC) DC input logic low VIH(AC) AC input logic high VIL(AC) AC input logic low VRefDQ(DC) Reference Voltage for DQ, DM inputs 0.49 * VDD 0.51 * VDD V 3, 4 VRefCA(DC) Reference Voltage for ADD, CMD inputs 0.49 * VDD 0.51 * VDD V 3, 4 VTT Termination voltage for DQ, DQS outputs VDDQ/2 - TBD VDDQ/2 + TBD V Vref + 0.175 1. For DQ and DM, Vref = VrefDQ. For input ony pins except RESET#, Vref = VrefCA. 2. The "t.b.d." entries might change based on overshoot and undershoot specification. 3. The ac peak noise on VRef may not allow VRef to deviate from VRef(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). For reference: approx. VDD/2 +/- 15 mV. The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in figure 6.2.1. It shows a valid reference voltage VRef(t) as a function of time. (VRef stands for VRefCA and VRefDQ likewise).VRef(DC) is the linear average of VRef(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in Table 1. Furthermore VRef(t) may temporarily deviate from VRef(DC) by no more than +/- 1% VDD. Rev. 0.1 / Dec 2008 20 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C voltage VDD VRef(t) VRef ac-noise VRef(DC)max VRef(DC) VDD/2 VRef(DC)min VSS time < Figure 6.2.1: Illustration of Vref(DC) tolerance and Vref AC-noise limits > The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VRef. "VRef " shall be understood as VRef(DC), as defined in Figure 6.2.1 This clarifies, that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VRef(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VRef ac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings. 6.2.2 DC & AC Logic Input Levels for Differential Signals Symbol Parameter VIHdiff Differential input logic high VILdiff Differential input logic low DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600 Unit Notes - V 1 - 0.200 V 1 Min Max + 0.200 Note1: Refer to "Overshoot and Undershoot Specification section 6.5 on 26 page Rev. 0.1 / Dec 2008 21 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 6.2.3 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK# and DQS, DQS#) must meet the requirements in Table 6.2.3 The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the midlevel between of VDD and VSS. VDD CK#, DQS# VIX VDD/2 VIX VIX CK, DQS VSS < Figure 6.2.3 Vix Definition > DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600 Symbol VIX Parameter Differential Input Cross Point Voltage relative to VDD/2 Unit Min Max - 150 + 150 Notes mV < Table 6.2.3: Cross point voltage for differential input signals (CK, DQS) > Rev. 0.1 / Dec 2008 22 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 6.3 Slew Rate Definitions 6.3.1 For Single Ended Input Signals - Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS) Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VRef and the first crossing of VIH(AC)min. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VRef and the first crossing of VIL(AC)max. - Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH) Hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VRef. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VRef. Measured Description Input slew rate for rising edge Min Max Vref VIH(AC)min Input slew rate for falling edge Vref VIL(AC)max Input slew rate for rising edge VIL(DC)max Vref Input slew rate for falling edge VIH(DC)min Vref Defined by Applicable for VIH(AC)min-Vref Delta TRS Vref-VIL(AC)max Setup (tIS, tDS) Delta TFS Vref-VIL(DC)max Delta TFH VIH(DC)min-Vref Hold (tIH, tDH) Delta TRH < Table 6.3.1: Single-Ended Input Slew Rate Definition > Part A: Set up Single Ended input Voltage(DQ,ADD, CMD) Delta TRS vIH(AC)min vIH(DC)min vRefDQ or vRefCA vIL(DC)max vIL(AC)max Delta TFS Rev. 0.1 / Dec 2008 23 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C P a rt B : H o ld Single Ended input Voltage(DQ,ADD, CMD) D e lta T R H v IH (A C )m in v IH (D C )m in v R e fD Q o r v R e fC A v IL (D C )m a x v IL (A C )m a x D e lta T F H < Figure 6.3.1: Input Nominal Slew Rate Definition for Single-Ended Signals > 6.3.2 Differential Input Signals Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown in below Table and Figure . Description Differential input slew rate for rising edge (CK-CK and DQS-DQS) Differential input slew rate for falling edge (CK-CK and DQS-DQS) Measured Min Max VILdiffmax VIHdiffmin VIHdiffmin VILdiffmax Defined by VIHdiffmin-VILdiffmax DeltaTRdiff VIHdiffmin-VILdiffmax DeltaTFdiff Note: The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds. Rev. 0.1 / Dec 2008 24 Differential Input Voltage (i.e. DQS-DQS; CK-CK) HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C D e lta T R d iff vIH d iffm in 0 vILd iffm a x D e lta T F d iff < Figure 6.3.2: Differential Input Slew Rate Definition for DQS,DQS# and CK,CK# > 6.4 DC & AC Output Buffer Levels 6.4.1 Single Ended DC & AC Output Levels Below table shows the output levels used for measurements of single ended signals. Symbol VOH(DC) VOM(DC) VOL(DC) VOH(AC) VOL(AC) Parameter DC output high measurement level (for IV curve linearity) DC output mid measurement level (for IV curve linearity) DC output low measurement level (for IV curve linearity) AC output high measurement level (for output SR) DDR3-800, 1066, 1333 and 1600 Unit 0.8 x VDDQ V 0.5 x VDDQ V 0.2 x VDDQ V VTT + 0.1 x VDDQ V Notes 1 AC output low measurement level VTT - 0.1 x VDDQ V 1 (for output SR) 1. The swing of 0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test load of 25 to VTT = VDDQ / 2. Rev. 0.1 / Dec 2008 25 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 6.4.2 Differential DC & AC Output Levels Below table shows the output levels used for measurements of differential signals. Symbol VOHdiff (AC) Parameter DDR3-800, 1066, 1333 and 1600 Unit Notes + 0.2 x VDDQ V 1 AC differential output high measurement level (for output SR) VOLdiff (AC) AC differential output low - 0.2 x VDDQ V 1 measurement level (for output SR) 1. The swing of ae 0.2 x VDDQ is based on approximately 50% of the static differential output high or low swingwith a driver impedance of 40Y and an effective test load of 25Y to VTT = VDDQ/2 at each of the differential output 6.4.3 Single Ended Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in below Table and Figure 6.4.3. Description Measured From To Single ended output slew rate for rising edge VOL(AC) VOH(AC) Single ended output slew rate for falling edge VOH(AC) VOL(AC) Defined by VOH(AC)-VOL(AC) DeltaTRse VOH(AC)-VOL(AC) DeltaTFse Note: Output slew rate is verified by design and characterization, and may not be subject to production test. Single Ended Output Voltage(l.e.DQ) D e lt a T R s e vO H (A C ) V vO L(A C ) D e lt a T F s e < Figure 6.4.3: Single Ended Output Slew Rate Definition > Rev. 0.1 / Dec 2008 26 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Parameter Symbol Single-ended Output Slew Rate SRQse DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Min Max Min Max Min Max Min Max 2.5 5 2.5 5 2.5 5 TBD 5 Units V/ns *** Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) For Ron = RZQ/7 setting < Table 6.4.3: Output Slew Rate (single-ended) > 6.4.4 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in below Table and Figure 6.4.4 Description Measured Defined by From To Differential output slew rate for rising edge VOLdiff(AC) VOHdiff(AC) Differential output slew rate for falling edge VOHdiff(AC) VOLdiff(AC) VOHdiff(AC)-VOLdiff(AC) DeltaTRdiff VOHdiff(AC)-VOLdiff(AC) DeltaTFdiff Note: Output slew rate is verified by design and characterization, and may not be subject to production test. Differential Output Voltage(i.e. DQS-DQS) D e lta T R d iff v O H d iff(A C ) O v O L d iff(A C ) D e lta T F d iff < Figure 6.4.4: Differential Output Slew Rate Definition > Rev. 0.1 / Dec 2008 27 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C DDR3-800 Parameter Differential Output Slew Rate Symbol SRQdiff DDR3-1066 DDR3-1333 DDR3-1600 Min Max Min Max Min Max Min Max 5 10 5 10 5 10 TBD 10 Units V/ns ***Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) diff: Differential Signals For Ron = RZQ/7 setting < Table 6.6.4: Differential Output Slew Rate > 6.5 Overshoot and Undershoot Specifications 6.5.1 Address and Control Overshoot and Undershoot Specifications Description Maximum peak amplitude allowed for overshoot area (see Figure) Maximum peak amplitude allowed for undershoot area (see Figure) Maximum overshoot area above VDD (See Figure) Maximum undershoot area below VSS (See Figure) Specification DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V 0.67 V-ns 0.5 V-ns 0.4 V-ns 0.33 V-ns 0.67 V-ns 0.5 V-ns 0.4 V-ns 0.33 V-ns < Table 6.5.1: AC Overshoot/Undershoot Specification for Address and Control Pins > < Figure 6.5.1: Address and Control Overshoot and Undershoot Definition > Maximum Amplitude Overshoot Area Volts (V) VDD VSS Undershoot Area Maximum Amplitude Time (ns) Rev. 0.1 / Dec 2008 28 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 6.5.2 Clock,Data,Strobe and Mask Overshoot and Undershoot Specifications Specification Description Maximum peak amplitude allowed for overshoot area (see Figure) Maximum peak amplitude allowed for undershoot area (see Figure) Maximum overshoot area above VDDQ (See Figure) Maximum undershoot area below VSSQ (See Figure) DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V 0.25 V-ns 0.19 V-ns 0.15 V-ns 0.13 V-ns 0.25 V-ns 0.19 V-ns 0.15 V-ns 0.13 V-ns < Table 6.5.2: AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask > M a x im u m A m p litu d e O v e rsh o o t A re a V o lts (V ) VDDQ VSSQ U n d e rsh o o t A re a M a x im u m A m p litu d e T im e (n s) C lo c k , D a ta S tro b e a n d M a sk O v e rsh o o t a n d U n d e rsh o o t D e fin itio n < Figure 6.5.2: Clock, Data, Strobe and Mask Overshoot and Undershoot Definition > Rev. 0.1 / Dec 2008 29 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 6.6 Pin Capacitance DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Min Max Min Max Min Max Min Max CIO 1.5 3.0 1.5 3.0 1.5 2.5 TBD TBD pF 1,2,3 Input capacitance, CK and CK# CCK TBD 1.6 TBD 1.6 TBD TBD TBD TBD pF 2,3,5 Input capacitance delta CK and CK# CDCK 0 0.15 0 0.15 TBD TBD TBD TBD pF 2,3,4 CI TBD 1.5 TBD 1.5 TBD TBD TBD TBD pF 2,3,6 CDDQS 0 0.20 0 0.20 TBD TBD TBD TBD pF 2,3,12 CDI_CTRL -0.5 0.3 -0.5 0.3 TBD TBD TBD TBD pF 2,3,7,8 Input capacitance delta CDI_ADD_ (All ADD/CMD input-only pins) CMD -0.5 0.5 -0.5 0.5 TBD TBD TBD TBD pF 2,3,9, 10 Input/output capacitance delta (DQ, DM, DQS, DQS#) -0.5 0.3 -0.5 0.3 TBD TBD TBD TBD pF 2,3,11 Parameter Symbol Input/output capacitance (DQ, DM, DQS, DQS#, TDQS, TDQS#) Input capacitance (All other input-only pins) Input capacitance delta, DQS and DQS# Input capacitance delta (All CTRL input-only pins) CDIO Units Notes Notes: 1. TDQS/TDQS# are not necessarily input function but since TDQS is sharing DM pin and the parasitic characterization of TDQS/TDQS# should be close as much as possible, Cio&Cdio requirement is applied (recommend deleting note or changing to "Although the DM, TDQS and TDQS# pins have different functions, the loading matches DQ and DQS.") 2. This parameter is not subject to production test. It is verified by design and characterization. Input capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER(VNA)") with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE, RESET# and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off. 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK#. 5. The minimum CCK will be equal to the minimum CI. 6. Input only pins include: ODT, CS, CKE, A0-A15, BA0-BA2, RAS#, CAS#, WE#. 7. CTRL pins defined as ODT, CS and CKE. 8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK#)) 9. ADD pins defined as A0-A15, BA0-BA2 and CMD pins are defined as RAS#, CAS# and WE#. 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK#)) 11. CDIO=CIO(DQ) - 0.5*(CIO(DQS)+CIO(DQS#)) 12. Absolute value of CIO(DQS) - CIO(DQS#) Rev. 0.1 / Dec 2008 30 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 6.7 IDD Specifications(TCASE: 0 to 95oC) 512MB, 64M x 64 U-DIMM: HMT164U6AFP6C Symbol DDR3 800 DDR3 1066 DDR3 1333 Unit note IDD0 360 420 480 mA IDD1 480 540 580 mA IDD2P(F) 100 120 140 mA IDD2P(S) 40 40 40 mA IDD2Q 180 240 280 mA IDD2N 200 240 300 mA IDD3P 140 180 200 mA IDD3N 220 280 340 mA IDD4W 700 880 1060 mA IDD4R 700 860 1020 mA IDD5B 740 780 840 mA IDD6(D) 40 40 40 mA 1 IDD6(S) 24 24 24 mA 1 IDD7 1300 1420 1720 mA 1GB, 128M x 64 U-DIMM: HMT112U6AFP8C Symbol DDR3 800 DDR3 1066 DDR3 1333 Unit IDD0 640 760 840 mA IDD1 760 880 960 mA IDD2P(F) 200 240 280 mA IDD2P(S) 80 80 80 mA IDD2Q 360 480 560 mA IDD2N 400 480 600 mA IDD3P 280 360 400 mA IDD3N 440 560 680 mA IDD4W 1120 1440 1560 mA IDD4R 1040 1320 1680 mA IDD5B 1480 1560 1720 mA IDD6(D) 80 80 80 mA 1 IDD6(S) 48 48 48 mA 1 IDD7 1800 2000 2440 mA Rev. 0.1 / Dec 2008 note 31 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 1GB, 128M x 72 U-DIMM: HMT112U7AFP8C Symbol DDR3 800 DDR3 1066 DDR3 1333 Unit note IDD0 720 855 945 mA IDD1 855 990 1080 mA IDD2P(F) 225 270 315 mA IDD2P(S) 90 90 90 mA IDD2Q 405 540 630 mA IDD2N 450 540 675 mA IDD3P 315 405 450 mA IDD3N 495 630 765 mA IDD4W 1260 1620 1755 mA IDD4R 1170 1485 1890 mA IDD5B 1665 1755 1935 mA IDD6(D) 90 90 90 mA 1 IDD6(S) 54 54 54 mA 1 IDD7 2025 2250 2745 mA 2GB, 256M x 64 U-DIMM: HMT125U6AFP8C Symbol DDR3 800 DDR3 1066 DDR3 1333 Unit IDD0 1040 1240 1440 mA IDD1 1160 1360 1560 mA IDD2P(F) 400 480 560 mA IDD2P(S) 160 160 160 mA IDD2Q 720 960 1120 mA IDD2N 800 960 1200 mA IDD3P 560 720 800 mA IDD3N 880 1120 1360 mA IDD4W 1520 1920 2160 mA IDD4R 1440 1800 2280 mA IDD5B 1880 2040 2320 mA IDD6(D) 160 160 160 mA 1 IDD6(S) 96 96 96 mA 1 IDD7 2200 2480 3040 mA Rev. 0.1 / Dec 2008 note 32 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 2GB, 256M x 72 U-DIMM: HMT125U7AFP8C Symbol DDR3 800 DDR3 1066 DDR3 1333 Unit note IDD0 1170 1395 1620 mA IDD1 1305 1530 1755 mA IDD2P(F) 450 540 630 mA IDD2P(S) 180 180 180 mA IDD2Q 810 1080 1260 mA IDD2N 900 1080 1350 mA IDD3P 630 810 900 mA IDD3N 990 1260 1530 mA IDD4W 1710 2160 2430 mA IDD4R 1620 2025 2565 mA IDD5B 2115 2295 2610 mA IDD6(D) 180 180 180 mA 1 IDD6(S) 108 108 108 mA 1 IDD7 2475 2790 3420 mA 6.7 IDD Measurement Conditions Within the tables provided further down, an overview about the IDD measurement conditions is provided as follows: Table 1 -- Overview of Tables providing IDD Measurement Conditions and DRAM Behavior Table number Measurement Conditions Table 5 on page 33 IDD0 and IDD1 Table 6 on page 36 IDD2N, IDD2Q, IDD2P(0), IDD2P(1) Table 7 on page 38 IDD3N and IDD3P Table 8 on page 39 IDD4R, IDD4W, IDD7 Table 9 on page 42 IDD7 for different Speed Grades and different tRRD, tFAW conditions Table 10 on page 43 IDD5B Table 11 on page 44 IDD6, IDD6ET Within the tables about IDD measurement conditions, the following definitions are used: - LOW is defined as VIN <= VILAC(max.); HIGH is defined as VIN >= VIHAC(min.). - STABLE is defined as inputs are stable at a HIGH or LOW level. - FLOATING is defined as inputs are VREF = VDDQ / 2. - SWITCHING is defined as described in the following 2 tables. Rev. 0.1 / Dec 2008 33 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Table 2 -- Definition of SWITCHING for Address and Command Input Signals SWITCHING for Address (row, column) and Command Signals (CS, RAS, CAS, WE) is defined as: If not otherwise mentioned the inputs are stable at HIGH or LOW during 4 clocks and change Address (row, column): then to the opposite value (e.g. Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax..... please see each IDDx definition for details Bank address: If not otherwise mentioned the bank addresses should be switched like the row/column addresses - please see each IDDx definition for details Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW} Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH,HIGH,HIGH} Command (CS, RAS, CAS, WE): Define Command Background Pattern = D D D D D D D D D D D D... If other commands are necessary (e.g. ACT for IDD0 or Read for IDD4R), the Background Pattern Command is substituted by the respective CS, RAS, CAS, WE levels of the necessary command. See each IDDx definition for details and figures 1,2,3 as examples. Table 3 -- Definition of SWITCHING for Data (DQ) SWITCHING for Data (DQ) is defined as Data (DQ) Data Masking (DM) Rev. 0.1 / Dec 2008 Data DQ is changing between HIGH and LOW every other data transfer (once per clock) for DQ signals, which means that data DQ is stable during one clock; see each IDDx definition for exceptions from this rule and for further details. See figures 1,2,3 as examples. NO Switching; DM must be driven LOW all the time 34 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Timing parameters are listed in the following table: Table 4 -- For IDD testing the following parameters are utilized. Parameter Bin DDR3-800 5-5-5 tCKmin(IDD) 6-6-6 DDR3-1066 6-6-6 2.5 CL(IDD) 7-7-7 DDR3-1333 8-8-8 7-7-7 8-8-8 1.875 DDR3-1600 9-9-9 8-8-8 1.5 9-9-9 101010 1.25 Unit ns 5 6 6 7 8 7 8 9 8 9 10 clk tRCDmin(IDD) 12.5 15 11.25 13.13 15 10.5 12 13.5 10 11.25 12.5 ns tRCmin(IDD) 50 52.5 48.75 50.63 52.50 46.5 48 49.5 tbd tbd tbd ns tRASmin(IDD) 37.5 37.5 37.5 37.5 37.5 36 36 36 tbd tbd tbd ns tRPmin(IDD) 12.5 15 11.25 13.13 15 10.5 12 13.5 10 11.25 12.5 ns x4/ x8 40 40 37.5 37.5 37.5 30 30 30 30 30 30 ns x16 50 50 50 50 50 45 45 45 40 40 40 ns x4/ x8 10 10 7.5 7.5 7.5 6.0 6.0 6.0 6.0 6.0 6.0 ns x16 10 10 10 10 10 7.5 7.5 7.5 7.5 7.5 7.5 ns tRFC(IDD) - 90 90 90 90 90 90 90 90 90 90 90 ns tRFC(IDD) - 1 110 110 110 110 110 110 110 110 110 110 110 ns tRFC(IDD) - 2 160 160 160 160 160 160 160 160 160 160 160 ns tRFC(IDD) - 4 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns tFAW(IDD) tRRD(IDD) 512Mb Gb Gb Gb The following conditions apply: - IDD specifications are tested after the device is properly initialized. - Input slew rate is specified by AC Parametric test conditions. - IDD parameters are specified with ODT and output buffer disabled (MR1 Bit A12). Rev. 0.1 / Dec 2008 35 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Table 5 -- IDD Measurement Conditions for IDD0 and IDD1 IDD0 Current Operating Current 0 Name -> One Bank Activate -> Precharge IDD1 Operating Current 1 -> One Bank Activate -> Read -> Precharge Measurement Condition Timing Diagram Example Figure 1 CKE HIGH HIGH External Clock on on tCK tCKmin(IDD) tCKmin(IDD) tRC tRCmin(IDD) tRCmin(IDD) tRAS tRASmin(IDD) tRASmin(IDD) tRCD n.a. tRCDmin(IDD) tRRD n.a. n.a. CL n.a. CL(IDD) AL n.a. 0 CS HIGH between. Activate and Precharge HIGH between Activate, Read and Commands Precharge Command Inputs SWITCHING as described in Table 2 SWITCHING as described in Table 2; only (CS,RAS, CAS, WE) only exceptions are Activate and exceptions are Activate, Read and Precharge commands; example of IDD0 Precharge commands; example of IDD1 pattern: pattern: A0DDDDDDDDDDDDDD P0 A0DDDDR0DDDDDDDDD P0 (DDR3-800: tRAS = 37.5ns between (DDR3-800 -555: tRCD = 12.5ns between (A)ctivate and (P)recharge to bank 0; (A)ctivate and (R)ead to bank 0; Definition of D and D: see Table 2 Definition of D and D: see Table 2) Rev. 0.1 / Dec 2008 36 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Table 5 -- IDD Measurement Conditions for IDD0 and IDD1 IDD0 Current Operating Current 0 Name -> One Bank Activate -> Precharge Row, Column Addresses IDD1 Operating Current 1 -> One Bank Activate -> Read -> Precharge Row addresses SWITCHING as described Row addresses SWITCHING as described in Table 2; in Table 2; Address Input A10 must be LOW all the Address Input A10 must be LOW all the time! time! Bank Addresses bank address is fixed (bank 0) bank address is fixed (bank 0) Data I/O SWITCHING as described in Table 3 Read Data: output data switches every clock, which means that Read data is stable during one clock cycle. To achieve Iout = 0mA, the output buffer should be switched off by MR1 Bit A12 set to "1". When there is no read data burst from DRAM, the DQ I/O should be FLOATING. Output Buffer DQ,DQS off / 1 off / 1 ODT disabled disabled / MR1 bits [A6, A2] / [0,0] / [0,0] Burst length n.a. 8 fixed / MR0 Bits [A1, A0] = {0,0} Active banks one one ACT-PRE loop ACT-RD-PRE loop all other all other / MR1 bit A12 Idle banks Precharge Power Down Mode / n.a. n.a. Mode Register Bit 12 Rev. 0.1 / Dec 2008 37 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T12 T14 T16 T18 CK 000 BA[2:0] ADDR_a[9:0] 000 3FF 000 3FF 000 00 11 00 11 00 3F ADDR_b[10] ADDR_c[12:11] CS RAS CAS WE CMD ACT DQ DM D D# D# D RD D# D# D D D# D# D D D# PRE D D D# 0 0 1 1 0 0 1 1 IDD1 Measurment Loop < Figure 1. IDD1 Example > (DDR3-800-555, 512Mb x8): Data DQ is shown but the output buffer should be switched off (per MR1 Bit A12 ="1") to achieve Iout = 0mA. Address inputs are split into 3 parts. a. In DDR3, the MRS Bit 12 defines DLL on/off behaviour ONLY for precharge power down. There are 2 different Precharge Power Down states possible: one with DLL on (fast exit, bit 12 = 1) and one with DLL off (slow exit, bit 12 = 0). b. Because it is an exit after precharge power down, the valid commands are: Activate, Refresh, Mode-Register Set, Enter - Self Refresh Rev. 0.1 / Dec 2008 38 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Table 6 -- IDD Measurement Conditions for IDD2N, IDD2P(1), IDD2P(0) and IDD2Q Name IDD2P(1) a IDD2N Current Precharge Power Precharge Standby Down Current Current Fast Exit MRS A12 Bit = 1 IDD2P(0) IDD2Q Precharge Power Down Current Slow Exit MRS A12 Bit = 0 Precharge Quiet Standby Current Measurement Condition Timing Diagram Example Figure 2 CKE HIGH LOW LOW HIGH External Clock on on on on tCK tCKmin(IDD) tCKmin(IDD) tCKmin(IDD) tCKmin(IDD) tRC n.a. n.a. n.a. n.a. tRAS n.a. n.a. n.a. n.a. tRCD n.a. n.a. n.a. n.a. tRRD n.a. n.a. n.a. n.a. CL n.a. n.a. n.a. n.a. AL n.a. n.a. n.a. n.a. CS HIGH STABLE STABLE HIGH Bank Address, Row Addr. and Command Inputs SWITCHING as described in Table 2 STABLE STABLE STABLE Data inputs SWITCHING FLOATING FLOATING FLOATING Output Buffer DQ,DQS / MR1 bit A12 off / 1 off / 1 off / 1 off / 1 ODT / MR1 bits [A6, A2] disabled / [0,0] disabled / [0,0] disabled / [0,0] disabled / [0,0] Burst length n.a. n.a. n.a. n.a. Active banks none none none none Idle banks all all all all Fast Exit / 1 (any valid command after tXPb) Slow Exit / 0 Slow exit (RD and n.a. ODT commands must satisfy tXPDLL-AL) Precharge Power Down Mode / Mode Register Bit a n.a. a. b. Rev. 0.1 / Dec 2008 39 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 CK BA[2:0] ADDR[12:0] 0 7 0 0 7 0 CS RAS CAS WE D# CMD DQ[7:0] FF 00 D# 00 FF D FF 00 D 00 FF D# FF 00 D# 00 FF D FF 00 D 00 FF D# FF 00 D# 00 FF FF DM <Figure 2. IDD2N / IDD3N Example > (DDR3-800-555, 512Mb x8) Rev. 0.1 / Dec 2008 40 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Table 7 -- IDD Measurement Conditions for IDD3N and IDD3P(fast exit) Current IDD3N Name Active Standby Current IDD3P Active Power-Down Currenta Always Fast Exit Measurement Condition Timing Diagram Example Figure 2 CKE HIGH LOW External Clock on on tCK tCKmin(IDD) tCKmin(IDD) tRC n.a. n.a. tRAS n.a. n.a. tRCD n.a. n.a. tRRD n.a. n.a. CL n.a. n.a. AL n.a. n.a. CS HIGH STABLE Addr. and cmd Inputs SWITCHING as described in Table 2 STABLE Data inputs SWITCHING as described in Table 3 FLOATING off / 1 off / 1 ODT disabled disabled / MR1 bits [A6, A2] / [0,0] / [0,0] Burst length n.a. n.a. Active banks all all Idle banks none none Output Buffer DQ,DQS / MR1 bit A12 Precharge Power Down Mode / Mode Register Bit a n.a. n.a. (Active Power Down Mode is always "Fast Exit" with DLL on a. DDR3 will offer only ONE active power down mode with DLL on (-> fast exit). MRS bit 12 will not be used for active power down. Instead bit 12 will be used to switch between two different precharge power down modes. Rev. 0.1 / Dec 2008 41 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Table 8 -- IDD Measurement Conditions for IDD4R, IDD4W and IDD7 Current IDD4R IDD4W IDD7 Name Operating Current Burst Read Operating Current Burst Write All Bank Interleave Read Current Measurement Condition Timing Diagram Example Figure 3 CKE HIGH HIGH HIGH External Clock on on on tCK tCKmin(IDD) tCKmin(IDD) tCKmin(IDD) tRC n.a. n.a. tRCmin(IDD) tRAS n.a. n.a. tRASmin(IDD) tRCD n.a. n.a. tRCDmin(IDD) tRRD n.a. n.a. tRRDmin(IDD) CL CL(IDD) CL(IDD) CL(IDD) AL 0 0 tRCDmin - 1 tCK CS HIGH btw. valid cmds HIGH btw. valid cmds HIGH btw. valid cmds Command Inputs (CS, RAS, CAS, WE) SWITCHING as described in Table 2; exceptions are Read commands => IDD4R Pattern: SWITCHING as described in Table 2; exceptions are Write commands => IDD4W Pattern: For patterns see Table 9 R0DDDR1DDDR2DDDR3.DD W0DDDW1DDDW2DDDW3 DDD W4... D R4..... Rx = Read from bank x; Wx = Write to bank x; Definition of D and D: see Definition of D and D: see Table 2 Table 2 Rev. 0.1 / Dec 2008 42 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Table 8 -- IDD Measurement Conditions for IDD4R, IDD4W and IDD7 Current IDD4R IDD4W IDD7 Name Operating Current Burst Read Operating Current Burst Write All Bank Interleave Read Current column addresses column addresses SWITCHING as described in SWITCHING as described in Table 2; Table 2; Address Input A10 must be Address Input A10 must be LOW all the time! LOW all the time! Row, Column Addresses Bank Addresses bank address cycling (0 -> 1 - bank address cycling (0 -> 1 > 2 -> 3...) Seamless Read Data Burst (BL8): output data switches every clock, which means that Read data is stable during one DQ I/O clock cycle. To achieve Iout = 0mA the output buffer should be > 2 -> 3...) STABLE during DESELECTs bank address cycling (0 -> 1 > 2 -> 3...), see pattern in Table 9 Seamless Write Data Burst Read Data (BL8): output data (BL8): input data switches switches every clock, which every clock, which means that means that Read data is Write data is stable during one stable during one clock cycle. clock cycle. To achieve Iout = 0mA the DM is low all the time. output buffer should be switched off by MR1 Bit A12 switched off by MR1 Bit A12 set to "1". set to "1". Output Buffer DQ,DQS off / 1 off / 1 off / 1 ODT disabled disabled disabled / MR1 bits [A6, A2] / [0,0] / [0,0] / [0,0] 8 fixed / MR0 Bits [A1, A0] = 8 fixed / MR0 Bits [A1, A0] = 8 fixed / MR0 Bits [A1, A0] = {0,0} {0,0} {0,0} Active banks all all all, rotational Idle banks none none none n.a. n.a. n.a. / MR1 bit A12 Burst length Precharge Power Down Mode / Mode Register Bit Rev. 0.1 / Dec 2008 43 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C CK BA[2:0] ADDR[12:0] 000 001 010 011 000 3FF 000 3FF 00 11 00 11 ADDR_b[10] ADDR_c[12:11] CS RAS CAS WE CMD[2:0] DQ[7:0] DM RD D D# D# RD D D# 00 00 FF D# FF 00 RD 00 FF D FF D# 00 00 FF D# FF 00 RD 00 FF FF -> Start of Measurement Loop < Figure 3. IDD4R Example > (DDR3-800-555, 512Mb x8): data DQ is shown but the output buffer should be switched off (per MR1 Bit A12="1") to achieve Iout = 0mA. Address inputs are split into 3 parts. Rev. 0.1 / Dec 2008 44 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Table 9 -- Speed IDD7 Pattern for different Speed Grades and different tRRD, tFAW conditions Bin Org. Mb/s IDD7 Patterna tFAW tFAW tRRD tRRD [ns] [CLK] [ns] [CLK] (Note this entire sequence is repeated.) all x4/x8 40 16 10 4 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D all x16 50 20 10 4 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D DDDD all x4/x8 37.5 20 7.5 4 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D DDDD all x16 50 27 10 6 A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D A4 RA4 D D D D A5 RA5 D D D D A6 RA6 D D D D A7 RA7 D D D D D D D all x4/x8 30 20 6 4 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D DDDD all x16 45 30 7.5 5 A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D D D D D D D D A4 RA4 D D D A5 RA5 D D D A6 RA6 D D D A7 RA7 D D D D D D D D D D D D D all x4/x8 30 24 6 5 A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D D A4 RA4 D D D A5 RA5 D D D A6 RA6 D D D A7 RA7 D D D D D D D 6 A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D D D D D D A4 RA4 D D D D A5 RA5 D D D D A6 RA6 D D D D A7 RA7 D D D D D D D D D DDD 800 1066 1333 1600 all x16 40 32 7.5 a. A0 = Activation of Bank 0; RA0 = Read with Auto-Precharge of Bank 0; D = Deselect Rev. 0.1 / Dec 2008 45 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Table 10 -- IDD Measurement Conditions for IDD5B IDD5B Current Name Burst Refresh Current Measurement Condition CKE HIGH External Clock on tCK tCKmin(IDD) tRC n.a. tRAS n.a. tRCD n.a. tRRD n.a. tRFC tRFCmin(IDD) CL n.a. AL n.a. CS HIGH btw. valid cmds Addr. and cmd Inputs SWITCHING Data inputs SWITCHING Output Buffer DQ,DQS / MR1 bit A12 off / 1 ODT / MR1 bits [A6, A2] disabled / [0,0] Burst length n.a. Active banks Refresh command every tRFC=tRFCmin Idle banks none Precharge Power Down Mode / Mode Register Bit n.a. Rev. 0.1 / Dec 2008 46 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C Table 11 -- IDD Measurement Conditions for IDD6 and IDD6ET Current IDD6 IDD6ET Name Self-Refresh Current Normal Temperature Range TCASE = 0. 85 C Self-Refresh Current Extended Temperature Range a TCASE = 0. 95 C Measurement Condition Temperature TCASE = 85 C TCASE = 95 C Auto Self Refresh (ASR) / MR2 Bit A6 Disabled / "0" Disabled / "0" Self Refresh Temperature Range (SRT) / MR2 Bit A7 Normal / "0" Extended / "1" CKE LOW LOW External Clock OFF; CK and CK at LOW OFF; CK and CK at LOW tCK n.a. n.a. tRC n.a. n.a. tRAS n.a. n.a. tRCD n.a. n.a. tRRD n.a. n.a. CL n.a. n.a. AL n.a. n.a. CS FLOATING FLOATING Command Inputs (RAS, CAS, WE) FLOATING FLOATING Row, Column Addresses FLOATING FLOATING Bank Addresses FLOATING FLOATING Data I/O FLOATING FLOATING Output Buffer DQ,DQS / MR1 bit A12 off / 1 off / 1 ODT / MR1 bits [A6, A2] disabled / [0,0] disabled / [0,0] Burst length n.a. n.a. Active banks all during self-refresh actions all during self-refresh actions Idle banks all btw. Self-Refresh actions all btw. Self-Refresh actions Precharge Power Down Mode / MR0 bit A12 n.a. n.a. a. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material. Rev. 0.1 / Dec 2008 47 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 7. Electrical Characteristics and AC Timing 7.1 Refresh Parameters by Device Density Parameter Symbol 512Mb 1Gb 2Gb 4Gb 8Gb Units tRFC 90 110 160 300 350 ns 0 xC < TCASE < 85 xC 7.8 7.8 7.8 7.8 7.8 ms 85 xC < TCASE < 95 xC 3.9 3.9 3.9 3.9 3.9 ms REF command to ACT or REF command time Average periodic refresh interval tREFI 7.2 DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin DDR3 800 Speed Bin DDR3-800D DDR3-800E 5-5-5 6-6-6 CL - nRCD - nRP Unit Symbol min max min max Internal read command to first data tAA 12.5 20 15 20 ns ACT to internal read or write delay time tRCD 12.5 -- 15 -- ns PRE command period tRP 12.5 -- 15 -- ns ACT to ACT or REF command period tRC 50 -- 52.5 -- ns ACT to PRE command period tRAS 37.5 9 * tREFI 37.5 9 * tREFI ns Parameter CL = 5 CWL = 5 tCK(AVG) 2.5 3.3 CL = 6 CWL = 5 tCK(AVG) 2.5 3.3 Supported CL Settings Supported CWL Settings Rev. 0.1 / Dec 2008 Reserved 2.5 3.3 Notes ns 1)2)3)4) ns 1)2)3) 5, 6 6 nCK 5 5 nCK 48 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C DDR3 1066 Speed Bin DDR3-1066E DDR3-1066F DDR3-1066G CL - nRCD - nRP 6-6-6 7-7-7 8-8-8 Unit Parameter Symbol min max min max min max Internal read command to first data tAA 11.25 20 13.125 20 15 20 ns ACT to internal read or write delay time tRCD 11.25 -- 13.125 -- 15 -- ns PRE command period tRP 11.25 -- 13.125 -- 15 -- ns ACT to ACT or REF command period tRC 48.75 -- 50.625 -- 52.5 -- ns ACT to PRE command period tRAS 37.5 9 * tREFI 37.5 9 * tREFI 37.5 9 * tREFI ns CWL = 5 tCK(AVG) 2.5 3.3 CWL = 6 tCK(AVG) CWL = 5 tCK(AVG) 2.5 CWL = 6 tCK(AVG) 1.875 CWL = 5 tCK(AVG) CWL = 6 tCK(AVG) CWL = 5 tCK(AVG) CWL = 6 tCK(AVG) CL = 5 CL = 6 CL = 7 CL = 8 Reserved 3.3 < 2.5 Reserved 1.875 < 2.5 Reserved 1.875 < 2.5 Reserved Reserved ns 1)2)3)4)6) Reserved Reserved ns 4) ns 1)2)3)6) 2.5 3.3 2.5 3.3 Reserved Reserved ns 1)2)3)4) Reserved Reserved ns 4) Reserved ns 1)2)3)4) Reserved ns 4) ns 1)2)3) 1.875 < 2.5 Reserved 1.875 < 2.5 1.875 < 2.5 Supported CL Settings 5, 6, 7, 8 6, 7, 8 6, 8 nCK Supported CWL Settings 5, 6 5, 6 5, 6 nCK Rev. 0.1 / Dec 2008 Note 49 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C DDR3 1333 Speed Bin DDR3-1333F (optional) CL - nRCD - nRP 7-7-7 DDR3-1333G DDR3-1333H DDR3-1333J (optional) Unit 8-8-8 9-9-9 Parameter Symbol min max min max min max min max Internal read command to first tAA 10.5 20 12 20 13.5 20 15 20 ns ACT to internal read or write delay time tRCD 10.5 -- 12 -- 13.5 -- 15 -- ns PRE command period tRP 10.5 -- 12 -- 13.5 -- 15 -- ns ACT to ACT or REF command period tRC 46.5 -- 48 -- 49.5 -- 51 -- ns ACT to PRE command period tRAS 36 9* tREFI 36 9* tREFI 36 9* tREFI 36 9* tREFI ns tCK(AVG) 2.5 3.3 2.5 3.3 CL = 5 CL = 6 CL = 7 CL = 8 CL = 9 CWL = 5 CWL = 6, 7 tCK(AVG) Reserved CWL = 5 tCK(AVG) 2.5 3.3 CWL = 6 tCK(AVG) 1.875 < 2.5 CWL = 7 tCK(AVG) CWL = 5 tCK(AVG) CWL = 6 tCK(AVG) 1.875 < 2.5 CWL = 7 tCK(AVG) 1.5 <1.875 CWL = 5 tCK(AVG) CWL = 6 tCK(AVG) 1.875 < 2.5 1.875 < 2.5 CWL = 7 tCK(AVG) 1.5 <1.875 1.5 <1.875 CWL = 5, 6 tCK(AVG) CWL = 7 tCK(AVG) CWL = 5, 6 tCK(AVG) CL = 10 Reserved CWL = 7 tCK(AVG) 2.5 3.3 Reserved Reserved ns 1,2,3,4,7 Reserved Reserved ns 4 ns 1,2,3,7 2.5 3.3 2.5 3.3 Reserved Reserved Reserved ns 1,2,3,4,7 Reserved Reserved Reserved Reserved ns 4 Reserved Reserved Reserved Reserved ns 4 Reserved Reserved ns 1,2,3,4,7 Reserved Reserved Reserved ns 1,2,3,4 Reserved Reserved Reserved ns 4 ns 1,2,3,7 Reserved Reserved 1.5 <1.875 Reserved 1.5 <1.875 1.875 < 2.5 Reserved 1.5 <1.875 Reserved 1.5 <1.875 1.875 < 2.5 1.875 < 2.5 Reserved Reserved ns 1,2,3,4 Reserved Reserved ns 4 Reserved ns 1,2,3,4 Reserved ns 4 ns 1,2,3 ns 5 1.5 <1.875 Reserved 1.5 <1.875 1.5 <1.875 (Optional) (Optional) (Optional) Supported CL Settings 5, 6, 7, 8, 9 5, 6, 7, 8, 9 6, 8, 9 6, 8, 10 nCK Supported CWL Settings 5, 6, 7 5, 6, 7 5, 6, 7 5, 6, 7 nCK Rev. 0.1 / Dec 2008 Note 10-10-10 50 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C DDR3 1600 Speed Bin CL - nRCD - nRP DDR3-1600G DDR3-1600H DDR3-1600J (optional) 8-8-8 9-9-9 10-10-10 DDR3-1600K (optional) Unit Parameter Symbol min max min max min max min max Internal read command to first data tAA 10 20 11.25 20 12.5 20 13.75 20 ns ACT to internal read or write delay time tRCD 10 -- 11.25 -- 12.5 -- 13.75 -- ns PRE command period tRP 10 -- 11.25 -- 12.5 -- 13.75 -- ns ACT to ACT or REF command period tRC 45 -- 46.25 -- 47.5 -- 48.75 -- ns ACT to PRE command period tRAS 35 9* tREFI 35 9* tREFI 35 9* tREFI 35 9* tREFI ns tCK(AVG) 2.5 3.3 2.5 3.3 2.5 3.3 CL = 5 CL = 6 CL = 7 CL = 8 CL = 9 CL = 10 CWL = 5 CWL = 6, 7, 8 tCK(AVG) Reserved Reserved Reserved CWL = 5 tCK(AVG) 2.5 3.3 2.5 3.3 CWL = 6 tCK(AVG) 1.875 < 2.5 1.875 < 2.5 CWL = 7, 8 tCK(AVG) Reserved CWL = 5 tCK(AVG) Reserved CWL = 6 tCK(AVG) 1.875 < 2.5 CWL = 7 tCK(AVG) 1.5 <1.875 CWL = 8 tCK(AVG) CWL = 5 tCK(AVG) CWL = 6 tCK(AVG) 1.875 < 2.5 1.875 < 2.5 CWL = 7 tCK(AVG) 1.5 <1.875 1.5 <1.875 CWL = 8 tCK(AVG) 1.25 < 1.5 CWL = 5, 6 tCK(AVG) CWL = 7 tCK(AVG) 1.5 <1.875 1.5 <1.875 CWL = 8 tCK(AVG) 1.25 < 1.5 1.25 < 1.5 CWL = 5, 6 tCK(AVG) CWL = 7 tCK(AVG) 1.5 <1.875 1.5 <1.875 1.5 <1.875 CWL = 8 tCK(AVG) 1.25 < 1.5 1.25 < 1.5 1.25 < 1.5 Rev. 0.1 / Dec 2008 2.5 3.3 Note 11-11-11 Reserved ns 1,2,3,4,8 Reserved ns 4 ns 1,2,3,8 2.5 3.3 Reserved Reserved ns 1,2,3,4,8 Reserved Reserved Reserved ns 4 Reserved Reserved Reserved ns 4 Reserved ns 1,2,3,4,8 1.875 < 2.5 1.875 < 2.5 Reserved Reserved Reserved ns 1,2,3,4,8 Reserved Reserved Reserved Reserved ns 4 Reserved Reserved Reserved Reserved ns 4 ns 1,2,3,8 Reserved Reserved 1.875 < 2.5 1.875 < 2.5 Reserved Reserved ns 1,2,3,4,8 Reserved Reserved Reserved ns 1,2,3,4 Reserved Reserved Reserved ns 4 Reserved ns 1,2,3,4,8 Reserved Reserved ns 1,2,3,4 Reserved Reserved ns 4 ns 1,2,3,8 ns 1,2,3,4 Reserved 1.5 <1.875 1.5 <1.875 Reserved 51 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C CWL = 5, 6, 7 tCK(AVG) CL = 11 CWL = 8 tCK(AVG) Supported CL Settings Supported CWL Settings Reserved 1.25 < 1.5 (Optional) Reserved 1.25 < 1.5 (Optional) Reserved 1.25 < 1.5 (Optional) 5, 6, 7, 8, 9, 10 5, 6, 7, 8, 9, 10 5, 6, 7, 8, 9, 10 5, 6, 7, 8 5, 6, 7, 8 5, 6, 7, 8 Reserved 1.25 < 1.5 ns 4 ns 1,2,3 ns 5 6, 8, 10, 11 nCK 5, 6, 7, 8 nCK *Speed Bin Table Notes* Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V); Notes: 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next `Supported CL'. 3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CLSELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CLSELECTED. 4. `Reserved' settings are not allowed. User must program a different value. 5. `Optional' settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier's data sheet and SPD information if and how this setting is supported. 6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. Rev. 0.1 / Dec 2008 52 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 8. Dimm Outline Diagram 8.1 164Mx64 - HMT164U6AFP(R)6C Front 2.10 0.15 Max R0.70 Min 1.45 30.00 SPD 4 x 3.00 0.10 17.30 DETAIL-B DETAIL-A 2 x 2.50 0.10 9.50 2 x 2.30 0.10 47.00 5.175 71.00 128.95 133.35 Back Side Detail - A Detail - B 3.18 0.3 0.15 2.50 0.20 3.80 0.35 0.05 1.27 0.10 FULL R 2.50 0.80 0.05 1.00 0.3~1.0 1.50 0.10 5.00 Note) All dimensions are in millimeters unless otherwise stated. Rev. 0.1 / Dec 2008 53 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 8.2 128Mx64 - HMT112U6AFP(R)8C Front 2.10 0.15 Min 1.45 Max R0.70 30.00 SPD 4 x 3.00 0.10 17.30 DETAIL-B DETAIL-A 2 x 2.50 0.10 9.50 2 x 2.30 0.10 47.00 5.175 71.00 128.95 133.35 Back Side Detail - A Detail - B 3.18 0.3 0.15 2.50 0.20 3.80 0.35 0.05 1.27 0.10 FULL R 2.50 0.80 0.05 1.00 0.3~1.0 1.50 0.10 5.00 Note) All dimensions are in millimeters unless otherwise stated. Rev. 0.1 / Dec 2008 54 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 8.3 128Mx72 - HMT112U7AFP(R)8C Front 2.10 0.15 Min 1.45 SPD Max R0.70 30.00 4 x 3.00 0.10 17.30 DETAIL-B DETAIL-A 2 x 2.50 0.10 9.50 2 x 2.30 0.10 47.00 5.175 71.00 128.95 133.35 Back Side Detail - A Detail - B 3.18 0.3 0.15 2.50 0.20 3.80 0.35 0.05 1.27 0.10 FULL R 2.50 0.80 0.05 1.00 0.3~1.0 1.50 0.10 5.00 Note) All dimensions are in millimeters unless otherwise stated. Rev. 0.1 / Dec 2008 55 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 8.4 256Mx64 - HMT125U6AFP(R)8C Front 2.10 0.15 Min 1.45 Max R0.70 30.00 SPD 4 x 3.00 0.10 17.30 DETAIL-B DETAIL-A 2 x 2.50 0.10 9.50 2 x 2.30 0.10 47.00 5.175 71.00 128.95 133.35 Back Detail - A Detail - B 4.00 2.50 0.20 3.80 0.35 0.05 1.27 0.10 FULL R 2.50 0.80 0.05 0.3 0.15 Side 1.00 0.3~1.0 1.50 0.10 5.00 Note) All dimensions are in millimeters unless otherwise stated. Rev. 0.1 / Dec 2008 56 HMT164U6AFP(R)6C HMT112U6(7)AFP(R)8C HMT125U6(7)AFP(R)8C 8.5 256Mx72 - HMT125U7AFP(R)8C Front 2.10 0.15 Min 1.45 Max R0.70 SPD 30.00 4 x 3.00 0.10 17.30 DETAIL-B DETAIL-A 2 x 2.50 0.10 9.50 2 x 2.30 0.10 47.00 5.175 71.00 128.95 133.35 Back Detail - A Detail - B 4.00 2.50 0.20 3.80 0.35 0.05 1.27 0.10 FULL R 2.50 0.80 0.05 0.3 0.15 Side 1.00 0.3~1.0 1.50 0.10 5.00 Note) All dimensions are in millimeters unless otherwise stated. Rev. 0.1 / Dec 2008 57