1
DS04-27202-3E
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP
SWITCHING REGULATOR
CONTROLLER
MB3769A
The Fujitsu MB3769A is a pulse-width-modulation controller which is applied to
fix ed frequency pulse modulation technique. The MB3769A contains wide band
width Op-Amp and high speed comparator to construct very high speed switching
regulator system up to 700 kHz. Output is suitable for powe r MOS FET drive
owing to adoption of totem pole output.
The MB3769A provides stand-by mode at low voltage power supply when it is
applied in primary control system.
•High frequency oscillator (f = 1 to 700 kHz)
•On-chip wide band frequency operation amplifier (BW = 8 MHz typ.)
•On-chip high speed comparator (td = 120 ns typ.)
•Internal reference voltage generator provides a stable reference supply
(5 V ± 2%)
•Low power dissipation (1.5 mA typ. at standby mode, 8 mA typ . at operating
mode)
•Output current ± 100 mA (± 600 mA at peak)
•High speed switching operation (tr = 60 ns, tf = 30 ns, CL = 1000 pF typ.)
•Adjustable Dead-time
•On-chip soft start and quick shut down functions
•Internal circuitry prohibits double pulse at dynamic current limit operation
•Under voltage lock out function (OFF to ON: 10 V typ. ON to OFF: 8 V typ.)
•On-chip output shut down circuit with latch function at over voltage
•On-chip Zener diode (15 V)
PLASTIC DIP 16-PIN
(DIP-16P-M04)
PLASTIC FPT 16-PIN
(FPT-16P-M06)
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields.
However, it is advised that normal precautions be taken
to av oid application of any v oltage higher than maximum
rated voltages to this high impedance circuit.
2
MB3769A
■PIN ASSIGNMENT
■ABSOLUTE MAXIMUM RATINGS (See NOTE)
*:Duty ≤ 5%
** : TA = 25 °C
*** : TA = 25 °C, FPT package is mounted on the epoxy board.
(4 cm x 4 cm x 0.15 cm)
NOTE : Permanent device damage may occur if the abov e Absolute Maximum Ratings are e xceeded. Functional operation
should be restricted to the conditions as detailed in the operational sections data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Rating Symbol Value Unit
Power Supply Voltage VCC 20 V
Output Current IOUT 120 (660*) mA
Operation Amp. Input Voltage Vin (OP) VCC + 0.3 (≤ 20) V
Power Dissipation: DIP
: FPT PD1000** mW
PD620*** mW
Operating Temp. : DIP
: FPT TOP -30 to +85 °C
TOP -30 to +75 °C
Storage Temp. TSTG -55 to +125 °C
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+IN (OP)
-IN (OP)
FB
DTC
CT
RT
GND
VL
+IN (C)
-IN (C)
VREF
OVP
VCC
VZ
VH
OUT
3
MB3769A
■
■■
■BLOCK DIAGRAM
+
-
+
-
-
+
+
+
+
+
+
-
-
+
S
R
Q
S
R
Q
Triangle Wave
Oscillator
Ov er Voltage Detector
-
+
Reference
Regulator +
-
Power
off
2.5 V
1.5 V to 3.5 V
(2.5 V)
15.4 V
30 kΩ
5.0 + 0.1 V
8/10 V STB
Over Current Detection Comparator
PWM
Comparator
1.85 V
1.8 V
STB STB
VREF
VH
VL
VREF
OUT
Error
Amp.
DTC
FB
-IN (OP)
OVP
C T
R T
V CC
V Z
GND
Fig. 1 - MB3769A Block Diagram
16
4
3
1
2
13
5
6
12
11
7
14
8
9
10
15
-IN (C)
+IN (C)
+IN (OP)
4
MB3769A
■RECOMMENDED OPERATING CONDITION
Parameter SymboL DIP package FPT package Unit
Min Typ Max Min Typ Max
Power Supply Voltage VCC 12 15 18 12 15 18 V
Output Current (DC) IOUT -100 - 100 -100 - 100 mA
Output Current (Peak) IOUT PEAK -600 - 600 -600 - 600 mA
Operation Amp. Input voltage VINOP -0.2 0 to VREF VCC -3 -0.2 0 to
VREF VCC-3 V
FB Sink Current ISINK --0.3--0.3mA
FB Source Current ISOURCE --2--2mA
Comparator Input Voltage VINC+-0.3 0 to 3 VCC -0.3 0 to 3 VCC V
VINC--0.3 0 to 2 2.5 -0.3 0 to 2 2.5 V
Reference Section Output Current IREF - 5 10 - 2 10 mA
Timing Resistor RT9185091850kΩ
Timing Capacitor CT100 680 106100 680 106pF
Oscillator Frequency fOSC 1 100 700 1 100 700 kHz
Zener Current IZ--5--5mA
Operating Temp. TOP -30 25 85 -30 25 75 °C
5
MB3769A
■
■■
■ELECTRICAL CHARACTERISTICS
(VCC=15V, TA=25°C)
Parameter Symbol Condition Value Unit
Min Typ Max
Reference
Section
Output Voltage VREF IREF = 1 mA 4.9 5.0 5.1 V
Input Regulation ∆ VRIN 12 V ≤ VCC ≤ 18 V - 2 15 mV
Load Regulation ∆ VRLD 1 mA ≤ IREF ≤10 mA - -1 -15 mV
Temp. Stability ∆ VRTEMP -30 °C ≤ TA ≤ 85 °C - ±200 ±750 µV/ °C
Short Circuit Output Current ISC VREF = 0 V 15 40 - mA
Oscillator
Section
Oscillator Frequency fOSC RT =18 kΩ
CT=680 pF 90 100 110 kHz
Voltage Stability ∆ fOSCIN 12 V ≤ VCC ≤ 18 V - ±0.03 - %
Temp. Stability ∆ fOSC /∆ T-30 °C ≤ TA ≤ 85 °C-±2-%
Dead -time
Control
Section
Input Bias Current ID-210µA
Max. Duty Cycle Dmax Vd = 1.5 V 75 80 85 %
Duty Cycle Set Dset Vd = 0.5 VREF 45 50 55 %
Input
Threshold
Voltage
0% Duty
Cycle VDO --3.53.8V
Max. Duty
Cycle VDM - 1.55 1.85 - V
Discharge Voltage VDH VCC= 7 V,
IDTC= -0.3 mA 4.5 - - V
Error
Amplifier
Section
Input Offset Voltage VIO (OP) V3 = 2.5 V - ±2 ±10 mV
Input Offset Current IIO (OP) V3 = 2.5 V - ±30 ±300 nA
Input Bias Current IIR (OP) V3 = 2.5 V -1 -0.3 - µA
Common-Mode Input Voltage VCM (OP) 12 V ≤ VCC ≤ 18 V -0.2 - VCC -3 V
Voltage Gain AV (OP) 0.5 V ≤ V3 ≤ 4 V 70 90 - dB
Band Width BW AV = 0dB - 8 - MHz
Slew Rate SR RL = 10 kΩ, AV = 0dB - 6 - V/µs
Common-Mode Rejection Rate CMR VIN = 0 to 10 V 65 80 - dB
“H” Level Output Voltage VOH I3 = -2 mA 4.0 4.6 - V
“L” Level Output Voltage VOL I3 = 0.3 mA - 0.1 0.5 V
6
MB3769A
■
■■
■ELECTRICAL CHARACTERISTICS (Continued)
* : VCC = 8V
(VCC=15V, TA=25°C)
Parameter Symbol Condition Value Unit
Min Typ Max
Current
Comparator
Input Offset Voltage VIO (C) VIN = 1 V - ±5±15mV
Input Bias Current IIB (C) VIN = 1 V -5 -1 - µA
Common-Mode Input Volt-
age VCM (C) -0-2.5V
Voltage Gain AV (C) --200-V/V
Response Time td 50 mV over drive - 120 250 ns
PWM
Comparator
Section
0% Duty Cycle VOPO RT = 18 kΩ
CT = 680 pF -3.53.8V
Max. Duty Cycle VOPM 1.55 1.85 - V
Output
Section
“H” Level Output Voltage VHIOUT = -100 mA 12.5 13.5 - V
“L” Level Output Voltage VLIOUT = 100 mA - 1.1 1.3 V
Rise Time tr CL = 1000 pF, RL = ∞- 60 120 ns
Fall Time tf CL = 1000 pF, RL = ∞-3080ns
Over
Voltage
Detector
Threshold Voltage VOVP - 2.4 2.5 2.6 V
Input Current IIOVP VIN = 0 V - 1.0 -0.2 - µA
VCC Reset VCC RST - 2.0 3.0 4.5 V
Under Volt-
age
Out Stop
Off to On VTHH - 9.2 10.0 10.8 V
On to Off VTHL - 7.2 8.0 8.8 V
Supply
Current
Standby * ISTB RT = 18 kΩ
4 pin Open -1.52.0mA
Operating ICC RT = 18 kW - 8.0 12.0 mA
Zener Voltage VZIZ = 1 mA - 15.4 - V
Zener Current IZV11-7 = 1 V - 0.03 - mA
7
MB3769A
Fig. 2 - MB3769A Test Circuit
16 15 14 13 12 11 10 9
12345678
+IN (C) -IN (C) VREF OVP VCC VZVHOUT
+IN (OP) -IN (OP) FB DTC CTRTGND VL
VFB VDTC
MB3769A
COMP
in
1.0 V 15.0 V OUTPUT
10 kΩ
18 kΩ680 pF
TEST INPUT
1000 pF
90%
10%
50%
tf
td
tr
1.05 V
1.0 V
<tr, tf, td>
3.5 V typ.
1.5 V typ.
Voltage at CT
COMP in
OUTPUT
0.95 V
tr of COMP-in should
be within 20 ns.
8
MB3769A
Soft Start Operation Quick Shutdown Operation
3.5 V
1.5 V
1.85V
(15 V)
10 V (typ.)
2.5 V
(1 V)
3 V
8 V
(typ.)
Standby Mode Over Voltage Detector
Latch OFF
Standby
Mode
Over Current
Detector Over Voltage
Detector
0 V
Dead-Time
Input Voltage
Triangle Wave
Form
Error Amp.
Output
PWM Comparator
Output
Output Wave
Form
Comp. Current
-in Wave Form
Comp. Current
+in Wave Form
Comp. Current
Latch Output
Voltage at OVP
OVP Latch
Power Supply
Voltage
Fig. 3 - MB3769A Operating Timing
9
MB3769A
■
■■
■FUNCTIONS
1. Error Amplifier
The error amplifier detects the output voltage of the switching regulator.
The error amplifier uses a high-speed operational amplifier with an 8 MHz bandwidth (typical) and 6 V/ms slew rate (typical).
For ease of use, the common mode input voltage ranges from -0.2 V to VCC-3 V. Figure 4 shows the equivalent circuit.
2. Overcurrent Detection Comparator
There are two methods for protection of the output transistor of this device from overcurrents; one restricts the transistor’s on-
time if an overcurrent that flows through the output transistor is detected from an average output current, and the other detects
an overcurrent in the external transistor (FET) and shuts the output down instantaneously. Using average output currents, the
peak current of the e xternal transistor (FET) cannot be detected, so an output transistor with a large saf e oper ation area (SO A)
margin is required.
For the method of detecting overcurrents in the e xternal transistor (FET), the output transistor can be protected against a shorted
filter capacitor or power-on surge current.
The MB3769A uses dynamic current limiting to detect overcurrents in the output transistor (FET). A high-speed comparator
and flip-flop are built-in.
To detect overcurrents, compare the v oltage at +IN (C) of current detection resistor connected the source of the output transistor
(FET), with the reference voltage (connected to -IN(C) ) using a comparator. To prevent output oscillation dur ing overcurrent,
flip-flop circuit protects against double pulses occurring within a cycle.
The output of overcurrent detector is ORed with other signals at the PWM comparator. See the example Application Example
for details on use.
Figure 5 shows the equivalent circuit of the over-current detection comparator.
Fig. 4 - MB3769A Equivalent Circuit Differential Amp.
VCC
GND
-IN (OP)
+IN (OP)
150 Ω
700 µA
VREF
To PWM
Comp.
Protection element
10
MB3769A
3. DTC: Dead Time Control (Soft-Start and Quick Shutdown)
The dead time control terminal and the error amplifier output are connected to the PWM comparator.
The maximum duty cycle for VDTC (voltage applied to pin 4) is obtained from the following for mula (approximate value at low
frequency): Duty Cycle = (3.5 - VDTC) x 50 (%) [0% ≤ duty cycle ≤ DMAX (80%) ]
The dead time control terminal is used to provide soft start.
In Figure 6, the DTC terminal is connected to the VREF terminal through R and C. Because capacitor C does not charge
instantaneously when the power is tur ned on, the output transistor is kept tur ned off. The DTC input voltage and the output
pulse width increase gradually according to the RC time constant so that the control system operates safely.
The quick shutdo wn function pre vents soft start malfunction when the power is turned off and on quickly. After the power is shut
down, soft star t is disabled because the DTC ter minal has low electric potential from the beginning if the power is tur ned on
again bef ore the capacitor is discharged. The MB3769A prev ents this by turning on the discharge transistor to quickly discharge
the capacitor in the stand-by mode.
Fig. 5 - MB3769A Equivalent Circuit Over Current Detection Comparator
Protection element
+IN (C)
VREF
To PWM
Comp.
-IN (C)
Fig. 6 - MB3769A Soft Start Function
VREF
DTC
C
R
Soft Start
VREF
DTC
CR
1
Soft Start + DTC
R2
11
MB3769A
4. Triangular Wave Oscillator
The oscillation frequency is expressed by the following formula:
F or master/slav e synchronized oper ation of sev eral MB3769As , the CT and RT terminals of the master MB3769A are connected
in the usual way and the CT ter minals of the master and slave device (s) are connected together. The slave MB3769A’s RT
terminal is connected to it’s VREF terminal to disable the slave’s oscillator. In this case, set 50/n kΩ (n is the number of master
and slave ICs) to the upper limit of RT so that internal bias currents do not stop the master oscillation.
5. Overvoltage Detector
The overvoltage detection circuit shuts the system power down if the switching regulator’s output voltage is abnormal or if
abnorm al voltage is appeared. The reference vo ltage is 2.5 V (VREF /2). The system power is shut down if the voltage at pin
13 rises above 2.5 V. The output is kept shut down by the latching circuit until the power supply is turned off (see Figure 3).
6. Stand-by Mode and Under-Voltage Lockout (UVLO)
Generally, VGS > 6 to 8 V is required to use power MOSFET for switching. UVLO is set so that output is on at VCC ≥ 10 V
(standard) when the power is turned on and is off at VCC ≤ 8 V (standard) when the power is turned off.
In the stand-by mode , the power supply current is limited to 2 mA or less when the output is inhibited b y the UVLO circuit. When
the MB3769A is operated from the 100 VA C line , the power supply current is supplied through resistor R (Figure 8). That is , the
IC power supply current is supplied by the AC line through resistor R until operation star ts. Current is then supplied from the
transformer tertiary winding, eliminating the need for a second power supply.
Two volts (typical) of hysteresis are provided for return from operation mode to stand-by mode not to retur n to stand-by mode
until output power is turned on or to a void malfunction due to noise.
[kHz]
fOSC ~ :µF
0.8 x CT x R T + 0.0002 ms :kΩ
1CT
RT
Fig. 7 - MB3769A Synchronized Oper ation
master
RT CT
slave
VREF RTCT
12
MB3769A
7. Output Section
Because the output ter minal (pin 9) carr ies a large current, the collector and emitter of the output transistor are brought out to
the VH and VL terminals. In principle, VH is connected to VCC and VL is connected to GND, but VH can be supplied from another
power supply (4 to 18 V). Note that VL and GND should be connected as close to the IC package as possible. A capacitor of
0.1 µF or more is inserted between VH and VL (see Figure 9).
Fig. 8 - MB3769A Primary Control
MB3769A
C
R
Fig. 9 - MB3769A Typical Connection Circuit Of Output
10
9
≥ 0.1 µF
12
78
13
MB3769A
■
■■
■APPLICATION EXAMPLE
Overcurrent Protection Circuit
The waveform at the output FET source terminal is shown in Figure 11. The RC time constant must be chosen so that the
voltage glitch in the waveform does not cause erroneous overcurrent detection. This time constant is should be from 5 to 100
ns. A detection current value depends on R or C because a waveform is weakened. To keep this glitch as small as possible,
the rectifiers on the transformer secondary winding must be the fast-recovery type.
Fig. 10 - MB3769A DC - DC Convertor
MB3769A
+IN (C) 16
IN (C) 15
VREF 14
OVP 13
VCC 12
VZ11
VH10
OUT 9
0.1 µF
20 kΩ
10 kΩ
R
C
100 kΩ330 pF
3.3 kΩ
220 pF
51 kΩ18 kΩ10 kΩ5.1 kΩ1 Ω
S
5 V
1 A
3.6 kΩ
2.4 kΩ
12 to 18 V
1+IN (OP)
2-IN (OP)
3FB
4DTC
5CT
6RT
7GND
8VL
Fig. 11 - MB3769A Output FET Source Point
Glitch
Point S waveform
14
MB3769A
100 VAC
R
22
kΩ4.7 µF
22
kΩ680
pF 18
kΩ10 kΩ15
kΩ
22
Ω
*
47 kΩ
+IN(OP)
-IN(OP)
FB
DTC
CT
RT
GND
+IN(C)
-IN(C)
VREF
OVP
VCC
VZ
VH
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
*:The resistance (22 Ω)
as an output current
limiter at pin 9 is re-
quired when driving
the FET which is more
than 1000 pF (CGS).
-
+
Fig. 12 -Primary Control
-
+
43
kΩ
51
kΩ
680
pF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+IN(OP)
-IN(OP)
FB
DTC
CT
RT
GND
VL
+IN(C)
-IN(C)
VREF
OVP
VCC
VZ
VH
OUT
Secondly power supply
15 V
0 V
10
kΩ18
kΩ
5.1 kΩ
39
kΩ
27
kΩ
10
kΩ
12 V
1000
pF
Fig. 13 -Secondly Control
15
MB3769A
■
■■
■SHORT PROTECTION CIRCUIT
The system power can be shut down to protect the output against intermittent short-circuits or continuous overloads. This
protection circuit can be configured using the OVP input as shown in Figure 14.
MB3769A
9
14
13
7
1 µFPC1 100 kΩ10 kΩ
20 kΩPC2
8
5
34
16
V0
(5V output)
PC2
PC1
OUT-B
500 Ω
HYS-A
500 Ω
MB3761
15 kΩ
IN-B
8.2 kΩ
IN-A
6.8 kΩ
Fig. 14 -Case I. (Over Protection Input)
Primary Mode
MB3769A
14
13 OVP
VREF
MB3761
8
5
36
12
IN-A
IN-B
15 kΩ
8.2 kΩ
6.8 kΩ
OUT-B
HYS-A
200 kΩ
1 µF
20 kΩ
V0 (5V output)
Fig. 15 -Case II. (Over Protection Input)
Secondly Mode
16
MB3769A
■
■■
■HOW TO SYNCHRONIZE WITH OUTSIDE CLOCK
The MB3769A oscillator circuit is shown in Figure 16. CT charge and discharge currents are e xpressed by the f ollowing f ormula:
This circuit shows that if the v oltage at the CT terminal is set to 1.5 V or less, one oscillation cycle ends and the ne xt cycle starts.
An example of an external synchronous clock circuit is shown in Figure 17.
5 V
RT
ICT = ±2 x I1 = ±
VREF
2.5 V
RT
-
+
+
-
-
+
S
R
Q
3.5 V
1.5 V
2 x I12 x I1
1 kΩ500
Ω500 Ω
300
Ω150Ω
I1
ICT
CT
(4 x I1)
65
Fig. 16 -Oscillator Circuit
5
6
MB3769A
RTCT
R(5.1 k Ω)VP
ex. MB74HC04
clamp circuit
(VL)
VPtP
tcycle
tcycle = 2.5 µs (fEXT = 400 kHz)
tP= 0.5 µs
RT= 11 k Ω
Fig. 17 -Typical Connection of Synchronized Outside Clock Circuit
tP’
VL
VCT 1.85
3.5 V
VTH
( 2.5 V)
.
.
Fig. 18 -Voltage Waveform at CT
The Figure 18 shows the CT terminal waveform.
VTH may be near 2.5 V. In this case, the maximum duty cycle is restricted
as shown in the formula below if tP’ = 0.
Dmax= ≤ 59% (VL = 0 V: No clamp circuit)
(3.5 - 1.85) + (3.5 - VTH)
(3.5 - VL ) + (3.5 - VTH )
When VTH = 2.5 V, CT can be provided by followings.
tcycle - tP =x
(3.5 - VL) + (3.5 - VTH)
fOSC(3.5 - 1.5 ) x 2
fOSC
1
17
MB3769A
Make VL high for a large duty cycle for the clamp circuit. The circuits below can be used because the clamp voltage must be
much lower than 1.5 V.
In circuit A, R1 and R2 must be determined considering the effects of tP
, R, or RT.
The transistor saturation voltage must be ver y small (<0.15 V) for any clamp circuit, so a transistor with a very small VCE (sat)
should be used.
CT ~ x(t
cycle - tP ) [pF] (RT: kΩ, tcycle, tP: ns)
14
0.8 x RT4.5 - VL
fOSC ~ 1
0.8 x CT x RT
0.1 µFR2 (1.2 kΩ)
(1.2 V)
R1 (4.7 kΩ)
VREF
A
(1.2 V)
0.1 µF
820 Ω
VREF
8
5
3
4MB3761
B
Fig. 19 -Clamp Circuit
18
MB3769A
■
■■
■SYNCHRONIZED OUTSIDE CLOCK CIRCUIT
5 pin
CT
150 pF 5.1 kΩVP
MB74HC04
1.No Clamp Circuit (Connect with GND)
CT = 150 pF + Prove Capacitor (~ 15 pF)
RT = 11 kΩ
2.Clamp Circuit A (Dividing Resistor)
CT = 220 pF + Prove capacitor (~ 15 pF)
RT = 11 kΩ
5 pin
CT
220 pF 5.1 kΩ
MB74HC04
VP
4.7 kΩ
1.2 kΩ
0.1
µF
3.Clamp Circuit B (Apply MB3761)
CT = 220 pF + Prove capacitor (~ 15 pF)
RT = 11 kΩ
5 pin
CT
220 pF 5.1 kΩVP
MB74HC04
0.1 µF
VREF
820 Ω8
5
4
3
VREF
MB3761
VP (5 V/div)
CT (1 V/div)
OUT (10 V/div)
GND Level (CT)
VP (5 V/div)
CT (1 V/div)
GND Level (CT)
OUT (10 V/div)
VP (5 V/div)
CT (1 V/div)
GND Level (CT)
OUT (10 V/div)
Fig. 20
Fig. 21
Fig. 22
10 V
1 V
500 nS
5 V
10 V
1 V
500 nS
5 V
10 V
1 V
500 nS
5 V
19
MB3769A
1
2.4 kΩ
11 kΩ
MB3769A
2.5 V
OUT
2.4 kΩ
15 V (VCC)
2
3
4
5
6
14
15
16
9
7813
12 10
Fig. 23 -Test Circuit
20
MB3769A
■
■■
■TYPICAL PERFORMANCE CHARACTERISTICS
10.0
8.0
6.0
4.0
2.0
0.0
0.0 4.0 8.0 12.0 16.0 20.0
Fig. 24 -Power Supply Current vs.
Power Supply Voltage
(Low Voltage stop of VCC)2
1
0-30 02550 85
Fig. 25 -Standby Current vs.Temp.
OVP
operating
V13 = 5 V
Normal
operating
V13 = 0 V
VCC = 8 V
Powe r Supply Voltage VCC (V)
OVP
operating
Temp. TA (°C)
Fig. 26 -Reference Voltage vs. Temp. Fig. 27 -“L” level Output Voltage vs.
“L” level Output Current
VCC = 15 V
TA = 25 °C
3
2
1
00.20.40.60.8
“L” level Output Current IOL (mA)
VCC = 15 V
IREF = 1 mA
5.1
5.0
4.9
0-30 0 25 50 85
±750 µV/C
Temp. TA (°C)
5
4
3
2
1
024 68 10
VCC = 15 V
TA = 25 °C
“H” level Output Current IOH (mA)
Fig. 28 -“H” level Output Voltage vs.
“H” level Output Current
Power Supply Current ICC (mA)
Reference Voltage VREF (V)
“H” level Output Voltage VOH (V)
Standly Current ISTB (mA)
“L” level Output Voltage VOL (V)
21
MB3769A
■
■■
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
700
500
400
300
200
100
50
20 710 2030405070
Fig. 29 -Oscillator Frequency vs. RT, CTFig. 30 -“H”, “L” level Output Voltage vs.
Oscillator Frequency
CT = 100 pF
CT = 220 pFCT = 680 pF
CT = 1000 pF
CT = 2200 pF
4
3
2
1
020 k 50 k 100 k 200 k 500 k 1 M
VH
VL
VH
VL
Fig. 31 -Duty Cycle vs. Dead Time Control
Voltage
Fig. 32 -Oscillator Frequency vs. Temp.
Fig. 33 -Dead Time Control Voltage vs.
Current(Standby Mode)
-4
-2
0
2
4VCC = 15 V
100 kHz
300 kHz
500 kHz
Target
fOSC = 100 kHz
±2 % typ.
fOSC = 200 kHz
fOSC = 500 kHz
VCC = 15 V
CT = 1000 pF
TA = 25 °C
5.0
4.0
3.0
2.0
VCC = 7 V
TA = 25 °C
1.0
0-0.2 -0.4 -0.6 -0.8 -1.0 -1.2
100
80
60
40
20
0012345
RT (kΩ)
Frequency fOSC (Hz)
Temp. TA (°C)
-30 0 25 50 85
Dead Time Control Voltage VDTC (V) Dead Time Control Current IDTC (mA)
VCC = 15 V
TA = 25 °C
Oscillator Frequency fOSC (kHz)
Dead Time Control Voltage VDTC (V)
“H”, “L” level Output Voltage VH, VL (V)
Oscillator Frequency fOSC (%)
Duty Cycle (%)
40
30
60
80
90
70
60
89
22
MB3769A
■
■■
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Fig. 34 -Gain/Phase vs. Frequency
(Set Gv = 60 dB)
VCC = 15 V
TA = 25 °C
Gain
Phase
60
40
20
0
10 k 100 k 1 M 10 M
-180
-240
-300
-360
fOSC = 500 kHz
fOSC = 200 kHz
VCC = 15 V
CL = 1000 pF
VDTC = 2.5 V
Fig. 35 -Duty cycle vs. Temp.
55
50
45
0-30 0 25 50 85
Fig. 36 -“L” level Output Voltage vs.
“L” level Output Current
VCC = 15 V
TA = 25 °CFig. 38 -tr/tf of Output and td of
Comparator vs. Temp.
160
140
120
100
80
60
40
20
0-30 0 -25 50 85
VCC = 15 V
CL = 1000 pF
td
tr
tf
Fig. 37 -“H” level Output Voltage vs.
“H” level Output Current
1.5
1.0
0.5
00100 200 300 400 500 600
14.0
13.5
13.0
12.5
00100 200 300 400 500 600
Frequency f (Hz)
Temp. TA (°C)
“L” level Output Current IOL (mA)
“H” level Output Current IOH (mA)
VCC = 15 V
TA = 25 °C
Temp. TA (°C)
Gain (dB)
“L” level Output Voltage VOL (V)
“H” level Output Voltage VOH (V)
Phase (deg)
Duty Cycle (%)
tr/tf/td (ns)
23
MB3769A
■
■■
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
6
5
4
3
2
-40 -20 0 20 40 60 80 100
Fig. 39 -OVP Latch Standby Power
Supply Current vs. Temp.
VCC = 8 V
4 pin open
13 pin = 3 V
Temp. TA (°C)
Fig. 40 -OVP Supply Voltage
Reset vs. Temp.
-40 -20 0 20 40 60 80 100
Temp. TA (°C)
5
4
3
2
1
0
Standby Power Supply Current (mA)
OVP Supply Voltage Reset (V)
0
24
MB3769A
.010±.002
Dimensions in
inches (millimeters)
16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-16P-M04)
1990 FUJITSU LIMITED D160335-2C-2
.770+.008
-.012 (19.55 )
+0.20
-0.30
.039+.012
-0
(0.99 )
+0.30
-0
.244±.010
(6.20±0.25)
INDEX-1
.100(2.54)
TYP
.050(1.27)
MAX
.020(0.51)MIN
.172(4.36)MAX
.118(3.00)MIN
.300(7.62)
TYP
15°MAX
.060+.012
-0
(1.52 )
+0.30
-0
INDEX-2
(0.25±0.05)
.018±.003
(0.46±0.08)
25
MB3769A
Dimensions in
inches (millimeters)
“A”
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P-M06)
1991 FUJITSU LIMITED F16015S-2C
.400+.010
-.008(10.15 )
+0.25
-0.20
.209±.012
(5.30±0.30)
INDEX
.004(0.10)
.050(1.27)
TYP .018±.004
(0.45±0.10) ∅.005(0.13)
.307±.016
(7.80±0.40)
.002(0.05)MIN
(STAND OFF HEIGHT)
.089(2.25)MAX
(MOUNTING HEIGHT)
.006 +.002
-.001 (0.15 )
+0.05
-0.02
.020±.008
(0.50±0.20)
.027(0.68)
MAX
.007(0.18)
MAX
.008(0.20)
.016(0.40)
Details of “A” part
M
.350(8.89) REF
“B”
.268+.016
-.008(6.80 )
+0.40
-0.20
.027(0.68)
MAX
.007(0.18)
MAX
.006(0.15)
Details of “B” part
.008(0.20)
MB3769A
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F9601
FUJITSU LIMITED Printed in Japan
