DC to 600 MHz,
Dual-Digital Variable Gain Amplifiers
Data Sheet AD8366
Rev. B Document Feedback
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FEATURES
Matched pair of differential, digitally controlled VGAs
Gain range: 4.5 dB to 20.25 dB
0.25 dB gain step size
Operating frequency
DC to 150 MHz (2 V p-p)
3 dB bandwidth: 600 MHz
Noise figure (NF)
11.4 dB at 10 MHz at maximum gain
18 dB at 10 MHz at minimum gain
OIP3: 45 dBm at 10 MHz
HD2/HD3
Better than −90 dBc for 2 V p-p output at 10 MHz at
maximum gain
Differential input and output
Adjustable output common-mode
Optional dc output offset correction
Serial/parallel mode gain control
Power-down feature
Single 5 V supply operation
APPLICATIONS
Baseband I/Q receivers
Diversity receivers
Wideband ADC drivers
FUNCTIONAL BLOCK DIAGRAM
VPSIA
IPPA
IPMA
ENBL
ICOM
IPMB
IPPB
VPSIB
BIT0/CS
BIT1/SDAT
BIT2/SCL
K
BIT3
OCOM
BIT4
BIT 5
DENA
DECA
OFSA
CCMA
VCMA
VPSOA
OPPA
OPMA
SENB
DECB
OFSB
CCMB
VCMB
VPSOB
OPPB
OPMB
DENB
DIGITAL GAIN
CONTROL LOGIC
07584-001
Figure 1.
GENERAL DESCRIPTION
The AD8366 is a matched pair of fully differential, low noise and
low distortion, digitally programmable variable gain amplifiers
(VGAs). The gain of each amplifier can be programmed separately
or simultaneously over a range of 4.5 dB to 20.25 dB in steps of
0.25 dB. The amplifier offers flat frequency performance from dc
to 70 MHz, independent of gain code.
The AD8366 offers excellent spurious-free dynamic range, suitable
for driving high resolution analog-to-digital converters (ADCs).
The NF at maximum gain is 11.4 dB at 10 MHz and increases
~2 dB for every 4 dB decrease in gain. Over the entire gain range,
the HD3/HD2 are better than −90 dBc for 2 V p-p at the output at
10 MHz into 200 Ω. The two-tone intermodulation distortion of
−90 dBc into 200 Ω translates to an OIP3 of 45 dBm (38 dBVrms).
The differential input impedance of 200  provides a well-defined
termination. The differential output has a low impedance of ~25 .
The output common-mode voltage defaults to VPOS/2 but can
be programmed via the VCMA and VCMB pins over a range
of voltages. The input common-mode voltage also defaults
to VPOS/2 but can be driven down to 1.5 V. A built-in, dc offset
compensation loop can be used to eliminate dc offsets from prior
stages in the signal chain. This loop can also be disabled if dc-
coupled operation is desired.
The digital interface allows for parallel or serial mode gain
programming. The AD8366 operates from a 4.75 V to 5.25 V
supply and consumes typically 180 mA. When disabled, the
part consumes roughly 3 mA. The AD8366 is fabricated using
Analog Devices, Inc., advanced silicon-germanium bipolar
process, and it is available in a 32-lead exposed paddle LFCSP
package. Performance is specified over the −40°C to +85°C
temperature range.
AD8366 Data Sheet
Rev. B | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Parallel and Serial Interface timing ............................................ 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Circuit Description ......................................................................... 15
Inputs ........................................................................................... 15
Outputs ........................................................................................ 15
Output Differential Offset Correction .................................... 15
Output Common-Mode Control ............................................. 15
Gain Control Interface ............................................................... 16
Applications Information .............................................................. 17
Basic Connections ...................................................................... 17
Direct Conversion Receiver Design ......................................... 18
Quadrature Errors and Image Rejection ................................. 18
Low Frequency IMD3 Performance ........................................ 19
Baseband Interface ..................................................................... 21
Characterization Setups ................................................................. 22
Evaluation Board ............................................................................ 25
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
8/2017—Rev. A to Rev. B
Change to Figure 4 ........................................................................... 7
Updated Outline Dimensions ....................................................... 28
Changes to Ordering Guide .......................................................... 28
3/2011—Rev. 0 to Rev. A
Changes to Table 2, Internal Power Dissipation Value ................ 6
10/2010—Revision 0: Initial Version
Data Sheet AD8366
Rev. B | Page 3 of 28
SPECIFICATIONS
VS = 5 V, TA = 25°C, ZS = 200 Ω, ZL = 200 Ω, f = 10 MHz, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Bandwidth 3 dB; all gain codes 600 MHz
1 dB; all gain codes 200 MHz
Slew Rate Maximum gain 1100 V/µs
Minimum gain 1500 V/µs
INPUT STAGE IPPA, IPMA, IPPB, IPMB
Linear Input Swing At minimum gain AV = 4.5 dB, 1 dB gain compression 3.6 V p-p
Differential Input Impedance 217 Ω
Minimum Input Common-Mode Voltage 1.5 V
Maximum Input Common-Mode Voltage VPOS/2 + 0.075 V
Input pins left floating VPOS/2 V
GAIN
Minimum Voltage Gain 4.5 dB
Maximum Voltage Gain 20.25 dB
Gain Step Size
All gain codes
0.25
dB
Gain Step Accuracy All gain codes ±0.25 dB
Gain Flatness Maximum gain, DC to 70 MHz 0.1 dB
Gain Mismatch Channel A/Channel B at minimum/maximum gain code 0.1 dB
Group Delay Flatness All gain codes, 20% fractional bandwidth, fC < 100 MHz <0.5 ns
Mismatch Channel A and Channel B at same gain code 2 ps
Gain Step Response Maximum gain to minimum gain 30 ns
Minimum gain to maximum gain 60 ns
Common-Mode Rejection Ratio −66.2 dB
OUTPUT STAGE
OPPA, OPMA, OPPB, OPMB, VCMA, VCMB
Linear Output Swing 1 dB gain compression 6 V p-p
Differential Output Impedance 28 Ω
Output DC Offset Inputs shorted, offset loop disabled at
minimum/maximum gain
−10/−30 mV
Inputs shorted, offset loop enabled (across all gain codes)
10
mV
Minimum Output Common-Mode Voltage HD3, HD2 > −90 dBc, 2 V p-p output 1.6 V
Maximum Output Common-Mode Voltage HD3, HD2 > −90 dBc, 2 V p-p output 3 V
VCMA and VCMB left floating VPOS/2 V
Common-Mode Setpoint Input Impedance 4 kΩ
NOISE/DISTORTION
3 MHz
Noise Figure Maximum gain 11.3 dB
Minimum gain 18.2 dB
Second Harmonic
2 V p-p output, maximum gain
−82
dBc
2 V p-p output, minimum gain −82 dBc
Third Harmonic 2 V p-p output, maximum gain −87 dBc
2 V p-p output, minimum gain −90 dBc
OIP31 2 V p-p composite, maximum gain 34 dBVrms
2 V p-p composite, minimum gain 35 dBVrms
OIP21 2 V p-p composite, maximum gain 76 dBVrms
2 V p-p composite, minimum gain 76 dBVrms
Output 1 dB Compression Point1 Maximum gain 6.7 dBVrms
Minimum gain 6.9 dBVrms
AD8366 Data Sheet
Rev. B | Page 4 of 28
Parameter Test Conditions/Comments Min Typ Max Unit
10 MHz
Noise Figure Maximum gain 11.4 dB
Minimum gain 18 dB
Second Harmonic 2 V p-p output, maximum gain −97 dBc
2 V p-p output, minimum gain −96 dBc
Third Harmonic 2 V p-p output, maximum gain −97 dBc
2 V p-p output, minimum gain −90 dBc
OIP31
2 V p-p composite, maximum gain
38
dBVrms
2 V p-p composite, minimum gain 36 dBVrms
OIP21 2 V p-p composite, maximum gain 72 dBVrms
2 V p-p composite, minimum gain 76 dBVrms
Output 1 dB Compression Point1 Maximum gain 7 dBVrms
Minimum gain
6.7
dBVrms
50 MHz
Noise Figure Maximum gain 11.8 dB
Minimum gain 18.2 dB
Second Harmonic 2 V p-p output, maximum gain −82 dBc
2 V p-p output, minimum gain
−84
dBc
Third Harmonic 2 V p-p output, maximum gain −80 dBc
2 V p-p output, minimum gain −71 dBc
OIP31
2 V p-p composite, maximum gain
32
dBVrms
2 V p-p composite, minimum gain 26 dBVrms
OIP21 2 V p-p composite, maximum gain 71 dBVrms
2 V p-p composite, minimum gain 78 dBVrms
Output 1 dB Compression Point1 Maximum gain 6.7 dBVrms
Minimum gain
6.7
dBVrms
DIGITAL LOGIC SENB, DENA, DENB, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5
Input High Voltage, VINH 2.2 V
Input Low Voltage, VINL 1.2 V
Input Capacitance, C
IN
1
pF
Input Resistance, RIN 50 kΩ
SPI INTERFACE TIMING SENB = high
fSCLK Serial clock frequency (maximum) 44.4 MHz
t1 CS rising edge to first SCLK rising edge (minimum) 7.5 ns
t2 SCLK high pulse width (minimum) 7.5 ns
t3 SCLK low pulse width (minimum) 15 ns
t4 SCLK falling edge to CS low (minimum) 7.5 ns
t5 SDAT setup time (minimum) 7.5 ns
t6 SDAT hold time (minimum) 15 ns
PARALLEL PORT TIMING SENB = low
t7 DENA/DENB high pulse width (minimum) 7.5 ns
t8 DENA/DENB low pulse width (minimum) 15 ns
t9 BITx setup time (minimum) 7.5 ns
t10 BITx hold time (minimum) 7.5 ns
POWER AND ENABLE VPSIA, VPSIB, VPSOA, VPSOB, ICOM, OCOM, ENBL
Supply Voltage Range 4.75 5.25 V
Total Supply Current ENBL = 5 V 180 mA
Disable Current ENBL = 0 V 3.2 mA
Disable Threshold 1.65 V
Enable Response Time Delay following high-to-low transition until device
meets full specifications
150 ns
Disable Response Time
Delay following low-to-high transition until device
produces full attenuation
3
µs
1 To convert to dBm for a 200 Ω load impedance, add 7 dB to the dBVrms value.
Data Sheet AD8366
Rev. B | Page 5 of 28
PARALLEL AND SERIAL INTERFACE TIMING
SCLK
CS
SENB
B-LSB B-MSB A-LSBXX
ALWAYS HIGH
SDAT
t
5
t
6
t
1
t
2
t
3
t
4
A-MSB
07584-003
Figure 2. SPI Port Timing Diagram
t
9
t
7
t
8
t
10
GAIN A, GAIN B
ALWAYS LOW
DENA
DENB
BIT[5:0]
SENB
GAIN A GAIN B
07584-004
Figure 3. Parallel Port Timing Diagram
AD8366 Data Sheet
Rev. B | Page 6 of 28
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltages, VPSIx and VPSOx 5.5 V
ENBL, SENB, DENA, DENB, BIT0, BIT1, BIT2,
BIT3, BIT4, BIT5
5.5 V
IPPA, IPMA, IPPB, IPMB 5.5 V
OPPA, OPMA, OPPB, OPMB 5.5 V
OFSA, OFSB 5.5 V
DECA, DECB, VCMA, VCMB, CCMA, CCMB
Internal Power Dissipation
θJA (With Pad Soldered to Board) 45.4°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Data Sheet AD8366
Rev. B | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED
TO GRO UND.
VPSIA
IPPA
IPMA
ENBL
ICOM
IPMB
IPPB
VPSIB
BIT0/CS
BIT1/SDAT
BIT2/SCLK
BIT3
OCOM
BIT4
BIT5
DENA
DECA
OFSA
CCMA
VCMA
VPSOA
OPPA
OPMA
SENB
DECB
OFSB
CCMB
VCMB
VPSOB
OPPB
OPMB
DENB
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
AD8366
TOP VIEW
(No t t o Scal e)
07584-028
Figure 4. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1, 8, 13, 28
VPSIA, VPSIB, VPSOB,
VPSOA
Input and Output Stage Positive Supply Voltage (4.75 V to 5.25 V).
2, 3, 6, 7 IPPA, IPMA, IPMB,
IPPB
Differential Inputs.
4 ENBL Chip Enable. Pull this pin high to enable.
5, 20 ICOM, OCOM Input and Output Ground Pins. Connect these pins via the lowest possible impedance to
ground.
9, 32 DECB, DECA VPOS/2 Reference Decoupling Node. Connect a decoupling capacitor from these nodes to
ground.
10, 31 OFSB, OFSA Output Offset Correction Loop Compensation. Connect a capacitor from these nodes to
ground to enable the correction loop. Tie this pin to ground to disable.
11, 30
CCMB, CCMA
Connect These Nodes to Ground.
12, 29 VCMB, VCMA Output Common-Mode Setpoint. These pins default to VPOS/2 if left open. Drive these pins
from a low impedance source to change the output common-mode voltage.
14, 15, 26, 27 OPPB, OPMB, OPMA,
OPPA
Differential Outputs.
16, 17 DENB, DENA Data Enable. Pull these pins high to address each or both channels for parallel gain
programming. These pins are not used in serial mode.
18, 19, 21, 22, 23, 24 BIT5, BIT4, BIT3,
BIT2/SCLK, BIT1/SDAT,
BIT0/CS
Parallel Data Path (When SENB Is Low). When SENB is high, BIT0 becomes a chip select (CS),
BIT1 becomes a serial data input (SDAT ), and BIT2 becomes a serial clock (SCLK). BIT3 to BIT5
are not used in serial mode.
25 SENB Serial Interface Enable. Pull this pin high for serial gain programming mode and pull this pin low
for parallel gain programming mode.
EPAD The exposed pad must be connected to ground.
AD8366 Data Sheet
Rev. B | Page 8 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, ZS = 200 Ω, ZL = 200 Ω, f = 10 MHz, unless otherwise noted.
4
6
8
10
12
14
16
18
20
22
0 5 10 15 20 25 30 35 40 45 50 55 60
GAI N ( dB)
07584-005
GAI N CODE
TA = +85°C
TA = +25°C
TA = –40° C
Figure 5. Gain vs. Gain Code at 500 kHz, 3 MHz, 10 MHz, and 50 MHz
07584-007
–10
5
0
5
10
15
20
25
100k 1M 10M 100M 1G
GAI N CHANNELA, GAI N CHANNEL B (d B)
FREQUENCY (Hz)
GAI N CODE 32
GAI N CODE 16
GAI N CODE 00
GAI N CODE 48
GAI N CODE 63
Figure 6. Frequency Response vs. Gain Code
07584-008
–1.0
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
010 20 30 40 50 60
AMPLITUDE MISMAT CH ( dB)
GAI N CODE
Figure 7. Channel A-to-Channel B Amplitude Mismatch vs. Gain Code,
2 V p-p Output
07584-006
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0 5 10 15 20 25 30 35 40 45 50 55 60
GAI N E RROR (dB)
GAI N CODE
FREQUENCY = 3M Hz
FREQUENCY = 50M Hz
T
A
= +85°C
T
A
= +25°C
T
A
= –40° C
Figure 8. Gain Error vs. Gain Code, Error Normalized to 10 MHz
07584-017
19.0
19.2
19.4
19.6
19.8
20.0
20.2
20.4
20.6
20.8
21.0
–40 –30 –20 –10 010 20 30 40 50 60 70 80
GAI N ( dB)
TEMPERATURE (°C)
Figure 9. Gain vs. Temperature at Maximum Gain at 10 MHz
07584-009
–1.0
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
010 20 30 40 50 60
PHASE MISMAT CH ( Degrees)
GAI N CODE
Figure 10. Channel A-to-Channel B Phase Mismatch vs. Gain Code,
2 V p-p Output
Data Sheet AD8366
Rev. B | Page 9 of 28
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
0510 15 20 25 30 35 40 45 50 55 60
OP1dB (dBVrms)
OP1dB (dBm)
GAI N CODE
T
A
= +85°C
T
A
= +25°C
T
A
= –40° C
07584-030
Figure 11. OP1dB vs. Gain Code at 500 kHz, 3 MHz, 10 MHz, and 50 MHz
10
15
20
25
30
35
40
45
50
55
60
0
5
10
15
20
25
30
35
40
45
50
0 5 10 15 20 25 30 35 40 45 50 55 60
OIP3 (dBVrms)
OI P 3 ( dBm)
GAI N CODE
T
A
= +85°C
T
A
= +25°C
T
A
= –40° C FREQUENCY = 10M Hz
FREQUENCY = 50M Hz
07584-039
Figure 12. OIP3 vs. Gain Code at 10 MHz and 50 MHz Frequency, 2 V p-p
Composite Output
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0 5 10 15 20 25 30 35 40 45 50 55 60
IM D3 ( dBc)
GAI N CODE
T
A
= +85°C
T
A
= +25°C
T
A
= –40° C
FREQUENCY = 10M Hz
FREQUENCY = 50M Hz
07584-042
Figure 13. Two-Tone Output IMD3 vs. Gain Code at 10 MHz and 50 MHz
Frequency, 2 V p-p Composite Output
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
010 20 30 40 50 60 70 80 90 100 110 120 130 140 150
OP1dB (dBVrms)
OP1dB (dBm)
FREQUENCY (MHz)
GAI N CODE 0
GAI N CODE 63
T
A
= +85°C
T
A
= +25°C
T
A
= –40° C
07584-029
Figure 14. OP1dB vs. Frequency at Gain Code 0 and Gain Code 63
0
5
10
15
20
25
30
35
40
45
50
010 20 30 40 50 60 70 80 90 100 110 120 130 140 150
OI P 3 ( dBm)
FREQUENCY (MHz)
GAI N CODE 32
GAI N CODE 0
T
A
= +85°C
T
A
= +25°C
T
A
= –40° C CHANNEL A
CHANNEL B
07584-041
GAI N CODE 63
Figure 15. OIP3 vs. Frequency, Gain Code 0, Gain Code 32, and Gain Code 63,
2 V p-p Composite Output
–110
–90
–70
–50
–30
–10
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
IM D3 ( dBc)
FREQUENCY (MHz)
GAI N CODE 0
TA = +85°C
TA = +25°C
TA = –40° C
CHANNEL A
CHANNEL B
GAI N CODE 63
GAI N CODE 32
07584-040
Figure 16. Two-Tone Output IMD3 vs. Frequency at Gain Code 0,
Gain Code 32, and Gain Code 63, 2 V p-p Composite Output
AD8366 Data Sheet
Rev. B | Page 10 of 28
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
100
0510 15 20 25 30 35 40 45 50 55 60
OIP2 (dBVrms)
OI P 2 ( dBm)
GAI N CODE
TA = +85°C
TA = +25°C
TA = –40° C FREQUENCY = 10M Hz
FREQUENCY = 50M Hz
07584-044
Figure 17. OIP2 vs. Gain Code at 10 MHz and 50 MHz Frequency,
2 V p-p Composite Output
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0510 15 20 25 30 35 40 45 50 55 60
IM D2 ( dBc)
GAI N CODE
TA = +85°C
TA = +25°C
TA = –40° C
FREQUENCY = 10M Hz
FREQUENCY = 50M Hz
07584-045
Figure 18. Two-Tone Output IMD2 vs. Gain Code at 10 MHz and 50 MHz
Frequency, 2 V p-p Composite Output
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
110 100 1000
HD2, HD3 ( dBc)
FREQUENCY (MHz)
HD2
HD3
GAI N CODE 0
GAI N CODE 32
GAI N CODE 63
07584-032
Figure 19. Harmonic Distortion vs. Frequency at Gain Code 0, Gain Code 32,
and Gain Code 63, 2 V p-p Output
0
10
20
30
40
50
60
70
80
90
100
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
OI P 2 ( dBm)
FREQUENCY (MHz)
TA = +85°C
TA = +25°C
TA = –40° C CHANNEL A
CHANNEL B
07584-043
GAI N CODE 0
GAI N CODE 63
Figure 20. OIP2 vs. Frequency at Gain Code 0 and Gain Code 63, 2 V p-p
Composite Output
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
010 20 30 40 50 60 70 80 90 100 110 120 130 140 150
IM D2 ( dBc)
FREQUENCY (MHz)
TA = +85°C
TA = +25°C
TA = –40° C
CHANNEL A
CHANNEL B
GAI N CODE 63
GAI N CODE 0
07584-052
Figure 21. Two-Tone Output IMD2 vs. Frequency,
Gain Code 0 and Gain Code 63, 2 V p-p Composite Output
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
HD3, GAI N CODE 0 (d Bc)
HD2, GAI N CODE 0 (d Bc)
VCMA, VCMB (V)
T
A
= +85°C
T
A
= +25°C
T
A
= –40° C
CHANNEL A
CHANNEL B
07584-023
Figure 22. HD3/HD2 vs. VOCM at 10 MHz, Gain Code 0, 2 V p-p Output
Data Sheet AD8366
Rev. B | Page 11 of 28
0
10
20
30
40
50
60
–3 –2 –1 0 1 2345
OI P 3 ( dBm)
P
OUT
PER TO NE (dBm)
07584-055
GAI N CODE 0
GAI N CODE 63
T
A
= +85°C
T
A
= +25°C
T
A
= –40° C
Figure 23. OIP3 vs. Output Power (POUT) at Minimum and Maximum Gain
Codes, 10 MHz Frequency
0
10
20
30
40
50
60
70
80
90
100
–8 –7 –6 –5 –4 –3 –2 –1 012345
OI P 2 ( dBm)
POUT PER TO NE ( dBm)
GAI N CODE 0
GAI N CODE 63
TA = +85°C
TA = +25°C
TA = –40° C
07584-060
Figure 24. OIP2 vs. Output Power (POUT) at Minimum and Maximum Gain
Codes, 10 MHz Frequency
–110
–105
–100
–95
–90
–85
–80
–75
–70
–65
–60
–5 –4 –3 –2 –1 01 2 3 4 5 6 7 8
HD2 (d Bc)
P
OUT
(d Bm)
T
A
= +85°C
T
A
= +25°C
T
A
= –40° C
07584-053
GAI N CODE 0
GAI N CODE 63
Figure 25. HD2 vs. Output Power (POUT) at Gain Code 0 and Gain Code 63,
10 MHz Frequency
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
–3 –2 –1 01234 5
IM D3 ( dBc)
P
OUT
PER TONE ( dBm)
GAI N CODE 0
GAI N CODE 63
T
A
= +85°C
T
A
= +25°C
T
A
= –40° C
07584-061
Figure 26. IMD3 vs. Output Power (POUT) at Minimum-to-Maximum Gain
Codes, 10 MHz Frequency
POUT PER TO NE ( dBm)
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
–8 –7 –6 –5 –4 –3 –2 –1 0123 4 5
IM D2 ( dBc)
GAI N CODE 0
GAI N CODE 63
TA = +85°C
TA = +25°C
TA = –40° C
07584-062
Figure 27. IMD2 vs. Output Power (POUT) at Minimum and Maximum Gain
Codes, 10 MHz Frequency
–120
–115
–110
–105
–100
–95
–90
–85
–80
–75
–70
–65
–60
–5 –4 –3 –2 –1 012345
HD3 (d Bc)
P
OUT
(d Bm)
T
A
= +85°C
T
A
= +25°C
T
A
= –40° C
07584-054
GAI N CODE 0
GAI N CODE 63
Figure 28. HD3 vs. Output Power (POUT) for Gain Code 0 and Gain Code 63,
10 MHz Frequency
AD8366 Data Sheet
Rev. B | Page 12 of 28
100
120
140
160
180
200
220
240
260
280
300
0510 15 20 25 30 35 40 45 50 55 60
SUPPLY CURRENT ( mA)
GAI N CODE
07584-038
TA = +85°C
TA = +25°C
TA = –40° C
Figure 29. Supply Current vs. Gain Code at 10 MHz
07584-011
10
12
14
16
18
20
22
24
26
28
30
0 5 10 15 20 25 30 35 40 45 50 55 60
NOISE FIGURE (dB)
GAI N CODE
CHANNEL B, F RE QUENCY = 0.5MHz
CHANNEL A, F RE QUENCY = 0.5MHz
CHANNEL B, F RE QUENCY = 3M Hz
CHANNEL A, F RE QUENCY = 3M Hz
CHANNEL B, F RE QUENCY = 10M Hz
CHANNEL A, F RE QUENCY = 10M Hz
CHANNEL B, F RE QUENCY = 50M Hz
CHANNEL A, F RE QUENCY = 50M Hz
Figure 30. Noise Figure vs. Gain Code at 0.5 MHz, 3 MHz, 10 MHz, and 50 MHz
07584-013
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
180
190
200
210
220
230
240
250
260
270
280
020 40 60 80 100 120 140 160 180 200
INPUT CAPACITANCE ( pF)
INPUT RES ISTANCE (Ω)
FREQUENCY (MHz)
CHANNEL A: RIN, GAIN CODE 0
CHANNEL A: RIN, GAIN CODE 32
CHANNEL A: RIN, GAIN CODE 63
CHANNEL A: RIN, GAIN CODE 0
CHANNEL B: RIN, GAIN CODE 32
CHANNEL B: RIN
, G AIN CO DE 63
CHANNEL A: C
IN
, G AIN CO DE 0
CHANNEL A: C
IN
, G AIN CO DE 63
CHANNEL B: C
IN
, G AIN CO DE 32
CHANNEL A: C
IN
, G AIN CO DE 32
CHANNEL B: C
IN
, G AIN CO DE 0
CHANNEL B: C
IN
, G AIN CO DE 63
Figure 31. Differential Parallel Input Resistance and Capacitance vs.
Frequency
07584-010
10
15
20
25
30
35
40
45
50
55
60
0.1 110 100 1000
NOISE SPECTRAL DENSITY (nV/√Hz)
FREQUENCY (kHz)
CHANNEL A
CHANNEL B
GAI N CODE 63
GAI N CODE 47
GAI N CODE 48
GAI N CODE 31
GAI N CODE 32
GAI N CODE 15
GAI N CODE 16
GAI N CODE 0
Figure 32. Noise Spectral Density vs. Frequency
07584-012
10
12
14
16
18
20
22
24
26
28
30
NOISE FIGURE (dB)
CHANNEL A
CHANNEL B
0.1 110 100 1000
FREQUENCY (kHz)
GAI N CODE 0
GAI N CODE 15
GAI N CODE 16
GAI N CODE 31
GAI N CODE 32
GAI N CODE 47
GAI N CODE 48
GAI N CODE 63
Figure 33. Noise Figure vs. Frequency
07584-014
4.5
4.8
5.1
5.4
5.7
6.0
6.3
6.6
6.9
7.2
7.5
10
13
16
19
22
25
28
31
34
37
40
020 40 60 80 100 120 140 160 180 200
OUT P UT I NDUCTNACE ( nH)
OUTPUT RESISTANCE (Ω)
FREQUENCY (MHz)
CHANNEL A: ROUT, GAI N CODE 0
CHANNEL A: ROUT, GAI N CODE 32
CHANNEL A: ROUT, GAI N CODE 63
CHANNEL B: ROUT, GAI N CODE 32
CHANNEL A: LOUT, GAI N CODE 0
CHANNEL A: LOUT, GAI N CODE 63
CHANNEL B: LOUT, GAI N CODE 32
CHANNEL A: LOUT, GAI N CODE 32
CHANNEL B: LOUT, GAI N CODE 0
CHANNEL B: LOUT, GAI N CODE 63
CHANNEL A: ROUT, GAI N CODE 0
CHANNEL B: ROUT, GAI N CODE 63
Figure 34. Differential Series Output Resistance and Inductance vs.
Frequency
Data Sheet AD8366
Rev. B | Page 13 of 28
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
PSRR (dB)
FREQUENCY (MHz)
PSRR GAIN CODE 0
PSRR GAIN CODE 63
07584-036
Figure 35. Power Supply Rejection Ratio (PSRR) vs. Frequency
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
GROUP DELAY (n s)
FREQUENCY (MHz)
GAI N CODE 32
GAI N CODE 0
GAI N CODE 63
07584-021
Figure 36. Group Delay vs. Frequency at Gain Code 0, Gain Code 32, and
Gain Code 63
–120
–100
–80
–60
–40
–20
0
110 100 1000
ISOLATION (dB)
FREQUENCY (MHz)
DRIVE N CHANNE L AT GAIN CODE 0
MEASURE D CHANNE L AT GAIN CO DE 63
MEASURE D CHANNE L AT GAIN CO DE 32
MEASURE D CHANNE L AT GAIN CO DE 0
07584-034
Figure 37. Channel-to-Channel Isolation vs. Frequency,
Channel A Driven, Channel B Measured
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
0 5 10 15 20 25 30 35 40 45 50 55 60
SFDR (dB)
GAI N CODE
FREQUENCY = 10M Hz
FREQUENCY = 50M Hz
TA = +85°C
TA = +25°C
TA = –40° C
07584-037
Figure 38. SFDR vs. Gain Code at 10 MHz and 50 MHz,
1 Hz Analysis Bandwidth
07584-016
0
10
20
30
40
50
60
70
80
90
1M 10M 100M 1G
CMRR (dB)
FREQUENCY (Hz)
GAI N CODE 32
GAI N CODE 63
GAI N CODE 0
Figure 39. Common-Mode Rejection Ratio (CMRR) vs. Frequency
0
110 100 1000
FO RWARD L E AKAGE ( dBm)
FREQUENCY (MHz)
P
IN
= +10d Bm
P
IN
= +5d Bm
P
IN
= 0dBm
P
IN
= –5dBm
P
IN
= –10dBm
–20
–40
–60
–80
–100
–120
–140
–160
07584-031
Figure 40. Forward Leakage vs. Frequency, Part Disabled
AD8366 Data Sheet
Rev. B | Page 14 of 28
–1.2
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
–5–4–3–2–1012345
OUTPUT VOLTAGE (V)
TIME (ns)
10pF
0pF
07584-067
Figure 41. Large Signal Pulse Response, Gain Code 0, Input Signal 1.2 V p-p,
0 pF and 10 pF Capacitive Loading Conditions
ΩΩ
5GS/s
100k pts
A CH1 1.60V
2
1
07584-065
CH1 1V CH2 100mV M1µs
T 4.02µs
Figure 42. ENBL Time Domain Response
FREQUENCY (MHz)
–120
–100
–80
–60
–40
–20
0
0.1 1 10 100 1000
S12 MAG (dB)
07584-033
Figure 43. Reverse Isolation (S12) vs. Frequency
–1.2
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
–5–4–3–2–1012345
OUTPUT VOLTAGE (V)
TIME (ns)
10pF
0pF
07584-068
Figure 44. Large Signal Pulse Response, Gain Code 63, Input Signal 240 mV p-p,
0 pF and 10 pF Capacitive Loading Conditions
CH3 50mV CH4 1VΩΩ
M 200ns 250MS/s 4.0ns/pt A CH4 2.48V
3
07584-064
Figure 45. Gain Step Time Domain Response, Minimum-to-Maximum Gain
(Time Scale 200 ns/division), CH4 = Digital Control Inputs
Data Sheet AD8366
Rev. B | Page 15 of 28
CIRCUIT DESCRIPTION
The AD8366 is a dual, differential, digitally controlled VGA
with 600 MHz of 3 dB bandwidth and a gain range of 4.5 dB to
20.25 dB adjustable in 0.25 dB steps. Using a proprietary variable
gain architecture, the AD8366 is able to achieve excellent linearity
(45 dBm) and noise performance (11.7 nV/√Hz) at 10 MHz at
minimum gain. Intended for use in direct conversion systems, the
part also includes dc offset correction that can be disabled easily
by grounding either OFSA or OFSB. In addition, the part offers
an adjustable output common-mode range of 1.6 V to 3 V.
The main signal path is shown in Figure 46. It consists of an
input transconductance, a variable-gain cell, and an output
transimpedance amplifier.
100Ω
100Ω
12.5Ω
12.5Ω
VARIABLE
CURRENT-GAIN
STAGE OUTPUT
BUFFER
ZAI
VIRTUAL
GROUND VIRTUAL
GROUND
INP
INM
OUTP
OUTM
07584-071
Figure 46. Main Signal Path
The input transconductance provides a broadband 200 Ω
differential termination and converts the input voltage to a
current. This current is fed into the variable current-gain cell.
The output of this cell goes into the transimpedance stage, which
generates the output voltage. The transimpedance is fixed at 500 Ω,
with a roughly 25 Ω differential output impedance.
INPUTS
The inputs to the digitally-controlled VGAs in the AD8366 are
differential and can be either ac- or dc-coupled. The AD8366
synthesizes a 200 Ω (differential) input impedance, with a return
loss (re: 200 Ω) of better than 10 dB to 200 MHz. The nominal
common-mode input voltage to the part is VPOS/2, but the AD8366
can be dc-coupled to parts with lower common modes if these
parts can sink current. The amount of current sinking required
depends on the input common-mode level and is given by
ISINK (per leg) = (VPOS/2 − VICM)/100
The input common-mode range is 1.5 V to VPOS/2.
OUTPUTS
The outputs of the digitally-controlled VGAs are differential and
can be either ac- or dc-coupled. The AD8366 synthesizes a 25 Ω
differential output impedance, with a return loss (re: 25 Ω) of
better than 10 dB to 120 MHz. The nominal common-mode
output voltage is VPOS/2; however, it can be lowered or raised by
driving the VCMA or VCMB pins.
OUTPUT DIFFERENTIAL OFFSET CORRECTION
To prevent significant levels of offset from appearing at the
outputs of the AD8366, each digitally controlled VGA has a
differential offset correction loop, as shown in Figure 47. This
loop senses any differential offset at the output and corrects for
it by injecting an opposing current at the input differential ground.
The loop is able to correct for input dc offsets of up to ±20 mV.
Because the loop automatically nulls out any dc or low frequency
offset, the effect of the loop is to introduce a high-pass corner into
the transfer function of the digitally controlled VGA. The
location of this high-pass corner depends on both the gain
setting and the value of the capacitor connected to the OFSx pin
(OFSA for DVGA A and OFSB for DVGA B) and is given by
( )
( )
( )
102π
40001.0374300
kHz
,3
+
+
=
OFS
GC
HPdB
C
f
where:
GC is the gain code (a value from 0 to 63).
COFS is the value of the capacitance connected to OFSA or OFSB,
in picofarads (pF).
The offset correction loop can be disabled by grounding either
OFSA or OFSB.
g
m1
g
m2
INP
INM
OFFSET
COMPENSATION
LOOP
VARIABLE-GAIN
STAGE OUTPUT
BUFFER
ZA
I
OUTP
OUTM
C
OFS
07584-073
Figure 47. Differential Offset Correction Loop
OUTPUT COMMON-MODE CONTROL
To interface to ADCs that require different input common-mode
voltages, the AD8366 has an adjustable output common-mode
level. The output common-mode level is normally set to VPOS/2;
however, it can be changed between 1.6 V and 3 V by driving
the VCMA pin or the VCMB pin. The input equivalent circuit
for the VCMA pin is shown in Figure 48; the VCMB pin has the
same input equivalent circuit.
4kΩ
500Ω
V
POS
/2
VCMA
07584-072
Figure 48. Input Equivalent Circuit for VCMA
AD8366 Data Sheet
Rev. B | Page 16 of 28
GAIN CONTROL INTERFACE
The AD8366 provides two methods of digital gain control:
serial or parallel. When the SENB pin is pulled low, the part
is in parallel gain control mode. In this mode, the two digitally
controlled VGAs can be programmed simultaneously, or one at
a time, depending on the levels at DENA and DENB. If the SENB
pin is pulled high, the part is in serial gain control mode, with
Pin 24, Pin 23, and Pin 22 corresponding to the CS, SDAT, and
SCLK signals, respectively.
The voltage gain of the AD8366 is well approximated by
Gain (dB) = GainCode × 0.253 + 4.5
Note that at several major transitions (15 to 16, 31 to 32, and 47 to
48), the gain changes significantly less (0 dB step) or significantly
more (0.5 dB step) than the desired 0.25 dB step. This is inherent
in the design of the part and is related to the partitioning of the
variable gain block into a fine-gain and a coarse-gain section.
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
0 5 10 15 20 25 30 35 40 45 50 55 60
GAIN STEP ERROR ( dB)
GAI N ( dB)
GAI N CODE
07584-063
Figure 49. Gain and Gain Step Error vs. Gain Code at 10 MHz
Data Sheet AD8366
Rev. B | Page 17 of 28
APPLICATIONS INFORMATION
BASIC CONNECTIONS
Figure 50 shows the basic connections for operating the AD8366.
A voltage from 4.75 V to 5.25 V must be applied to the supply
pins. Each supply pin must be decoupled with at least one low
inductance, surface-mount ceramic capacitor of 0.1 µF placed as
close as possible to the device.
The differential input impedance is 200 Ω and sits at a nominal
common-mode voltage of VPOS/2. The inputs can be dc-coupled
or ac-coupled. If using direct dc coupling, the common-mode
voltage, VCM, can range from 1.5 V to VPOS/2.
The output buffers of the AD8366 are low impedance around
25 Ω designed to drive ADC inputs. The output common-mode
voltage defaults to VPOS/2; however, it can be adjusted by applying a
desired external voltage to VCMA/VCMB. The common-mode
voltage can be adjusted from 1.6 V to 3.0 V without significant
harmonic distortion degradation.
To enable the AD8366, the ENBL pin must be pulled high. Taking
ENBL low disables the device, reducing current consumption to
approximately 3 mA at ambient temperature.
VPSIA
IPPA
IPMA
ENBL
ICOM
IPMB
IPPB
VPSIB
BIT0/CS
BIT1/SDAT
BIT2/SCLK
BIT3
OCOM
BIT4
BIT5
DENA
DECB
OFSB
CCMB
VCMB
VPSOB
OPPB
OPMB
DENB
DECA
OFSA
CCMA
VCMA
VPSOA
OPPA
OPMA
SENB
VPOS
AD8366
VPOS
0.01µF
0.01µF
0.01µF
8200pF
8200pF
0.01µF
0.01µF
0.01µF
0.01µF
VPOS
0.1µF 0.1µF
VPOS
0.1µF 0.1µF
VPOS 0.1µF 0.1µF
PARALLEL/SERIAL
CONT ROL INT E RFACE (P CI)
CHANNEL A
OUTPUT
CHANNEL B
OUTPUT
CHANNEL A
INPUT
CHANNEL B
INPUT
07584-046
Figure 50. Basic Connections
AD8366 Data Sheet
Rev. B | Page 18 of 28
RF LO
MATCHING
NETWORK PAD
FILTER
BALUN
LC LOW-
PASS
FILTER
LC LOW-
PASS
FILTER
LC LOW-
PASS
FILTER
LC LOW-
PASS
FILTER
ADL5523
ADL5380 AD8366
ADL5523
0
90
ADF4350
TO
ADC
07584-047
Figure 51. Direct Conversion Receiver Block Diagram
DIRECT CONVERSION RECEIVER DESIGN
A direct conversion receiver directly demodulates an RF modulated
carrier to baseband frequencies, where the signals can be detected
and the conveyed information recovered. Eliminating the IF
stages and directly converting the signal to effectively zero IF
results in reduced component count. The image problems
associated with the traditional superheterodyne architectures
can be ignored as well. However, there are different challenges
associated with direct conversion that include LO leakage, dc
offsets, quadrature imperfections, and image rejection. LO
leakage causes self mixing that results in squaring of the LO
waveform which generates a dc offset that falls in band for the
direct conversion receiver. Residual dc offsets create a similar
interfering signal that falls in band. I/Q amplitude and phase
mismatch lead to degraded SNR performance and poor image
rejection in the direct conversion system. Figure 51 shows the
block diagram for a direct conversion receiver system.
QUADRATURE ERRORS AND IMAGE REJECTION
An overall RF-to-baseband EVM performance was measured
with the ADL5380 IQ demodulator preceding the AD8366, as
shown in Figure 56. In this setup, no LC low-pass filters were used
between the ADL5380 and AD8366. A 1900 MHz W-CDMA RF
signal with a 3.84 MHz symbol rate was used. The local oscillator
(LO) is set at 1900 MHz to obtain a zero IF baseband signal.
The gain of the AD8366 is set to maximum gain (~20.25 dB).
Figure 52 shows the SNR vs. the input power of the cascaded
system for a 5 MHz analysis bandwidth. The broad input power
range over which the system exhibits strong SNR performance
reflects the superior dynamic range of the AD8366.
0
5
10
15
20
25
30
35
40
45
–75 –65 –55 –45 –35 –25 –15 –5 5
SNR (dB)
INPUT POW ER (dBm)
07584-048
Figure 52. SNR vs. RF Input Power Level
The image rejection ratio is the ratio of the intermediate frequency
(IF) signal level produced by the desired input frequency to that
produced by the image frequency. The image rejection ratio is
expressed in decibels (dB). Appropriate image rejection is critical
because the image power can be much higher than that of the
desired signal, thereby plaguing the downconversion process.
Amplitude and phase balance between the I/Q channels are
critical for high levels of image rejection. Image rejection of
greater than 47 dB was measured for the combined ADL5380
and the AD8366 for a 5 MHz baseband frequency, as seen in
Figure 53. This level of image rejection corresponds to a ±0.5°
phase mismatch and a ±0.05 dB of amplitude mismatch for the
combined ADL5380 and AD8366. Looking back to Figure 7 and
Figure 10, the AD8366 exhibits only ±0.05 dB of amplitude mismatch
and ±0.05o of phase mismatch, thus implying that the AD8366
does not introduce additional amplitude and phase imbalance.
25
30
35
40
45
50
55
900 150013001100 1700 1900 2100 2300 2500 2700 2900
RF FREQUENCY (MHz)
IM AG E RE JE CTI ON (d B)
07584-049
Figure 53. Image Rejection vs. RF Frequency
Data Sheet AD8366
Rev. B | Page 19 of 28
LOW FREQUENCY IMD3 PERFORMANCE
To measure the IMD3 data at low frequencies, wideband
transformer baluns from North Hills Signal Processing Corp.
were used, specifically the 0301BB and the 0520BB. Figure 55
shows the IMD3 performance vs. frequency for a 2 V p-p
composite output. The IMD3 performance was also measured
for the combined ADL5380 and AD8366 system, as shown in
Figure 56, with an FFT spectrum analyzer. An FFT spectrum
analyzer works very similar to a typical ADC, the input signal
is digitized at a high sampling rate that is then passed through an
antialiasing filter. The resulting signal is transformed to the
frequency domain using fast Fourier transforms (FFT).
The single-ended RF signal from the source generator is converted
to a differential signal using a balun that gets demodulated and
down converted to differential IF signals through the ADL5380.
This differential IF signal drives the AD8366, thus eliminating
the need for low frequency baluns. Figure 54 shows the IMD3
performance vs. frequency over the 500 kHz to 5 MHz range
for minimum and maximum gain code setting on the AD8366.
During the measurements, the output was set to 2 V p-p composite.
–90
–80
–70
–60
–50
–40
–30
–20
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IM D3 ( dBc)
FREQUENCY (MHz)
GC63
GC0
07584-018
Figure 54. System IMD3 vs. Frequency, 2 V p-p Composite at
the Output of the AD8366
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0
5
10
15
20
25
30
35
40
45
50
0 5 10 15 20 25 30 35 40 45 50 55 60
IM D3 ( dBc)
OI P 3 ( dBm)
GAI N CODE
FREQUENCY = 1M Hz
FREQUENCY = 3M Hz
07584-035
Figure 55. OIP3 on Low Frequency, 2 V p-p Composite
AD8366 Data Sheet
Rev. B | Page 20 of 28
V
POS
0.1µF 100pFV
POS
0.1µF
100pF
LO
BALUN
100pF100pF
V
POS
BALUN
RFIN
100pF
100pF
VPOS
0.1µF 100pF
1
24 23 22 21 2019
78 9 10 11 12
2
3
4
5
6
18
17
16
15
14
13
VCC
GND
RFIP
RFIN
GND
ADJ
GND
GND
QHI
QLO
GND
VCC
ENBL
GND
LOIP
LOIN
GND
NC
GND
GND
IHI
ILO
GND
VCC
ADL5380
AD8366
BIT0
BIT1
BIT2
BIT3
OCOM
BIT4
BIT5
DENA
VPSIA
IPPA
IPMA
ENBL
ICOM
IPMB
IPPB
VPSIB
DECA
CCMA
VPSOA
OPMA
OFSA
VCMA
OPPA
SENB
DECB
CCMB
VPSOB
OPMB
OFSB
VCMB
OPPB
DENB
VPOS
0.01µF
0.1µF
0.01µF
V
POS
V
POS
0.1µF
0.1µF
PARALLEL/SERIAL
CONT ROL INT E RFACE
V
POS
0.1µF 0.01µF 0.1µF
0.01µF
0.01µF C
OFS
V
POS
0.01µF
200Ω
200Ω
Q CHANNEL
C
OFS
07584-050
I CHANNEL
Figure 56. ADL5380 and AD8366 Interface Block Diagram
Data Sheet AD8366
Rev. B | Page 21 of 28
BASEBAND INTERFACE
In most direct-conversion receiver designs, it is desirable to select a
wanted carrier within a specified band. The desired channel can be
demodulated by tuning the LO to the appropriate carrier frequency.
If the desired RF band contains multiple carriers of interest, the
adjacent carriers would also be down converted to a lower IF
frequency. These adjacent carriers can be a problem if they are
large relative to the desired carrier because they can overdrive
the baseband signal detection circuitry. As a result, it is often
necessary to insert a filter to provide sufficient rejection of the
adjacent carriers.
It is necessary to consider the overall source and load impedance
presented by the AD8366 and the ADC input to design the
filter network. The differential baseband output impedance of
the AD8366 is 25 Ω and is designed to drive a high impedance
ADC input. It may be desirable to terminate the ADC input down
to the lower impedance by using a terminating resistor, such as
500 Ω. The terminating resistor helps to better define the input
impedance at the ADC input at the cost of a slightly reduced gain.
The order and type of filter network depends on the desired high
frequency rejection required, pass-band ripple, and group delay.
Figure 57 shows the schematic for a typical fourth-order, Chebyshev,
low-pass filter. Table 4 shows the typical values of the filter
components for a fourth-order, Chebyshev, low-pass filter with
a differential source impedance of 25 Ω and a differential load
impedance of 200 Ω.
L1
L2
C1
L3
L4
C2 Z
LOAD
Z
SOURCE
07584-051
Figure 57. Schematic of a Fourth-Order, Chebyshev, Low-Pass Filter
Table 4. Typical Values for Fourth-Order, Chebyshev, Low-Pass Filter
3 dB Corner (MHz) ZSOURCE (Ω) ZLOAD (Ω) L1 (µH) L2 (µH) L3 (µH) L4 (µH) C1 (pF) C2 (pF)
5 25 200 6.6 6.6 6.0 6.0 220 180
10 25 200 3.3 3.3 3 3 110 90
28 25 200 1.2 1.2 1 1 39 33
AD8366 Data Sheet
Rev. B | Page 22 of 28
CHARACTERIZATION SETUPS
Figure 58 and Figure 59 are characterization setups used
extensively to characterize the AD8366. Characterization was
done on single-ended and differential evaluation boards. The
bulk of the characterization was done using an automated VEE
program to control the equipment as shown in Figure 58. This
setup was used to measure P1dB, OIP3, OIP2, IMD2, IMD3,
harmonic distortion, gain, gain error, supply current, and noise
density. All measurements were done with a 200 Ω load. All balun,
output matching network, and filter losses were de-embedded.
Gain error was measured with constant input power. All other
measurements were done on 2 V p-p (4 dBm, re: 200 Ω) on
the output of the device under test (DUT), and 2 V p-p composite
output for two-tone measurements. To measure harmonic
distortion, band-pass and band-reject filters were used on
the input and output of the DUT.
Figure 59 shows the setup used to make differential measurements.
All measurements on this setup were done in a 50 Ω system and
post processed to reference the measurements to a 200 Ω system.
Gain and phase mismatch were measured with 2 V p-p on the
output, and small signal frequency responses were measured
with −30 dBm on the input of the DUT.
Data Sheet AD8366
Rev. B | Page 23 of 28
AGILENT 34980A
MULTIFUNCTION SWITCH
(WITH 34950 AND 34921 MODULES)
AGILENT 34401A DMM
(IN DC I MODE FOR SUPPLY
CURRENT MEASUREMENT)
AGILENT E3631A POWER
SUPPLY
BAND PASS
AGILENT E8251D
SIGNAL GENERATOR
AGILENT E8251A
SIGNAL GENERATOR
AGILENT E4440A
SPECTRUM ANALYZER
COMBINER
IEEE
IEEE
IEEE
IEEE
IEEE
IEEE
RF SWITCH
MATRIX
KEITHLEY
RF SWITCH
MATRIX
KEITHLEY
AD8366
EVALUATION BOARD
BAND REJECT
IEEE
IEEE
07584-069
CH1
RF IN
CH2
RF IN
CH1
RF OUT
CH2
RF OUT
Figure 58. Characterization Setup, Single-Ended Measurements
AD8366 Data Sheet
Rev. B | Page 24 of 28
AD8366
EVALUATION BOARD
CH1
OP
CH1
OM
CH2
OP
CH2
OM
CH2
IP
CH2
IM
CH2
IP
CH2
IM
Rohde & Schwarz ZVA8
RF SWITCH
MATRIX
KEITHLEY
AGILENT E3631A
POWER SUPPLY
07584-070
Figure 59. Characterization Setup, Differential Measurements
Data Sheet AD8366
Rev. B | Page 25 of 28
EVALUATION BOARD
The schematic for the AD8366 evaluation board is shown in Figure 60. The board can be used for single-ended or differential baseband
analysis. The default configuration of the board is for single-ended baseband analysis.
C33
S4
AD8366
DENA
VPSIA
IPPA
IPMA
ENBL
ICOM
IPMB
IPPB
VPSIB
DECA
CCMA
VPSOA
OPMA
OFSA
VCMA
OPPA
SENB
DECB
CCMB
VPSOB
OPMB
OFSB
VCMB
OPPB
DENB
BIT0
BIT1
BIT2
BIT3
OCOM
BIT4
BIT5
R30 R29
R34
R69
R65R67
R71 R70
R35
R39
T3
C26
C24
R16
R19
R20
R58
R47R46
R63 R62
R21
R15
T2
C5
C21
R13
R12
R17
R48
R44R45
R54 R50
R18
R14
T1
C20
C18
R33 R31
R36
R72
R68R80
R74 R73
R37
R38
T4
C27
C25
R40 VPSI_A
S9
R61 VPSI_A
S2
R41 VPSI_A
S6
R42 VPSI_A
S8
R43 VPSI_A
S3
R26
R32
VPSI_A
C11C2
C29
S5
R53 VPSI_A
S10
R64
BIT2
VPSI_A
C31
S7
R57 VPSI_A
VPSO_A
VCMA
VPSO_B
VCMB
C12 C3
C10 S12
C9
ENBL
VPSI_BVPSI_A
U1
BIT2
C23
R6
C16
VPSO_B
R5
C15
VPSO_A
VPOS
R4
C14
VPSI_B
R3
C13
C1
VPSI_A
S1
VPSI_A R79
C30
ENBL R10
VPSI_A R22
C22
VCMA R24
VPSI_B R28
C28
VCMB
07584-056
S11
Figure 60. Evaluation Board Schematic
AD8366 Data Sheet
Rev. B | Page 26 of 28
07584-059
Figure 61. AD8366 Evaluation Board Printed Circuit Board (PCB), Top Side
07584-058
Figure 62. AD8366 Evaluation Board PCB, Bottom Side
Table 5. Evaluation Board Configuration Options
Components Function Default Conditions
C1, C13 to C16, R3 to R6 Power supply decoupling. Nominal supply decoupling consists of a
0.1 μF capacitor to ground followed by 0.01 μF capacitors to ground
positioned as close to the device as possible.
C1 = 0.1 μF (size 0603),
C13 to C16 = 0.01 μF (size 0402),
R3 to R6 = 0 Ω (size 0603)
T1, T2, C5, C18, C20, C21,
R12 to R21, R44 to R48,
R50, R54, R58, R62, R63
Input interface. The default configuration of the evaluation board is
for single-ended operation. T1 and T2 are 4:1 impedance ratio baluns to
transform a 50 Ω single-ended input into a 200 Ω balanced differential
signal. R12 to R14 and R15, R16, and R19 are populated for appropriate
balun interface. R44 to R48 and R50, R54, R58, R62, and R63 are
provided for generic placement of matching components. C5, C18,
C20, and C21 are balun decoupling capacitors. R17, R18, R20, and
R21 can be populated with 0 Ω, and the balun interfacing resistors
can be removed to bypass T1 and T2 for differential interfacing.
T1, T2 = ADT4-6T+ (Mini-Circuits),
C5, C20 = 0.1 μF (size 0402),
C18, C21 = do not install,
R12 to R16, R19, R44 to R47 = 0 Ω
(size 0402),
R17, R18, R20, R21,R48, R50, R54,
R58, R62, and R63 = open (size 0402)
T3, T4, C24 to C27, R29 to
R31, R33 to R39, R65, R67
to R74, R80
Output interface. The default configuration of the evaluation board
is for single-ended operation. T3 and T4 are 4:1 impedance ratio
baluns to transform a 50 Ω single-ended output into a 200 Ω balanced
differential load. R29 to R31, R33, R38, and R39 are populated for
appropriate balun interface. R65, R67 to R74, and R80 are provided
for generic placement of matching components. C24, C25, C26, and
C27 are balun decoupling capacitors. R34 to R37 can be populated
with 0 Ω, and the balun interfacing resistors can be removed to
bypass T3 and T4 for differential interfacing.
T3, T4 = ADT4-6T+ (Mini-Circuits),
C24, C25 = 0.1 μF (size 0402),
C26, C27 = do not install,
R29 to R31, R33, R38, R39, R65, R67,
R68, R80 = 0 Ω (size 0402),
R34 to R37, R69 to R74 = open (size 0402)
Data Sheet AD8366
Rev. B | Page 27 of 28
Components Function Default Conditions
S1, S5, S7, R53, R57, R79,
C29, C30, C31
Enable interface includes device enable and data enable.
Device enable. The AD8366 is enabled by applying a logic high
voltage to the ENBL pin. The device is enabled when the S1 switch is
set in the down position (high), connecting the ENBL pin to VPSI_A.
Data enable. DENA and DENB are used to enable the data path for
Channel A and Channel B, respectively. Channel A is enabled when
the S5 switch is set in the down position (high), connecting the DENA
pin to VPSI_A. Likewise, Channel B is enabled when the S7 switch is
set in the down position (high), connecting the DENB pin to VPSI_A.
Both channels are disabled by setting the switches to the up position,
connecting the DENA and DENB pins to GND.
S1, S5, S7 = installed,
R53, R57 = 5.1 kΩ (size 0603),
R79 = 10 kΩ (size 0402),
C30 = 0.01 µF (size 0402),
C29, C31 = 1500 pF (size 0402)
S2, S3, S4, S6, S8, S9, S10
R26, R32, R40 to R43, R61,
R64, C23, C33, U1
Serial/parallel interface control. SENB is used to set the data control
either in parallel or serial mode. The parallel interface is enabled when
S4 is in the up position (low). The serial interface is enabled when S4
is in the down position (high).
For SENB pulled low, BIT0 (S9) sets 0.25 dB gain, BIT1 (S2) sets 0.5 dB
gain, BIT2 (S3) sets 1 dB gain, BIT3 (S6) sets 2 dB gain, BIT4 (S8) sets
4 dB gain, and BIT5 (S10) sets 8 dB gain.
For SENB pulled high, BIT0 becomes a chip select (CS), BIT1 becomes
a serial data input (SDAT), and BIT2 becomes serial clock (SCLK). BIT3 to
BIT5 are not used in serial mode. U1 is used to deglitch the SCLK signal.
S2, S3, S4, S6, S8, S9, S10 = installed,
R26 = 698 kΩ (size 0603),
R32, R40 to R43, R61, R64 = 5.1 kΩ
(size 0603),
C23, C33 = 1500 pF (size 0603),
U1 = SN74LVC2G14 inverter chip
S11, S12, C9, C10
DC offset correction loop compensation.
The dc offset correction loop is enabled (high) with S11 and S12 for
Channel A and Channel B, respectively, when the enabled pins, OFSA/
OFSB, are connected to ground through the C9 and C10 capacitors.
When disabled (low), OFSA/OFSB are connected to ground directly.
S11, S12 = installed,
C9, C10 = 8200 pF (size 0402)
R10, R22, R24, R28, C22,
C28
Output common-mode setpoint. The output common mode on
Channel A and Channel B can be set externally when applied to
VCMA and VCMB. The resistive change through the potentiometer
sets a variable VCMA voltage. If left open, the output common mode
defaults to VPOS/2.
R10, R24 = 10 kΩ potentiometers,
R22, R28 = 0 Ω,
C22, C28 = 0.1 µF (size 0402)
C2, C3, C11, C12 Reference output decoupling capacitor to circuit common. C2, C3 = 0.1 µF (size 0402),
C11, C12 = 0.01 µF (size 0402)
AD8366 Data Sheet
Rev. B | Page 28 of 28
OUTLINE DIMENSIONS
1
0.50
BSC
BOTTOM VIEWTOP VIEW
PIN 1
INDICATOR
32
916
17
24
25
8
EXPOSED
PAD
PIN 1
INDICATOR
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
0.30
0.25
0.18
5.10
5.00 SQ
4.90
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.50
0.40
0.30
0.20 MIN
2.85
2.70 SQ
2.55
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-2.
08-22-2013-A
PKG-004332
Figure 63. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-21)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD8366ACPZ-R7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP] CP-32-21
AD8366-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
©2010–2017 Analog Devices, Inc. All rights reserved. Trademarks
and
registered trademarks are the property of their respective owners.
D07584-0-8/17(B)