NUS6189MNTWG - ON Semiconductor

October, 2008 − Rev. 0

Publication Order Number:

NUS6189MN/D

NUS6189MN

Low Profile Overvoltage

Protection IC with

Integrated MOSFET

This device represents a new level of safety and integration by

combining an overvoltage protection circuit (OVP) with a 30 V

P−channel power MOSFET, a low VCE(SAT) transistor, and low

RDS(on) power MOSFET or charging. The OVP is specifically

designed to protect sensitive electronic circuitry from overvoltage

transients and power supply faults. During such events, the IC quickly

disconnects the input supply from the load, thus protecting it. The

integration of the additional transistor and power MOSFET reduces

layout space and promotes better charging performance.

The IC is optimized for applications that use an external AC−DC

adapter or a car accessory charger to power a portable product or

recharge its internal batteries.

Features

•Overvoltage Turn−Off Time of Less Than 1.0 ms

•Accurate Voltage Threshold of 6.85 V, Nominal

•Undervoltage Lockout Protection; 2.8 V, Nominal

•High Accuracy Undervoltage Threshold of 2.0%

•−30 V Integrated P−Channel Power MOSFET

•Low RDS(on) = 50 mW @ −4.5 V

•High Performance −12 V P−Channel Power MOSFET

•Single−Low Vce(sat) Transistors as Charging Power Mux

•Compact 3.0 x 4.0 mm QFN Package

•Maximum Solder Reflow Temperature @ 260°C

•This is a Pb−Free Device

Benefits

•Provide Battery Protection

•Integrated Solution Offers Cost and Space Savings

•Integrated Solution Improves System Reliability

•Optimized for Commercial PMUs from Top Suppliers

Applications

•Portable Computers and PDAs

•Cell Phones and Handheld Products

•Digital Cameras

QFN22

CASE 485AT

Device Package Shipping†

ORDERING INFORMATION

MARKING

DIAGRAM

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

NUS6189MNTWG QFN22

(Pb−Free)

3000 / Tape & Reel

http://onsemi.com

(Note: Microdot may be in either location)

1NUS

6189

ALYWG

NUS6189 = Specific Device Code

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

NUS6189MN

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Batt

Base

Collector

Batt

Control

GND

Batt

(Top View)

Collector

711

Source2

Gate2

Emitter

Collector

VCC

OVPOUT

VIN

Batt

Source1

Gate1

Batt

Figure 1. Pinout

OVPOUT

Qualcomm

QSC60xx

Adapter

Input

OVP

CHG CTL

VSense

VCHG

VSense

Vbat

Bat FET

Battery

Figure 2. Typical Charging Solution for Qualcomm QSC60xx

12 MOSFET2

BJT

MOSFET1

4,5,6,7

2,16,17,21,22

Blocks Integrated

in NUS6189

OVPOUT

GND

VIN

Base

Batt

Collector

Source1

Gate1

Emitter

9, 11, 13

VCC

Source2

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FUNCTIONAL PIN DESCRIPTIONS

Pin Function Description

1Source 1 This pin is the source of MOSFET1 and connects to the more negative Vsense pin of the PMIC and

to the more negative side of the current sense resistor.

2, 16, 17, 21, 22 Batt These pins are the drain of MOSFET2 and connect to the battery and the Vbat pin of the PMIC.

3 Base The base of the internal bipolar transistor is connected to this pin. It connects to the Charge Control

pin of the PMIC.

4, 5, 6, 7 Collector The collector of the internal bipolar transistor connects to these pins and should be connected to the

more positive side of the current sense resistor as well as the more positive Vsense pin of the PMIC.

8 Emitter This pin is connected to the emitter of the bipolar transistor. It should be connected externally to the

OVPOUT pins.

9, 11, 13 OVPOUT These pins are the output of the OVP circuit. Internally they connect to the drain of MOSFET2. These

pins connect externally to the Vcharge pin of the PMIC.

10 Gate2 This pin is the gate of MOSFET2. It is not normally connected to external circuitry.

12 Source 2 The source of the OVP FET is connected to this pin. This pin needs to be connected to pins 14 & 15.

14 VCC This pin is the VCC pin of the OVP chip. It needs to be connected to pins 12 and 15.

15 VIN This pin senses the output voltage of the charger. If the voltage on this input rises above the over-

voltage threshold (VTH), the OVPOUT pin will be driven to within 1.0 V of VIN, thus disconnecting the

FET. The nominal threshold level is 6.85 V. This pin needs to be connected to pins 12 and 14.

18 Gate1 This pin is the gate of MOSFET1. It connects to the Bat FET pin of the PMIC.

19 Gnd This is the ground reference pin for the OVP chip.

20 Control This logic signal is used to control the state of OVPOUT and turn−on/off the P−channel MOSFET. A

logic level high results in the OVPOUT signal being driven to within 1.0 V of VCC which turns off

MOSFET2. If this pin is not used, it should be connected to ground.

NUS6189MN

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MAXIMUM RATINGS

Rating Symbol Value Unit

VIN to Ground VIN -0.3 to 30 V

Gate2 Voltage to Ground VG2 -0.3 to 30 V

Control Pin to Ground VCNTRL -0.3 to 13 V

Shunt Voltage (OVPOUT to Batt) Vshunt 12 V

Maximum Power Dissipation (TA = 50°C, Notes 1 & 3) PD1.2 W

Thermal Resistance, Junction-to-Air (Note 1)

Average q for chip, minimum copper

Maximum q for power device, minimum copper

Average q, for chip (Note 2)

Maximum q for power device (Note 1)

Average q for chip (Note 1)

Maximum q for power device (Note 1)

qJ-A 137

145

103

°C/W

Operating Case Temperature (Note 4) TCmax 125 °C

Operating Ambient Temperature (PD = 0.5 W, Note 1) TAmb 109 °C

Operating Junction Temperature (All Dice) TJmax 150 °C

Thermal Resistance Junction−to−Case (Note 4) YJC 30 °C/W

Storage Temperature Range Tstg -65 to 150 °C

Continuous Input Current (TA = 50°C, Notes 1 & 3) Imax 2.6 A

Gate-to-Source Voltage MOSFET1 VGS1 ±8.0 V

Drain-to-Source Voltage MOSFET1 VDS1 −12 V

Drain-to-Source Voltage MOSFET2 VDS2 −30 V

Collector-Emitter Voltage BJT VCEO −20 V

Collector-Base Voltage BJT VCBO −20 V

Emitter-Base Voltage BJT VEBO −7.0 V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. Surface−mounted on FR4 board using 1 inch sq pad size (Cu area = 1.127 in sq [1 oz] including traces).

2. Surface−mounted on FR4 board using 0.25 inch sq pad size (Cu area = 0.37 in sq [1 oz] including traces).

3. VIN = 6.0 V, all power devices fully enhanced.

4. Surface−mounted on FR4 board using 400 mm sq pad size, 4 oz Cu, PD < 800 mW.

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ELECTRICAL CHARACTERISTICS (TJ = 25°C, CNTRL ≤ 1.5 V, VCC = 6.0 V, unless otherwise specified)

Characteristic Symbol Min Typ Max Unit

OVP THRESHOLD

Input Threshold (VIN Increasing) Vth 6.65 6.85 7.08 V

Input Hysteresis (VIN Decreasing) Vhyst 50 150 200 mV

Input Impedance (VIN = Vth) RIN 70 150 – kW

CONTROL INPUT

Control Voltage High (Output On) VcntrlHI 1.50 – – V

Control Voltage Low (Output Off) VcntrlLO – – 0.50 V

Control Current High (Vih = 5.0 V) Iih – 95 200 mA

Control Current Low (Vil = 0.5 V) Iil – 10 −mA

OVP GATE DRIVE VOLTAGE

Gate2 Voltage High (VIN = 8.0 V; ISource = 10 mA)

Gate2 Voltage High (VIN = 8.0 V; ISource = 0.25 mA)

Gate2 Voltage High (VIN = 8.0 V; ISource = 0 mA)

Voh VIN – 1.0

VIN – 0.25

VIN – 0.1

–

Gate2 Voltage Low

(VIN = 6.0 V; ISink = 0 mA, Control = 0 V)

Vol – – 0.10 V

Gate2 Sink Current (VIN < VTh, OVPOUT = 1.0 V, Note 5) ISink 10 33 50 mA

TIMING

Turn on Delay − Input

(VIN stepped down from 8 to 6 V; measured at 50% point of OVPOUT

, Note 5)

ton_IN – – 10 ms

Turn off Delay − Input (VIN stepped up from 6.0 to 8.0 V; CL = 12 nF Output >

VIN − 1.0 V)

toff_IN – 0.5 1.0 ms

Turn on Delay − Control (Control signal stepped down from 2.0 to 0.5 V;

measured to 50% point of OVPOUT

, Note 5)

ton_CT – – 10 ms

Turn off Delay − Control (Control signal stepped up from 0.5 to 2.0 V; CL = 12

nF Output > VIN −1.0 V)

toff_CT – 1.0 2.0 ms

TOTAL DEVICE

VIN Operating Voltage Range (Note 5) VIN 3.0 4.8 25 V

Input Bias Current IBias – 0.75 1.0 mA

Undervoltage Lockout (VIN Decreasing) VLock 2.5 2.8 3.0 V

OVP FET (MOSFET2) (TJ = 25°C, VCC = 6.0 V, unless otherwise specified)

Voltage Drop (VIN to OVPOUT

, VGS = -4.5 V)

ILoad = 0.6 A

ILoad = 1.0 A

ILoad = 1.0 A, TJ = 150°C (Note 5)

VOVP –

–

100

135

On Resistance

ILoad = 0.6 A

ILoad = 1.0 A

ILoad = 1.0 A, TJ = 150°C (Note 5)

RDS(on)

–

−

100

135

Off State Leakage Current

TJ = 125°C

ILeak –

–

-0.1

–

-1.0

-100

CHARGING BJT (TJ = 25°C, unless otherwise specified)

Collector-Emitter Cutoff Current (VCES = -20 V, Note 5) ICES – – -0.1 mA

DC Current Gain (IB = -2.0 mA, VCE = -2.0 V, Note 6) hfe 180 – – –

Collector-Emitter Saturation Voltage

IC = -1.0 A, IB = -0.01 A

IC = -1.0 A, IB = -0.1 A

VCE(sat) –

–

-0.10

-0.069

-0.12

-0.09

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ELECTRICAL CHARACTERISTICS (TJ = 25°C, CNTRL ≤ 1.5 V, VCC = 6.0 V, unless otherwise specified)

Characteristic UnitMaxTypMinSymbol

Input Capacitance (VEB = -0.5 V, f = 1.0 MHz, Note 5) Cibo – 240 400 pF

Output Capacitance (VCB = -3.0 V, f = 1.0 MHz, Note 5) Cobo – 50 100 pF

CHARGING FET (MOSFET1) (TJ = 25°C, unless otherwise specified)

Voltage Drop Across FET

VGS = -4.5 V, ILoad = 1.0 A

VGS = -2.5 V, ILoad = 1.0 A

VGS = -4.5 V, ILoad = 1.0 A, TJ = 150°C (Note 5)

VDS –

–

On Resistance

VGS = -4.5 V, ILoad = 1.0 A

VGS = -2.5 V, ILoad = 1.0 A

VGS = -4.5 V, ILoad = 1.0 A, TJ = 150°C, (Note 5)

RDS(on)

–

−

Off State Leakage Current (Note 5)

TJ = 125°C

ILeak –

–

−0.1

–

−1.0

−10

Input Capacitance CISS – 1330 – pF

Output Capacitance COSS – 200 – pF

Reverse Transfer Capacitance CRSS –115 – pF

Total Gate Charge (Note 5) QG(TOT) – 13 15.7 nC

Threshold Gate Charge QG(TH) – 1.5 – nC

Gate-to-Source Charge QGS – 2.2 – nC

Gate-to-Drain Charge QGD – 2.9 – nC

Gate Resistance RG– 14.4 – W

Forward Transconductance (VDS = -6 V, ID = 1.0 A) gfs – 0.9 – S

Gate Threshold Voltage (VGS = VDS, ID = -250 mA) VGS(th) −0.45 −0.67 −1.1 V

Negative Threshold Temperature Coefficient VGS(th)/TJ– 2.7 – mV/

°C

5. Guaranteed by design.

6. Pulsed Condition: Pulse Width = 300 us, Duty Cycle < 2%.

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TYPICAL CHARACTERISTICS − 12V, P−CHANNEL MOSFETS (MOSFET1 − CHARGING)

Figure 3. On−Region Characteristics Figure 4. Transfer Characteristics

−VDS, DRAIN−TO−SOURCE VOLTAGE (V) −VGS, GATE−TO−SOURCE VOLTAGE (V)

6543210

2.01.51.00.5

Figure 5. On−Resistance vs. Drain Current Figure 6. On−Resistance vs. Drain Current and

Gate Voltage

−ID, DRAIN CURRENT (A) −ID, DRAIN CURRENT (A)

654321

0.02

0.03

0.04

0.05

654321

0.02

0.03

0.04

0.05

Figure 7. On−Resistance Variation with

Temperature

Figure 8. Drain−to−Source Leakage Current

vs. Voltage

TJ, JUNCTION TEMPERATURE (°C) −VDS, DRAIN−TO−SOURCE VOLTAGE (V)

1251007550250−25−50

0.6

0.8

1.0

1.2

1.4

1.6

12108642

100

1,000

10,000

−ID, DRAIN CURRENT (A)

RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)

RDS(on), DRAIN−TO−SOURCE

RESISTANCE (NORMALIZED)

−IDSS, LEAKAGE (nA)

TJ = 25°C

VGS = −1.4 V

−1.5 V

−1.6 V

−1.7 − −8.0 V VDS ≥ −10 V

VGS = 4.5 V

TJ = 100°C

TJ = 25°C

TJ = −55°C

TJ = 100°C

TJ = 25°C

TJ = −55°C

VGS = −2.5 V

TJ = 25°C

VGS = −4.5 V

150

ID = −3 A

VGS = −4.5 V TJ = 150°C

TJ = 100°C

VGS = 0 V

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TYPICAL CHARACTERISTICS − 12V, P−CHANNEL MOSFETS (MOSFET1 − CHARGING)

Figure 9. Capacitance Variation

Figure 10. Gate−to−Source and

Drain−to−Source Voltage vs. Total Charge

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)

Qg, TOTAL GATE CHARGE (nC)

1286420−2−4

400

800

1200

1600

2000

2400

2800

14121086420

Figure 11. Resistive Switching Time Variation

vs. Gate Resistance

Figure 12. Diode Forward Voltage vs. Current

RG, GATE RESISTANCE (W)−VSD, SOURCE−TO−DRAIN VOLTAGE (V)

100101

100

1,000

1.00.80.60.40.20

0.01

0.1

Figure 13. Maximum Rated Forward Biased

Safe Operating Area

−VDS, DRAIN−TO−SOURCE VOLTAGE (V)

1001010.1

0.01

0.1

100

C, CAPACITANCE (pF)

−VGS, GATE−TO−SOURCE VOLTAGE (V)

t, TIME (ns)

−IS, SOURCE CURRENT (A)

−ID, DRAIN CURRENT (A)

TJ = 25°C

VDS = 0 V

Ciss

Crss

Coss ID = −3 A

TJ = 25°C

td(off)

td(on)

VGS = 0 V TJ = 25°C

TJ = 150°CTJ = −55°C

100 ms

1 ms

10 ms

Mounted on 2″ sq.

FR4 board (0.5″ sq.

2 oz. Cu single

sided) with MOSFET

die operating.

Single Pulse

TC = 25°C

RDS(on) Limit

Thermal Limit

Package Limit

VDD = −12 V

ID = −3.0 A

VGS = −4.5 V

VDS

VGS

Qgd

Qgs

−VDS, DRAIN−TO−SOURCE VOLTAGE (V)

Ciss

VGS = 0 V

−VGS −VDS

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TYPICAL CHARACTERISTICS − 12V, P−CHANNEL MOSFETS (MOSFET1 − CHARGING)

Figure 14. FET Thermal Response

t, TIME (s)

1E+001E−011E−031E−04 1E−021E−051E−06

0.001

0.01

0.1

RqJA, EFFECTIVE TRANSIENT

THERMAL RESPONSE

1E+01 1E+02 1E+03

Single Pulse

D = 0.5

0.2

0.1

0.05

0.02

0.01

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TYPICAL CHARACTERISTICS − SINGLE PNP TRANSISTOR (BJT − CHARGING)

−55°C

VCE(sat) = 150°C

IC/IB = 10

25°C

Figure 15. Collector Emitter Saturation Voltage

vs. Collector Current

Figure 16. Collector Emitter Saturation Voltage

vs. Collector Current

IC, COLLECTOR CURRENT (A)

101.00.10.010.001

0.05

0.1

0.15

0.2

0.25

Figure 17. DC Current Gain vs. Collector

Current

Figure 18. Base Emitter Saturation Voltage vs.

Collector Current

IC, COLLECTOR CURRENT (A) IC, COLLECTOR CURRENT (A)

101.00.10.010.001

100

150

300

350

500

700

750

800

101.00.10.010.001

0.3

0.4

0.5

0.6

0.7

0.8

1.0

1.1

Figure 19. Base Emitter Turn−On Voltage vs.

Collector Current

Figure 20. Saturation Region

IC, COLLECTOR CURRENT (A) IB, BASE CURRENT (mA)

101.00.10.010.001

0.1

0.2

0.3

0.4

0.5

0.8

0.9

1.0

100101.00.10.01

0.2

0.4

0.6

0.8

1.0

VCE(sat), COLLECTOR EMITTER

SATURATION VOLTAGE (V)

hFE, DC CURRENT GAIN

VBE(sat), BASE EMITTER

SATURATION VOLTAGE (V)

VBE(on), BASE EMITTER TURN−ON

VOLTAGE (V)

VCE, COLLECTOR−EMITTER

VOLTAGE (V)

IC/IB = 100

25°C−55°C

IC, COLLECTOR CURRENT (A)

101.00.10.010.001

0.05

0.1

0.15

0.2

0.35

VCE(sat), COLLECTOR EMITTER

SATURATION VOLTAGE (V)

VCE(sat) = 150°C

0.25

0.3

650

600

550

200

250

400

450

0.9

150°C (5.0 V)

150°C (2.0 V)

25°C (5.0 V)

25°C (2.0 V)

−55°C (5.0 V)

−55°C (2.0 V)

25°C

−55°C

150°C

0.6

0.7 25°C

−55°C

150°C

VCE = −2.0 V VCE (V) IC = 500 mA

300 mA

10 mA

100 mA

IC/IB = 10

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TYPICAL CHARACTERISTICS − SINGLE PNP TRANSISTOR (BJT − CHARGING)

10 ms

100 ms

1 s

Thermal Limit

1 ms

Cibo (pF)

Figure 21. Input Capacitance Figure 22. Output Capacitance

VEB, EMITTER BASE VOLTAGE (V)

4.03.02.01.00

125

150

300

325

350

Figure 23. Safe Operating Area

VCE (Vdc)

1001.00.10.01

0.01

0.1

Cibo, INPUT CAPACITANCE (pF)

IC (A)

VCB, COLLECTOR BASE VOLTAGE (V)

168.06.00

130

170

Cobo, OUTPUT CAPACITANCE (pF)

150

6.05.0

200

225

250

275

175

Cobo (pF)

2.0 4.0 141210

1.0

110

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TYPICAL PERFORMANCE CURVES − OVERVOLTAGE PROTECTION IC

(TA= 25°C, unless otherwise specified)

1.0

0.9

0.8

0.7

0.6

0.5

−40 −25 −10 5 203550658095

Temperature (°C)

7.05

7.00

6.95

6.90

6.85

6.80

6.75

6.70

−40 −25 −10 5 203550658095

Ambient Temperature (°C)

Voltage (V)

Isupply (mA)

Figure 24. Typical Vth Threshold Variation vs.

Temperature

Figure 25. Typical Supply Current vs. Temperature

Icc ) Iin, VCC + 6 V

100

10 100 1000 10000

Figure 26. Typical Maximum Drain Peak Current vs Pulse Width

(Non−repetitive Single Pulse, VGS = 10 V, TA = 255C)

PULSE WIDTH (ms)

IDpk, AMPS (A)

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TYPICAL PERFORMANCE CURVES − 30V, P−CHANNEL MOSFET (MOSFET2 − OVP)

(TA= 25°C, unless otherwise specified)

−8 V

1.20.8

−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

−ID, DRAIN CURRENT (AMPS)

0.4

Figure 27. On−Region Characteristics Figure 28. On−Resistance vs. Gate−to−Source

Voltage

1000

100

Figure 29. Drain−to−Source Leakage Current

vs. Voltage

−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

−IDSS, LEAKAGE CURRENT (nA)

210

0.1

Figure 30. Diode Forward Voltage vs. Current

−VGS, GATE VOLTAGE (VOLTS)

TJ = 25°C

100000

VGS = 0 V

RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)

−3 V

25 30

−3.2 V

−3.4 V

−4.5 V

0.2

1.6 2

10000

468

TJ = 100°C

TJ = 150°C

9357

TJ = 25°C

ID = −3.7 A

3.22.82.4 3.6 4

−3.6 V

−3.8 V

−4 V

−4.2 V

−10V

−6 V

−5 V

−5.5 V

0.9

−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

−IS, SOURCE CURRENT (AMPS)

TJ = 25°C

1.00.40.3

0.5 0.80.6

0.1

0.7 1.1

VGS = 0 V

TJ = −55°C

TJ = 150°C

TJ = 100°C

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PACKAGE DIMENSIONS

QFN22, 3x4, 0.5P

CASE 485AT−01

ISSUE B

SOLDERING FOOTPRINT*

0.50

0.52

22X

DIMENSIONS: MILLIMETERS

PITCH

22X

4.30

1.47

1.55

0.925

3.30

1.47

1.21

1.58

0.39

1.14

0.30

PACKAGE

OUTLINE

ÈÈÈ

PIN 1

REFERENCE

C0.15

C0.08

25X

C0.10

SIDE VIEW

TOP VIEW

BOTTOM VIEW

22X

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30 MM FROM TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PADS AS WELL AS THE TERMINALS.

DIM MIN NOM

MILLIMETERS

A0.80 0.90

A1 0.00 0.025

A3 0.20 REF

b0.20 0.25

D3.00 BSC

D2 1.45 1.50

E4.00 BSC

E2 1.05 1.10

e0.50 BSC

K0.25 −−−

L0.30 0.325

0.10 B

0.05

CNOTE 3

22X

16X

DETAIL A

OPTIONAL

CONSTRUCTIONS

NOTE 4 SEATING

PLANE

DETAIL B

L1 −−− −−−

G1.35 1.40

G1 0.95 1.05

G2 0.855 0.885

E3 1.30 1.35

E4 1.40 1.45

D3 0.52 0.57

D4 1.02 1.07

ÉÉÉ

ÇÇÇ

ÉÉ

DETAIL B

MOLD CMPDEXPOSED Cu

OPTIONAL

CONSTRUCTIONS

DETAIL A

1.00

0.05

0.30

1.55

1.15

−−−

0.35

0.15

1.50

1.15

0.915

1.40

1.50

0.62

1.12

MAX

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

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