W83195BR-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
Publication Release Date: May 23, 2005
- 1 - Revision A1
W83195BR-25
Step-less Frequency Solano 815 Clock
Gen. 3-DIMM, with S.S.T.
Date: May 23, 2005 Revision: A1
W83195BR-25
- 2 -
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 3
2. PRODUCT FEATURES .............................................................................................................. 3
3. PIN CONFIGURATION ...............................................................................................................4
4. PIN DESCRIPTION..................................................................................................................... 4
4.1 Crystal I/O.................................................................................................................................4
4.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs............................................................................5
4.3 I2C Control Interface ................................................................................................................5
4.4 Fixed Frequency Outputs.........................................................................................................6
4.5 Power Pins................................................................................................................................6
5. FREQUENCY SELECTION BY HARDWARE ............................................................................ 7
6. SERIAL CONTROL REGISTERS............................................................................................... 8
6.1 Register 0: CPU Frequency Select Register.........................................................................10
6.2 Register 1: CPU Clock Register (1 = Active, 0 = Inactive)....................................................10
6.3 Register 2: SDRAM Clock Register (1 = Active, 0 = Inactive) ..............................................10
6.4 Register 3: PCI Clock Register (1 = Active, 0 = Inactive) .....................................................11
6.5 Register 4: Additional Register (1 = Active, 0 = Inactive)......................................................11
6.6 Register 5: SDRAM Clock Register (1 = Active, 0 = Inactive) ..............................................11
6.7 Register 6 Watchdog Timer Register ....................................................................................12
6.8 Register 7: M/N Program Register ........................................................................................12
6.9 Register 8: M/N Program Register ........................................................................................12
6.10 Register 9: Spread Spectrum Programming Register ..........................................................13
6.11 Register 10: Divisor and Step-less Enable Register .............................................................13
6.12 Register 11: Winbond Chip ID Register (Read Only) ...........................................................14
6.13 Register 12: Winbond Chip ID Register (Read Only) ...........................................................14
7. SPECIFICATIONS .................................................................................................................... 15
7.1 Absolute Maximum Ratings...................................................................................................15
7.2 Electronical Characteristics---Input/Output............................................................................15
7.3 Electronical Characteristics of CPU Clock ............................................................................16
7.4 Electronical Characteristics of 3V66 Clock............................................................................16
7.5 Electronical Characteristics of SDRAM Clock.......................................................................17
7.6 Electronical Characteristics of PCI Clock ..............................................................................17
7.7 Electronical Characteristics of 48MHz, REF Clock ...............................................................18
8. ORDERING INFORMATION..................................................................................................... 18
9. HOW TO READ THE TOP MARKING...................................................................................... 19
10. PACKAGE DRAWING AND DIMENSIONS.............................................................................. 19
11. REVISION HISTORY ................................................................................................................20
W83195BR-25
Publication Release Date: May 23, 2005
- 3 - Revision A1
1. GENERAL DESCRIPTION
The W83195BR-25 is a Clock Synthesizer for Intel 815 Solano chipset. W83195BR-25 provides all
clocks required for high-speed RISC or CISC microprocessor and also provides 64 different
frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally
selectable with smooth transitions.
The W83195BR-25 provides I2C serial bus interface to program the registers to enable or disable each
clock outputs and provides 0.25% and 0.5% center type spread spectrum to reduce EMI.
The W83195BR-25 provides step less frequency programming by controlling the VCO freq. and the
clock output divisor ratio. Also skew of CPU, SDRAM and 3V66 clock outputs are programmable. A
watch dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal.
The W83195BR-25 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF
loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as
maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide
better than 0.5V /ns slew rate.
2. PRODUCT FEATURES
• 2 CPU clocks (2.5V)
• 3 3V-66 clocks (3.3V)
• 12 SDRAM clocks for 3 DIMMs(3.3V)
• 8 PCI synchronous clocks.
• Optional single or mixed supply:
(VDDR = VDDP=VDDS = VDD48 = VDD3 = 3.3V, VDDA=VDDC=2.5V)
• Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns
• Smooth frequency switch with selections from 66.8 to 200MHz
• I
2C 2-Wire serial interface and I2C read back
• 0.25% center and 0.5% center type spread spectrum
• Programmable registers to enable/stop each output and select modes
(Mode as Tri-state or Normal)
• 48 MHz for USB
• 24 MHz for super I/O
• Packaged in 56-pin SSOP
W83195BR-25
- 4 -
3. PIN CONFIGURATION
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDDR
VSS
Xin
Xout
VDD3
PCICLK0/ FS0&
VSS
PCICLK6^
PCICLK2/SEL24_48*
PCICLK3^/Mode1*
PCICLK4^
SDRAM_F
VSS
3V66-0
VDDP
PD#/RESET$
*SDATA
*SDCLK
VddA
REF0/ FS4&^
IOAPIC
VSS
CPUCLK0
VDDC
CPUCLK1
VSS
SDRAM 0
SDRAM 1
SDRAM 2
VDDS
SDRAM 3
VSS
SDRAM 4
SDRAM 5
SDRAM 6
SDRAM 7
VSS
VDDS
48MHz/ *FS3 ^
24_48MHz/ FS2&
PCICLK5^
VDD48
VSS
3V66-1
VDDP
PCICLK1/ *FS1
PCICLK7
VSS VSS
VDDS
VDDS
SDRAM 8
SDRAM 9
SDRAM 11
SDRAM 10
49
50
51
52
53
54
55
56
3V66-2
4. PIN DESCRIPTION
BUFFER TYPE SYMBOL DESCRIPTION
IN Input
OUT Output
I/O Bi-directional Pin
# Active Low
& Internal 120KΩ pull-down
* Internal 120kΩ pull-up
4.1 Crystal I/O
PIN PIN NAME TYPE DESCRIPTION
2 Xin IN Crystal input with internal loading capacitors (36pF) and
feedback resistors.
3 Xout OUT Crystal output at 14.318MHz nominally with internal
loading capacitors (36pF).
W83195BR-25
Publication Release Date: May 23, 2005
- 5 - Revision A1
4.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs
PIN PIN NAME TYPE DESCRIPTION
52,51 CPUCLK [0:1] OUT Low skew (< 250ps) clock outputs for host frequencies
such as CPU and Chipset.
PD# IN Mode1*=1, Power Down mode when driven low. 22
RESET$ OUT Mode1*=0, RESET# open drain (4ms low active pulse
when Watch Dog time out)
54 IOAPIC
OUT Clock outputs synchronous with PCI clock and powered
by VddA.
38,48,47,46
,44,43,42,
40,39,31,30
,27, 26
SDRAM_F, SDRAM
[0:11]
OUT SDRAM clock outputs.
PCICLK0 OUT 3.3V 33MHz PCI clock during normal operation. 11
FS0& IN Latched input for FS0 at initial power up for H/W
selecting the output frequency of CPU, SDR
A
M and PCI
clocks (Default=0).
PCICLK1 OUT Low skew (< 250ps) PCI clock outputs. 12
*FS1 IN Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and PCI
clocks (Default=1).
PCICLK2 OUT Low skew (< 250ps) PCI clock outputs. 13
*SEL24_48 IN Latched input for SEL24_48 at initial power up for the
output frequency of 24MHz(HIGH) and 48MHz(LOW)
clocks.
PCICLK3 OUT Low skew (< 250ps) PCI clock outputs. 15
Mode1* IN Latched input for Mode* pin at initial power up for the
output PD# /RESET# output selection.
16,17,19,20 PCICLK [4:7] OUT Low skew (< 250ps) PCI clock outputs.
6,7,8 3V66 [0:2] OUT 3.3V output clocks for the chipset.
4.3 I2C Control Interface
PIN Pin Name Type Description
24 *SDATA I/O Serial data of I2C 2-wire control interface with internal
pull-up resistor.
23 *SDCLK IN Serial clock of I2C 2-wire control interface with internal
pull-up resistor.
W83195BR-25
- 6 -
4.4 Fixed Frequency Outputs
PIN PIN NAME TYPE DESCRIPTION
REF0 OUT 14.318MHz reference clock. This REF output is the
stronger buffer for ISA bus loads.
56
FS4& IN Latched input for FS4 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and PCI
clocks (Default=0).
24_48MHz OUT 24MHz or 48MHz output clock. Default is 24MHz. 35
FS2& IN Latched input for FS2 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and PCI
clocks (Default=0).
48MHz OUT 48MHz output clock. 34
FS3* IN Latched input for FS3 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and PCI
clocks (Default=1).
4.5 Power Pins
PIN PIN NAME DESCRIPTION
53,55 VddC,VddA Power supply for CPU & IOAPIC, 2.5V or 3.3V.
33 Vdd48 Power supply for 48MHz output,3.3V.
9 Vdd3 Power supply for 3V_66 output, 3.3V.
10,18 VddP Power supply for PCICLK, 3.3V.
1 VddR Power supply for REF0, 3.3V.
45,37,32,25 VddS Power supply for SDRAM_F, SDRAM [0:11], nominal 3.3V.
4,5,14,21,28,29,36, 41,
49.50
Vss Circuit Ground.
W83195BR-25
Publication Release Date: May 23, 2005
- 7 - Revision A1
5. FREQUENCY SELECTION BY HARDWARE
FS4 FS3 FS2 FS1 FS0 CPU (MHZ) SDRAM (MHZ) 3V66(MHZ) PCI (MHZ) IOAPIC (MHZ)
0 0 0 0 0 55.00 82.50 55.00 27.50 13.75
0 0 0 0 1 60.00 90.00 60.00 30.00 15.00
0 0 0 1 0 66.80 100.20 66.80 33.40 16.70
0 0 0 1 1 68.33 102.50 68.33 34.17 17.08
0 0 1 0 0 70.00 105.00 70.00 35.00 17.50
0 0 1 0 1 72.00 108.00 72.00 36.00 18.00
0 0 1 1 0 75.00 112.50 75.00 37.50 18.75
0 0 1 1 1 77.00 115.50 77.00 38.50 19.25
0 1 0 0 0 83.30 83.30 55.53 27.77 13.88
0 1 0 0 1 90.00 90.00 60.00 30.00 15.00
0 1 0 1 0 100.30 100.30 66.87 33.43 16.72
0 1 0 1 1 103.00 103.00 68.67 34.33 17.17
0 1 1 0 0 112.50 112.50 75.00 37.50 18.75
0 1 1 0 1 115.00 115.00 76.67 38.33 19.17
0 1 1 1 0 120.00 120.00 80.00 40.00 20.00
0 1 1 1 1 125.00 125.00 83.33 41.67 20.83
1 0 0 0 0 128.00 128.00 64.00 32.00 16.00
1 0 0 0 1 130.00 130.00 65.00 32.50 16.25
1 0 0 1 0 133.70 133.70 66.85 33.43 16.71
1 0 0 1 1 137.00 137.00 68.50 34.25 17.13
1 0 1 0 0 140.00 140.00 70.00 35.00 17.50
1 0 1 0 1 145.00 145.00 72.50 36.25 18.13
1 0 1 1 0 150.00 150.00 75.00 37.50 18.75
1 0 1 1 1 153.33 153.33 76.67 38.33 19.17
1 1 0 0 0 125.00 93.75 62.50 31.25 15.63
1 1 0 0 1 130.00 97.50 65.00 32.50 16.25
1 1 0 1 0 133.70 100.28 66.85 33.43 16.71
1 1 0 1 1 137.00 102.75 68.50 34.25 17.13
1 1 1 0 0 140.00 105.00 70.00 35.00 17.50
1 1 1 0 1 145.00 108.75 72.50 36.25 18.13
1 1 1 1 0 150.00 112.50 75.00 37.50 18.75
1 1 1 1 1 153.33 115.00 76.67 38.33 19.17
W83195BR-25
- 8 -
6. SERIAL CONTROL REGISTERS
The Pin column lists the affected pin number and the @PowerUp column gives the state at true power
up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte
Count” byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in
these two bytes are considered "don't care", they must be sent and will be acknowledge. After that,
the below described sequence (Register 0, Register 1, Register 2...) will be valid and acknowledged.
Frequency Table Setting by I2C (SEL5 ~ SEL0)
SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0 CPU
(MHz)
SDRAM
(MHz)
3V66
(MHz) PCI (MHz) IOAPIC
(MHz)
0 0 0 0 0 0 55.00 82.50 55.00 27.50 13.75
0 0 0 0 0 1 60.00 90.00 60.00 30.00 15.00
0 0 0 0 1 0 66.80 100.20 66.80 33.40 16.70
0 0 0 0 1 1 68.33 102.50 68.33 34.17 17.08
0 0 0 1 0 0 70.00 105.00 70.00 35.00 17.50
0 0 0 1 0 1 72.00 108.00 72.00 36.00 18.00
0 0 0 1 1 0 75.00 112.50 75.00 37.50 18.75
0 0 0 1 1 1 77.00 115.50 77.00 38.50 19.25
0 0 1 0 0 0 83.30 83.30 55.53 27.77 13.88
0 0 1 0 0 1 90.00 90.00 60.00 30.00 15.00
0 0 1 0 1 0 100.30 100.30 66.87 33.43 16.72
0 0 1 0 1 1 103.00 103.00 68.67 34.33 17.17
0 0 1 1 0 0 112.50 112.50 75.00 37.50 18.75
0 0 1 1 0 1 115.00 115.00 76.67 38.33 19.17
0 0 1 1 1 0 120.00 120.00 80.00 40.00 20.00
0 0 1 1 1 1 125.00 125.00 83.33 41.67 20.83
0 1 0 0 0 0 128.00 128.00 64.00 32.00 16.00
0 1 0 0 0 1 130.00 130.00 65.00 32.50 16.25
0 1 0 0 1 0 133.70 133.70 66.85 33.43 16.71
0 1 0 0 1 1 137.00 137.00 68.50 34.25 17.13
0 1 0 1 0 0 140.00 140.00 70.00 35.00 17.50
0 1 0 1 0 1 145.00 145.00 72.50 36.25 18.13
0 1 0 1 1 0 150.00 150.00 75.00 37.50 18.75
0 1 0 1 1 1 153.33 153.33 76.67 38.33 19.17
0 1 1 0 0 0 125.00 93.75 62.50 31.25 15.63
0 1 1 0 0 1 130.00 97.50 65.00 32.50 16.25
0 1 1 0 1 0 133.70 100.28 66.85 33.43 16.71
0 1 1 0 1 1 137.00 102.75 68.50 34.25 17.13
0 1 1 1 0 0 140.00 105.00 70.00 35.00 17.50
0 1 1 1 0 1 145.00 108.75 72.50 36.25 18.13
0 1 1 1 1 0 150.00 112.50 75.00 37.50 18.75
0 1 1 1 1 1 153.33 115.00 76.67 38.33 19.17
W83195BR-25
Publication Release Date: May 23, 2005
- 9 - Revision A1
Frequency Table Setting by I2C (SEL5 ~ SEL0), continued.
SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0 CPU
(MHz)
SDRAM
(MHz)
3V66
(MHz) PCI (MHz) IOAPIC
(MHz)
1 0 0 0 0 0 66.8 133.00 66.80 33.40 16.70
1 0 0 0 0 1 135.00 135.00 67.50 33.75 16.88
1 0 0 0 1 0 142.00 142.00 71.00 35.50 17.75
1 0 0 0 1 1 143.00 143.00 71.50 35.75 17.88
1 0 0 1 0 0 144.00 144.00 72.00 36.00 18.00
1 0 0 1 0 1 146.00 146.00 73.00 36.50 18.25
1 0 0 1 1 0 147.00 147.00 73.50 36.75 18.38
1 0 0 1 1 1 148.00 148.00 74.00 37.00 18.50
1 0 1 0 0 0 100.20 133.00 66.80 33.40 16.70
1 0 1 0 0 1 156.00 156.00 78.00 39.00 19.50
1 0 1 0 1 0 158.00 158.00 79.00 39.50 19.75
1 0 1 0 1 1 160.00 160.00 80.00 40.00 20.00
1 0 1 1 0 0 135.00 101.25 67.50 33.75 16.88
1 0 1 1 0 1 139.00 104.25 69.50 34.75 17.38
1 0 1 1 1 0 141.00 105.75 70.50 35.25 17.63
1 0 1 1 1 1 142.00 106.50 71.00 35.50 17.75
1 1 0 0 0 0 143.00 107.25 71.50 35.75 17.88
1 1 0 0 0 1 144.00 108.00 72.00 36.00 18.00
1 1 0 0 1 0 146.00 109.50 73.00 36.50 18.25
1 1 0 0 1 1 147.00 110.25 73.50 36.75 18.38
1 1 0 1 0 0 148.00 111.00 74.00 37.00 18.50
1 1 0 1 0 1 149.00 111.75 74.50 37.25 18.63
1 1 0 1 1 0 153.00 114.75 76.50 38.25 19.13
1 1 0 1 1 1 157.00 117.75 78.50 39.25 19.63
1 1 1 0 0 0 159.00 119.25 79.50 39.75 19.88
1 1 1 0 0 1 162.00 121.50 81.00 40.50 20.25
1 1 1 0 1 0 164.00 123.00 82.00 41.00 20.50
1 1 1 0 1 1 170.00 127.50 85.00 42.50 21.25
1 1 1 1 0 0 175.00 116.67 58.30 29.15 14.58
1 1 1 1 0 1 180.00 120.00 60.00 30.00 15.00
1 1 1 1 1 0 190.00 190.00 63.33 31.67 15.83
1 1 1 1 1 1 200.40 133.60 66.80 33.40 16.70
W83195BR-25
- 10 -
6.1 Register 0: CPU Frequency Select Register
BIT @POWERUP PIN DESCRIPTION
7 0 - SSEL3 (Frequency table selection by software via I2C)
6 0 - SSEL2 (Frequency table selection by software via I2C)
5 0 - SSEL1 (Frequency table selection by software via I2C)
4 0 - SSEL0 (Frequency table selection by software via I2C)
3 0 - 0 = Selection by hardware
1 = Selection by software I2C - Bit (2, 7:4)
2 0 - SSEL4 (Frequency table selection by software via I2C)
1 0 - SSEL5 (Frequency table selection by software via I2C)
0 0 - 0 = Running
1 = Tristate all outputs
6.2 Register 1: CPU Clock Register (1 = Active, 0 = Inactive)
BIT @POWERUP PIN DESCRIPTION
7 X - FS0#
6 X - FS1#
5 X - FS2#
4 X - FS3#
3 X - FS4#
2 0 -
1 = ±0.25% Center type Spread Spectrum Modulation
0 = ±0.5% Center type Spread Spectrum Modulation
1 0 - 0 = Normal
1 = Spread Spectrum enabled
0 1 - 1 = Center type Spread Spectrum Modulation
0 = Down type Spread Spectrum Modulation
6.3 Register 2: SDRAM Clock Register (1 = Active, 0 = Inactive)
BIT @POWERUP PIN DESCRIPTION
7 1 39 SDRAM7 (Active / Inactive)
6 1 40 SDRAM6 (Active / Inactive)
5 1 42 SDRAM5 (Active / Inactive)
4 1 43 SDRAM4 (Active / Inactive)
3 1 44 SDRAM3 (Active / Inactive)
2 1 46 SDRAM2 (Active / Inactive)
1 1 47 SDRAM1 (Active / Inactive)
0 1 48 SDRAM0 (Active / Inactive)
W83195BR-25
Publication Release Date: May 23, 2005
- 11 - Revision A1
6.4 Register 3: PCI Clock Register (1 = Active, 0 = Inactive)
BIT @POWERUP PIN DESCRIPTION
7 1 20 PCICLK7 (Active / Inactive)
6 1 19 PCICLK6 (Active / Inactive)
5 1 17 PCICLK5 (Active / Inactive)
4 1 16 PCICLK4 (Active / Inactive)
3 1 15 PCICLK3 (Active / Inactive)
2 1 13 PCICLK2 (Active / Inactive)
1 1 12 PCICLK1 (Active / Inactive)
0 1 11 PCICLK0 (Active / Inactive)
6.5 Register 4: Additional Register (1 = Active, 0 = Inactive)
BIT @POWERUP PIN DESCRIPTION
7 1 8 3V66_2(Active / Inactive)
6 1 7 3V66_1(Active / Inactive)
5 1 6 3V66_0(Active / Inactive)
4 1 26 SDRAM11 (Active / Inactive)
3 1 27 SDRAM10 (Active / Inactive)
2 1 30 SDRAM9 (Active / Inactive)
1 1 31 SDRAM8 (Active / Inactive)
0 1 38 SDRAM_F (Active / Inactive)
6.6 Register 5: SDRAM Clock Register (1 = Active, 0 = Inactive)
BIT @POWERUP PIN DESCRIPTION
7 1 - CSkew2 (CPU to SDRAM skew program bit)
6 0 - CSkew1 (CPU to SDRAM skew program bit)
5 0 - CSkew0 (CPU to SDRAM skew program bit)
4 1 - CASkew2 (CPU to 3V66 skew program bit)
3 0 - CASkew1 (CPU to 3V66 skew program bit)
2 0 - CASkew0 (CPU to 3V66 skew program bit)
1 1 51 CPUCLK1 (Active / Inactive)
0 1 52 CPUCLK0 (Active / Inactive)
W83195BR-25
- 12 -
6.7 Register 6 Watchdog Timer Register
BIT @POWERUP PIN DESCRIPTION
7 0 - Enable Count 1 = start timer 0 = stop timer
6 0 - Second timeout status (READ ONLY)
5 0 - Second count 5
4 0 - Second count 4
3 0 - Second count 3
2 0 - Second count 2
1 0 - Second count 1
0 0 - Second count 0
6.8 Register 7: M/N Program Register
BIT @POWERUP PIN DESCRIPTION
7 0 - N value bit 8
6 0 - Test 1(Please do not modify)
5 1 - Test 0 (Please do not modify)
4 0 - M value bit 4
3 0 - M value bit 3
2 0 - M value bit 2
1 0 - M value bit 1
0 0 - M value bit 0
6.9 Register 8: M/N Program Register
BIT @POWERUP PIN DESCRIPTION
7 0 - N value bit 7
6 0 - N value bit 6
5 0 - N value bit 5
4 0 - N value bit 4
3 0 - N value bit 3
2 0 - N value bit 2
1 0 - N value bit 1
0 0 - N value bit 0
W83195BR-25
Publication Release Date: May 23, 2005
- 13 - Revision A1
6.10 Register 9: Spread Spectrum Programming Register
BIT @POWERUP PIN DESCRIPTION
7 0 - Spread spectrum up count 3
6 0 - Spread spectrum up count 2
5 0 - Spread spectrum up count 1
4 0 - Spread spectrum up count 0
3 0 - Spread spectrum down count 3
2 0 - Spread spectrum down count 2
1 0 - Spread spectrum down count 1
0 0 - Spread spectrum down count 0
6.11 Register 10: Divisor and Step-less Enable Register
BIT @POWERUP PIN DESCRIPTION
7 0 - 0: use frequency table
1: use M/N register to program frequency
The equation is VCO freq. = 14.318MHz * (N+4)/M
6 X - Ratio SEL3
5 X - Ratio SEL2
4 X - Ratio SEL1
3 X - Ratio SEL0
2 0 - Reserved
1 0 - Reserved
0 0 - Reserved
Register10 Bit3-6 Ratio
Bit6 Bit 5 Bit 4 Bit 3
DS3 DS2 DS1 DS0 CPU SDRAM 3V66
0 0 0 0 4 4 6
0 0 0 1 3 3 6
0 0 1 0 2 3 6
0 0 1 1 2 2 6
0 1 0 0 6 4 6
0 1 0 1 3 4 6
0 1 1 0 6 3 6
0 1 1 1 4 3 6
1 0 x x 2 2 4
1 1 x x 2 4 6
W83195BR-25
- 14 -
6.12 Register 11: Winbond Chip ID Register (Read Only)
BIT @POWERUP PIN DESCRIPTION
7 0
- Winbond Chip ID
6 1
- Winbond Chip ID
5 0
- Winbond Chip ID
4 1
- Winbond Chip ID
3 0
- Winbond Chip ID
2 0
- Winbond Chip ID
1 0
- Winbond Chip ID
0 0
- Winbond Chip ID
6.13 Register 12: Winbond Chip ID Register (Read Only)
BIT @POWERUP PIN DESCRIPTION
7 0
- Winbond Chip ID
6 0
- Winbond Chip ID
5 0
- Winbond Chip ID
4 1
- Winbond Chip ID
3 0
- Winbond Version ID
2 0
- Winbond Version ID
1 1
- Winbond Version ID
0 0
- Winbond Version ID
W83195BR-25
Publication Release Date: May 23, 2005
- 15 - Revision A1
7. SPECIFICATIONS
7.1 Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused
inputs must always be tied to an appropriate logic voltage level (Ground or Vdd).
SYMBOL PARAMETER RATING
Vdd , VIN Voltage on any pin with respect to GND - 0.5 V to + 7.0 V
TSTG Storage Temperature - 65°C to + 150°C
TB Ambient Temperature - 55°C to + 125°C
TA Operating Temperature 0°C to + 70°C
7.2 Electronical Characteristics---Input/Output
Vddq1=Vddq2 = Vddq3 = Vddq4 =3.3V, VddL1 =VddL2= 2.5V , TA = 0
°
C to +70
°
C
Parameter Symbol Min Typ Max Units Test Conditions
Input Low Voltage VIL Vss-0.3 0.8
Vdc
Input High Voltage VIH 2.0 Vdd+0.3 Vdc
Input Low Current IIL -5 µA No pull-up resistors
Input Low Current IIL -200 µA Pull-up resistros
Input High Current IIH -5 5 µA
Input Capacitance CIN 5 pF Logic inputs
C
OUT 6 pF Output capacitance
C
INX 27 45 pF Xin and Xout
Operating Supply
Current
Idd3 100 MA CPU = 66.6 MHz
PCI = 33.3 Mhz with
load
Power Down Supply
Current
Idd2 600
µA
Settling Time Ts 3 mS From first crossing to
1% target freq.
Delay tPZH,tPZH 1 10 nS Output enable delay
t
PLZ,tPZH 1 10 nS Output enable delay
W83195BR-25
- 16 -
7.3 Electronical Characteristics of CPU Clock
Vdd=2.5V +/- 5%; CL=10-20pF
PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
Ouput Impedance RDSP 13.5 40 Ohm
Ouput Impedance RDSN 13.5 40 Ohm
Output Low Voltage VOL 0.4 V IOL=1mA
Output High Voltage VOH 2.0 V IOH=-1mA
Output Low Current IOL 27 30 MA
Output High Current IOH -27 -27 MA
Pull-Up Current Min IOH(min) -27 MA Vout = 1.0 V
Pull-Up Current Max IOH(max) -27 MA Vout = 2.0V
Rise/Fall Time Min
Between 0.4 V and 2.0 V
TRF(min) 0.4 ns 10pF Load
Rise/Fall Time Max
Between 0.4 V and 2.0 V
TRF(max) 1.6 ns 20pF Load
Duty Cycle Dt 45 55 % VT=1.25V
Skew TSK 175 ps VT=1.25V
Jitter Tsc-c 250 ps VT=1.25V
7.4 Electronical Characteristics of 3V66 Clock
Vdd=3.3V +/- 5%; CL=10-30pF
PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
Ouput Impedance RDSP 15 55 Ohm
Ouput Impedance RDSN 15 55 Ohm
Output Low Voltage VOL 0.55 V IOL=1mA
Output High Voltage VOH 2.4 V IOH=-1mA
Output Low Current IOL 30 38 MA
Output High Current IOH -33 -33 MA
Rise/Fall Time Min
Between 0.4 V and 2.0 V
TRF(min) 0.4 ns 10pF Load
Rise/Fall Time Max
Between 0.4 V and 2.0 V
TRF(max) 1.6 ns 20pF Load
Duty Cycle Dt 45 55 % VT=1.5V
Skew TSK 175 ps VT=1.5V
Jitter Tsc-c 500 ps VT=1.5V
W83195BR-25
Publication Release Date: May 23, 2005
- 17 - Revision A1
7.5 Electronical Characteristics of SDRAM Clock
Vdd=3.3V +/- 5%; CL=20-30pF
PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
Ouput Impedance RDSP 13.5 40 Ohm
Ouput Impedance RDSN 13.5 40 Ohm
Output Low Voltage VOL 0.45 V IOL=1mA
Output High Voltage VOH 2.4 V IOH=-1mA
Output Low Current IOL 54 54 MA
Output High Current IOH -54 -45 MA
Rise/Fall Time Min
Between 0.4 V and 2.0 V
TRF(min) 0.4 ns 10pF Load
Rise/Fall Time Max
Between 0.4 V and 2.0 V
TRF(max) 1.6 ns 20pF Load
Duty Cycle Dt 45 55 % VT=1.5V
Skew TSK 250 ps VT=1.5V
Jitter Tsc-c 250 ps VT=1.5V
7.6 Electronical Characteristics of PCI Clock
Vdd=3.3V +/- 5%; CL=10-30pF
PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
Ouput Impedance RDSP 15 55 Ohm
Ouput Impedance RDSN 15 55 Ohm
Output Low Voltage VOL 0.55 V IOL=1mA
Output High Voltage VOH 2.4 V IOH=-1mA
Output Low Current IOL 30 38 MA
Output High Current IOH -33 -33 MA
Rise/Fall Time Min
Between 0.4 V and 2.0 V
TRF(min) 0.5 ns 10pF Load
Rise/Fall Time Max
Between 0.4 V and 2.0 V
TRF(max) 2.0 ns 20pF Load
Duty Cycle Dt 45 55 % VT=1.5V
Skew TSK 500 ps VT=1.5V
Jitter Tsc-c 500 ps VT=1.5V
W83195BR-25
- 18 -
7.7 Electronical Characteristics of 48MHz, REF Clock
Vdd=3.3V +/- 5%; CL=10-20pF
PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
Ouput Impedance RDSP 20 55 Ohm
Ouput Impedance RDSN 20 55 Ohm
Output Low Voltage VOL 0.4 V IOL=1mA
Output High Voltage VOH 2.4 V IOH=-1mA
Output Low Current IOL 29 27 MA
Output High Current IOH -29 -23 MA
RiseTime TR 1.8 4 ns 10pF Load
Fall Time TF 1.7 4 ns 20pF Load
Duty Cycle Dt 45 55 % VT=1.5V
Skew TSK 500 ps VT=1.5V
Jitter Tsc-c 1000 ps VT=1.5V
8. ORDERING INFORMATION
PART NUMBER PACKAGE TYPE PRODUCTION FLOW
W83195BR-25 56 PIN SSOP Commercial, 0°C to +70°C
W83195BR-25
Publication Release Date: May 23, 2005
- 19 - Revision A1
9. HOW TO READ THE TOP MARKING
1st line: Winbond logo and the type number: W83195BR-25
2nd line: Tracking code 2 8051234
2: wafers manufactured in Winbond FAB 2
8051234: wafer production series lot number
3rd line: Tracking code 814 G A B
814: packages made in '98, week 14
G: assembly house ID; O means OSE, G means GR
A: Internal use code
B: IC revision
All the trademarks of products and companies mentioned in this data sheet belong to their
respective owners.
10. PACKAGE DRAWING AND DIMENSIONS
E
e
b
Y
SEATING PLANE
c
L
c
L1
0
0.008
0.400
0.292
7.52
0
7.42
8
7.59
10.31
b
E
D
c
18.2
9
10.16
A1
A2
A
10.41
18.54
18.42
2.79
2.34
8
0.2990.296
0.092
0.110
0.410
0.720 0.7300.725
0.406
MIN.
DIMENSION IN INCH
SYMBOL
DIMENSION IN MM
MIN. NOM MAX. MAX.NOM
0.20
e
L
L1
Y
θ
0.008 0.0135
0.005 0.010
0.024 0.032
0.055
0.003
0.20 0.34
0.13 0.25
0.51 0.760.64 0.020 0.0300.025
0.61 0.81
1.40
0.08
H
θ
θ
2.57 0.101
0.095
0.012 0.016
0.088 0.090
0.010
0.040
2.41
0.30 0.41
2.24 2.29
0.25
1.02
W83195BR-25
28051234
814GAB
W83195BR-25
- 20 -
11. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
n.a. All of the versions before 0.50 are for internal
use.
1.0 02/Apr n.a. Change version and version on web site to
1.0
2.0 02/19/2003 All Update new form
A1 May 23, 2005 20 ADD Important Notice
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
Winbond Electronics Corporation America
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
Winbond Electronics (H.K.) Ltd.
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
FAX: 852-27552064
Unit 9-15, 22F, Millennium City,
TEL: 852-27513100
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Winbond Electronics (Shanghai) Ltd.
200336 China
FAX: 86-21-62365998
27F, 2299 Yan An W. Rd. Shanghai,
TEL: 86-21-62365999
Winbond Electronics Corporation Japan
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
FAX: 81-45-4781800
7F Daini-ueno BLDG, 3-7-18
TEL: 81-45-4781881
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
