IRF2907ZS-7PPbF
HEXFET® Power MOSFET
VDSS = 75V
RDS(on) = 3.8mΩ
ID = 160A
07/23/10
www.irf.com 1
HEXFET® is a registered trademark of International Rectifier.
S
D
G
Features
lAdvanced Process Technology
lUltra Low On-Resistance
l175°C Operating Temperature
lFast Switching
lRepetitive Avalanche Allowed up to Tjmax
S (Pin 2, 3, 5, 6, 7)
G (Pin 1)
Absolute Maximum Ratings
Parameter Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) A
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (See Fig. 9)
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited)
IDM Pulsed Drain Current
c
PD @TC = 25°C Maximum Power Dissipation W
Linear Derating Factor W/°C
VGS Gate-to-Source Voltage V
EAS Single Pulse Avalanche Energy (Thermally Limited)
d
mJ
EAS (tested) Single Pulse Avalanche Energy Tested Value
h
IAR Avalanche Current
c
A
EAR Repetitive Avalanche Energy
g
mJ
TJ Operating Junction and °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case
j
––– 0.50 °C/W
RθCS Case-to-Sink, Flat, Greased Surface 0.50 –––
RθJA Junction-to-Ambient
j
––– 62
RθJA Junction-to-Ambient (PCB Mount, steady state)
ij
––– 40
Max.
180
120
700
160
10 lbf•in (1.1N•m)
300
2.0
± 20
160
410
See Fig.12a,12b,15,16
300 (1.6mm from case )
-55 to + 175
Description
This HEXFET® Power MOSFET utilizes the latest
processing techniques and advanced packaging
technology to achieve extremely low on-resistance
and world -class current ratings. Additional features
of this design are a 175°C junction operating tem-
perature, fast switching speed and improved repeti-
tive avalanche rating . These features combine to
make this design an extremely efficient and reliable
device for use in Server & Telecom OR'ing and low
voltage Motor Drive Applications.
PD - 97031D
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Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C,
L=0.026mH, RG = 25Ω, IAS = 110A, VGS =10V.
Part not recommended for use above this value.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same
charging time as Coss while VDS is rising from 0 to 80%
VDSS.
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
This value determined from sample failure population. 100%
tested to this value in production.
This is applied to D2Pak, when mounted on 1" square PCB
( FR-4 or G-10 Material ). For recommended footprint and
soldering techniques refer to application note #AN-994.
Rθ is measured at TJ of approximately 90°C.
S
D
G
S
D
G
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. T
y
p. Max. Units
V(BR)DSS Drain-to-Source Breakdown Volta
g
e75––––––V
∆ΒVDSS
/
∆TJ Breakdown Volta
g
e Temp. Coefficient ––– 0.066 ––– V/°C
RDS(on) SMD Static Drain-to-Source On-Resistance ––– 3.0 3.8 mΩ
VGS(th) Gate Threshold Volta
g
e 2.0 ––– 4.0 V
g
fs Forward Transconductance 94 ––– ––– S
IDSS Drain-to-Source Leaka
g
e Current ––– ––– 20
A
––– ––– 250
IGSS Gate-to-Source Forward Leaka
g
e ––– ––– 200 nA
Gate-to-Source Reverse Leaka
g
e ––– ––– -200
QgTotal Gate Char
g
e ––– 170 260 nC
Qgs Gate-to-Source Char
g
e ––– 55 –––
Qgd Gate-to-Drain ("Miller") Char
g
e ––– 66 –––
td(on) Turn-On Dela
y
Time ––– 21 ––– ns
trRise Time ––– 90 –––
td(off) Turn-Off Dela
y
Time ––– 92 –––
tfFall Time ––– 44 –––
LDInternal Drain Inductance ––– 4.5 ––– nH Between lead,
6mm (0.25in.)
LSInternal Source Inductance ––– 7.5 ––– from packa
g
e
and center of die contact
Ciss Input Capacitance ––– 7580 ––– pF
Coss Output Capacitance ––– 970 –––
Crss Reverse Transfer Capacitance ––– 540 –––
Coss Output Capacitance ––– 3750 –––
Coss Output Capacitance ––– 650 –––
Coss eff. Effective Output Capacitance ––– 1110 –––
Diode Characteristics
Parameter Min. T
y
p. Max. Units
ISContinuous Source Current ––– ––– 160
(Body Diode) A
ISM Pulsed Source Current ––– ––– 700
(Body Diode)
c
VSD Diode Forward Voltage ––– ––– 1.3 V
trr Reverse Recovery Time –––3553ns
Qrr Reverse Recover
y
Char
g
e ––– 40 60 nC
VDS = VGS, ID = 250µA
VDS = 75V, VGS = 0V
VDS = 75V, VGS = 0V, TJ = 125°C
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 110A
e
TJ = 25°C, IF = 110A, VDD = 38V
di/dt = 100A/
µ
s
e
TJ = 25°C, IS = 110A, VGS = 0V
e
showing the
integral reverse
p-n junction diode.
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 10V
d
MOSFET symbol
VGS = 0V
VDS = 25V
VGS = 0V, VDS = 60V, ƒ = 1.0MHz
Conditions
VGS = 0V, VDS = 0V to 60V
ƒ = 1.0MHz, See Fig. 5
RG = 2.6Ω
ID = 110A
VDS = 25V, ID = 110A
VDD = 38V
ID = 110A
VGS = 20V
VGS = -20V
VDS = 60V
VGS = 10V
e
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Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance
vs. Drain Current
0.1 110 100 1000
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
≤60µs PULSE WIDTH
Tj = 25°C
4.5V
0.1 110 100 1000
VDS, Drain-to-Source Voltage (V)
10
100
1000
ID, Drain-to-Source Current (A)
4.5V
≤60µs PULSE WIDTH
Tj = 175°C
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
1 2 3 4 5 6 7 8
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (Α)
TJ = 25°C
TJ = 175°C
VDS = 25V
≤60µs PULSE WIDTH
0 25 50 75 100 125 150
ID,Drain-to-Source Current (A)
0
50
100
150
200
Gfs, Forward Transconductance (S)
TJ = 25°C
TJ = 175°C
VDS = 10V
380µs PULSE WIDTH
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
110 100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
100000
C, Capacitance(pF)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0 50 100 150 200
QG Total Gate Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
VGS, Gate-to-Source Voltage (V)
VDS= 60V
VDS= 38V
VDS= 15V
ID= 110A
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VSD, Source-to-Drain Voltage (V)
0.1
1
10
100
1000
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
0.1 1.0 10.0 100.0
VDS, Drain-toSource Voltage (V)
0.1
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
DC
LIMITED BY PACKAGE
IRF2907ZS-7PPbF
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Normalized On-Resistance
vs. Temperature
-60 -40 -20 020 40 60 80 100120140160180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
2.5
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 180A
VGS = 10V
25 50 75 100 125 150 175
TC , Case Temperature (°C)
0
40
80
120
160
200
ID, Drain Current (A)
Limited By Package
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
0.0001
0.001
0.01
0.1
1
Thermal Response ( Z thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W) τi (sec)
0.1072 0.000096
0.2787 0.002614
0.1143 0.013847
τJ
τJ
τ1
τ1
τ2
τ2τ3
τ3
R1
R1R2
R2R3
R3
τ
τC
Ci i/Ri
Ci= τi/Ri
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QG
QGS QGD
VG
Charge
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 14. Threshold Voltage vs. Temperature
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
100
200
300
400
500
600
700
EAS , Single Pulse Avalanche Energy (mJ)
ID
TOP 24A
34A
BOTTOM 110A
-75 -50 -25 025 50 75 100 125 150 175 200
TJ , Temperature ( °C )
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VGS(th) Gate threshold Voltage (V)
ID = 250µA
ID = 1.0mA
ID = 1.0A
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Fig 15. Typical Avalanche Current vs.Pulsewidth
Fig 16. Maximum Avalanche Energy
vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
1
10
100
1000
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses
0.01
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
50
100
150
200
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 1% Duty Cycle
ID = 110A
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Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P. W .
Period
* V
GS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
VDS
90%
10%
VGS
t
d(on)
t
r
t
d(off)
t
f
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
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D2Pak - 7 Pin Package Outline
Dimensions are shown in millimeters (inches)
D2Pak - 7 Pin Part Marking Information
14
Notes:
1. For an Automotive Qualified version of this part please see http://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
IRF2907ZS-7PPbF
10 www.irf.com
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IRs Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 07/2010
D2Pak - 7 Pin Tape and Reel