CY7C1021DV33
1-Mbit (64 K × 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-05460 Rev. *H Revised November 24, 2014
1-Mbit (64 K × 16) Static RAM
Features
■Temperature ranges
❐Industrial: –40 °C to 85 °C
❐Automotive-A: –40 °C to 85 °C
■Pin-and function-compatible with CY7C1021CV33
■High speed
❐tAA = 10 ns
■Low active power
❐ICC = 60 mA @ 10 ns
■Low CMOS standby power
❐ISB2 = 3 mA
■2.0 V data retention
■Automatic power-down when deselected
■CMOS for optimum speed/power
■Independent control of upper and low er bits
■Available in Pb-free 44-pin 400-Mil wide molded SOJ, 44-pin
TSOP II and 48-ball VFBGA packages
Functional Description
The CY7C1021DV33 is a high-perfo rmance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
automatic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW . If Byte Low Enable (BLE) is
LOW, then data from I/O pins (I/O0 through I/O7), is written into
the location specified on the address pins (A0 through A15). If
Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8
through I/O15) is written into the location specified on the address
pins (A0 through A15).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW , then data
from the memory location specified by the address pins will
appear on I/O0 to I/O7. If Byte High Enab le (BHE) is LOW, then
data from memory will appear on I/O8 to I/O15. See the truth table
at the end of this data sheet for a complete descripti on of Read
and Write modes.
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a Write operation (CE
LOW, and WE LOW).
The CY7C1021DV33 is available in Pb-free 44-pin 400-Mil wide
Molded SOJ, 44-pin TSOP II and 48-ball VFBGA packages.
For a complete list of related resources, click here.
64K x 16
RAM Array I/O
0
–I/O
7
ROW DECODER
A
7
A
6
A
5
A
4
A
3
A
0
COLUMN DECODER
A
9
A
10
A
11
A
12
A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
2
A
1
I/O
8
–I/O
15
CE
WE
BLE
BHE
A
8
Logic Block Diagram
CY7C1021DV33
Document Number: 38-05460 Rev. *H Page 2 of 18
Contents
Selection Guide ................................................................3
Pin Configurations ...........................................................3
Maximum Ratings .............................................................4
Operating Range ..................... .. ........................................4
Electrical Characteristics .................................................4
DC Electrical Characteristics .......................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics .......................................6
Data Retention Waveform ................................................6
Switching Characteristics .................... .. ..........................7
Switching Waveforms .............. .......................... .. ... .........8
Truth Table ......................................................................1 1
Ordering Information ......................................................12
Ordering Code Definitions .........................................12
Package Diagrams ..........................................................13
Acronyms ........................................................................15
Document Conventions .................................................15
Units of Measure ............. ............................ ..............15
Document History Page ............... ..................................16
Sales, Solutions, and Legal Information ......................18
Worldwide Sales and Design Support .......................18
Products .................................................................... 18
PSoC® Solutions ......................................................18
Cypress Developer Community ...................... ... ........18
Technical Support .....................................................18
CY7C1021DV33
Document Number: 38-05460 Rev. *H Page 3 of 18
Selection Guide
Description -10 (Industrial /
Automotive-A) Unit
Maximum access time 10 ns
Maximum operating current 60 mA
Maximum CMOS standby current 3mA
Pin Configurations
SOJ, TSOP II and VFBGA pinouts are as follows. [1]
WE
VCC
A11
A10
NC
A6
A0
A3CE
I/O
10
I/O8
I/O9
A4
A5
I/O
11
I/O13
I/O12
I/O14
I/O15
VSS
A9
A8
OE
VSS
A7
I/O0
BHE
NC
A2
A1
BLE
VCC
I/O1
I/O2
I/O3
I/O4
I/O5I/O6
I/O7
A15
A14
A13
A12
NC
NC NC
3
26
5
4
1
D
E
B
A
C
F
G
H
NC
NC
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15 29
30
A
5
18
17
20
19 27
28
25
26
22
21 23
24
48-ball VFBGA
SOJ/TSOP II
Top View Top View
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
14
A
15
A
8
A
9
A
10
A
11
A
12
A
13
NC NC
OE
BHE
BLE
CE
WE
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
V
CC
V
SS
V
SS
NC
10
Note
1. NC pins are not connected on the die.
CY7C1021DV33
Document Number: 38-05460 Rev. *H Page 4 of 18
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature with
power applied ..........................................–55 C to +125 C
Supply voltage on
VCC to Relative GND [2] ...............................–0.3 V to +4.6 V
DC Voltage applied to outputs
in high Z St ate [2] ................................–0.3 V to VCC + 0.3 V
DC input voltage [2] .............................–0.3 V to VCC + 0.3 V
Current into outputs (LOW) ........................................20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) ..........................> 2001 V
Latch-up current ....................................................> 200 mA
Operating Range
Range Ambient
Temperature VCC Speed
Industrial –40 °C to +85 °C 3.3 V 0.3 V 10 ns
Automotive-A –40 °C to +85 °C 10 ns
Electrical Characteristics
Over the Operating Range
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions -10 (Industrial /
Automotive-A) Unit
Min Max
VOH Output HIGH voltage VCC = Min, IOH = –4.0 mA 2.4 – V
VOL Output LOW voltage VCC = Min, IOL = 8.0 mA – 0.4 V
VIH Input HIGH voltage 2.0 VCC + 0.3 V
VIL Input LOW voltage [2] 0.3 0.8 V
IIX Input leakage current GND < VI < VCC 1+1A
IOZ Output leakage current GND < VI < VCC, Output Disabled 1+1A
ICC VCC operating supply current VCC = Max, IOUT = 0 mA,
f = fMAX = 1/tRC 100 MHz – 60 mA
83 MHz – 55 mA
66 MHz – 45 mA
40 MHz – 30 mA
ISB1 Automatic CE Power-Down
Current – TTL Inputs Max VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX –10mA
ISB2 Automatic CE Power-Down
Current – CMOS Inputs Max VCC, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V, f = 0 –3mA
Note
2. VIL(min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns.
CY7C1021DV33
Document Number: 38-05460 Rev. *H Page 5 of 18
Capacitance
Parameter [3] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VCC = 3.3 V 8 pF
COUT Output capacitance 8pF
Thermal Resist ance
Parameter [3] Description Test Conditions SOJ TSOP II VFBGA Unit
JA Thermal resistance
(junction to ambient) Still Air , soldered on a 3 × 4.5
inch, four-layer printed circuit
board
59.52 53.91 36 C/W
JC Thermal resistance
(junction to case) 36.75 21.24 9 C/W
AC Test Loads and Waveforms
Figure 1. AC Test Loads and Waveforms [4]
90%
10%
3.0 V
GND
90%
10%
ALL INPUT PULSES
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT Rise Time: 1 V/ns Fall Time: 1 V/ns
30 pF*
OUTPUT
Z = 50
50
1.5 V
(b)
(a)
3.3 V
OUTPUT
5 pF
(c)
R 317
R2
351
High-Z characteristics:
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High Z) are tested using the load conditions shown in Figure 1 (a). High Z characteristics are tested for all speeds using the test load
shown in Figure 1 (c).
CY7C1021DV33
Document Number: 38-05460 Rev. *H Page 6 of 18
Data Retention Characteristics
Over the Operating R ange
Parameter Description Conditions Min Max Unit
VDR VCC for dat a retention 2 – V
ICCDR Data retention current VCC = VDR = 2.0 V, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V Industrial –3mA
tCDR[5] Chip deselect to data retention
time 0–ns
tR[6] Operation recovery time tRC –ns
Data Retention Waveform Figure 2. Data Retention Waveform
Notes
5. Tested initially and after any design or process changes that may affect these parameters.
6. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s.
CY7C1021DV33
Document Number: 38-05460 Rev. *H Page 7 of 18
Switching Characteristics
Over the Operating Range
Parameter [7] Description -10 (Industrial /
Automotive-A) Unit
Min Max
Read Cycle
tpower[8] VCC(typical) to the first access 100 – s
tRC Read cycle time 10 – ns
tAA Address to data valid – 10 ns
tOHA Data hold from address change 3 – ns
tACE CE LOW to data valid – 10 ns
tDOE OE LOW to data valid – 5 ns
tLZOE OE LOW to low Z [9] 0–ns
tHZOE OE HIGH to high Z [9, 10] –5ns
tLZCE CE LOW to low Z [9] 3–ns
tHZCE CE HIGH to high Z [9, 10] –5ns
tPU[11] CE LOW to power-up 0 – ns
tPD[11] CE HIGH to power-down – 10 ns
tDBE Byte Enable to data valid – 5 ns
tLZBE Byte Enable to low Z 0 – ns
tHZBE Byte Disable to high Z – 6 ns
Write Cycle [12, 13]
tWC Write cycle time 10 – ns
tSCE CE LOW to write end 8 – ns
tAW Address set-up to write end 8 – ns
tHA Address hold from write end 0 – ns
tSA Address set-up to write start 0 – ns
tPWE WE pulse width 7–ns
tSD Data set-up to write end 5 – ns
tHD Data hold from write end 0 – ns
tLZWE WE HIGH to low Z [9] 3–ns
tHZWE WE LOW to high Z [9, 10] –5ns
tBW Byte enable to end of write 7 – ns
Notes
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V.
8. tPOWER gives the minimum amount of time that the powe r supply should be at ty pical VCC values until the first memory access can be performed.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and t HZWE is less than tLZWE for any given device.
10.tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (c) of Figure 1 on page 5. Transition is measured when the outputs enter a high impedance state.
11. This parameter is guarant eed by design and is not tested.
12.The internal W rite time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW . C E, WE and BHE/BLE must be LOW to initiate a Write and
the transition of these signals can terminate the Write. The input data set-up and hold timing should be ref erenced to the leading edge of the signal that terminates
the Write.
13.The minimum write pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to the sum of tSD and t HZWE.
CY7C1021DV33
Document Number: 38-05460 Rev. *H Page 8 of 18
Switching Waveforms
Figure 3. Read Cycle No. 1 (Address Transitio n Con t rolled) [14, 15]
Figure 4. Read Cycle No. 2 (OE Controlled) [15, 16]
PREVIOUS DATA VALID DATA VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZBE
tPD
tDBE
tLZBE
tHZCE
HIGH
IMPEDANCE
ICC
ISB
OE
CE
ADDRESS
DATA OUT
VCC
SUPPLY
BHE,BLE
CURRENT
Notes
14.Device is continuously selected. OE, CE, BHE and/or BLE = VIL.
15.WE is HIGH for Read cycle.
16.Address valid prior to or coincident with CE transition LOW .
CY7C1021DV33
Document Number: 38-05460 Rev. *H Page 9 of 18
Figure 5. Write Cycle No. 1 (CE Controlled) [17, 18]
Figure 6. Write Cycle No. 2 (BLE or BHE Controlled)
Switching Waveforms (continued)
tHD
tSD
tSCE
tSA
tHA
tAW
tPWE
tWC
BW
t
DATA I/O
ADDRESS
CE
WE
BHE,BLE
DATA IN VALID
tHD
tSD
tBW
tSA
tHA
tAW
tPWE
tWC
tSCE
DATA I/O
ADDRESS
BHE,BLE
CE
WE
DATA IN VALID
Notes
17.Data I/O is high impedance if OE or BHE and/or BLE = VIH.
18.If C E goes HIGH simultaneously with W E going HIGH, the output remains in a high-impedance state.
CY7C1021DV33
Document Number: 38-05460 Rev. *H Page 10 of 18
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [19]
Switching Waveforms (continued)
tHD
tSD
tSCE
tHA
tAW
tPWE
tWC
tBW
tSA
tLZWE
tHZWE
DATA I/O
ADDRESS
CE
WE
BHE,BLE
DATA IN VALID
Note
19.The minimum write pulse width should be equal to t he sum of tSD and tHZWE.
CY7C1021DV33
Document Number: 38-05460 Rev. *H Page 11 of 18
Truth Table
CE OE WE BLE BHE I/O0–I/O7I/O8–I/O15 Mode Power
H X X X X High-Z High-Z Power-down Standby (ISB)
L L H L L Data Out Data Out Read – All bits Active (ICC)
L H Data Out High-Z Read – Lower bits only Active (ICC)
H L High-Z Data Out Read – Upper bits only Active (ICC)
L X L L L Data In Data In Write – All bits Active (ICC)
L H Data In High-Z Write – Lower bits only Active (ICC)
H L High-Z Data In Write – Upper bits only Active (ICC)
L H H X X High-Z High-Z Selected, outputs disabled Active (ICC)
L X X H H High-Z High-Z Selected, outputs disabled Active (ICC)
CY7C1021DV33
Document Number: 38-05460 Rev. *H Page 12 of 18
Ordering Code Definitions
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
10 CY7C1021DV33-10VXI 51-85082 44-pin (400-Mil) Molded SOJ (Pb-free) Industrial
CY7C1021DV33-10ZSXI 51-85087 44-pin TSOP Type II (Pb-free)
CY7C1021DV33-10BVXI 51-85150 48-ball VFBGA (Pb-free)
10 CY7C1021DV33-10ZSXA 51-85087 44-pin TSOP Type II (Pb-free) Automotive-A
Please contact your local Cypress sales representative for availability of these parts.
Temperature Range: X = I or A or E
I = Industrial; A = Automotive-A; E = Automotive-E
Pb-free
Package Type: XX = V or ZS or BV
V = 44-pin Molded SOJ
ZS = 44-pin TSOP Type II
BV = 48-ball VFBGA
Speed: XX = 10 ns or 12 ns
V33 = Voltage range (3 V to 3.6 V)
D = C9, 90 nm Technol og y
1 = Data width × 16-bits
02 = 1-Mbit density
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
CCY 1 - XX X702 V33 XD1 XX
CY7C1021DV33
Document Number: 38-05460 Rev. *H Page 13 of 18
Package Diagrams Figure 8. 44-pin SOJ (400 Mils) V44.4 Packa ge Outline, 51-85082
Figure 9. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85082 *E
51-85087 *E
CY7C1021DV33
Document Number: 38-05460 Rev. *H Page 14 of 18
Figure 10. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
Package Diagrams (continued)
51-85150 *H
CY7C1021DV33
Document Number: 38-05460 Rev. *H Page 15 of 18
Acronyms Document Conventions
Units of Measure
Acronym Description
BHE Byte High Enable
BLE Byte Low Enable
CMOS Complementary Metal Oxide Semiconductor
CE Chip Enable
I/O Input/Output
OE Output Enable
SOJ Small-Outline J-leaded
SRAM Static Random Access Memory
TSOP Thin Small-Outline Package
TTL Transistor-Transistor Logic
VFBGA Very Fine-Pitch Ball Grid Array
WE Write Enable
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
µA microampere
µs microsecond
mA milliampere
ns nanosecond
% percent
pF picofarad
Vvolt
Wwatt
CY7C1021DV33
Document Number: 38-05460 Rev. *H Page 16 of 18
Document History Page
Document Title: CY7C1021DV33, 1-Mbit (64 K × 16) Static RAM
Document Number: 38-05460
Rev. ECN No. Issue Date Orig. of
Change Description of Change
** 201560 See ECN SWI Advance Information data sheet for C9 IPP.
*A 233693 See ECN RKF Upda ted Electrical Characteristics (modified as per Eros (Spec # 01-02165)).
Updated Ordering Information (included Pb-free offering).
*B 263769 See ECN RKF Upda ted Functional Description (Changed I/O1–I/O16 to I/O0–I/O15).
Updated Pin Configurations (Changed I/O1–I/O16 to I/O0–I/O15).
Added Data Retention Characteristics and Data Retention Waveform.
Updated Switching Characteristics (Added Tpower p arameter and its details).
Updated Ordering Information (Added shade, no change in part numbers).
*C 307601 See ECN RKF Upda ted Selection Guide (Reduced S peed bins to -8 and -10 ns (Removed -12
and -15 speed bins related information)).
Updated Electrical Chara c teristics (Reduced Speed bins to -8 and -10 ns
(Removed -12 and -15 speed bins related information)).
Updated Switching Characteristics (Reduced Speed bins to -8 and -10 ns
(Removed -12 and -15 speed bins related information)).
Updated Ordering Information (Updated part numbers).
*D 520652 See ECN VKN Changed status from Preliminary to Final.
Updated Features (Removed Commercial Operating range related information
and included Automotive-A, Automotive-E Operating range related
information).
Updated Selection Guide (Removed -8 speed bin related information and
incldued -12 speed bin related information).
Updated Oper ating Range (Removed Commercial Operating range related
information and included Automotive-A, Automotive-E Operating range related
information).
Updated Electrical Chara c teristics (Updated DC Electrical Charac teristics
(Removed -8 speed bin related information and included -12 speed bin related
information, removed Commercial Operating range related information and
included Automotive-A, Automotive-E Operating range related information),
Updated Note 2 (Chang ed VIH(max) from VCC + 2 V to VCC + 1 V), added ICC
parameter values for the frequencies 83 MHz, 66 MHz and 40 MHz).
Updated Thermal Resistance (Replaced TBD with values for all packages).
Updated Switching Characteristics (Removed -8 speed bin related information
and included -12 speed bin related information, removed Commercial
Operating range related information and included Automotive-A, Automotive-E
Operating range related information).
Updated Data Retention Characteristics (Removed Commercial Operating
range related information and included Automotive-A, Automotive-E Operating
range related information).
Updated Ordering Information (Updated part numbers).
*E 2898399 03/24/2010 AJU Updated Package Diagrams.
*F 3109897 12/14/2010 AJU Added Ordering Code Definitions.
Updated Package Diagrams.
CY7C1021DV33
Document Number: 38-05460 Rev. *H Page 17 of 18
*G 3421856 10/25/2011 TAVA Updated Features (Removed Automotive-E Operating range related
information).
Updated Selection Guide (Removed Automotive-E Operating range related
information, removed -12 speed bin related in formation).
Updated Oper ating Range (Removed Automoti ve-E Operating range related
information, removed -12 speed bin related in formation).
Updated Electrical Chara c teristics (Updated DC Electrical Charac teristics
(Removed Automotive-E Operating range related information, removed -12
speed bin related information)).
Updated Switching Characteristics (Removed Automotive-E Operating range
related information, remo ved -12 speed bin related information).
Updated Data Retention Characteristics (Removed Automotive-E Operating
range related information).
Updated Switching Waveforms.
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams.
Updated to new te mplate.
*H 4578364 11/24/2014 MEMJ Updated Functional Description:
Added “For a complete list of related resources, click here.” at the end.
Updated Switching Characteristics:
Added Note 13 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 19 and referred the same note in Figure 7.
Updated Ordering Information (Removed shade, no change in part numbers).
Updated Package Diagrams:
spec 51-85082 – Changed revision from *D to *E.
spec 51-85087 – Changed revision from *D to *E.
spec 51-85150 – Changed revision from *G to *H.
Added Acronyms and Units of Measure.
Updated to new te mplate.
Completing Sunset Review.
Document History Page (continued)
Document Title: CY7C1021DV33, 1-Mbit (64 K × 16) Static RAM
Document Number: 38-05460
Rev. ECN No. Issue Date Orig. of
Change Description of Change
Document Number: 38-05460 Rev. *H Revised November 24, 2014 Page 18 of 18
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C1021DV33
© Cypress Semicondu ctor Corpor ation, 2004-2014. The informatio n contai ned herei n is subject to chan ge without no tice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress pro d ucts ar e not war ran t ed no r int e nded to be used fo r
medical, life supp or t, l if e savin g, cr it ical control or safety applicatio ns, unl ess pu r suant to an express written agreemen t w it h Cypr ess. Fu rth er mor e, Cypre ss does not auth or iz e it s pr o ducts for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all cha rges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent prot ection (Un ited States and foreign),
United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of lice nsee product to be used on ly in conjunction wit h a Cypress
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the express written permiss i on of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY A ND FITNESS FOR A PARTICULAR PURPOSE. Cy press reserves the right to make changes without further notice to the materials des cribed herei n. Cypress doe s not
assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and i n doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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