1
FEATURES
APPLICATIONS
DESCRIPTION/ORDERING INFORMATION
Typical Application Circuit
TPS737xx
GNDEN FB
IN OUT
VIN VOUT
Optional
1.0 µF
OFF ON
IN
NC
NC
EN
8
7
6
5
OUT
NC
NR/FB
GND
1
2
3
4
DRB PACKAGE
(TOP VIEW)
NC – No internal connection
TPS73719-Q1
TPS73733-Q1
www.ti.com
........................................................................................................................................................................................... SBVS123 – DECEMBER 2008
1-A LOW-DROPOUT REGULATORWITH REVERSE CURRENT PROTECTION
2
•Qualified for Automotive Applications •Thermal Shutdown and Current Limit for FaultProtection•Stable with 1.0- µF or Larger Ceramic OutputCapacitor •Available in Multiple Output Voltage Versions•Input Voltage Range: 2.2 V to 5.5 V – Adjustable Output: 1.20 V to 5.5 V•Ultra-Low Dropout Voltage: 130 mV typ at 1 A – Custom Outputs Available Using FactoryPackage-Level Programming•Excellent Load Transient Response, Even WithOnly 1.0- µF Output Capacitor•NMOS Topology Delivers Low Reverse
•Point of Load Regulation for DSPs, FPGAs,Leakage Current
ASICs, and Microprocessors•1.0% Initial Accuracy
•Post-Regulation for Switching Supplies•3% Overall Accuracy Over Line, Load, and
•Portable/Battery-Powered EquipmentTemperature
•Less Than 20-nA (Typ) Quiescent Current inShutdown Mode
The TPS737xx family of linear low-dropout (LDO) voltage regulators uses an NMOS pass element in avoltage-follower configuration. This topology is relatively insensitive to output capacitor value and ESR, allowinga wide variety of load configurations. Load transient response is excellent, even with a small 1.0- µF ceramicoutput capacitor. The NMOS topology also allows very low dropout.
The TPS737xx family uses an advanced BiCMOS process to yield high precision while delivering very lowdropout voltages and low ground pin current. Current consumption, when not enabled, is under 20 nA and idealfor portable applications. These devices are protected by thermal shutdown and foldback current limit.
ORDERING INFORMATION
(1)
T
A
V
OUT
(TYP) PACKAGE
(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
3.3 V TPS73733QDRBRQ1 733Q– 40 ° C to 125 ° C 1.9 V SON – DRB Reel of 3000 TPS73719QDRBRQ1 719QAdjustable TPS73701QDRBRQ1 PREVIEW
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
Copyright © 2008, Texas Instruments IncorporatedPRODUCTION DATA information current as of publication date.Products conform to specifications per the terms of TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
(1)
TPS73719-Q1
TPS73733-Q1
SBVS123 – DECEMBER 2008 ...........................................................................................................................................................................................
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
over operating free-air temperature range unless otherwise noted
(1)
V
IN
range – 0.3 V to 6.0 VV
EN
range – 0.3 V to 6.0 VV
OUT
range – 0.3 V to 5.5 VV
NR
, V
FB
range – 0.3 V to 6.0 VPeak output current Internally limitedOutput short-circuit duration IndefiniteContinuous total power dissipation See Dissipation Ratings TableJunction temperature range, T
J
– 55 ° C to 150 ° CStorage temperature range – 65 ° C to 150 ° CESD rating, HBM 2000 VESD rating, CDM 500 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristicsis not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
DERATING FACTOR T
A
≤25 ° C T
A
= 70 ° C T
A
= 85 ° CBOARD PACKAGE R
θJC
R
θJA
ABOVE T
A
= 25 ° C POWER RATING POWER RATING POWER RATING
High-K
(2) (3)
DRB 1.2 ° C/W 40 ° C/W 25.0 mW/ ° C 2.50 W 1.38 W 1.0 W
(1) See Power Dissipation in the Applications section for more information related to thermal design.(2) The JEDEC High-K (2s2p) board design used to derive this data was a 3-inch x 3-inch, multilayer board with 1-ounce internal power andground planes and 2-ounce copper traces on the top and bottom of the board.(3) Based on preliminary thermal simulations.
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ELECTRICAL CHARACTERISTICS
TPS73719-Q1
TPS73733-Q1
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........................................................................................................................................................................................... SBVS123 – DECEMBER 2008
over operating temperature range (T
J
= – 40 ° C to 125 ° C), V
IN
= (V
OUT(nom)
+ 1.0 V)
(1)
, I
OUT
= 10 mA, V
EN
= 2.2 V, C
OUT
= 2.2 µF(unless otherwise noted). Typical values are at T
J
= 25 ° C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IN
Input voltage range
(1), (2)
2.2 5.5 VV
FB
Internal reference (TPS73701) T
J
= 25 ° C 1.192 1.2 1.216 VOutput voltage range (TPS73701)
(3)
V
FB
5.5 – V
DO
VNominal T
J
= 25 ° C – 1.0 +1.05.36 V < V
IN
< 5.5 V, V
OUT
= 5.08 V,10 mA < I
OUT
< 800 mA, – 2.0 +2.0V
OUT
Accuracy
(1), (4)
– 40 ° C < T
J
< 85 ° C, TPS73701 %Over V
IN
,
V
OUT
+ 0.5 V ≤V
IN
≤5.5 V,I
OUT
, and – 3.0 ± 0.5 +3.010 mA ≤I
OUT
≤1 Atemperature
ΔV
OUT
%/
Line regulation
(1)
V
OUT(nom)
+ 0.5 V ≤V
IN
≤5.5 V 0.01 %/VΔV
IN
1 mA ≤I
OUT
≤1 A 0.002ΔV
OUT
%/
Load regulation %/mAΔI
OUT
10 mA ≤I
OUT
≤1 A 0.0005Dropout voltage
(5)V
DO
I
OUT
= 1 A 130 500 mV(V
IN
= V
OUT(nom)
– 0.1 V)Z
O
(DO) Output impedance in dropout 2.2 V ≤V
IN
≤V
OUT
+ V
DO
0.25 Ω
I
CL
Output current limit V
OUT
= 0.9 × V
OUT(nom)
1.05 1.6 2.2 AI
SC
Short-circuit current V
OUT
= 0 V 450 mAI
REV
Reverse leakage current
(6)
( – I
IN
) V
EN
≤0.5 V, 0 V ≤V
IN
≤V
OUT
0.1 µAI
OUT
= 10 mA (I
Q
) 400I
GND
GND pin current µAI
OUT
= 1 A 1300I
SHDN
Shutdown current (I
GND
) V
EN
≤0.5 V, V
OUT
≤V
IN
≤5.5 V 20 nAI
FB
FB pin current (TPS73701) 0.1 0.6 µAf = 100 Hz, I
OUT
= 1 A 58Power-supply rejection ratio (ripplePSRR dBrejection)
f = 10 kHz, I
OUT
= 1 A 37Output noise voltageV
N
C
OUT
= 10 µF 27 × V
OUT
µV
RMSBW = 10 Hz to 100 kHzt
STR
Startup time V
OUT
= 3 V, R
L
= 30 Ω, C
OUT
= 1 µF 600 µsV
EN(HI)
EN pin high (enabled) 1.7 V
IN
VV
EN(LO)
EN pin low (shutdown) 0 0.5 VI
EN(HI)
EN pin current (enabled) V
EN
= 5.5 V 20 nAShutdown, temperature increasing 160T
SD
Thermal shutdown temperature ° CReset, temperature decreasing 140T
J
Operating junction temperature – 40 125 ° C
(1) Minimum V
IN
= V
OUT
+ V
DO
or 2.2V, whichever is greater.(2) For V
OUT(nom)
< 1.6 V, when V
IN
≤1.6 V, the output will lock to V
IN
and may result in an overvoltage condition on the output. To avoidthis situation, disable the device before powering down V
IN
.(3) TPS73701 is tested at V
OUT
= 1.2 V.(4) Tolerance of external resistors not included in this specification.(5) V
DO
is not measured for fixed output versions with V
OUT(nom)
< 2.3 V, because minimum V
IN
= 2.2 V.(6) Fixed-voltage versions only; see the Applications section for more information.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
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FUNCTIONAL BLOCK DIAGRAMS
Servo
Error
Amp
Ref
27 kW
8 kW
Current
Limit
Thermal
Protection
Bandgap
NR
OUT
R1
R2
EN
GND
IN
R1+ R2= 80 kW
4-MHz
Charge Pump
VO
1.2 V
1.5 V
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
R1
Short
23.2 kW
28.0 kW
39.2 kW
44.2 kW
46.4 kW
52.3 kW
R2
Open
95.3 kW
56.2 kW
36.5 kW
33.2 kW
30.9 kW
30.1 kW
Standard 1% Resistor Values for
Common Output Voltages
NOTE: VOUT = (R1+ R2)/R2× 1.204;
R || R
1 2 ≅19 kWfor best accuracy.
Servo
Error
Amp
Ref
Current
Limit
Thermal
Protection
Bandgap
OUT
FB
R1
R2
EN
GND
IN
80 kW
8 kW
27 kW
4-MHz
Charge Pump
TPS73719-Q1
TPS73733-Q1
SBVS123 – DECEMBER 2008 ...........................................................................................................................................................................................
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Figure 1. Fixed Voltage Version
Figure 2. Adjustable Voltage Version
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IN
NC
NC
EN
8
7
6
5
OUT
NC
NR/FB
GND
1
2
3
4
DRB PACKAGE
3mm x 3mm SON
(TOP VIEW)
NC – No internal connection
TPS73719-Q1
TPS73733-Q1
www.ti.com
........................................................................................................................................................................................... SBVS123 – DECEMBER 2008
Table 1. Terminal Functions
TERMINAL
DESCRIPTIONNAME NO.
IN 8 Unregulated input supplyGND 4, Pad Ground
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdownEN 5 mode. Refer to the Shutdown section under Applications Information for more details. EN must not be leftfloating and can be connected to IN if not used.Fixed voltage versions only. Connecting an external capacitor to this pin bypasses noise generated by theNR 3
internal bandgap, reducing output noise to very low levels.Adjustable voltage version only. This is the input to the control loop error amplifier, and it is used to set theFB 3
output voltage of the device.OUT 1 Regulator output. A 1.0- µF or larger capacitor of any type is required for stability.NC 2, 6, 7 No internal connection
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TYPICAL CHARACTERISTICS
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
ChangeinV (%)
OUT
0 100 200 300 400 500 600 700 800 900 1000
I (mA)
OUT
ReferredtoI =10mA
OUT
-40 C°
+125 C°
+25 C°
0.20
0.15
0.10
0.05
0
-0.05
-0.10
-0.15
-0.20
ChangeinV (%)
OUT
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V V-(V)
IN OUT
+125 C°+25 C°
- °40 C
ReferredtoV =V +1.0VatI =10mA
IN OUT OUT
200
180
160
140
120
100
80
60
40
20
0
V (mV)
DO
0 100 200 300 400 500 600 700 800 900 1000
I (mA)
OUT
+125°C+25°C
V =2.5V
OUT
-40 C°
200
180
160
140
120
100
80
60
40
20
0
V (mV)
DO
-50 -25 0 25 50 75 100 150
Temperature( C)°
125
30
25
20
15
10
5
0
PercentofUnits(%)
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
V Error (%)
OUT
I =10mA
OUT
18
16
14
12
10
8
6
4
2
0
PercentofUnits(%)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
WorstCasedV /dT(ppm/°C)
OUT
I =10mA
OUT
TPS73719-Q1
TPS73733-Q1
SBVS123 – DECEMBER 2008 ...........................................................................................................................................................................................
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T
J
= 25 ° C, V
IN
= (V
OUT(nom)
+ 1.0 V), I
OUT
= 10 mA, V
EN
= 2.2 V, C
OUT
= 2.2 µF (unless otherwise noted)
LOAD REGULATION LINE REGULATION
Figure 3. Figure 4.
DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs TEMPERATURE
Figure 5. Figure 6.
OUTPUT VOLTAGE HISTOGRAM DROPOUT VOLTAGE DRIFT HISTOGRAM
Figure 7. Figure 8.
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2500
2000
1500
1000
500
0
I (mA)
GND
0 200 400 600 800 1000
I (mA)
OUT
V =5.0V
IN
V =3.3V
IN
V =2.2V
IN
1
0.1
0.01
I(mA)
GND
-50 -25 0 25 50 75 100 125
Temperature (°C)
V =0.5V
ENABLE
V =V +0.5V
IN OUT
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
CurrentLimit(mA)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
V (V)
OUT
V =3.3V
OUT
ICL
ISC
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
CurrentLimit(A)
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V (V)
IN
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
CurrentLimit(A)
-50 -25 0 25 50 75 100 125
Temperature(°C)
V =1.2V
OUT
TPS73719-Q1
TPS73733-Q1
www.ti.com
........................................................................................................................................................................................... SBVS123 – DECEMBER 2008
TYPICAL CHARACTERISTICS (continued)T
J
= 25 ° C, V
IN
= (V
OUT(nom)
+ 1.0 V), I
OUT
= 10 mA, V
EN
= 2.2 V, C
OUT
= 2.2 µF (unless otherwise noted)
GROUND PIN CURRENT vs OUTPUT CURRENT GROUND PIN CURRENT vs TEMPERATURE
Figure 9. Figure 10.
GROUND PIN CURRENT IN SHUTDOWNvs TEMPERATURE CURRENT LIMIT vs V
OUT
(FOLDBACK)
Figure 11. Figure 12.
CURRENT LIMIT vs V
IN
CURRENT LIMIT vs TEMPERATURE
Figure 13. Figure 14.
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10k10
90
80
70
60
50
40
30
20
10
0
RippleRejection(dB)
100 1k 100k 1M 10M
Frequency(Hz)
I =1mA
OUT
C =1mF
OUT
I =1mA
OUT
C =Any
OUT
I =1mA
OUT
C =10mF
OUT
I =100mA
OUT
C =Any
OUT
I =100mA
OUT
C =10mF
OUT
I =100mA
O
C =1mF
O
40
35
30
25
20
15
10
5
0
PSRR(dB)
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
V V-(V)
IN OUT
Frequency=10kHz
C =10 F
V =2.5V
I =100mA
m
OUT
OUT
OUT
1
0.1
0.01
eV/mÖ( Hz)
N
10 100 1k 10k 100k
Frequency(Hz)
C =1 Fm
OUT
C =10 Fm
OUT
I =150mA
OUT
60
55
50
45
40
35
30
25
20
V (RMS)
N
C (F)
FB
10p 100p 1n 10n
V =2.5V
OUT
C =0mF
OUT
R =39.2kW
1
10Hz<Frequency<100kHz
60
50
40
30
20
10
0
VN(RMS)
C ( F)m
OUT
0.1 1 10
VOUT = 5.0V
VOUT = 3.3V
VOUT = 1.5V
CNR = 0.01 Fm
10Hz < Frequency < 100kHz
140
120
100
80
60
40
20
0
VN(RMS)
CNR (F)
1p 10p 100p 1n 10n
VOUT = 5.0V
VOUT = 3.3V
VOUT = 1.5V
COUT = 0 Fm
10Hz < Frequency < 100kHz
TPS73719-Q1
TPS73733-Q1
SBVS123 – DECEMBER 2008 ...........................................................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)T
J
= 25 ° C, V
IN
= (V
OUT(nom)
+ 1.0 V), I
OUT
= 10 mA, V
EN
= 2.2 V, C
OUT
= 2.2 µF (unless otherwise noted)
PSRR (RIPPLE REJECTION) vsPSRR (RIPPLE REJECTION) vs FREQUENCY V
IN
– V
OUT
Figure 15. Figure 16.
TPS73701NOISE SPECTRAL DENSITY RMS NOISE VOLTAGE vs C
FB
Figure 17. Figure 18.
RMS NOISE VOLTAGE vs C
OUT
RMS NOISE VOLTAGE vs C
NR
Figure 19. Figure 20.
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10 s/divm
200mV/div VOUT
IOUT
C =10nF
NR
C =10 F
OUT m
10mA
1A
10 s/divm
100mV/div VOUT
VIN
C =10nF
NR
C =10 F
OUT m
4.3V
5.3V
100 s/divm
1V/div
1V/div
2V
0V
VOUT
VEN
R =20W
L
C =10 Fm
OUT
R =20W
L
C =1 Fm
OUT
100 s/divm
1V/div
1V/div
VOUT
VEN
R =20W
L
C =10 Fm
OUT
2V
0V
R =20W
L
C =1 Fm
OUT
6
5
4
3
2
1
0
-1
-2
Volts
50ms/div
VIN
VOUT
10
1
0.1
0.01
I(nA)
ENABLE
-50 -25 0 25 50 75 100 125
Temperature (°C)
TPS73719-Q1
TPS73733-Q1
www.ti.com
........................................................................................................................................................................................... SBVS123 – DECEMBER 2008
TYPICAL CHARACTERISTICS (continued)T
J
= 25 ° C, V
IN
= (V
OUT(nom)
+ 1.0 V), I
OUT
= 10 mA, V
EN
= 2.2 V, C
OUT
= 2.2 µF (unless otherwise noted)
TPS73733 TPS73733LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
Figure 21. Figure 22.
TPS73701 TPS73701TURN-ON RESPONSE TURN-OFF RESPONSE
Figure 23. Figure 24.
TPS73701, V
OUT
= 3.3VPOWER-UP/POWER-DOWN I
ENABLE
vs TEMPERATURE
Figure 25. Figure 26.
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160
140
120
100
80
60
40
20
0
I(nA)
FB
-50 -25 0 25 50 75 100 125
Temperature( C)°
160
140
120
100
80
60
40
20
0
IFB (nA)
−50 −25 0 25 50 75 100 125
Temperature( C)°
10 s/divm
100mV/div VOUT
IOUT
250mA
10mA
C =10 Fm
OUT
C =10nF
FB
R =39.2kW
1
5 s/divm
100mV/div VOUT
VIN
4.5V
3.5V
C =10 Fm
OUT
V =2.5V
OUT
C =10nF
FB
TPS73719-Q1
TPS73733-Q1
SBVS123 – DECEMBER 2008 ...........................................................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)T
J
= 25 ° C, V
IN
= (V
OUT(nom)
+ 1.0 V), I
OUT
= 10 mA, V
EN
= 2.2 V, C
OUT
= 2.2 µF (unless otherwise noted)
TPS73701 TPS73701I
FB
vs TEMPERATURE I
FB
vs TEMPERATURE
Figure 27. Figure 28.
TPS73701 TPS73701LOAD TRANSIENT, ADJUSTABLE VERSION LINE TRANSIENT, ADJUSTABLE VERSION
Figure 29. Figure 30.
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APPLICATION INFORMATION
TPS737xx
GNDEN
IN OUT
VIN VOUT
ON
OFF
TPS73701
GNDEN FB
IN OUT
VIN VOUT
VOUT = x1.204
(R1+ R2)
R2
R1CFB
R2
Optionalinputcapacitor.
Mayimprovesource
impedance,noise,orPSRR.
Optionaloutputcapacitor.
Mayimproveloadtransient,
noise,orPSRR.
Optionalcapacitor
reducesoutputnoise
andimproves
transientresponse.
OFF ON
Input and Output Capacitor Requirements
TPS73719-Q1
TPS73733-Q1
www.ti.com
........................................................................................................................................................................................... SBVS123 – DECEMBER 2008
The TPS737xx belongs to a family of new generation LDO regulators that use an NMOS pass transistor toachieve ultra-low-dropout performance, reverse current blockage, and freedom from output capacitor constraints.These features combined with an enable input make the TPS737xx ideal for portable applications. This regulatorfamily offers a wide selection of fixed output voltage versions and an adjustable output version. All versions havethermal and over-current protection, including foldback current limit.
Figure 31 shows the basic circuit connections for the fixed voltage models. Figure 32 gives the connections forthe adjustable output version (TPS73701).
Figure 31. Typical Application Circuit for Fixed-Voltage Versions
Figure 32. Typical Application Circuit for Adjustable-Voltage Version
R
1
and R
2
can be calculated for any output voltage using the formula shown in Figure 32 . Sample resistor valuesfor common output voltages are shown in Figure 2 .
For best accuracy, make the parallel combination of R
1
and R
2
approximately equal to 19 k Ω. This 19 k Ω, inaddition to the internal 8-k Ωresistor, presents the same impedance to the error amp as the 27-k Ωbandgapreference output. This impedance helps compensate for leakages into the error amp terminals.
Although an input capacitor is not required for stability if input impedance is very low, it is good analog designpractice to connect a 0.1- µF to 1- µF low equivalent series resistance (ESR) capacitor across the input supplynear the regulator. This capacitor counteracts reactive input sources and improves transient response, noiserejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transientsare anticipated or the device is located several inches from the power source.
The TPS737xx requires a 1.0- µF output capacitor for stability. It is designed to be stable for all available typesand values of capacitors. In applications where multiple low ESR capacitors are in parallel, ringing may occurwhen the product of C
OUT
and total ESR drops below 50 n ΩF. Total ESR includes all parasitic resistances,including capacitor ESR and board, socket, and solder joint resistance. In most applications, the sum of capacitorESR and trace resistance will meet this requirement.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s) :TPS73733-Q1
Output Noise
VN+32mVRMS (R1)R2)
R2
+32mVRMS VOUT
VREF
(1)
VNǒmVRMSǓ+27ǒmVRMS
VǓ VOUT (V)
(2)
V V
N RMS
(m)=8.5 (V)x VOUT
()
mVRMS
V
(3)
Board Layout Recommendation to Improve PSRR and Noise Performance
Internal Current Limit
Enable Pin and Shutdown
TPS73719-Q1
TPS73733-Q1
SBVS123 – DECEMBER 2008 ...........................................................................................................................................................................................
www.ti.com
A precision bandgap reference is used to generate the internal reference voltage, V
REF
. This reference is thedominant noise source within the TPS737xx and it generates approximately 32 µV
RMS
(10 Hz to 100 kHz) at thereference output (NR). The regulator control loop gains up the reference noise with the same gain as thereference voltage, so that the noise voltage of the regulator is approximately given by:
Since the value of V
REF
is 1.2V, this relationship reduces to:
for the case of no C
NR
.
An internal 27k Ωresistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltagereference when an external noise reduction capacitor, C
NR
, is connected from NR to ground. For C
NR
= 10 nF,the total noise in the 10-Hz to 100-kHz bandwidth is reduced by a factor of ~3.2, giving the approximaterelationship in Equation 3 for C
NR
= 10 nF.
This noise reduction effect is shown as RMS Noise Voltage vs C
NR
in the Typical Characteristics section.
The TPS73701 adjustable version does not have the NR pin available. However, connecting a feedbackcapacitor, C
FB
, from the output to the feedback pin (FB) reduces output noise and improve load transientperformance. This capacitor should be limited to 0.1 µF.
The TPS737xx uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate ofthe NMOS pass element above V
OUT
. The charge pump generates ~250 µV of switching noise at ~4 MHz;however, charge-pump noise contribution is negligible at the output of the regulator for most values of I
OUT
andC
OUT
.
To improve ac performance such as PSRR, output noise, and transient response, it is recommended that theprinted circuit board (PCB) be designed with separate ground planes for V
IN
and V
OUT
, with each ground planeconnected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor shouldconnect directly to the GND pin of the device.
The TPS737xx internal current limit helps protect the regulator during fault conditions. Foldback current limithelps to protect the regulator from damage during output short-circuit conditions by reducing current limit whenV
OUT
drops below 0.5 V. See Figure 12 in the Typical Characteristics section.
The enable pin (EN) is active high and is compatible with standard TTL-CMOS levels. A V
EN
below 0.5 V (max)turns the regulator off and drops the GND pin current to approximately 10 nA. When EN is used to shutdown theregulator, all charge is removed from the pass transistor gate, and the output ramps back up to a regulated V
OUT(see Figure 23 ).
When shutdown capability is not required, EN can be connected to V
IN
. However, the pass gate may not bedischarged using this configuration, and the pass transistor may be left on (enhanced) for a significant time afterV
IN
has been removed. This scenario can result in reverse current flow (if the IN pin is low impedance) and fasterramp times upon power-up. In addition, for V
IN
ramp times slower than a few milliseconds, the output mayovershoot upon power-up.
12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s) :TPS73733-Q1
Dropout Voltage
Transient Response
dV
dT +VOUT
COUT 80kWøRLOAD
(4)
dV
dT +VOUT
COUT 80kWø(R1)R2)øRLOAD
(5)
Reverse Current
TPS73719-Q1
TPS73733-Q1
www.ti.com
........................................................................................................................................................................................... SBVS123 – DECEMBER 2008
The TPS737xx uses an NMOS pass transistor to achieve extremely low dropout. When (V
IN
– V
OUT
) is less thanthe dropout voltage (V
DO
), the NMOS pass device is in its linear region of operation and the input-to-outputresistance is the R
DS, ON
of the NMOS pass element.
For large step changes in load current, the TPS737xx requires a larger voltage drop from V
IN
to V
OUT
to avoiddegraded transient response. The boundary of this transient dropout region is approximately twice the dcdropout. Values of V
IN
– V
OUT
above this line ensure normal transient response.
Operating in the transient dropout region can cause an increase in recovery time. The time required to recoverfrom a load transient is a function of the magnitude of the change in load current rate, the rate of change in loadcurrent, and the available headroom (V
IN
to V
OUT
voltage drop). Under worst-case conditions [full-scaleinstantaneous load change with (V
IN
– V
OUT
) close to dc dropout levels], the TPS737xx can take a couple ofhundred microseconds to return to the specified regulation accuracy.
The low open-loop output impedance provided by the NMOS pass element in a voltage follower configurationallows operation without a 1.0- µF output capacitor. As with any regulator, the addition of additional capacitancefrom the OUT pin to ground reduces undershoot magnitude but increases its duration. In the adjustable version,the addition of a capacitor, C
FB
, from the OUT pin to the FB pin will also improve the transient response.
The TPS737xx does not have active pulldown when the output is overvoltage. This architecture allowsapplications that connect higher voltage sources, such as alternate power supplies, to the output. Thisarchitecture also results in an output overshoot of several percent if the load current quickly drops to zero when acapacitor is connected to the output. The duration of overshoot can be reduced by adding a load resistor. Theovershoot decays at a rate determined by output capacitor C
OUT
and the internal/external load resistance. Therate of decay is given by Equation 4 and Equation 5 .
(Fixed voltage version)
(Adjustable voltage version)
The NMOS pass element of the TPS737xx provides inherent protection against current flow from the output ofthe regulator to the input when the gate of the pass device is pulled low. To ensure that all charge is removedfrom the gate of the pass element, the EN pin must be driven low before the input voltage is removed. If this isnot done, the pass element may be left on because of stored charge on the gate.
After the EN pin is driven low, no bias voltage is needed on any pin for reverse current blocking. Note thatreverse current is specified as the current flowing out of the IN pin because of voltage applied on the OUT pin.There will be additional current flowing into the OUT pin as a result of the 80-k Ωinternal resistor divider toground (see Figure 1 and Figure 2 ).
For the TPS73701, reverse current may flow when V
FB
is more than 1.0V above V
IN
.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s) :TPS73733-Q1
Thermal Protection
Power Dissipation
PD+ǒVIN *VOUTǓ IOUT
(6)
Package Mounting
TPS73719-Q1
TPS73733-Q1
SBVS123 – DECEMBER 2008 ...........................................................................................................................................................................................
www.ti.com
Thermal protection disables the output when the junction temperature rises to approximately 160 ° C, allowing thedevice to cool. When the junction temperature cools to approximately 140 ° C, the output circuitry is againenabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protectioncircuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage due tooverheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequateheatsink. For reliable operation, junction temperature should be limited to 125 ° C maximum. To estimate themargin of safety in a complete design (including heatsink), increase the ambient temperature until the thermalprotection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection shouldtrigger at least 35 ° C above the maximum expected ambient condition of your application. This produces aworst-case junction temperature of 125 ° C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS737xx has been designed to protect against overload conditions. Itwas not intended to replace proper heatsinking. Continuously running the TPS737xx into thermal shutdowndegrades device reliability.
The ability to remove heat from the die is different for each package type, presenting different considerations inthe PCB layout. The PCB area around the device that is free of other components moves the heat from thedevice to the ambient air. Performance data for JEDEC low- and high-K boards are shown in the PowerDissipation Ratings table. Using heavier copper will increase the effectiveness in removing heat from the device.The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (P
D
) is equal to the product ofthe output current times the voltage drop across the output pass element (V
IN
to V
OUT
):
Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the requiredoutput voltage.
Solder pad footprint recommendations for the TPS737xx are presented in Application Bulletin Solder PadRecommendations for Surface-Mount Devices (SBFA015 ), available from the Texas Instruments web site atwww.ti.com .
14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s) :TPS73733-Q1
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS73719QDRBRQ1 ACTIVE SON DRB 8 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TPS73733QDRBRQ1 ACTIVE SON DRB 8 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS73733-Q1 :
•Catalog: TPS73733
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 6-Apr-2009
Addendum-Page 1
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