SMDP-67206FV-15/883 - Atmel Corporation

Rev. E–20-Aug-01

Features

•First-in first-out dual port memory

•16384 x 9 organization

•Fast Flag and access times: 15, 30ns

•Wide temperature range: - 55 °C to + 125 °C

•Fully expandable by word width or depth

•Asynchronous read/write operations

•Empty, full and half flags in single device mode

•Retransmit capability

•Bi-directional applications

•Battery back-up opera tion: 2V data retentio n

•TTL compatible

•Single 5V + 10% power supply

•QML Q and V with SMD 5962-93177

Description

The M67206F implements a first-in first-out algorithm, featuring asynchronous

read/write operations. The FULL and EMPTY flags prevent data overflow and under-

flow. The E xpansio n logic allows unli mited ex pansion in wor d size and dept h with n o

timing penalties. Twin ad dres s p ointers autom ati ca ll y g ener a te in ter nal read and write

addresses, and no external address informatio n is required. Address poi nters are

automati cally increm ented with the wri te pin and read pin. The 9 bits wide data ar e

used in data commu nica tions app lica tions wher e a parity bit for error ch ecking is nec-

essary. The Re transmi t pin r ese ts the R ead po in ter to zer o with out affect ing t he write

pointer. This is very useful for retransmitting data when an error is detected in the

system.

Using an array of eight transistors (8 T) memory cell, the M67206F combines an

extremely low standby supply current (typ = 0.1 µA) with a fas t access time at 15 ns

over the fu ll temp erature ra nge. All versio ns offer batte ry back up data reten tion ca pa-

bility with a typical power consumption at less than 2 µW.

The M672 06F is pr ocess ed accordi ng to the m ethods of the la test rev ision of th e MIL

PRF 38535 (Q and V) or ESA SCC 9000.

Rad Tolerant

High Speed

16 K x 9

Parallel FIFO

M67206F

Rev. E–20-Aug-01

Interface

Block Diagram

Pin Configuration

3M67206F Rev. E–20-Aug-01

Pin Names

Signal Description

Data In (I0 - I8)Data inputs for 9 - bit data

Reset (RS ) Reset occur s whenever the Res et (RS) in put is taken to a low state. Reset returns both

internal read and write pointers to the first loc ation. A reset is required after power-up

before a write operation can be enabled. Both the Read Enable (R) and Wri te Enable

(W) inputs must be in the high state during the period shown in Figure 1. (i.e. tRSS before

the rising e dge o f RS) and sho uld not c hange u ntil tRSR afte r the rising edge of RS . The

Half-Full Flag (HF) will be reset to high After Reset (RS)

Figure 1. Reset

Notes: 1. EF, FF and HF may change status during reset, but flags will be valid at tRSC.

2. W and R = VIH around the rising edge of RS.

NAMES DESCRIPTION

I0-8 Inputs

Q0-8 Outputs

WWrite Enable

RRead Enable

RS Reset

EF Empty Flag

FF Full Flag

XO/HF Expansion Out/Half-Full Flag

XI Expansion IN

FL/RT First Load/Retransmit

VCC Power Supply

GND Ground

M67206F

Rev. E–20-Aug-01

Write Enable (W)A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set.

Data set-up and hold times must be maintained in the rise time of the leading edge of

the Write Enable (W) . Data is stor ed sequentially in the Ram arr ay, regardless o f any

current read operation.

Once half the memory is filled, and during the falling edge of the next write operation,

the Half-Full Flag (HF) will be se t to low and remain in this state until the difference

between the wri te and read pointers is les s than or equ al to half of the total available

memory in the device. The Half-Full Flag (HF) is th en reset b y the risi ng edge of the

read operation.

To prev ent data o verflow, the Full Fla g (FF) will go low, inhibiti ng further write oper a-

tions. On completion of a valid read operation, the Full Flag (FF) will go high after TRFF,

allowing a valid write to begin. When the FIFO stack is full, the internal write pointer is

blocked from W, so that external changes to W will have no effect on the full FIFO stack.

Read Enable (R)A read cycle is initiated on the falling edge of the Read Enable (R) provided that the

Empty Flag (EF) is not set. The data is accessed on a first in/first out basis, not including

any current write operations. After Read Enable (R) goes high, the Data Outputs (Q0 -

Q8) will return to a hi gh impedan ce state unti l the next Rea d operati on. When al l the

data in the FIFO stack has been read, the Empty Flag (EF) will go low, allowing the

“final” read cycle, but inhibiting further read operations while the data outputs remain in

a high impedance s tate. Once a valid write operation ha s been completed, the Empty

Flag (EF) will go high after tWEF and a valid read may then be initiated. When the FIFO

stack is empty, the internal read pointer is blocked from R, so that external changes to R

will have no effect on the empty FIFO stack.

First Load/Retransmit

(FL/RT) This is a dual-purpose input. In the Depth Expansion Mode, this pin is connected to

ground to in dicat e that it is the first loaded (s ee Opera ting Mod es). In th e Single Dev ice

Mode, this pin a cts as the retr ans mit input. The Singl e Dev ice Mode is i nitia ted b y c on-

necting the Expan si on In (XI ) to ground.

The M67206F can be set to retransmit data when the Retransmit Enable Contr ol (RT)

input is pulsed low. A retransmit operation will set the internal read point to the first loca-

tion and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be

in the h igh state duri ng retransm it. The retran smit feat ure is intend ed for use when a

numbe r of wr it es ar e eq ual to or less than the depth of th e FIF O ha s occ urr ed si nc e th e

last RS cycle. The retrans mit featu re i s not c ompati ble with the D epth Expans ion Mode

and w ill affect the Hal f-Full Fl ag (HF), in accordance with the relative locations of the

read and write pointers.

Expansion In (XI)This input is a dual-purpose pin. Expansion In (XI) is connec ted to GND to indicate an

operation in the single device mode. Expansion In (XI) is connected to Expansion Out

(XO) of the previous device in the Depth Expansion or Daisy Chain modes.

Full Flag (FF)The Full Flag (FF) will go low, inhibiting further write operations when the write pointer is

one location less than the read pointer, in dicating that the device is full. If the read

pointer is not moved after Reset (RS), the Full Flag (FF) will go low after 16384 writes.

Empty Flag (EF)The Empty Flag (EF) will go low, inhibiting further read operations when the read pointer

is equal to the write pointer, indicating that the device is empty.

5M67206F Rev. E–20-Aug-01

Expansion Out/Half-Full

Flag (XO/HF) This is a dual-purpose output. In the single device mode, when Expansion In (XI) is con-

nected to ground, this output acts as an indication of a half-full memory.

After half the memory is filled and on the falling edge of the next write operation, the

Half-Full Fl ag ( HF ) wi ll be se t to lo w an d wi ll remain se t un til the differe nc e be twee n th e

write and read pointe rs is less tha n or equal to half of the total memory of the de vice.

The Half-Full Flag (HF) is then reset by the rising edge of the read operation.

In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of

the previous device. This output acts as a signal to the next device in the Daisy Chain by

provid ing a pul se to the ne xt devi ce w hen the prev ious de vic e reaches the last memo ry

location.

Data Output (Q0 - Q 8)DATA output for 9-bit wide data. This data is in a high impedance condition whenever

Read (R) is in a high state.

M67206F

Rev. E–20-Aug-01

Functional Description

Operating Modes

Single Device Mode A single M67206F may be used when the application requirements are for 16384 words

or less. The M67206F is in a Single Device Configuration when the Expansion In (XI) control

input is grounded (see Figure 2.). In this mode the Half-Full Flag (HF), which is an active low

output, is shared with Expansion Out (XO).

Figure 2. Block Diagram of Single 16384 × 9

Width Expansion Mode Word wid th ma y be increas ed simpl y by connecting the c orr esp ond in g input contro l si g-

nals of multiple devices. Status flags (EF, FF and HF) can be detected from any device.

Figu re 3 demon st r at es an 18-b i t wo r d widt h by us i ng two M67 20 6 F . An y w ord wid th ca n be

attained by adding additional M67206F.

Figure 3. Block Diagram of 16384 X 18 FIFO Memory Used in Width Expansion Mode

Note: Flag detection is accomplished by monitoring the FF, EF and the HF signals on either

(any) device used in the width expansion configuration. Do not connect any output con-

trol signals together.

(HALF-FULL FLAG)

WRITE (W)(R) READ

DATAIN

(I) DATAOUT

(Q)

FULL FLAG

RESET

(FF)

(RS)

EMPTY F L AG

RETRANSMIT

(EF)

(RT)

EXPANSION IN (XI)

M67206F

7M67206F Rev. E–20-Aug-01

Table 1. Reset and retransmit

Single Device Configuration/Width Expansion Mode

Table 2. Reset and First Load Truth Table

Depth Expansion/Compound Expansion Mode

Depth Expansion (Daisy

Chain) Mode The M67206F can be easily adapted for applications which require more than 16384

words. Figure 4. demonstrates Depth Expansion using three M67206F. Any depth can

be achieved by adding additional 67206F.

The M6 7206F o perate s in the D epth E xpans ion confi guration if th e foll owing cond itions

are met:

1. The first device must be designated by connecting the First Load (FL) control

input to ground.

2. All other devices must have FL in the high stat e.

3. The Expansion Out (XO) pin of each device must be connected to the Expansion In

(XI) pin of the next device. See Figure 4

4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag

(EF). This requires that all EF’s and all FFs be ØRed (i.e. all must be set to generate the

correc t composite FF or EF). Se e Figur e 4.

5. The Retransmit (RT) fu nc tion an d Ha lf-F ull Fl ag (HF ) are not available in the Depth

Expansion Mode.

Compound Expansion

Module It is quite simple to apply the two expansion techniques described above together to cre-

ate large FIFO arrays (see Figure 5).

MODE INPUTS INTERNAL STATUS OUTPUTS

RS RT XI Read Pointer Write Pointer EF FF HF

Reset 0 X 0 Location Zero Location Zero 0 1 1

Retransmit 1 0 0 Location Zero Unchanged X X X

Read/Write 1 1 0 Increment (1) Increment(1) XXX

1. Pointer will increment if flag is high.

MODE INPUTS INTERNAL STATUS OUTPUTS

RS FL XI Read Pointer Write Pointer EF FF

Reset First Device 0 0 (1) Location Zero Location Zero 0 1

Reset All Othe r Devi ces 0 1 (1) Location Zero Location Zero 0 1

Read/Write 1 X (1) XX XX

1. XI is connected to XO of previous device.

See Figure 4.

M67206F

Rev. E–20-Aug-01

Bidirectional Mode Applications whic h require data buffering between two systems (each system being

capable of Re ad and Wri te op erations ) can be c reated by co uplin g M672 06F as sho wn

in Figure 6. Care must be taken to ensure that the appropriate flag is monitored by each

syste m (i.e. FF is monitored on the device on which W is in use; EF is monitored on the device

on which R is in use). Both Depth Expansion and Width Expansion may be used in this mode.

Data Flow - Through

Modes Two types of flow-through modes are permitted: a read flow-through and a write flow-

throu gh mode . In the re ad flow-t hrough mode (Fi gure 17.) the FI FO stac k allows a sin-

gle word to be read after one word has been written to an empty FIFO stack. The data is

enabled on the bus at (tWEF + tA) ns after the lead ing edge of W which is known as the

first write edge and remains on the bus until the R line is raised from low to high, after which the

bus will go into a three-state mode after tRHZ ns. The EF line will show a pulse indicating tem-

porary reset and then will be set. In the interval in which R is low, more words may be written to

the FIF O stac k (the su bseq uen t writ es afte r the fi rst writ e edge will re set the Empty Fl ag) ; how-

ever, the same word (written on the first write edge) presented to the output bus as the read

pointer will not be incremented if R is low. On to ggling R, the remaining words written to the

FIFO will appear on the output bus in accordance with the read cycle timings.

In the write flow -through mode (Figure 18), the F IFO stack allo ws a single word of da ta

to be written immediately after a single word of data has been read from a full FIFO

stack. The R line causes the FF to be reset, but the W line, being low, causes it to be set again

in antici pation of a new dat a wo rd. The new word is load ed int o th e FIFO stack on the lea ding

edge of W. The W line must be toggled when FF is not set in order to write new data into the

FIFO stack and to increment the write pointer.

Figure 4. Block Diagram of 49152 × 9 FIFO Memory (Depth expansion).

9M67206F Rev. E–20-Aug-01

Figure 5. Compound FIFO Expansion

Notes: 1. For depth expansion block see section on Depth Expansion and Figure 4.

2. For Flag detection see section on Width Expansion and Figure 3

Figure 6. Bidirectional FIFO Mode.

M67206F

Rev. E–20-Aug-01

Electrical Characteristics

Absolute Maximum

Ratings Supply voltage (VCC - GND):..................................- 0.3V to 7.0V

Input or Output voltage applied: .............................(GND - 0.3V) to (Vcc + 0.3V)

Storage temperature: ..............................................- 65 °C to + 150 °C

DC Parameters

OPERAT ING RANGE OPERATING SUPPLY

VOLTAGE OPERATING TEMPERATURE

Military Vcc = 5V ± 10% – 55 °C to + 125 °C

Parameter Description M 67206F-30 M 67206F-15 UNIT VAL UE

ICCOP (1) Operating

supply current 110 120 mA Max

ICCSB (2) Standby

supply current 55mAMax

ICCPD (3) Power down

current 400 400 µAMax

1. Icc measurements are made with outputs open.

2. R = W = RS = FL/RT = VIH.

3. All input = Vcc.

PARAMETER DESCRIPTION M67206F UNIT VALUE

ILI (1) Input leakage current ± 1 µAMax

ILO (2) Output leakage current ± 1 µAMax

VIL (3) Input low voltage 0.8 V Max

VIH (3) Input high voltage 2.2 V Min

VOL (4) Output low voltage 0.4 V Max

VOH (4) Output high voltage 2.4 V Min

C IN (5) Input capacitance 8 pF Max

C OUT (5) Output capacitance 8 pF Max

1. 0.4 ≤ Vin ≤ Vcc.

2. R = VI H, 0.4 ≤ VOUT ≤ VCC.

3. VIH max = Vcc + 0.3 V. VIL min = -0.3 V or -1 V pulse width 50 ns. For XI input, VIH= 2.8V

4. Vcc min, IOL = 8 mA, IOH = -2 mA.

5. Guaranteed but not tested .

11 M67206F Rev. E–20-Aug-01

AC Test Conditions Input pulse levels: .............................................Gnd to 3.0V

Input rise/Fall times: ........................................5 ns

Input timing refer ence lev el s: ............................1.5V

Output reference levels: ....................................1.5V

Output load:.......................................................See Figure 7.

Figure 7. Output Load

Table 3. AC Parameters

SYMBOL (1) SYMBOL (2) PARAMETER (3) (4) M67206F- 15 M67206F- 30 UNIT

Min Max Min Max

READ CYCLE

TRLRL tRC Read cyc le time 25 - 40 - ns

TRLQV tA Access time - 15 - 30 ns

TRHRL tRR Read recovery time 10 - 10 - ns

TRLRH tRPW Read pulse width (5) 15 - 30 - ns

TRLQX tRLZ Read low to data low Z (6) 0-5-ns

TWHQX tWLZ Write low to data low Z (6) (7) 3-5-ns

TRHQX tDV Data valid from read high 5 - 5 - ns

TRHQZ tRHZ Read high to data high Z (6) - 15 - 20 ns

WRITE CYCLE

TWLWL tWC Write cycle time 25 - 40 - ns

TWLWH tWP W Write p u l s e w i dth (5) 15 - 30 - ns

TWHWL tWR Write recovery time 10 - 10 - ns

TDVWH tDS Data set-up time 9 - 18 - ns

TWHDX tDH Data hold time 0 - 0 - ns

RESET CYCLE

TRSLWL tRSC Rese t c ycle tim e 25 - 40 - ns

M67206F

Rev. E–20-Aug-01

TRSLRSH tRS Res et pulse width (5) 15 - 30 - ns

TWHRSH tRSS Reset set-up time 20 - 30 - ns

TRSH W L tRSR Reset reco very time 10 - 10 - ns

RETRANSMIT CYCLE

TRTLWL tRTC Retransmit cycle time 25 - 40 - ns

TRTLRTH tRT Retransmit pulse width (5) 15 - 30 - ns

TWHRTH tRTS Retransmit set-up time (6) 15 - 30 - ns

TRTHWL t RTR Retransmit recovery time 10 - 10 - ns

FLAGS

TRSLEF L tEF L Reset to EF low - 25 - 30 ns

TRSLFFH tHFH, tFFH Reset to HF/FF high - 25 - 30 ns

TRLEFL tREF Read low to EF low - 15 - 30 ns

TRHFFH tRFF Read high to FF high - 25 - 30 ns

TEFHRH tRPE Read width after EF high 15 - 30 - ns

TWHEFH tWEF Write high to EF high - 15 - 30 ns

TWLFFL tWFF Wr ite low to FF low - 20 - 30 ns

TWLHFL tWHF Wr ite low to HF low - 30 - 30 ns

TRHHFH tRHF Read high to HF high - 30 - 30 ns

TFFHWH tW PF Write width after FF high 15 - 30 - ns

EXPANSION

TWLXOL tXOL Read/Write to XO low - 15 - 30 ns

TWHXOH tXOH Read/Write to XO high - 15 - 30 ns

TXILXIH tXI X I pulse width 15 - 30 - ns

TX IH XIL tXIR XI reco v ery time 10 - 10 - ns

TXILRL tXIS XI set-up time 10 - 10 - ns

1. STD symbol.

2. ALT symbol.

3. Timings referenced as in ac t est conditions.

4. All pa rameters tested only.

5. Pulse widths less than minimum value are not allowed.

6. Values guaranteed by design, not currently tested.

7. Only applies to read data flow-through mode.

13 M67206F Rev. E–20-Aug-01

Figure 8. Asynchronous Write and Read Operation

Figure 9. Full Flag from Last Write to First Read

M67206F

Rev. E–20-Aug-01

Figure 10. Empty Flag from Last Read to First Write

Figure 11 . Retransmit

Figure 12. Empty Flag Timing

tWEF

tRPE

15 M67206F Rev. E–20-Aug-01

Figure 13. Full Flag Timing

Figure 14. Half Full Flag Timing

M67206F

Rev. E–20-Aug-01

Figure 15. Expansion Out

Figure 16. Expansion In

17 M67206F Rev. E–20-Aug-01

Figure 17. Read Data Flow - Through Mode

Figure 18. Write Data Flow - Through Mode

M67206F

Rev. E–20-Aug-01

Ordering Information

Note: (*)contact factory

Reference Number Temperature Range Speed Package Quality Flow

MMCP-67206FV-15-E(*) 25°C 15ns SB28.3 Engineering Samples

MMCP-67206FV-15 -55 to +125°C 15ns SB28.3 Mil.

MMCP-67206FV-30 -55 to +125°C 30ns SB28.3 Mil.

SMCP-67206FV- 15SB -55 to +125°C 15ns SB28.3 SCC B

SMCP-67206FV- 30SB -55 to +125°C 30ns SB28.3 SCC B

SMCP-67206FV-15SC -55 to +125°C 15ns SB28.3 SCC C

SMCP-67206FV-30SC -55 to +125°C 30ns SB28.3 SCC C

MMCP-67206FV- 15/883(*) -55 to +125°C 15ns SB28.3 MI L-883 B

MMCP-67206FV- 30/883(*) -55 to +125°C 30ns SB28.3 MI L-883 B

SMCP-67206FV- 15/ 883(*) -55 to +125°C 15ns SB 28.3 MIL-883 S

SMCP-67206FV- 30/ 883(*) -55 to +125°C 30ns SB 28.3 MIL-883 S

5962-9317704QUC -55 to +125°C 15ns SB28.3 QML Q

5962-9317702QUC -55 to +125°C 30ns SB28.3 QML Q

5962-9317704VUC -55 to +125°C 15ns SB 28.3 QML V

5962-9317702VUC -55 to +125°C 30ns SB 28.3 QML V

MMDP-67206FV-15-E 25°C 15ns FP28.4 Engineering Samples

MMDP-67206FV-15 -55 to +125°C 15ns FP28.4 Mil.

MMDP-67206FV-30 -55 to +125°C 30ns FP28.4 Mil.

SMDP-67206FV- 15SB -55 to +125°C 15ns FP28.4 SCC B

SMDP-67206FV- 30SB -55 to +125°C 30ns FP28.4 SCC B

SMDP-67206FV-15SC -55 to +125°C 15ns FP28.4 SCC C

SMDP-67206FV-30SC -55 to +125°C 30ns FP28.4 SCC C

MMDP-67206FV- 15/883(*) -55 to +125°C 15ns FP28.4 MIL-883 B

MMDP-67206FV- 30/883(*) -55 to +125°C 30ns FP28.4 MIL-883 B

SMDP-67206FV- 15/ 883(*) -55 to +125°C 15ns FP28.4 MIL-883 S

SMDP-67206FV- 30/ 883(*) -55 to +125°C 30ns FP28.4 MIL-883 S

5962-9317704QZC -55 to +125°C 15ns FP28.4 QML Q

5962-9317702QZC -55 to +125°C 30ns FP28.4 QML Q

5962-9317704VZC -55 to +125°C 15ns FP28.4 QML V

5962-9317702VZC -55 to +125°C 30ns FP28.4 QML V

MM0-67206FV-15-E 25°C 15ns Die Engineering Samples

5962-9317704Q9A -55 to +125°C 15ns Die QML Q

5962-9317704V9A -55 to +125°C 15ns Die QML V

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this doc ument, reserves the right to change devices or specif ications detailed herein at any time without notice, and does

not make any co mmitment to update the inform ation contained herein. No licenses to patents or other intellectual property of Atmel are granted

by the Company in connection with the sale of Atmel pr oducts, expres sly or by implication. Atmel’s products are not authorized for use as critical

components in life support dev ices o r systems .

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