CY74FCT163LD374APAC - Cypress Semiconductor

16 -Bit Registers

fax id: 7051

CY74FCT163374

CY74FCT163H374

CY74FCT163LD374

CY74FCT163LDH374

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

March 19

1997 – Revised April 20

1998

H374

Features

• Low power, pin-compati ble replacement for LCX, LPT,

LVC, LVCH & LVT families

• 5V toler ant i nputs and outputs*

• 6 mA & 24 mA bal anced drive outputs

• Power-off disable outputs permits live insertion

• Edge-rate control cir cuitry f or reduced noise

• FCT-C speed at 5.2 ns

• Latc h-up perf orman ce exce eds JEDEC standard no. 17

• Typical output skew < 250 ps

• Industrial temperature range of –40°C to +85°C

• TSSOP (19.6 -mil pit ch) or SSOP (25-mil pitch)

• Typical Volp (ground bounce) performance exceeds Mil

Std 883D

•V

CC = 2.7V to 3.6V

• ESD (HBM) > 2000V

CY74FCT163H374

• Bus hold on data inputs

• Eliminates the need f or external pull -up or pull-do wn

resistors

• *Dev ices with bus hold are not rec ommended for trans-

lating rail-t o-rail CMOS signals to 3. 3V logi c levels

CY74FCT163LD2374

• Lite Drive™ option for low noise applications

• 6 mA bal anced drive outputs

• FCT-A speed at 6. 5 ns

•V

CC = 3.0V to 3.6V

• ESD (HBM) > 1100V

Functional Descripti on

These de vi ces are 16-bi t D-type regis ters desi gned f or use as

buffered registers in high-speed, low power bus applications.

These de v ices ca n be used as two i nde pendent 8 -bit regis ters

or as a single 16-bit register by connecting the output Enable

(OE) and Clock (CLK) inputs. The outputs are 24-mA balanced

output drivers with curr ent limiti ng resistors to reduce th e need

for external terminating resistors, and provide for minimal un-

dershoot and reduced ground bounce. Flow-through pinout

and small shrink pac kaging aid in simplifying board layout.

The CY74FCT163H374 and CY74FCT163LDH374 have “bus

hold” on the data inputs, which retain the input’s last state

whenever the source driving the input goes to high impedance.

This eliminates the need for pull-up/down resistors and pre-

vents float ing inputs.

The CY74FCT163374 and the CY74FCT16LD374 are

designed with inputs and outputs capable of being driven by

5.0V buses, allowing them to be used in mixed voltage

systems as translators. The outputs are also designed with a

power off disable feature enabling them to be used in

appli cations requiring live insertion.

Lite Dr ive is a trademark of Cyp ress Semicond uctor Corporation.

Logic Block Diagrams CY74FCT163374, CY74F CT163H374, Pin Configurat ion

1OE

1CLK

1D11O1

TO 7 OTHER CHANNELS

2OE

2CLK

2D12O1

GND

1OE

SSOP/TSSOP

Top View

1O1

1O2

1O3

1O4

1D1

1D2

1D3

1D4

1CLK

GND

VCC

1O7

1O8

1O5

1O6

1D5

1D6

1D7

1D8

VCC

GND

2O3

2O4

2O1

2O2

2D1

2D2

2D3

2D4

GND

VCC

2O7

2O8

2O5

2O6

2D5

2D6

2D7

2D8

VCC

GND

2OE 2CLK

TO 7 OTHER CHANNELS

CY74FCT163LD374, CY74FCT163LDH374

CY74FCT163374

CY74FCT163H374

CY74FCT163LD374

CY74FCT163LDH374

Maximum Ratings[3, 4]

(Above which the useful life may be impaired. For user

guidelines, not tested.)

Storage Temperature ..................................... −55°C to +125°C

Ambient Temperature with

Power Applied.................................................. −55°C to +125°C

Supply Voltage Range. .....................................0.5V to +4.6V

DC Input Voltage.................................................−0.5V to +7.0V

DC Output Voltage..............................................−0.5V to +7.0V

DC Output Current

(Maximum Sink Current/Pin)...........................−60 t o +120 m A

Power Dissipation..........................................................1.0W

Function Table[1]

Inputs Outputs

FunctionDCLK OE O

X L H Z High-Z

X H H Z

L L L Load

H L H

L H Z

H H Z

Pin Description

Name Description

DData Inputs[2]

CLK Clock Input s

OE Three-State Output Enable Inputs (Active LOW)

OThree-State Outputs

Operating Range

Range Ambient

Temperature VCC

Industrial −40°C to +85°C 2.7V to 3.6V

Electric al Characteri stic s for Non Bus Hold Dev ic es Over the Operating Range VCC=2.7V to 3.6V

Parameter Description Test Conditions Min. Typ.[5] Max. Unit

VIH Input HIGH Voltage All In p ut s 2.0 5.5 V

VIL Input LOW Voltage 0.8 V

VHInput Hysteresis[6] 100 mV

VIK Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V

IIH Input HIGH Current VCC=Max., VI=5.5 ±1µA

IIL Input LOW Current VCC=Max., VI=GND ±1µA

IOZH High Impeda nce O utput Curren t

(Three-Stat e Output pins) VCC=Max., VOUT=5.5V ±1µA

IOZL High Impeda nce O utput Curren t

(Three-Stat e Output pins) VCC=Max., VOUT=GND ±1µA

IOS Short Ci rcuit Current[7] VCC=Max., VOUT=GND –60 –135 –240 mA

IOFF Power -Of f Disable VCC=0V, VOUT≤4.5V ±100 µA

ICC Quiescent Power Supply Current VIN≤0.2V,

VIN>VCC–0.2V VCC=Max. 0.1 10 µA

∆ICC Quiescent Power Supply Current

(TTL inputs HIGH) VIN=VCC–0.6V[8] VCC=Max. 2.0 30 µA

Notes:

1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = HIGH Impedance. = LOW-to-HIGH Transition.

2. On the CY74FCT163H374 & CY74FCT163LDH374 these pins have “bus hold.”

3. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are o ver the operating free-air temperature

range.

4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground

5. Typical values are at VCC=3.3V, TA = +25°C ambient.

6. This parameter is guaranteed but not tested.

7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample

and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of

a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter

tests, IOS tests should be performed last.

8. Per TTL driven input; all other inputs at VCC or GND.

CY74FCT163374

CY74FCT163H374

CY74FCT163LD374

CY74FCT163LDH374

Electrical Characteristics For Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V

Parameter Description Test Conditions Min. Typ.[5] Max. Unit

VIH Input HIGH Voltage All Inputs 2.0 VCC V

VIL Input LOW Voltage 0.8 V

VHInput Hysteresis[6] 100 mV

VIK Input Clamp Diode Voltage VCC=M in ., IIN=–18 m A –0.7 – 1.2 V

IIH Input HIGH Current VCC=Max., VI=VCC ±100 µA

IIL Input LOW Current ±100 µA

IBBH

IBBL Bus Hold Sustain Curr ent on Bus Hol d Input[9] VCC=Min. VI=2.0V –50 µA

VI=0.8V +50 µA

IBHHO

IBHLO Bus Hold Overdrive Current on Bus Hold Input[9] VCC=Max., VI=1.5V ±500 µA

IOZH High Impeda nce O utput Curren t

(Three-Stat e Output pins) VCC=Max., VOUT=VCC ±1µA

IOZL High Impeda nce O utput Curren t

(Three-Stat e Output pins) VCC=Max., VOUT=GND ±1µA

IOS Short Ci rcuit Current[7] VCC=Max., VOUT=GND –60 –135 –240 mA

IOFF Power -Of f Disable VCC=0V, VOUT≤4.5V ±100 µA

ICC Quiescent Power Supply Current VIN<0.2V VCC=Max. +40 µA

∆ICC Quiesce nt Power supply Current

(TTL inputs HIGH) VIN=VCC–0.6V[8] VCC=Max. +350 µA

Electrical Characteristics For Balanced Drive Devices Over the Operating Range VCC=2.7V to 3.6V

Parameter Description Test Conditions Min. Typ.[5] Max. Unit

IODL Output LOW Dynamic Current[7] VCC=3.3V, VIN=VIH

or VIL, VOUT=1.5V 45 110 mA

IODH Output HIG H Dynamic Current[7] VCC=3.3V, VIN=VIH

or VIL, VOUT=1.5V –45 –110 mA

VOH Output HIGH Voltage VCC=Mi n ., IOH= –0. 1 mA VCC–0.2 V

VCC=Mi n ., IOH= –8 mA 2.4[10] 3.0 V

VCC=3.0V, IOH= –24 mA 2.0 3.0 V

VOL Output LOW Voltage VCC=Mi n ., IOL= 0.1 mA 0.2 V

VCC=Mi n ., IOL= 24 mA 0.3 0.55

Electrical Characteristics For Lite Drive Devices Ov er the Operating Range VCC=3.0V to 3.6V

Parameter Description Test Conditions Min. Typ.[5] Max. Unit

IODL Output LOW Dynamic Current[7] VCC=3.3V, VIN=VIH

or VIL, VOUT=1.5V 15.0 45 mA

IODH Output HIG H Dynamic Current[7] VCC=3.3V, VIN=VIH

or VIL, VOUT=1.5V –15.0 –45 mA

VOH Output HIGH Voltage VCC=3.0 V, IOH= –6 mA 2.4 3.0 V

VOL Output LOW Voltage VCC=3.0 V, IOL= 6 mA 0.55 V

Notes:

9. Pins with bus hold are described in Pin Description.

10. VOH=VCC–0.6V at rated current.

CY74FCT163374

CY74FCT163H374

CY74FCT163LD374

CY74FCT163LDH374

Capacitance[6](TA = +25°C , f = 1.0 MHz)

Parameter Description Test Condi ti ons Typ.[5] Max. Unit

CIN Input Capacitance VIN = 0V 4.5 6.0 pF

COUT Output Capacitance VOUT = 0V 5.5 8.0 pF

Power Suppl y Characteri stic s

Parameter Description Test Condi ti ons Typ.[5] Max. Unit

ICCD Dyna mic Power Supply

Current[11] VCC=Max., One Input Toggling,

50% Duty Cycle,

Outputs Open, OE=GND

VIN=VCC or

VIN=GND 50 75 µA/MHz

ICTota l Power Supply

Current[12] VCC=Max., f1=10 MHz, 50%

Duty Cycle, Out puts Ope n, One

Bit Toggling, OE=GND

VIN=VCC or

VIN=GND 0.5 0.8 mA

VIN=VCC–0.6V o r

VIN=GND 0.5 0.8 mA

VCC=Max., f1=2.5 MHz, 50%

Duty Cycle, Outputs Open, Six-

teen Bits Toggling, OE=GND

VIN=VCC or

VIN=GND 2.0 3.0[13] mA

VIN=VCC–0.6V o r

VIN=GND 2.0 3.3[13] mA

Swi tch i ng C h aracteri sti cs Ove r the Operating Range VCC=3.0V to 3.6V[14,15]

Parameter Description

CY74FCT163374A

CY74FCT163H374A CY74FCT163374C

CY74FCT163H374C

Min. Max. Min. Max. Unit Fig. No.[16]

tPLH

tPHL Propagation Delay Clock to

Output 1.5 6.5 1.5 5.2 ns 1, 3

tPZH

tPZL Output Enable Time 1.5 6.5 1.5 5.5 ns 1, 7, 8

tPHZ

tPLZ Out p ut Di sable T i m e 1.5 5.5 1.5 5.0 ns 1, 7, 8

tSU Input Setup time 2.0 2.0 ns 1, 4

tH Input Hold time 1.5 -1.5 -ns 1. 4

tSK(O) Output Skew[17] 0.5 0.5 ns —

Notes:

11. This parameter is not directly testable, but is derived f or use in Total Power Supply calculations.

12. IC=I

QUIESCENT + IINPUTS + IDYNAMIC

IC=I

CC+∆ICCDHNT+ICCD(f0/2 + f1N1)

ICC = Quiescent Current with CMOS input levels

∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)

DH= Duty Cycle for TTL inputs HIGH

NT= Number of TTL inputs at DH

ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)

f0= Clock frequency f o r registered devices, otherwise zero

f1= Input signal frequency

N1= Number of inputs changing at f1

All currents are in milliamps and all frequencies are in megahertz.

13. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.

14. Minimum limits are guaranteed but not tested on Propagation Delays.

15. For VCC =2.7, propagation delay, output enable and output disable times should be degraded by 20%.

16. See “Parameter Measurement Information” in the General Information section.

17. Skew between any tw o outputs of the same package switching in the same direction. This parameter is guaranteed by design.

CY74FCT163374

CY74FCT163H374

CY74FCT163LD374

CY74FCT163LDH374

Document #: 38-00577-A

Swi tch i ng C h aracteri sti cs Ov er the Operating Range VCC=3.0V to 3. 6V [14,15]

Parameter Description

CY74FCT163LD374[18]

CY74FCT163LDH374 CY74FCT163LD374A[18]

CY74FCT163LDH374A

Min. Max. Min. Max. Unit Fi g. No.[16]

tPLH

tPHL Propagation Delay Clock to

Q Output 1.5 10 1.5 6.5 ns 1, 3

tPZH

tPZL Output Enab le Time 1.5 12.5 1. 5 6.5 ns 1, 7, 8

tPHZ

tPLZ Output Disable Time 1.5 8.0 1.5 5.5 ns 1, 7, 8

tSU In put Se tup time 2.0 2.0 ns 1, 4

tH Inp u t H o ld ti me 1. 5 1.5 ns 1, 4

tSK(O) Output Skew[17] 0.5 0.5 ns —

Note:

18. For Lite Drive de vices the load capacitance is 30 pF. For all others it is 50 pF.

Ordering Information CY74FCT163374

Speed

(ns) Ordering Code Package

Name Packag e Type Operating

Range

5.2 CY74FCT163374CPAC Z48 48-Lead (240-Mil) TSSOP Industrial

CY74FCT163374CPVC O48 48-Lead (300-Mil) SSOP

6.5 CY74FCT163374APAC Z48 48-Lead (240-Mil) TSSOP Industrial

CY74FCT163374APVC O48 48-Lead (300-Mil) SSOP

Ordering Information CY74FCT163H374

Speed

(ns) Ordering Code Package

Name P ac kage Type Operating

Range

5.2 CY74FCT163H374CPAC Z48 48-Lead (24 0-Mil) TSSOP Industrial

CY74FCT163H374CPVC O48 48-Lead (300-Mil) SSOP

6.5 CY74FCT163H374APAC Z48 48-Lead (240-Mil) TSSOP Industrial

CY74FCT163H374APVC O48 48-Lead (300-Mil) SSOP

Ordering Information CY74FCT163LD374

Speed

(ns) Ordering Code Package

Name Packag e Type Operating

Range

6.5 CY74FCT16 3LD374APAC Z48 48-Lead (240-Mil) TSSOP Indus trial

CY74FCT163LD374APVC O48 48-Lead (30 0-Mi l) SSOP

10 CY74FCT163LD374PAC Z48 48-Lead (240-Mil) TSSOP I ndustrial

CY74FCT163LD374PVC O48 48-L ead (300-Mil ) SSOP

Ordering Information CY74FCT163LDH374

Speed

(ns) Ordering Code Package

Name Packag374e Type Operating

Range

6.5 CY74FCT16 3LDH374APAC Z48 48-Lead (240-Mil) TSSOP Indus trial

CY74FCT163LDH374APVC O48 48-Lead (30 0-Mi l) SSOP

10 CY74FCT163LDH374PAC Z48 48-Lead (24 0-Mil) TSSOP Industrial

CY74FCT163LDH374PAC O48 48-Lead (300-Mil) SSOP

CY74FCT163374

CY74FCT163H374

CY74FCT163LD374

CY74FCT163LDH374

of any circui try other than circuitry embodied in a Cypress Semic onductor product. Nor does it conv ey or imply any license under patent or oth er rights . Cypress Semiconductor does not authorize

its products for use as critical components in life-suppor t systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support sy stems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

1CY74FCT163H374

Package Di ag ra ms

48-Lead Shrunk Small Outline PackageO48

48-Lead Thin Shrunk Small Outline Package Z48