MCP444X/446X 7/8-Bit Quad I2C Digital POT with Nonvolatile Memory (c) 2010 Microchip Technology Inc. MCP44X1 Quad Potentiometers P3A P3W P3B HVC/A0 SCL SDA VSS P1B P1W P1A 20 19 18 17 16 15 14 12 12 11 1 2 3 4 5 6 7 8 9 10 P2A P2W P2B VDD A1 RESET WP P0B P0W P0A P2B P2W P2A P3A P3W TSSOP 20 19 18 17 16 1 3 SDA 4 VSS 5 VDD EP 21 6 7 8 13 RESET 12 WP 11 P0B 9 10 P0W 2 SCL P0A HVC/A0 15 14 A1 P1A P3B P1B * Quad Resistor Network * Potentiometer or Rheostat configuration options * Resistor Network Resolution - 7-bit: 128 Resistors (129 Taps) - 8-bit: 256 Resistors (257 Taps) * RAB Resistances options of: - 5 k - 10 k - 50 k - 100 k * Zero Scale to Full Scale Wiper operation * Low Wiper Resistance: 75 (typical) * Low Tempco: - Absolute (Rheostat): 50 ppm typical (0C to 70C) - Ratiometric (Potentiometer): 15 ppm typical * Nonvolatile Memory - Automatic Recall of Saved Wiper Setting - WiperLockTM Technology - 5 General Purpose Memory Locations * I2C Serial Interface - 100 kHz, 400 kHz, and 3.4 MHz support * Serial protocol allows: - High-Speed Read/Write to wiper - Read/Write to EEPROM - Write Protect to be enabled/disable - WiperLock to be enabled/disabled * Resistor Network Terminal Disconnect Feature via Terminal Control (TCON) Register * Reset input pin * Write Protect Feature: - Hardware Write Protect (WP) Control pin - Software Write Protect (WP) Configuration bit * Brown-out reset protection (1.5V typical) * Serial Interface Inactive current (2.5 uA typical) * High-Voltage Tolerant Digital Inputs: Up to 12.5V * Supports Split Rail Applications * Internal weak pull-up on all digital inputs (except SCL and SDA) * Wide Operating Voltage: - 2.7V to 5.5V - Device Characteristics Specified - 1.8V to 5.5V - Device Operation * Wide Bandwidth (-3 dB) Operation: - 2 MHz (typical) for 5.0 k device * Extended temperature range (-40C to +125C) * Package Types: 4x4 QFN-20, TSSOP-20 and TSSOP-14 Package Types (Top View) P1W Features 4x4 QFN MCP44X2 Quad Rheostat P3W P3B HVC/A0 SCL SDA VSS P1B 1 2 3 4 5 6 7 14 13 12 11 10 9 8 P2W P2B VDD A1 P0B P0W P1W TSSOP DS22265A-page 1 MCP444X/446X Device Block Diagram VDD Power-up/ Brown-out Control VSS WP RESET P0W Wiper 0 & TCON0 Register I2C Serial Interface Module & Control Logic (WiperLockTM Technology) A1 HVC/A0 SCL SDA P0A Resistor Network 0 (Pot 0) P0B P1A Resistor Network 1 (Pot 1) P1W Wiper 1 & TCON0 Register Memory (16x9) Wiper0 (V & NV) Wiper1 (V & NV) Wiper2 (V & NV) Wiper3 (V & NV) P1B P2A Resistor Network 2 (Pot 2) TCON0 TCON1 STATUS Data EEPROM (5 x 9-bits) P2W Wiper 2 & TCON1 Register P2B P3A Resistor Network 3 (Pot 3) P3W Wiper 3 & TCON1 Register P3B No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V 4 I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 129 1.8V to 5.5V 2 Rheostat (1) Resistance (typical) RAB Options (k) Wiper - RW () # of Taps RAM MCP4432 (3) Wiper Configuration POR Wiper Setting WiperLock Technology 4 Potentiometer (1) I2C Device Control MCP4431(3) # of POTs Memory Type Device Features VDD Operating Range(2) MCP4441 4 Potentiometer I C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V MCP4442 4 Rheostat I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 129 2.7V to 5.5V MCP4451(3) 4 Potentiometer(1) I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V MCP4452(3) 4 Rheostat I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0 75 257 1.8V to 5.5V MCP4461 4 Potentiometer(1) I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V MCP4462 4 Rheostat I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0 75 257 2.7V to 5.5V Note 1: 2: 3: Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor). Analog characteristics only tested from 2.7V to 5.5V unless otherwise noted. Please check Microchip web site for device release and availability. DS22265A-page 2 (c) 2010 Microchip Technology Inc. MCP444X/446X 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Voltage on VDD with respect to VSS ................ -0.6V to +7.0V Voltage on HVC/A0, A1, SCL, SDA, WP, and RESET with respect to VSS ................................... -0.6V to 12.5V Voltage on all other pins (PxA, PxW, and PxB) with respect to VSS ......................................... -0.3V to VDD + 0.3V Input clamp current, IIK (VI < 0, VI > VDD, VI > VPP ON HV pins) ......................20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ..................................................20 mA Maximum output current sunk by any Output pin ......................................................................................25 mA Maximum output current sourced by any Output pin ed ......................................................................................25 mA Maximum current out of VSS pin .................................100 mA Maximum current into VDD pin ....................................100 mA Maximum current into PXA, PXW & PXB pins ............2.5 mA Storage temperature ....................................-65C to +150C Ambient temperature with power applied ..................................................................... -40C to +125C Package power dissipation (TA = +50C, TJ = +150C) Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TSSOP-14....................................................... 1000 mW TSSOP-20....................................................... 1110 mW QFN-20 (4x4) .................................................. 2320 mW Soldering temperature of leads (10 seconds) ............. +300C ESD protection on all pins ................................... 4 kV (HBM), .......................................................................... 300V (MM) Maximum Junction Temperature (TJ) ......................... +150C (c) 2010 Microchip Technology Inc. DS22265A-page 3 MCP444X/446X AC/DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Parameters Sym Min Typ Max Units Supply Voltage VDD HVC/A0, SDA, SCL, A1, WP, RESET pin Voltage Range VHV 2.7 1.8 VSS -- -- -- 5.5 2.7 12.5V V V V VSS -- V -- -- VDD + 8.0V 1.65 VDD Start Voltage to ensure Wiper Reset VDD Rise Rate to ensure Power-on Reset Delay after device exits the reset state (VDD > VBOR) Supply Current (Note 10) VBOR VDDRR (Note 9) V Conditions Serial Interface only. VDD The HVC/A0 pin will be at one 4.5V of three input levels VDD < (VIL, VIH or VIHH). (Note 6) 4.5V RAM retention voltage (VRAM) < VBOR V/ms TBORD -- 10 20 s IDD -- -- 600 A Serial Interface Active, HVC/A0 = VIH (or VIL) (Note 11) Write all 0's to volatile Wiper 0 VDD = 5.5V, FSCL @ 3.4 MHz -- -- 250 A Serial Interface Active, HVC/A0 = VIH (or VIL) (Note 11) Write all 0's to volatile Wiper 0 VDD = 5.5V, FSCL @ 100 kHz -- -- 575 A EE Write Current (Write Cycle) (Nonvolatile device only), VDD = 5.5V, FSCL = 400 kHz, Write all 0's to Nonvolatile Wiper 0 SCL = VIL or VIH -- 2.5 5 A Serial Interface Inactive, (Stop condition, SCL = SDA = VIH), Wiper = 0 VDD = 5.5V, HVC/A0 = VIH Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at VW with VA = VDD and VB = VSS. 3: MCP44X1 only. 4: MCP44X2 only, includes VWZSE and VWFSE. 5: Resistor terminals A, W and B's polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification. DS22265A-page 4 (c) 2010 Microchip Technology Inc. MCP444X/446X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics Parameters All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym Min Typ Max Units Resistance ( 20%) RAB 4.0 8.0 40.0 80.0 6.0 12.0 60.0 120.0 Resolution N Step Resistance RS 5 10 50 100 257 129 RAB / (256) RAB / (128) 0.2 0.2 0.2 0.2 0.25 0.25 0.25 0.25 75 75 50 100 150 15 -- k k k k Taps Taps -- 1.50 1.25 1.0 1.0 1.75 1.50 1.25 1.25 160 300 -- -- -- -- % % % % % % % % ppm/C ppm/C ppm/C ppm/C -- -- Nominal Resistance Match (| RABWC RABMEAN |) / RABMEAN (| RBWWC RBWMEAN |) / RBWMEAN Wiper Resistance (Note 3, Note 4) Nominal Resistance Tempco RW RAB/T -- -- -- -- -- -- -- -- -- -- -- -- -- -- Conditions -502 devices (Note 1) -103 devices (Note 1) -503 devices (Note 1) -104 devices (Note 1) 8-bit No Missing Codes 7-bit No Missing Codes 8-bit Note 6 7-bit Note 6 5 k MCP44X1 devices only 10 k 50 k 100 k 5 k Code = Full Scale 10 k 50 k 100 k VDD = 5.5 V, IW = 2.0 mA, code = 00h VDD = 2.7 V, IW = 2.0 mA, code = 00h TA = -20C to +70C TA = -40C to +85C TA = -40C to +125C Code = Midscale (80h or 40h) Ratiometeric VWB/T Tempco Resistance RTRACK Section 2.0 ppm/C See Typical Performance Curves Tracking Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at VW with VA = VDD and VB = VSS. 3: MCP44X1 only. 4: MCP44X2 only, includes VWZSE and VWFSE. 5: Resistor terminals A, W and B's polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification. (c) 2010 Microchip Technology Inc. DS22265A-page 5 MCP444X/446X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Parameters Sym Min Typ Max Units Resistor Terminal Input Voltage Range (Terminals A, B and W) Maximum current through A, W or B (Note 6) VA,VW,VB Vss -- VDD V IW -- -- 2.5 mA Terminal A IAW, W = Full Scale (FS) -- -- 2.5 mA Terminal B IBW, W = Zero Scale (ZS) -- -- 2.5 mA Terminal W IAW (W = FS) or IBW (W = ZS) -- -- -- -- -- -- -- -- -- -- -- 100 100 100 1.38 0.688 0.138 0.069 -- -- -- mA mA mA mA nA nA nA Maximum RAB current (IAB) (Note 6) IAB Conditions Note 5, Note 6 VB = 0V, VA = 5.5V, RAB(MIN) = 4000 VB = 0V, VA = 5.5V, RAB(MIN) = 8000 VB = 0V, VA = 5.5V, RAB(MIN) = 40000 VB = 0V, VA = 5.5V, RAB(MIN) = 80000 Leakage current IWL MCP44X1 PxA = PxW = PxB = VSS into A, W or B MCP44X2 PxB = PxW = VSS Terminals Disconnected (R0A = R0W = R0B = 0; R1A = R1W = R1B = 0; R2A = R2W = R2B = 0; R3A = R3W = R3B = 0) Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at VW with VA = VDD and VB = VSS. 3: MCP44X1 only. 4: MCP44X2 only, includes VWZSE and VWFSE. 5: Resistor terminals A, W and B's polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification. DS22265A-page 6 (c) 2010 Microchip Technology Inc. MCP444X/446X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics Parameters All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym Min Typ Max Units Conditions 8-bit 3.0V VDD 5.5V 7-bit 3.0V VDD 5.5V 10 k 8-bit 3.0V VDD 5.5V 7-bit 3.0V VDD 5.5V 50 k 8-bit 3.0V VDD 5.5V 7-bit 3.0V VDD 5.5V 100 k 8-bit 3.0V VDD 5.5V 7-bit 3.0V VDD 5.5V Zero Scale Error VWZSE 5 k 8-bit 3.0V VDD 5.5V (MCP44X1 only) 7-bit 3.0V VDD 5.5V (8-bit code = 00h, 10 k 8-bit 3.0V VDD 5.5V 7-bit code = 00h) 7-bit 3.0V VDD 5.5V 50 k 8-bit 3.0V VDD 5.5V 7-bit 3.0V VDD 5.5V 100 k 8-bit 3.0V VDD 5.5V 7-bit 3.0V VDD 5.5V Potentiometer INL 8-bit 3.0V VDD 5.5V Integral MCP44X1 devices only 7-bit Non-linearity (Note 2) Potentiometer DNL -0.5 0.25 +0.5 LSb 8-bit 3.0V VDD 5.5V Differential NonMCP44X1 devices only -0.25 0.125 +0.25 LSb 7-bit linearity (Note 2) Bandwidth -3 dB BW -- 2 -- MHz 5 k 8-bit Code = 80h (See Figure 2-72, -- 2 -- MHz 7-bit Code = 40h load = 30 pF) -- 1 -- MHz 10 k 8-bit Code = 80h -- 1 -- MHz 7-bit Code = 40h -- 200 -- kHz 50 k 8-bit Code = 80h -- 200 -- kHz 7-bit Code = 40h -- 100 -- kHz 100 k 8-bit Code = 80h -- 100 -- kHz 7-bit Code = 40h Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at VW with VA = VDD and VB = VSS. 3: MCP44X1 only. 4: MCP44X2 only, includes VWZSE and VWFSE. 5: Resistor terminals A, W and B's polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification. Full Scale Error (MCP44X1 only) (8-bit code = 100h, 7-bit code = 80h) VWFSE (c) 2010 Microchip Technology Inc. -6.0 -4.0 -3.5 -2.0 -0.8 -0.5 -0.5 -0.5 -- -- -- -- -- -- -- -- -1 -0.5 -0.1 -0.1 -0.1 -0.1 -0.1 -0.1 -0.1 -0.1 +0.1 +0.1 +0.1 +0.1 +0.1 +0.1 +0.1 +0.1 0.5 0.25 -- -- -- -- -- -- -- -- +6.0 +3.0 +3.5 +2.0 +0.8 +0.5 +0.5 +0.5 +1 +0.5 LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb 5 k DS22265A-page 7 MCP444X/446X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Parameters Sym Min Typ Max Units Conditions Rheostat Integral Non-linearity MCP44X1 (Note 4, Note 8) MCP44X2 devices only (Note 4) R-INL -1.5 -8.25 0.5 +4.5 +1.5 +8.25 LSb LSb -1.125 -6.0 0.5 +4.5 +1.125 +6.0 LSb LSb -1.5 -5.5 0.5 +2.5 +1.5 +5.5 LSb LSb -1.125 -4.0 0.5 +2.5 +1.125 +4.0 LSb LSb -1.5 -2.0 0.5 +1 +1.5 +2.0 LSb LSb -1.125 -1.5 0.5 +1 +1.125 +1.5 LSb LSb 7-bit -1.0 -1.5 0.5 +0.25 +1.0 +1.5 LSb LSb 100 k 8-bit -0.8 -1.125 0.5 +0.25 +0.8 +1.125 LSb LSb 7-bit 5 k 8-bit 7-bit 10 k 8-bit 7-bit 50 k 8-bit 5.5V, IW = 900 A 3.0V, IW = 480 A (Note 7) 5.5V, IW = 900 A 3.0V, IW = 480 A (Note 7) 5.5V, IW = 450 A 3.0V, IW = 240 A (Note 7) 5.5V, IW = 450 A 3.0V, IW = 240 A (Note 7) 5.5V, IW = 90 A 3.0V, IW = 48 A (Note 7) 5.5V, IW = 90 A 3.0V, IW = 48 A (Note 7) 5.5V, IW = 45 A 3.0V, IW = 24 A (Note 7) 5.5V, IW = 45 A 3.0V, IW = 24 A (Note 7) Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP44X1 only. MCP44X2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification. Note 1: 2: 3: 4: 5: 6: 7: DS22265A-page 8 (c) 2010 Microchip Technology Inc. MCP444X/446X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Parameters Sym Rheostat Differential Nonlinearity MCP44X1 (Note 4, Note 8) MCP44X2 devices only (Note 4) R-DNL Min Typ Max Units Conditions 5.5V, IW = 900 A 3.0V, IW = 480 A (Note 7) -0.375 0.25 +0.375 LSb 7-bit 5.5V, IW = 900 A -0.75 +0.5 +0.75 LSb 3.0V, IW = 480 A (Note 7) -0.5 0.25 +0.5 LSb 10 k 8-bit 5.5V, IW = 450 A -1.0 +0.25 +1.0 LSb 3.0V, IW = 240 A (Note 7) -0.375 0.25 +0.375 LSb 7-bit 5.5V, IW = 450 A -0.75 +0.5 +0.75 LSb 3.0V, IW = 240 A (Note 7) -0.5 0.25 +0.5 LSb 50 k 8-bit 5.5V, IW = 90 A -0.5 0.25 +0.5 LSb 3.0V, IW = 48 A (Note 7) -0.375 0.25 +0.375 LSb 7-bit 5.5V, IW = 90 A -0.375 0.25 +0.375 LSb 3.0V, IW = 48 A (Note 7) -0.5 0.25 +0.5 LSb 100 k 8-bit 5.5V, IW = 45 A -0.5 0.25 +0.5 LSb 3.0V, IW = 24 A (Note 7) -0.375 0.25 +0.375 LSb 7-bit 5.5V, IW = 45 A -0.375 0.25 +0.375 LSb 3.0V, IW = 24 A (Note 7) CAW -- 75 -- pF f =1 MHz, Code = Full Scale Capacitance (PA) Capacitance (Pw) CW -- 120 -- pF f =1 MHz, Code = Full Scale Capacitance (PB) CBW -- 75 -- pF f =1 MHz, Code = Full Scale Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at VW with VA = VDD and VB = VSS. 3: MCP44X1 only. 4: MCP44X2 only, includes VWZSE and VWFSE. 5: Resistor terminals A, W and B's polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification. (c) 2010 Microchip Technology Inc. -0.5 -1.0 0.25 +0.5 +0.5 +1.0 LSb LSb 5 k 8-bit DS22265A-page 9 MCP444X/446X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics Parameters All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym Min Typ Max Digital Inputs/Outputs (HVC/A0, A1, SDA, SCL, WP, RESET) Schmitt Trigger VIH 0.45 VDD -- -- High Input Threshold 0.5 VDD -- -- Units V V Conditions All Inputs except SDA and SCL 2.7V VDD 5.5V (Allows 2.7V Digital VDD with 5V Analog VDD) 1.8V VDD 2.7V -- 0.7 VDD -- 0.7 VDD 0.7 VDD -- 0.7 VDD -- -- -- -0.5 -- -0.5 -- -0.5 -- -0.5 -- -- 0.1VDD N.A. -- N.A. -- 0.1 VDD -- 0.05 VDD -- 0.1 VDD -- 0.1 VDD -- 9.0 -- VMAX V 100 kHz SDA VMAX V 400 kHz and VMAX V 1.7 MHz SCL VMAX V 3.4 Mhz Schmitt Trigger VIL 0.2VDD V All inputs except SDA and SCL Low Input 0.3VDD V 100 kHz SDA 400 kHz Threshold 0.3VDD V and 0.3VDD V SCL 1.7 MHz 0.3VDD V 3.4 Mhz Hysteresis of VHYS -- V All inputs except SDA and SCL Schmitt Trigger -- V VDD < 2.0V 100 kHz Inputs -- V VDD 2.0V SDA -- V VDD < 2.0V and 400 kHz -- V VDD 2.0V SCL -- V 1.7 MHz -- V 3.4 Mhz High Voltage Input VIHHEN 12.5 V Threshold for WiperLock Technology Entry Voltage (Note 6) -- -- VDD + High Voltage Input VIHHEX V 0.8V Exit Voltage (Note 6) -- -- 12.5 V Pin can tolerate VMAX or less. High Voltage Limit VMAX (Note 6) VSS -- 0.2VDD V VDD < 2.0V, IOL = 1 mA, Output Low VOL Voltage (SDA) VSS -- 0.4 V VDD 2.0V, IOL = 3 mA Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at VW with VA = VDD and VB = VSS. 3: MCP44X1 only. 4: MCP44X2 only, includes VWZSE and VWFSE. 5: Resistor terminals A, W and B's polarity with respect to each other is not restricted. 6: This specification by design. 7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification. DS22265A-page 10 (c) 2010 Microchip Technology Inc. MCP444X/446X AC/DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) DC Characteristics Parameters Weak Pull-up Current All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym Min Typ Max Units IPU -- -- 1.75 mA -- -- 170 16 -- -- A k Internal VDD pull-up, VIHH pull-down, VDD = 5.5V, VHVC = 12.5V HVC pin, VDD = 5.5V, VHVC = 3V VDD = 5.5V, VHVC = 3V -- 16 -- k VDD = 5.5V, VRESET = 0V -1 -- 1 A -- 10 -- pF VIN = VDD (all pins) and VIN = VSS (all pins except RESET) fC = 20 MHz 0h 0h -- -- 1FF 1FFh 1FFh hex hex hex 8-bit device 7-bit device All Terminals connected -- 0h 1M -- 080h 040h 000h -- 1FFh Cycles hex hex hex hex HVC Pull-up / RHVC Pull-down Resistance RESET Pull-up RRESET Resistance Input Leakage IIL Current Pin Capacitance CIN, COUT RAM (Wiper, TCON) Value Value Range N TCON POR/BOR Setting EEPROM Endurance EEPROM Range Initial NV Wiper POR/BOR Setting Initial EEPROM POR/BOR Setting EEPROM Programming Write Cycle Time Power Requirements Power Supply Sensitivity (MCP44X1) Endurance N N N Conditions 8-bit 7-bit WiperLock Technology = Off WiperLock Technology = Off VDD = 2.7V to 5.5V, VA = 2.7V, Code = 80h VDD = 2.7V to 5.5V, VA = 2.7V, Code = 40h tWC -- 3 10 ms PSS -- 0.0015 0.0035 %/% 8-bit -- 0.0015 0.0035 %/% 7-bit Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. MCP44X1 only. MCP44X2 only, includes VWZSE and VWFSE. Resistor terminals A, W and B's polarity with respect to each other is not restricted. This specification by design. Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. 8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested. 9: POR/BOR is not rate dependent. 10: Supply current is independent of current through the resistor network. 11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification. Note 1: 2: 3: 4: 5: 6: 7: (c) 2010 Microchip Technology Inc. DS22265A-page 11 MCP444X/446X I2C Mode Timing Waveforms and Requirements 1.1 RESET tRST SCL tRSTD VIH VIH SDA Wx FIGURE 1-1: TABLE 1-1: RESET Waveforms. RESET TIMING Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (extended) Timing Characteristics Parameters All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices. Typical specifications represent values for VDD = 5.5V, TA = +25C. Sym Min Typ Max Units RESET pulse width tRST 50 -- -- ns RESET rising edge normal mode (Wiper driving and I2C interface operational) tRSTD -- -- 20 ns DS22265A-page 12 Conditions (c) 2010 Microchip Technology Inc. MCP444X/446X VIHH HVC/A0 VIH 94 or VIL 95 SCL VIH or VIL 93 91 90 92 SDA STOP Condition START Condition I2C Bus Start/Stop Bits Timing Waveforms. FIGURE 1-2: TABLE 1-2: I2C BUS START/STOP BITS REQUIREMENTS I2C AC Characteristics Param. Symbol No. FSCL D102 90 91 92 93 94 95 Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (Extended) Operating Voltage VDD range is described in AC/DC characteristics Characteristic Standard Mode Fast Mode High-Speed 1.7 High-Speed 3.4 Cb Bus capacitive 100 kHz mode loading 400 kHz mode 1.7 MHz mode 3.4 MHz mode TSU:STA START condition 100 kHz mode Setup time 400 kHz mode 1.7 MHz mode 3.4 MHz mode THD:STA START condition 100 kHz mode Hold time 400 kHz mode 1.7 MHz mode 3.4 MHz mode 100 kHz mode TSU:STO STOP condition Setup time 400 kHz mode 1.7 MHz mode 3.4 MHz mode THD:STO STOP condition 100 kHz mode Hold time 400 kHz mode 1.7 MHz mode 3.4 MHz mode THVCSU HVC to SCL Setup time THVCHD SCL to HVC Hold time (c) 2010 Microchip Technology Inc. Min Max Units 0 0 0 0 -- -- -- -- 4700 600 160 160 4000 600 160 160 4000 600 160 160 4000 600 160 160 25 25 100 400 1.7 3.4 400 400 400 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- kHz kHz MHz MHz pF pF pF pF ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns uS uS Conditions Cb = 400 pF, 1.8V - 5.5V Cb = 400 pF, 2.7V - 5.5V Cb = 400 pF, 4.5V - 5.5V Cb = 100 pF, 4.5V - 5.5V Only relevant for repeated START condition After this period the first clock pulse is generated High Voltage Commands High Voltage Commands DS22265A-page 13 MCP444X/446X 103 102 100 101 SCL 90 106 91 92 107 SDA In 110 109 109 SDA Out I2C Bus Data Timing. FIGURE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE) TABLE 1-3: I2C AC Characteristics Param. No. Sym Characteristic 100 THIGH Clock high time 101 Note 1: 2: 3: 4: 5: 6: 7: TLOW Clock low time Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (Extended) Operating Voltage VDD range is described in AC/DC characteristics Min Max Units 100 kHz mode 4000 -- ns 1.8V-5.5V 400 kHz mode 600 -- ns 2.7V-5.5V 1.7 MHz mode 120 ns 4.5V-5.5V 3.4 MHz mode 60 -- ns 4.5V-5.5V 100 kHz mode 4700 -- ns 1.8V-5.5V 400 kHz mode 1300 -- ns 2.7V-5.5V ns 4.5V-5.5V -- ns 4.5V-5.5V 1.7 MHz mode 320 3.4 MHz mode 160 Conditions As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. The MCP44X1/MCP44X2 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. Use Cb in pF for the calculations. Not Tested. A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. Ensured by the TAA 3.4 MHz specification test. DS22265A-page 14 (c) 2010 Microchip Technology Inc. MCP444X/446X TABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED) I2C AC Characteristics Param. No. Sym 102A (5) TRSCL 102B (5) 103A 103B (5) (5) 106 Note 1: 2: 3: 4: 5: 6: 7: TRSDA TFSCL TFSDA THD:DAT Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (Extended) Operating Voltage VDD range is described in AC/DC characteristics Characteristic SCL rise time SDA rise time SCL fall time SDA fall time Data input hold time Min Max Units Conditions 100 kHz mode -- 1000 ns 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10 to 400 pF (100 pF maximum for 3.4 MHz mode) 1.7 MHz mode 20 80 ns 1.7 MHz mode 20 160 ns 3.4 MHz mode 10 40 ns 3.4 MHz mode 10 80 ns After a Repeated Start condition or an Acknowledge bit 100 kHz mode -- 1000 ns Cb is specified to be from 10 to 400 pF (100 pF max for 3.4 MHz mode) 400 kHz mode 20 + 0.1Cb 300 ns 1.7 MHz mode 20 160 ns 3.4 MHz mode 10 80 ns 100 kHz mode -- 300 ns 400 kHz mode 20 + 0.1Cb 300 ns 1.7 MHz mode 20 80 ns 3.4 MHz mode 10 40 ns 100 kHz mode -- 300 ns 400 kHz mode 20 + 0.1Cb (4) 300 ns 1.7 MHz mode 20 160 ns 3.4 MHz mode 10 80 ns After a Repeated Start condition or an Acknowledge bit Cb is specified to be from 10 to 400 pF (100 pF max for 3.4 MHz mode) Cb is specified to be from 10 to 400 pF (100 pF max for 3.4 MHz mode) 100 kHz mode 0 -- ns 1.8V-5.5V, Note 6 400 kHz mode 0 -- ns 2.7V-5.5V, Note 6 1.7 MHz mode 0 -- ns 4.5V-5.5V, Note 6 3.4 MHz mode 0 -- ns 4.5V-5.5V, Note 6 As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. The MCP44X1/MCP44X2 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. Use Cb in pF for the calculations. Not Tested. A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. Ensured by the TAA 3.4 MHz specification test. (c) 2010 Microchip Technology Inc. DS22265A-page 15 MCP444X/446X I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED) TABLE 1-3: I2C AC Characteristics Param. No. 107 109 110 Sym 2: 3: 4: 5: 6: 7: Characteristic TSU:DAT Data input setup time TAA TBUF TSP Note 1: Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (Extended) Operating Voltage VDD range is described in AC/DC characteristics Output valid from clock Bus free time Input filter spike suppression (SDA and SCL) Min Max Units Conditions 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns 1.7 MHz mode 10 -- ns 3.4 MHz mode 10 -- ns 100 kHz mode -- 3450 ns 400 kHz mode -- 900 ns 1.7 MHz mode -- 150 ns Cb = 100 pF, Note 1, Note 7 -- 310 ns Cb = 400 pF, Note 1, Note 5 3.4 MHz mode -- 150 ns Cb = 100 pF, Note 1 100 kHz mode 4700 -- ns Time the bus must be free before a new transmission can start 400 kHz mode 1300 -- ns 1.7 MHz mode N.A. -- ns 3.4 MHz mode N.A. -- ns 100 kHz mode -- 50 ns 400 kHz mode -- 50 ns Note 2 Note 1 Philips Spec states N.A. 1.7 MHz mode -- 10 ns Spike suppression 3.4 MHz mode -- 10 ns Spike suppression As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. The MCP44X1/MCP44X2 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. Use Cb in pF for the calculations. Not Tested. A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. Ensured by the TAA 3.4 MHz specification test. DS22265A-page 16 (c) 2010 Microchip Technology Inc. MCP444X/446X TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND. Parameters Sym Min Typ Max Units Specified Temperature Range TA -40 -- +125 C Operating Temperature Range TA -40 -- +125 C Storage Temperature Range TA -65 -- +150 C Thermal Resistance, 14L-TSSOP JA -- 100 -- C/W Thermal Resistance, 20L-QFN JA -- 43 -- C/W Thermal Resistance, 20L-TSSOP JA -- 90 -- C/W Conditions Temperature Ranges Thermal Package Resistances (c) 2010 Microchip Technology Inc. DS22265A-page 17 MCP444X/446X NOTES: DS22265A-page 18 (c) 2010 Microchip Technology Inc. MCP444X/446X 2.0 TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: 250 550 500 450 400 350 300 250 200 150 100 50 0 200 1.7MHz, 5.5V 1.7MHz, 4.5V 400kHz, 5.5V 100kHz, 5.5V IHVC 150 100 50 400kHz, 2.7V IHVC (A) 3.4MHz, 4.5V RHVC 100kHz, 2.7V 0 -40 0 40 80 Temperature (C) 120 FIGURE 2-1: Device Current (IDD) vs. I2C Frequency (fSCL) and Ambient Temperature (VDD = 2.7V and 5.5V). 2 3 4 5 6 7 VHVC (V) 8 9 10 FIGURE 2-4: HVC/A0 Pull-up/Pull-down Resistance (RHVC) and Current (IHVC) vs. HVC/ A0 Input Voltage (VHVC) (VDD = 5.5V). 3.0 12.0 2.5 HVC/A0 Threshold (V) Standby Current (ISHDN) (A) 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 3.4MHz, 5.5V RHVC (kOhms) IDD (A) Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. 5.5V 2.0 1.5 2.7V 1.0 0.5 0.0 10.0 5.5V Entry 8.0 6.0 2.7V Entry 5.5V Exit 2.7V Exit 4.0 2.0 0.0 -40 0 40 80 Ambient Temperature (C) 120 FIGURE 2-2: Device Current (ISHDN) and VDD. (HVC/A0 = VDD) vs. Ambient Temperature. -40 0 40 80 Ambient Temperature (C) 120 FIGURE 2-5: HVC/A0 High Input Entry/ Exit Threshold vs. Ambient Temperature and VDD. EE Write Current (IWRITE) (A) 500 400 5.5V 300 200 2.7V 100 0 -40 0 40 80 Ambient Temperature (C) 120 FIGURE 2-3: Write Current (IWRITE) vs. Ambient Temperature and VDD. (c) 2010 Microchip Technology Inc. DS22265A-page 19 MCP444X/446X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. 0.3 0.2 0.1 80 0 60 -0.1 125C 20 0 -0.2 RW -40C 25C 85C 260 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL DNL 180 0 140 RW 100 -0.1 125C 60 -40C 25C 85C 20 -0.2 -0.3 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-7: 5 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). DS22265A-page 20 -0.25 40 85C 25C DNL -40C -0.75 RW -1.25 32 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-8: 5 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL 6 INL 220 0.1 0.75 60 260 0.2 1.25 0.25 300 0.3 INL 220 125C Rw 125C INL 125C DNL 80 0 Error (LSb) Wiper Resistance (RW) (ohms) -40C Rw -40C INL -40C DNL 85C Rw 85C INL 85C DNL 20 FIGURE 2-6: 5 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 300 25C Rw 25C INL 25C DNL INL 125C -0.3 64 96 128 160 192 224 256 Wiper Setting (decimal) 32 -40C Rw -40C INL -40C DNL 100 INL DNL 40 120 Error (LSb) 125C Rw 125C INL 125C DNL 4 180 2 140 RW Error (LSb) 85C Rw 85C INL 85C DNL Wiper Resistance (RW) (ohms) 100 25C Rw 25C INL 25C DNL Wiper Resistance (RW) (ohms) -40C Rw -40C INL -40C DNL Error (LSb) Wiper Resistance (RW) (ohms) 120 100 0 -40C 60 125C 20 0 32 85C 25C DNL -2 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-9: 5 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). (c) 2010 Microchip Technology Inc. MCP444X/446X 5300 6000 5250 5000 Resistance () Nominal Resistance (RAB) (Ohms) Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. 2.7V 5200 5150 5100 4000 3000 2000 -40C +25C +85C +125C 1000 5.5V 5050 0 -40 0 40 80 Ambient Temperature (C) 120 FIGURE 2-10: 5 k - Nominal Resistance (RAB) () vs. Ambient Temperature and VDD. 0 32 64 96 128 160 Wiper Code 192 224 256 FIGURE 2-11: 5 k - RWB () vs. Wiper Setting and Ambient Temperature (VDD = 5.5V, IW = 190 A). 6000 Resistance () 5000 4000 3000 2000 -40C +25C +85C +125C 1000 0 0 32 64 96 128 160 Wiper Code 192 224 256 FIGURE 2-12: 5 k - RWB () vs. Wiper Setting and Ambient Temperature (VDD = 3.0V, IW = 190 A). (c) 2010 Microchip Technology Inc. DS22265A-page 21 MCP444X/446X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. 2.50% CH0 CH2 52 50 PPM / C 1.50% Error % 54 -40C +25C +85C +125C 0.50% -0.50% CH1 CH3 48 46 44 -1.50% 42 40 -2.50% 0 32 64 96 128 160 192 224 0 256 32 64 Wiper Code FIGURE 2-13: 5 k - Worst Case RBW from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting and Temperature (VDD = 5.5V, IW = 190 A). 2.50% 224 256 100 CH0 CH2 95 90 PPM / C Error % 192 FIGURE 2-15: 5 k - RWB PPM/C vs. Wiper Setting. (RBW(code=n, 125C)-RBW(code=n, 40C) )/RBW(code = 256, 25C)/165C * 1,000,000) (VDD = 5.5V, IW = 190 A). -40C +25C +85C +125C 1.50% 96 128 160 Wiper Code 0.50% -0.50% CH1 CH3 85 80 75 70 -1.50% 65 60 -2.50% 0 32 64 96 128 160 192 224 256 Wiper Code FIGURE 2-14: 5 k - Worst Case RBW from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting and Temperature (VDD = 3.0V, IW = 190 A). DS22265A-page 22 0 32 64 96 128 160 Wiper Code 192 224 256 FIGURE 2-16: 5 k - RWB PPM/C vs. Wiper Setting. (RBW(code=n, 125C)-RBW(code=n, 40C) )/RBW(code = 256, 25C)/165C * 1,000,000) (VDD = 3.0V, IW = 190 A). (c) 2010 Microchip Technology Inc. MCP444X/446X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. FIGURE 2-17: 5 k - Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 s/Div). FIGURE 2-20: 5 k - Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 s/Div). FIGURE 2-18: 5 k - Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 s/Div). FIGURE 2-21: 5 k - Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 s/Div). FIGURE 2-19: 5 k - Power-Up Wiper Response Time (20 ms/Div). (c) 2010 Microchip Technology Inc. DS22265A-page 23 MCP444X/446X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. 125C Rw 125C INL 125C DNL INL DNL 0.3 0.2 0.1 80 0 60 -0.1 40 25C -40C 125C 85C 120 100 -0.2 RW 20 0 40 220 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL INL DNL 0.1 180 0 140 100 RW 60 -40C 25C 125C 85C 20 0 32 300 0.3 0.2 -0.1 -0.2 -0.3 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-23: 10 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). DS22265A-page 24 32 85C 25C RW -40C DNL -0.5 -1 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-24: 10 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). Wiper Resistance (RW) (ohms) 260 25C Rw 25C INL 25C DNL 1 60 0 Error (LSb) Wiper Resistance (RW) (ohms) -40C Rw -40C INL -40C DNL 125C Rw 125C INL 125C DNL 80 20 FIGURE 2-22: 10 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 85C Rw 85C INL 85C DNL 0.5 125C -0.3 25C Rw 25C INL 25C DNL INL 0 25 50 75 100 125 150 175 200 225 250 Wiper Setting (decimal) 300 -40C Rw -40C INL -40C DNL Error (LSb) 85C Rw 85C INL 85C DNL -40C Rw -40C INL -40C DNL 260 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL 4 3 INL 220 2 180 1 140 0 100 -40C 60 DNL RW Error (LSb) 100 25C Rw 25C INL 25C DNL Wiper Resistance (RW) (ohms) -40C Rw -40C INL -40C DNL Error (LSb) Wiper Resistance (RW) (ohms) 120 -1 125C 85C 25C 20 -2 0 25 50 75 100 125 150 175 200 225 250 Wiper Setting (decimal) FIGURE 2-25: 10 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). (c) 2010 Microchip Technology Inc. MCP444X/446X 10250 12000 10200 10000 Resistance () Nominal Resistance (RAB) (Ohms) Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. 10150 2.7V 10100 5.5V 10050 8000 6000 4000 -40C +25C +85C +125C 2000 10000 -40 0 40 80 Ambient Temperature (C) 0 120 FIGURE 2-26: 10 k - Nominal Resistance (RAB) () vs. Ambient Temperature and VDD. 0 32 64 96 128 160 Wiper Code 192 224 256 FIGURE 2-27: 10 k - RWB () vs. Wiper Setting and Ambient Temperature (VDD = 5.5V, IW = 150 A). 12000 Resistance () 10000 8000 6000 4000 -40C +25C +85C +125C 2000 0 0 32 64 96 128 160 Wiper Code 192 224 256 FIGURE 2-28: 10 k - RWB () vs. Wiper Setting and Ambient Temperature (VDD = 3.0V, IW = 150 A). (c) 2010 Microchip Technology Inc. DS22265A-page 25 MCP444X/446X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. 1.50% -40C +85C 1.00% 45 40 PPM / C 0.50% Error % 50 +25C +125C 0.00% -0.50% 35 30 25 20 -1.00% CH0 CH2 15 10 -1.50% 0 32 64 96 128 160 192 224 0 256 32 64 Wiper Code FIGURE 2-29: 10 k - Worst Case RBW from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting and Temperature (VDD = 5.5V, IW = 150 A). 1.50% -40C +85C 1.00% 96 128 160 Wiper Code 192 224 256 FIGURE 2-31: 10 k - RWB PPM/C vs. Wiper Setting. (RBW(code=n, 125C)-RBW(code=n, 40C) )/RBW(code = 256, 25C)/165C * 1,000,000) (VDD = 5.5V, IW = 150 A). 60 +25C +125C 55 50 PPM / C 0.50% Error % CH1 CH3 0.00% -0.50% 45 40 35 30 -1.00% CH0 CH2 25 CH1 CH3 20 -1.50% 0 32 64 96 128 160 192 224 256 Wiper Code FIGURE 2-30: 10 k - Worst Case RBW from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting and Temperature (VDD = 3.0V, IW = 150 A). DS22265A-page 26 0 32 64 96 128 160 Wiper Code 192 224 256 FIGURE 2-32: 10 k - RWB PPM/C vs. Wiper Setting. (RBW(code=n, 125C)-RBW(code=n, 40C) )/RBW(code = 256, 25C)/165C * 1,000,000) (VDD = 3.0V, IW = 150 A). (c) 2010 Microchip Technology Inc. MCP444X/446X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. FIGURE 2-33: 10 k - Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 s/Div). FIGURE 2-35: 10 k - Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 s/Div). FIGURE 2-34: 10 k - Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 s/Div). FIGURE 2-36: 10 k - Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 s/Div). (c) 2010 Microchip Technology Inc. DS22265A-page 27 MCP444X/446X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. INL DNL 0.3 0.2 0.1 80 0 60 -0.1 40 125C 25C 85C 20 0 -40C 120 100 -0.2 RW -0.3 64 96 128 160 192 224 256 Wiper Setting (decimal) 32 260 220 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL INL DNL 180 0 140 RW 100 -40C 60 125C 85C 25C 20 0 32 -0.1 -0.2 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-38: 50 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). DS22265A-page 28 -0.1 40 85C 25C 125C 32 -40C RW -0.2 -0.3 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-39: 50 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL INL 125C Rw 125C INL 125C DNL 1 0.75 0.5 DNL 0.25 180 0 140 RW 100 -0.25 -0.5 -40C 60 125C -0.3 0.1 0 220 0.1 0.2 60 260 0.2 0.3 125C Rw 125C INL 125C DNL DNL 300 0.3 85C Rw 85C INL 85C DNL 80 0 Error (LSb) Wiper Resistance (RW) (ohms) -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL INL 20 FIGURE 2-37: 50 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 300 -40C Rw -40C INL -40C DNL Error (LSb) 125C Rw 125C INL 125C DNL Error (LSb) 85C Rw 85C INL 85C DNL Wiper Resistance (RW) (ohms) 100 25C Rw 25C INL 25C DNL Wiper Resistance (RW) (ohms) -40C Rw -40C INL -40C DNL Error (LSb) Wiper Resistance (RW) (ohms) 120 85C 25C 20 0 32 64 -0.75 -1 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-40: 50 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). (c) 2010 Microchip Technology Inc. MCP444X/446X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. 60000 50600 50000 50400 50200 Resistance () Nominal Resistance (RAB) (Ohms) 50800 2.7V 50000 5.5V 49800 49600 40000 30000 20000 -40C +25C +85C +125C 10000 49400 -40 0 40 80 Ambient Temperature (C) 0 120 FIGURE 2-41: 50 k - Nominal Resistance (RAB) () vs. Ambient Temperature and VDD. 0 32 64 96 128 160 Wiper Code 192 224 256 FIGURE 2-42: 50 k - RWB () vs. Wiper Setting and Ambient Temperature (VDD = 5.5V, IW = 90 A). 60000 Resistance () 50000 40000 30000 -40C +25C +85C +125C 20000 10000 0 0 32 64 96 128 160 Wiper Code 192 224 256 FIGURE 2-43: 50 k - RWB () vs. Wiper Setting and Ambient Temperature (VDD = 3.0V, IW = 48 A). (c) 2010 Microchip Technology Inc. DS22265A-page 29 MCP444X/446X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. 7.00% -40C +85C 6.00% +25C +125C 4.00% PPM / C Error % 5.00% 3.00% 2.00% 1.00% 0.00% -1.00% 0 32 64 96 128 160 192 224 7 6 5 4 3 2 1 0 -1 -2 -3 CH0 CH2 0 256 32 CH1 CH3 64 Wiper Code FIGURE 2-44: 50 k - Worst Case RBW from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting and Temperature (VDD = 5.5V, IW = 90 A). 192 224 256 FIGURE 2-46: 50 k - RWB PPM/C vs. Wiper Setting. (RBW(code=n, 125C)-RBW(code=n, 40C) )/RBW(code = 256, 25C)/165C * 1,000,000) (VDD = 5.5V, IW = 90 A). 12 4.00% -40C +85C 3.00% +25C +125C 10 8 PPM / C 2.00% Error % 96 128 160 Wiper Code 1.00% 0.00% 6 4 2 CH0 CH2 0 -1.00% CH1 CH3 -2 -2.00% 0 32 64 96 128 160 192 224 256 Wiper Code FIGURE 2-45: 50 k - Worst Case RBW from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting and Temperature (VDD = 3.0V, IW = 48 A). DS22265A-page 30 0 32 64 96 128 160 Wiper Code 192 224 256 FIGURE 2-47: 50 k - RWB PPM/C vs. Wiper Setting. (RBW(code=n, 125C)-RBW(code=n, 40C) )/RBW(code = 256, 25C)/165C * 1,000,000) (VDD = 3.0V, IW = 48 A). (c) 2010 Microchip Technology Inc. MCP444X/446X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. FIGURE 2-48: 50 k - Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 s/Div). FIGURE 2-50: 50 k - Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 s/Div). FIGURE 2-49: 50 k - Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 s/Div). FIGURE 2-51: 50 k - Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 s/Div). (c) 2010 Microchip Technology Inc. DS22265A-page 31 MCP444X/446X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. 125C Rw 125C INL 125C DNL 0.2 DNL 0 60 -0.1 40 25C -40C -40C Rw -40C INL -40C DNL 100 0.1 INL 80 120 RW -0.2 64 96 128 160 192 224 256 Wiper Setting (decimal) 32 -40C Rw -40C INL -40C DNL 260 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL INL 220 DNL 125C Rw 125C INL 125C DNL -0.1 40 -40C 0.1 0.05 180 0 140 RW 60 -40C 125C 85C 25C 20 0 32 -0.1 -0.15 -0.2 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-53: 100 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). DS22265A-page 32 32 -0.2 -0.3 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-54: 100 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL INL 220 -0.05 100 RW 125C 85C 25C 260 0.15 0.1 0 300 0.2 Error (LSb) Wiper Resistance (RW) (ohms) 300 0.2 60 0 FIGURE 2-52: 100 k Pot Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 0.3 125C Rw 125C INL 125C DNL DNL 80 20 Wiper Resistance (Rw) (ohms) 0 85C Rw 85C INL 85C DNL INL 125C 85C 20 25C Rw 25C INL 25C DNL Error (LSb) 85C Rw 85C INL 85C DNL 0.6 0.4 0.2 DNL 180 0 140 RW 100 60 -40C -0.2 Error (LSb) 100 25C Rw 25C INL 25C DNL Wiper Resistance (RW) (ohms) -40C Rw -40C INL -40C DNL Error (LSb) Wiper Resistance (RW) (ohms) 120 -0.4 125C 85C 25C 20 -0.6 0 32 64 96 128 160 192 224 256 Wiper Setting (decimal) FIGURE 2-55: 100 k Rheo Mode - RW (), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 3.0V). (c) 2010 Microchip Technology Inc. MCP444X/446X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. 120000 100000 101000 100500 Resistance () Nominal Resistance (RAB) (Ohms) 101500 2.7V 100000 5.5V 99500 80000 60000 -40C +25C +85C +125C 40000 20000 99000 -40 0 40 80 Ambient Temperature (C) 0 120 FIGURE 2-56: 100 k - Nominal Resistance (RAB) () vs. Ambient Temperature and VDD . 0 32 64 96 128 160 Wiper Code 192 224 256 FIGURE 2-57: 100 k - RWB () vs. Wiper Setting and Ambient Temperature (VDD = 5.5V, IW = 45 A). 120000 Resistance () 100000 80000 60000 40000 -40C +25C +85C +125C 20000 0 0 32 64 96 128 160 Wiper Code 192 224 256 FIGURE 2-58: 100 k - RWB () vs. Wiper Setting and Ambient Temperature (VDD = 3.0V, IW = 24 A). (c) 2010 Microchip Technology Inc. DS22265A-page 33 MCP444X/446X 14.00% 13.00% 12.00% 11.00% 10.00% 9.00% 8.00% 7.00% 6.00% 5.00% 4.00% 3.00% 2.00% 1.00% 0.00% -1.00% -40C +85C 16 +25C +125C 14 12 PPM / C Error % Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. 10 8 6 4 CH0 CH2 2 0 0 32 64 96 128 160 192 224 0 256 32 64 Wiper Code FIGURE 2-59: 100 k - Worst Case RBW from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting and Temperature (VDD = 5.5V, IW = 45 A). 7.00% -40C +85C 6.00% 2.00% 224 256 16 14 PPM / C 3.00% 192 18 +25C +125C 4.00% 96 128 160 Wiper Code FIGURE 2-61: 100 k - RWB PPM/C vs. Wiper Setting. (RBW(code=n, 125C)-RBW(code=n, 40C) )/RBW(code = 256, 25C)/165C * 1,000,000) (VDD = 5.5V, IW = 45 A). 5.00% Error % CH1 CH3 12 10 8 6 1.00% 4 0.00% 2 CH0 CH2 CH1 CH3 0 -1.00% 0 32 64 96 128 160 192 224 256 Wiper Code FIGURE 2-60: 100 k - Worst Case RBW from Average RBW (RBW0-RBW3) Error (%) vs. Wiper Setting and Temperature (VDD = 3.0V, IW = 24 A). DS22265A-page 34 0 32 64 96 128 160 Wiper Code 192 224 256 FIGURE 2-62: 100 k - RWB PPM/C vs. Wiper Setting. (RBW(code=n, 125C)-RBW(code=n, 40C) )/RBW(code = 256, 25C)/165C * 1,000,000) (VDD = 3.0V, IW = 24 A). (c) 2010 Microchip Technology Inc. MCP444X/446X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. FIGURE 2-63: 100 k - Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V) (1 s/Div). FIGURE 2-65: 100 k - Low-Voltage Increment Wiper Settling Time (VDD = 2.7V) (1 s/Div). FIGURE 2-64: 100 k - Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V) (1 s/Div). FIGURE 2-66: 100 k - Low-Voltage Increment Wiper Settling Time (VDD = 5.5V) (1 s/Div). (c) 2010 Microchip Technology Inc. DS22265A-page 35 MCP444X/446X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. 4 3.5 5.5V VOL (mV) VIH (V) 3 2.5 2 2.7V 1.5 230 210 2.7V 190 170 150 130 5.5V 110 90 70 50 1 -40 0 40 80 120 Temperature (C) FIGURE 2-67: Temperature. -40 0 40 80 120 Temperature (C) VIH (SDA, SCL) vs. VDD and FIGURE 2-69: VOL (SDA) vs. VDD and Temperature (IOL = 3 mA). 2 VIL (V) 5.5V 1.5 2.7V 1 -40 0 40 80 120 Temperature (C) FIGURE 2-68: Temperature. DS22265A-page 36 VIL (SDA, SCL) vs. VDD and (c) 2010 Microchip Technology Inc. MCP444X/446X Note: Unless otherwise indicated, TA = +25C, VDD = 5V, VSS = 0V. 2.1 Test Circuits 4.5 4.0 tWC (ms) 3.5 +5V 2.7V A VIN 3.0 2.5 5.5V 2.0 -40 0 40 80 Temperature (C) B Offset GND 1.5 1.6 + VOUT - 2.5V DC 120 FIGURE 2-70: Nominal EEPROM Write Cycle Time vs. VDD and Temperature. W FIGURE 2-72: Test. -3 db Gain vs. Frequency 1.4 VDD (V) 1.2 floating VA A 1.0 0.8 0.6 VW W 0.4 IW 0.2 0.0 -40 0 FIGURE 2-71: and Temperature. 40 80 Temperature (C) 120 B VB RBW = VW/IW RW = (VW-VA)/IW POR/BOR Trip point vs. VDD (c) 2010 Microchip Technology Inc. FIGURE 2-73: RBW and RW Measurement. DS22265A-page 37 MCP444X/446X NOTES: DS22265A-page 38 (c) 2010 Microchip Technology Inc. MCP444X/446X 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. Additional descriptions of the device pins follows. TABLE 3-1: PINOUT DESCRIPTION FOR THE MCP444X/446X Pin TSSOP Symbol I/O Buffer Type Weak Pull-up/ down (Note 1) QFN Standard Function 14L 20L 20L -- 1 19 P3A A Analog No Potentiometer 3 Terminal A 1 2 20 P3W A Analog No Potentiometer 3 Wiper Terminal 1 P3B A Analog No Potentiometer 3 Terminal B I HV w/ST "smart" 2 3 3 4 2 HVC/A0 4 5 3 SCL I HV w/ST No I2C Clock Input 5 6 4 SDA I HV w/ST No I2C Serial Data I/O. Open Drain output 6 7 5 VSS -- P -- Ground 7 8 6 P1B A Analog No Potentiometer 1 Terminal B 8 9 7 P1W A Analog No Potentiometer 1 Wiper Terminal -- 10 8 P1A A Analog No Potentiometer 1 Terminal A A Analog No Potentiometer 0 Terminal A High Voltage Command / I2C Address 0 -- 11 9 P0A 9 12 10 P0W A Analog No Potentiometer 0 Wiper Terminal 10 13 11 P0B A Analog No Potentiometer 0 Terminal B -- 14 12 WP I HV w/ST "smart" 13 RESET I HV w/ST Yes I HV w/ST "smart" -- 15 Hardware EEPROM Write Protect Hardware Reset Pin 11 16 14 A1 12 17 15 VDD -- P -- Positive Power Supply Input 13 18 16 P2B A Analog No Potentiometer 2 Terminal B A Analog No Potentiometer 2 Wiper Terminal I2C Address 1 14 19 17 P2W -- 20 18 P2A A Analog No Potentiometer 2 Terminal A -- -- 21 EP -- -- -- Exposed Pad. (Note 2) Legend: Note 1: 2: HV w/ST = High Voltage tolerant input (with Schmidtt trigger input) A = Analog pins (Potentiometer terminals) I = digital input (high Z) O = digital output I/O = Input / Output P = Power The pin's "smart" pull-up shuts off while the pin is forced low. This is done to reduce the standby and shut-down current. The QFN package has a contact on the bottom of the package. This contact is conductively connected to the die substrate, and therefore should be unconnected or connected to the same ground as the device's VSS pin. (c) 2010 Microchip Technology Inc. DS22265A-page 39 MCP444X/446X 3.1 High Voltage Command / Address 0 (HVC/A0) The HVC/A0 pin is the Address 0 input for the I2C interface as well as the High Voltage Command pin. At the device's POR/BOR the value of the A0 address bit is latched. This input along with the A1 pin completes the device address. This allows up to 4 MCP44XX devices to be on a single I2C bus. 3.7 Potentiometer Terminal A The terminal A pin is available on the MCP44X1 devices, and is connected to the internal potentiometer's terminal A. The potentiometer's terminal A is the fixed connection to the Full Scale wiper value of the digital potentiometer. This corresponds to a wiper value of 0x100 for 8-bit devices or 0x80 for 7-bit devices. During normal operation, the voltage on this pin determines whether the I2C command is a normal command or a High Voltage command (when HVC/A0 = VIHH). The terminal A pin does not have a polarity relative to the terminal W or B pins. The terminal A pin can support both positive and negative current. The voltage on terminal A must be between VSS and VDD. 3.2 The terminal A pin is not available on the MCP44X2 devices, and the internally terminal A signal is floating. Serial Clock (SCL) The SCL pin is the serial interfaces Serial Clock pin. This pin is connected to the Host Controllers SCL pin. The MCP44XX is a slave device, so its SCL pin accepts only external clock signals. 3.3 Serial Data (SDA) The SDA pin is the serial interfaces Serial Data pin. This pin is connected to the Host Controllers SDA pin. The SDA pin is an open-drain N-channel driver. 3.4 Ground (VSS) The VSS pin is the device ground reference. 3.5 Potentiometer Terminal B The terminal B pin is connected to the internal potentiometer's terminal B. The potentiometer's terminal B is the fixed connection to the Zero Scale wiper value of the digital potentiometer. This corresponds to a wiper value of 0x00 for both 7-bit and 8-bit devices. The terminal B pin does not have a polarity relative to the terminal W or A pins. The terminal B pin can support both positive and negative current. The voltage on terminal B must be between VSS and VDD. MCP44XX devices have four terminal B pins, one for each resistor network. MCP44X1 devices have four terminal A pins, one for each resistor network. Terminal A is not available on the MCP44X2 devices. 3.8 Write Protect (WP) The WP pin is used to force the nonvolatile memory to be write protected. 3.9 Reset (RESET) The RESET pin is used to force the device into the POR/BOR state. 3.10 Address 1 (A1) The A1 pin is the I2C interface's Address 1 pin. Along with the A0 pins, up to 4 MCP44XX devices can be on a single I2C bus. 3.11 Positive Power Supply Input (VDD) The VDD pin is the device's positive power supply input. The input power supply is relative to VSS. While the device VDD < Vmin (2.7V), the electrical performance of the device may not meet the data sheet specifications. 3.12 No Connect (NC) These pins should be either connected to VDD or VSS. 3.6 Potentiometer Wiper (W) Terminal The terminal W pin is connected to the internal potentiometer's terminal W (the wiper). The wiper terminal is the adjustable terminal of the digital potentiometer. The terminal W pin does not have a polarity relative to terminals A or B pins. The terminal W pin can support both positive and negative current. The voltage on terminal W must be between VSS and VDD. 3.13 Exposed Pad (EP) This pad is conductively connected to the device's substrate. This pad should be tied to the same potential as the VSS pin (or left unconnected). This pad could be used to assist as a heat sink for the device when connected to a PCB heat sink. MCP44XX devices have four terminal W pins, one for each resistor network. DS22265A-page 40 (c) 2010 Microchip Technology Inc. MCP444X/446X 4.0 FUNCTIONAL OVERVIEW This Data Sheet covers a family of four nonvolatile Digital Potentiometer and Rheostat devices that will be referred to as MCP44XX. The MCP44X1 devices are the Potentiometer configuration, while the MCP44X2 devices are the Rheostat configuration. As the Device Block Diagram shows, there are four main functional blocks. These are: * * * * POR/BOR and RESET Operation Memory Map Resistor Network Serial Interface (I2C) The POR/BOR operation and the Memory Map are discussed in this section and the Resistor Network and I2C operation are described in their own sections. The Device Commands commands are discussed in Section 7.0. 4.1 POR/BOR and RESET Operation The Power-on Reset is the case where the device is having power applied to it from VSS. The Brown-out Reset occurs when a device had power applied to it, and that power (voltage) drops below the specified range. The devices RAM retention voltage (VRAM) is lower than the POR/BOR voltage trip point (VPOR/VBOR). The maximum VPOR/VBOR voltage is less then 1.8V. When VPOR/VBOR < VDD < 2.7V, the electrical performance may not meet the data sheet specifications. In this region, the device is capable of reading and writing to its EEPROM and incrementing, decrementing, reading and writing to its volatile memory if the proper serial command is executed. When VDD < VPOR/VBOR or the RESET pin is Low, the pin weak pull-ups are enabled. 4.1.1 POWER-ON RESET When the device powers up, the device VDD will cross the VPOR/VBOR voltage. Once the VDD voltage crosses the VPOR/VBOR voltage, the following happens: * The volatile wiper register is loaded with value in the corresponding nonvolatile wiper register * The TCON registers are loaded with their default value * The device is capable of digital operation (c) 2010 Microchip Technology Inc. 4.1.2 BROWN-OUT RESET When the device powers down, the device VDD will cross the VPOR/VBOR voltage. Once the VDD voltage decreases below the VPOR/VBOR voltage, the following happens: * Serial Interface is disabled * EEPROM Writes are disabled If the VDD voltage decreases below the VRAM voltage, the following happens: * Volatile wiper registers may become corrupted * TCON registers may become corrupted As the voltage recovers above the VPOR/VBOR voltage, see Section 4.1.1 "Power-on Reset". Serial commands not completed due to a brown-out condition may cause the memory location (volatile and nonvolatile) to become corrupted. 4.1.3 RESET PIN The RESET pin can be used to force the device into the POR/BOR state of the device. When the RESET pin is forced Low, the device is forced into the reset state. This means that the TCON and STATUS registers are forced to their default values and the volatile wiper registers are loaded with the value in the corresponding Nonvolatile wiper register. Also the I2C interface is disabled. Any nonvolatile write cycle is not interrupted, and allowed to complete. This feature allows a hardware method for all registers to be updated at the same time. 4.1.4 INTERACTION OF RESET PIN AND BOR/POR CIRCUITRY Figure 4-1 shows how the RESET pin signal and the POR/BOR signal interact to control the hardware reset state of the device. RESET (from pin) Device reset POR/BOR signal FIGURE 4-1: POR/BOR Signal and RESET Pin Interaction. DS22265A-page 41 MCP444X/446X 4.2 Memory Map The device memory has 16 locations that are 9-bit wide (16x9 bits). This memory space contains both volatile and nonvolatile locations (see Table 4-1). TABLE 4-1: Address MEMORY MAP AND THE SUPPORTED COMMANDS Function Memory Type Allowed Commands Disallowed Commands (2) Factory Initialization 00h Volatile Wiper 0 RAM Read, Write, Increment, Decrement -- -- 01h Volatile Wiper 1 RAM Read, Write, Increment, Decrement -- -- 02h Nonvolatile Wiper 0 EEPROM Read, Write (1) Increment, Decrement 03h Nonvolatile Wiper 1 EEPROM Read, Write (1) Increment, Decrement 8-bit 80h 7-bit 40h 8-bit 80h 7-bit 40h 04h Volatile TCON0 Register RAM Read, Write Increment, Decrement -- 05h Status Register RAM Read Write, Increment, Decrement -- 06h Volatile Wiper 2 RAM Read, Write, Increment, Decrement -- -- 07h Volatile Wiper 3 RAM Read, Write, Increment, Decrement -- -- 08h Nonvolatile Wiper 2 EEPROM Read, Write (1) Increment, Decrement 09h Nonvolatile Wiper 3 0Ah Volatile TCON1 Register 0Bh Data EEPROM EEPROM Read, Write (1) Increment, Decrement 8-bit 80h 7-bit 40h 8-bit 80h 7-bit 40h RAM Read, Write Increment, Decrement -- EEPROM Read, Write (1) Increment, Decrement 000h (1) 0Ch Data EEPROM EEPROM Read, Write Increment, Decrement 000h 0Dh Data EEPROM EEPROM Read, Write (1) Increment, Decrement 000h (1) Increment, Decrement 000h Increment, Decrement 000h 0Eh Data EEPROM EEPROM Read, Write 0Fh Data EEPROM EEPROM Read, Write (1) Note 1: 2: When an EEPROM write is active, these are invalid commands and will generate an error condition. The user should use a read of the Status register to determine when the write cycle has completed. To exit the error condition, the user must take the HVC pin to the VIH level and then back to the active state (VIL or VIHH). This command on this address will generate an error condition. To exit the error condition, the user must take the HVC pin to the VIH level and then back to the active state (VIL or VIHH). DS22265A-page 42 (c) 2010 Microchip Technology Inc. MCP444X/446X 4.2.1 4.2.1.4 NONVOLATILE MEMORY (EEPROM) This memory can be grouped into two uses of nonvolatile memory. These are: * General Purpose Registers * Nonvolatile Wiper Registers The nonvolatile wipers start functioning below the devices VPOR/VBOR trip point. 4.2.1.1 General Purpose Registers These locations allow the user to store up to 5 (9-bit) locations worth of information. 4.2.1.2 Nonvolatile Wiper Registers These locations contain the wiper values that are loaded into the corresponding volatile wiper register whenever the device has a POR/BOR event. There are four registers, one for each resistor network. The nonvolatile wiper register enables stand-alone operation of the device (without Microcontroller control) after being programmed to the desired value. 4.2.1.3 Factory Initialization of Nonvolatile Memory (EEPROM) The Nonvolatile Wiper values will be initialized to mid-scale value. This is shown in Table 4-2. The General purpose EEPROM memory will be programmed to a default value of 0x000. It is good practice in the manufacturing flow to configure the device to your desired settings. -502 5.0 k Mid scale 80h 40h Disabled -103 10.0 k Mid scale 80h 40h Disabled -503 50.0 k Mid scale 80h 40h Disabled -104 100.0 k Mid scale 80h 40h Disabled Resistance Code Default POR Wiper Setting Wiper Code WiperLockTM Technology and Write Protect Setting DEFAULT FACTORY SETTINGS SELECTION Typical RAB Value TABLE 4-2: (c) 2010 Microchip Technology Inc. 8-bit 7-bit Special Features There are 5 nonvolatile bits that are not directly mapped into the address space. These bits control the following functions: * * * * * EEPROM Write Protect WiperLock Technology for Nonvolatile Wiper 0 WiperLock Technology for Nonvolatile Wiper 1 WiperLock Technology for Nonvolatile Wiper 2 WiperLock Technology for Nonvolatile Wiper 3 The operation of WiperLock Technology is discussed in Section 5.3. The state of the WL0, WL1, WL2, WL3, and WP bits is reflected in the STATUS register (see Register 4-1). EEPROM Write Protect All internal EEPROM memory can be Write Protected. When EEPROM memory is Write Protected, Write commands to the internal EEPROM are prevented. Write Protect (WP) can be enabled/disabled by two methods. These are: * External WP Hardware pin (MCP44X1 devices only) * Nonvolatile configuration bit (WP) High Voltage commands are required to enable and disable the nonvolatile WP bit. These commands are shown in Section 7.8 "Modify Write Protect or WiperLock Technology (High Voltage)". To write to EEPROM, both the external WP pin and the internal WP EEPROM bit must be disabled. Write Protect does not block commands to the volatile registers. 4.2.2 VOLATILE MEMORY (RAM) There are seven Volatile Memory locations. These are: * * * * * * * Volatile Wiper 0 Volatile Wiper 1 Volatile Wiper 2 Volatile Wiper 3 Status Register Terminal Control (TCON0) Register 0 Terminal Control (TCON)1 Register 1 The volatile memory starts functioning at the RAM retention voltage (VRAM). DS22265A-page 43 MCP444X/446X 4.2.2.1 Status (STATUS) Register This register contains 7 status bits. These bits show the state of the WiperLock bits, the Write Protect bit, and if an EEPROM write cycle is active. The STATUS register can be accessed via the READ commands. Register 41 describes each STATUS register bit. The STATUS register is placed at Address 05h. REGISTER 4-1: R-1 STATUS REGISTER R-1 D8:D7 R-1 WL3 R-1 (1) WL2 R-0 (1) EEWA R-x WL1 R-x (1) WL0 (1) R-1 R-x -- WP (1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 8-7 D8:D7: Reserved. Forced to "1" bit 6 WL3: WiperLock Status bit for Resistor Network 3 (Refer to Section 5.3 "WiperLock Technology" for further information) The WiperLock Technology bit (WL3) prevents the Volatile and Nonvolatile Wiper 3 addresses and the TCON1 register bits R3HW, R3A, R3W, and R3B from being written to. High Voltage commands are required to enable and disable WiperLock Technology. 1 = Wiper and TCON1 register bits R3HW, R3A, R3W, and R3B of Resistor Network 3 (Pot 3) are "Locked" (Write Protected) 0 = Wiper and TCON1 of Resistor Network 3 (Pot 3) can be modified Note: bit 5 WL2: WiperLock Status bit for Resistor Network 2 (Refer to Section 5.3 "WiperLock Technology" for further information) The WiperLock Technology bit (WL2) prevents the Volatile and Nonvolatile Wiper 2 addresses and the TCON1 register bits R2HW, R2A, R2W, and R2B from being written to. High Voltage commands are required to enable and disable WiperLock Technology. 1 = Wiper and TCON1 register bits R2HW, R2A, R2W, and R2B of Resistor Network 2 (Pot 2) are "Locked" (Write Protected) 0 = Wiper and TCON1 of Resistor Network 2 (Pot 2) can be modified Note: bit 4 Note 1: The WL3 bit always reflects the result of the last programming cycle to the nonvolatile WL3 bit. After a POR/BOR or RESET pin event, the WL3 bit is loaded with the nonvolatile WL3 bit value. The WL0 bit always reflects the result of the last programming cycle to the nonvolatile WL0 bit. After a POR/BOR or RESET pin event, the WL0 bit is loaded with the nonvolatile WL0 bit value. EEWA: EEPROM Write Active Status bit This bit indicates if the EEPROM Write Cycle is occurring. 1 = An EEPROM Write cycle is currently occurring. Only serial commands to the Volatile memory locations are allowed (addresses 00h, 01h, 04h, and 05h) 0 = An EEPROM Write cycle is NOT currently occurring Requires a High Voltage command to modify the state of this bit (for Nonvolatile devices only). This bit is not directly written, but reflects the system state (for this feature). DS22265A-page 44 (c) 2010 Microchip Technology Inc. MCP444X/446X REGISTER 4-1: bit 3 WL1: WiperLock Status bit for Resistor Network 1 (Refer to Section 5.3 "WiperLock Technology" for further information) The WiperLock Technology bit (WL1) prevents the Volatile and Nonvolatile Wiper 1 addresses and the TCON0 register bits R1HW, R1A, R1W, and R1B from being written to. High Voltage commands are required to enable and disable WiperLock Technology. 1 = Wiper and TCON0 register bits R1HW, R1A, R1W, and R1B of Resistor Network 1 (Pot 1) are "Locked" (Write Protected) 0 = Wiper and TCON0 of Resistor Network 1 (Pot 1) can be modified Note: bit 2 STATUS REGISTER (CONTINUED) The WL1 bit always reflects the result of the last programming cycle to the nonvolatile WL1 bit. After a POR/BOR or RESET pin event, the WL1 bit is loaded with the nonvolatile WL1 bit value. WL0: WiperLock Status bit for Resistor Network 0 (Refer to Section 5.3 "WiperLock Technology" for further information) The WiperLock Technology bit (WL0) prevents the Volatile and Nonvolatile Wiper 0 addresses and the TCON0 register bits R0HW, R0A, R0W, and R0B from being written to. High Voltage commands are required to enable and disable WiperLock Technology. 1 = Wiper and TCON0 register bits R0HW, R0A, R0W, and R0B of Resistor Network 0 (Pot 0) are "Locked" (Write Protected) 0 = Wiper and TCON0 of Resistor Network 0 (Pot 0) can be modified Note: The WL0 bit always reflects the result of the last programming cycle to the nonvolatile WL0 bit. After a POR/BOR or RESET pin event, the WL0 bit is loaded with the nonvolatile WL0 bit value. bit 1 Reserved: Forced to "1" bit 0 WP: EEPROM Write Protect Status bit (Refer to Section "EEPROM Write Protect" for further information) This bit indicates the status of the write protection on the EEPROM memory. When Write Protect is enabled, writes to all nonvolatile memory are prevented. This includes the General Purpose EEPROM memory, and the nonvolatile Wiper registers. Write Protect does not block modification of the volatile wiper register values or the volatile TCON0 and TCON1 register values (via Increment, Decrement, or Write commands). This status bit is an OR of the devices Write Protect pin (WP) and the internal nonvolatile WP bit. High Voltage commands are required to enable and disable the internal WP EEPROM bit. 1 = EEPROM memory is Write Protected 0 = EEPROM memory can be written Note 1: Requires a High Voltage command to modify the state of this bit (for Nonvolatile devices only). This bit is not directly written, but reflects the system state (for this feature). (c) 2010 Microchip Technology Inc. DS22265A-page 45 MCP444X/446X 4.2.2.2 Terminal Control (TCON) Registers There are two Terminal Control (TCON) Registers. These are called TCON0 and TCON1. Each register contains 8 control bits, four bits for each Wiper. Register 4-2 describes each bit of the TCON0 register, while Register 4-3 describes each bit of the TCON1 register. The state of each resistor network terminal connection is individually controlled. That is, each terminal connection (A, B and W) can be individually connected/ disconnected from the resistor network. This allows the system to minimize the currents through the digital potentiometer. DS22265A-page 46 The value that is written to the specified TCON register will appear on the appropriate resistor network terminals when the serial command has completed. When the WL1 bit is enabled, writes to the TCON0 register bits R1HW, R1A, R1W, and R1B are inhibited. When the WL0 bit is enabled, writes to the TCON0 register bits R0HW, R0A, R0W, and R0B are inhibited. When the WL3 bit is enabled, writes to the TCON1 register bits R3HW, R3A, R3W, and R3B are inhibited. When the WL2 bit is enabled, writes to the TCON1 register bits R2HW, R2A, R2W, and R2B are inhibited. On a POR/BOR these registers are loaded with 1FFh (9-bit), for all terminals connected. The Host Controller needs to detect the POR/BOR event and then update the Volatile TCON register values. (c) 2010 Microchip Technology Inc. MCP444X/446X REGISTER 4-2: TCON0 BITS (1) R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 D8 R1HW R1A R1W R1B R0HW R0A R0W R0B bit 8 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 8 D8: Reserved. Forced to "1" bit 7 R1HW: Resistor 1 Hardware Configuration Control bit This bit forces Resistor 1 into the "shutdown" configuration of the Hardware pin 1 = Resistor 1 is NOT forced to the hardware pin "shutdown" configuration 0 = Resistor 1 is forced to the hardware pin "shutdown" configuration bit 6 R1A: Resistor 1 Terminal A (P1A pin) Connect Control bit This bit connects/disconnects the Resistor 1 Terminal A to the Resistor 1 Network 1 = P1A pin is connected to the Resistor 1 Network 0 = P1A pin is disconnected from the Resistor 1 Network bit 5 R1W: Resistor 1 Wiper (P1W pin) Connect Control bit This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network 1 = P1W pin is connected to the Resistor 1 Network 0 = P1W pin is disconnected from the Resistor 1 Network bit 4 R1B: Resistor 1 Terminal B (P1B pin) Connect Control bit This bit connects/disconnects the Resistor 1 Terminal B to the Resistor 1 Network 1 = P1B pin is connected to the Resistor 1 Network 0 = P1B pin is disconnected from the Resistor 1 Network bit 3 R0HW: Resistor 0 Hardware Configuration Control bit This bit forces Resistor 0 into the "shutdown" configuration of the Hardware pin 1 = Resistor 0 is NOT forced to the hardware pin "shutdown" configuration 0 = Resistor 0 is forced to the hardware pin "shutdown" configuration bit 2 R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network 1 = P0A pin is connected to the Resistor 0 Network 0 = P0A pin is disconnected from the Resistor 0 Network bit 1 R0W: Resistor 0 Wiper (P0W pin) Connect Control bit This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network 1 = P0W pin is connected to the Resistor 0 Network 0 = P0W pin is disconnected from the Resistor 0 Network bit 0 R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network 1 = P0B pin is connected to the Resistor 0 Network 0 = P0B pin is disconnected from the Resistor 0 Network Note 1: These bits do not affect the wiper register values. (c) 2010 Microchip Technology Inc. DS22265A-page 47 MCP444X/446X REGISTER 4-3: TCON1 BITS (1) R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 D8 R3HW R3A R3W R3B R2HW R2A R2W R2B bit 8 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 8 D8: Reserved. Forced to "1" bit 7 R3HW: Resistor 3 Hardware Configuration Control bit This bit forces Resistor 3 into the "shutdown" configuration of the Hardware pin 1 = Resistor 3 is NOT forced to the hardware pin "shutdown" configuration 0 = Resistor 3 is forced to the hardware pin "shutdown" configuration bit 6 R3A: Resistor 3 Terminal A (P3A pin) Connect Control bit This bit connects/disconnects the Resistor 3 Terminal A to the Resistor 3 Network 1 = P3A pin is connected to the Resistor 3 Network 0 = P3A pin is disconnected from the Resistor 3 Network bit 5 R3W: Resistor 3 Wiper (P3W pin) Connect Control bit This bit connects/disconnects the Resistor 3 Wiper to the Resistor 3 Network 1 = P3W pin is connected to the Resistor 3 Network 0 = P3W pin is disconnected from the Resistor 3 Network bit 4 R3B: Resistor 3 Terminal B (P3B pin) Connect Control bit This bit connects/disconnects the Resistor 3 Terminal B to the Resistor 3 Network 1 = P3B pin is connected to the Resistor 3 Network 0 = P3B pin is disconnected from the Resistor 3 Network bit 3 R2HW: Resistor 2 Hardware Configuration Control bit This bit forces Resistor 2 into the "shutdown" configuration of the Hardware pin 1 = Resistor 2 is NOT forced to the hardware pin "shutdown" configuration 0 = Resistor 2 is forced to the hardware pin "shutdown" configuration bit 2 R2A: Resistor 2 Terminal A (P0A pin) Connect Control bit This bit connects/disconnects the Resistor 2 Terminal A to the Resistor 2 Network 1 = P2A pin is connected to the Resistor 2 Network 0 = P2A pin is disconnected from the Resistor 2 Network bit 1 R2W: Resistor 2 Wiper (P0W pin) Connect Control bit This bit connects/disconnects the Resistor 2 Wiper to the Resistor 2 Network 1 = P2W pin is connected to the Resistor 2 Network 0 = P2W pin is disconnected from the Resistor 2 Network bit 0 R2B: Resistor 2 Terminal B (P2B pin) Connect Control bit This bit connects/disconnects the Resistor 2 Terminal B to the Resistor 2 Network 1 = P2B pin is connected to the Resistor 2 Network 0 = P2B pin is disconnected from the Resistor 2 Network Note 1: These bits do not affect the wiper register values. DS22265A-page 48 (c) 2010 Microchip Technology Inc. MCP444X/446X 5.0 RESISTOR NETWORK 5.1 The Resistor Network has either 7-bit or 8-bit resolution. Each Resistor Network allows zero scale to full scale connections. Figure 5-1 shows a block diagram for the resistive network of a device. The Resistor Network is made up of several parts. These include: * Resistor Ladder * Wiper * Shutdown (Terminal Connections) Devices have four resistor networks. These are referred to as Pot 0, Pot 1 Pot 2, and Pot 3. A RW RS RW RS RW R RAB S 8-Bit N= 257 (1) (100h) 7-Bit N= 128 (80h) 256 (1) (FFh) 127 (7Fh) 255 (FEh) 126 (7Eh) (1) RW RS RW 1 (01h) 0 (00h) 0 (00h) (1) The resistor ladder is a series of equal value resistors (RS) with a connection point (tap) between the two resistors. The total number of resistors in the series (ladder) determines the RAB resistance (see Figure 51). The end points of the resistor ladder are connected to analog switches which are connected to the device Terminal A and Terminal B pins. The RAB (and RS) resistance has small variations over voltage and temperature. For an 8-bit device, there are 256 resistors in a string between terminal A and terminal B. The wiper can be set to tap onto any of these 256 resistors, thus providing 257 possible settings (including terminal A and terminal B). For a 7-bit device, there are 128 resistors in a string between terminal A and terminal B. The wiper can be set to tap onto any of these 128 resistors, thus providing 129 possible settings (including terminal A and terminal B). Equation 5-1 shows the calculation for the step resistance. EQUATION 5-1: W 1 (1) (01h) Resistor Ladder Module RS CALCULATION RAB RS = ------------( 256 ) 8-bit Device R AB R S = -------------( 128 ) 7-bit Device Analog Mux B Note 1: The wiper resistance is dependent on several factors including, wiper code, device VDD, Terminal voltages (on A, B, and W), and temperature. Also for the same conditions, each tap selection resistance has a small variation. This RW variation has greater effects on some specifications (such as INL) for the smaller resistance devices (5.0 k) compared to larger resistance devices (100.0 k). FIGURE 5-1: Resistor Block Diagram. (c) 2010 Microchip Technology Inc. DS22265A-page 49 MCP444X/446X 5.2 Wiper 5.3 Each tap point (between the RS resistors) is a connection point for an analog switch. The opposite side of the analog switch is connected to a common signal which is connected to the Terminal W (Wiper) pin. A value in the volatile wiper register selects which analog switch to close, connecting the W terminal to the selected node of the resistor ladder. The wiper can connect directly to Terminal B or to Terminal A. A zero scale connections, connects the Terminal W (wiper) to Terminal B (wiper setting of 000h). A full scale connection, connects the Terminal W (wiper) to Terminal A (wiper setting of 100h or 80h). In these configurations, the only resistance between the Terminal W and the other Terminal (A or B) is that of the analog switches. A wiper setting value greater than full scale (wiper setting of 100h for 8-bit device or 80h for 7-bit devices) will also be a Full Scale setting (Terminal W (wiper) connected to Terminal A). Table 5-1 illustrates the full wiper setting map. Equation 5-2 illustrates the calculation used to determine the resistance between the wiper and terminal B. EQUATION 5-2: RWB CALCULATION R AB N R WB = -------------- + R W ( 256 ) 8-bit Device N = 0 to 256 (decimal) R WB R AB N = -------------- + R W ( 128 ) 7-bit Device N = 0 to 128 (decimal) TABLE 5-1: WiperLock Technology The MCP44XX device's WiperLock technology allows application-specific calibration settings to be secured in the EEPROM without requiring the use of an additional write-protect pin. There are four WiperLock Technology configuration bits (WL0, WL1, WL2, and WL3). These bits prevent the Nonvolatile and Volatile addresses and bits for the specified resistor network from being written. The WiperLock technology prevents commands from doing the following: the serial * Changing a volatile wiper value * Writing to the specified nonvolatile wiper memory location * Changing the related volatile TCON register bits For either Resistor Network 0, Resistor Network 1, Resistor Network 2, or Resistor Network 3 (Potx), the WLx bit controls the following: * Nonvolatile Wiper Register * Volatile Wiper Register * Volatile TCON register bits RxHW, RxA, RxW, and RxB High Voltage commands are required to enable and disable WiperLock. Please refer to the Modify Write Protect or WiperLock Technology (High Voltage) command for operation. 5.3.1 POR/BOR OPERATION WHEN WIPERLOCK TECHNOLOGY ENABLED The WiperLock Technology state is not affected by a POR/BOR event. A POR/BOR event will load the Volatile Wiper register value with the Nonvolatile Wiper register value, refer to Section 4.1. VOLATILE WIPER VALUE VS. WIPER POSITION MAP Wiper Setting Properties 7-bit 8-bit 3FFh - 3FFh - Reserved (Full Scale (W = A)), 081h 101h Increment and Decrement commands ignored 080h 100h Full Scale (W = A), Increment commands ignored 07Fh - 0FFh - W = N 041h 081h 040h 080h W = N (Mid Scale) 03Fh - 07Fh - W = N 001h 001h 000h 000h Zero Scale (W = B) Decrement command ignored DS22265A-page 50 (c) 2010 Microchip Technology Inc. MCP444X/446X Shutdown Shutdown is used to minimize the device's current consumption. The MCP44XX has one method to achieve this. This is: * Terminal Control Register (TCON) This is different from the MCP42XXX devices in that the Hardware Shutdown Pin (SHDN) has been replaced by a RESET pin. The Hardware Shutdown Pin function is still available via software commands to the TCON register. 5.4.1 TERMINAL CONTROL REGISTER (TCON) The Terminal Control (TCON) register is a volatile register used to configure the connection of each resistor network terminal pin (A, B, and W) to the Resistor Network. These registers are shown in Register 4-2 and Register 4-3. The RxHW bit does NOT corrupt the values in the Volatile Wiper Registers nor the TCON register. When the Shutdown mode is exited (RxHW bit = "1"): * The device returns to the Wiper setting specified by the Volatile Wiper value * The TCON register bits return to controlling the terminal connection state A Resistor Network 5.4 W B FIGURE 5-2: Resistor Network Shutdown State (RxHW = `0'). The RxHW bits forces the selected resistor network into the same state as the MCP42X1's SHDN pin. Alternate low power configurations may be achieved with the RxA, RxW, and RxB bits. When the RxHW bit is "0": * The P0A, P1A, P2A, and P3A terminals are disconnected * The P0W, P1W, P2W, and P3W terminals are simultaneously connect to the P0B, P1B, P2B, and P3B terminals, respectively (see Figure 5-2) Note: When the RxHW bit forces the resistor network into the hardware SHDN state, the state of the TCON0 or TCON1 register's RxA, RxW, and RxB bits is overridden (ignored). When the state of the RxHW bit no longer forces the resistor network into the hardware SHDN state, the TCON0 or TCON1 register's RxA, RxW, and RxB bits return to controlling the terminal connection state. In other words, the RxHW bit does not corrupt the state of the RxA, RxW, and RxB bits. (c) 2010 Microchip Technology Inc. DS22265A-page 51 MCP444X/446X NOTES: DS22265A-page 52 (c) 2010 Microchip Technology Inc. MCP444X/446X 6.0 SERIAL INTERFACE (I2C) The MCP44XX devices support the I2C serial protocol. The MCP44XX I2C's module operates in Slave mode (does not generate the serial clock). Figure 6-1 shows a typical I2C Interface connection. All I2C interface signals are high-voltage tolerant. The MCP44XX devices use the two-wire I2C serial interface. This interface can operate in standard, fast or High-Speed mode. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access and generates the START and STOP conditions. The MCP44XX device works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. Communication is initiated by the master (microcontroller) which sends the START bit, followed by the slave address byte. The first byte transmitted is always the slave address byte, which contains the device code, the address bits, and the R/W bit. Refer to the Phillips I2C document for more details of the I2C specifications. Typical I2C Interface Connections MCP4XXX 6.1 Signal Descriptions The I2C interface uses up to four pins (signals). These are: * * * * SDA (Serial Data) SCL (Serial Clock) A0 (Address 0 bit) A1 (Address 1 bit) 6.1.1 SERIAL DATA (SDA) The Serial Data (SDA) signal is the data signal of the device. The value on this pin is latched on the rising edge of the SCL signal when the signal is an input. With the exception of the START and STOP conditions, the high or low state of the SDA pin can only change when the clock signal on the SCL pin is low. During the high period of the clock, the SDA pin's value (high or low) must be stable. Changes in the SDA pin's value while the SCL pin is HIGH will be interpreted as a START or a STOP condition. 6.1.2 SERIAL CLOCK (SCL) The Serial Clock (SCL) signal is the clock signal of the device. The rising edge of the SCL signal latches the value on the SDA pin. The MCP44XX supports three I2C interface clock modes: * Standard Mode: clock rates up to 100 kHz * Fast Mode: clock rates up to 400 kHz * High-Speed Mode (HS mode): clock rates up to 3.4 MHz Host Controller SCL SCL SDA SDA The MCP44XX will not stretch the clock signal (SCL) since memory read access occur fast enough. I/O (1) HVC/A0 (2) Depending on the clock rate mode, the interface will display different characteristics. A1 (2, 3) 6.1.3 THE ADDRESS BITS (A1:A0) Note 1: If High voltage commands are desired, some type of external circuitry needs to be implemented. There are up to two hardware pins used to specify the device address. The number of address pins is determined by the part number. 2: These pins have internal pull-ups. If faster rise times are required, then external pull-ups should be added. Address 0 is multiplexed with the High Voltage Command (HVC) function. So the state of A0 is latched on the MCP4XXX's POR/BOR event. 3: This pin could be tied high, low, or connected to an I/O pin of the Host Controller. The state of the A1 pin should be static, that is they should be tied high or tied low. FIGURE 6-1: Diagram. Typical I2C Interface Block 6.1.3.1 The High Voltage Command (HVC) Signal The High Voltage Command (HVC) signal is multiplexed with Address 0 (A0) and is used to indicate that the command, or sequence of commands, are in the High Voltage mode. High Voltage commands allow the device's WiperLock Technology and write protect features to be enabled and disabled. The HVC pin has an internal resistor connection to the MCP44XXs internal VDD signal. (c) 2010 Microchip Technology Inc. DS22265A-page 53 MCP444X/446X 6.2 I2C Operation 6.2.1.3 The MCP44XX's I2C module is compatible with the Philips I2C specification. The following lists some of the modules features: * 7-bit slave addressing * Supports three clock rate modes: - Standard mode, clock rates up to 100 kHz - Fast mode, clock rates up to 400 kHz - High-speed mode (HS mode), clock rates up to 3.4 MHz * Support Multi-Master Applications * General call addressing * Internal weak pull-ups on interface signals The I2C 10-bit addressing mode is not supported. The Philips I2C specification only defines the field types, field lengths, timings, etc. of a frame. The frame content defines the behavior of the device. The frame content for the MCP44XX is defined in Section 7.0. 6.2.1 I2C BIT STATES AND SEQUENCE Figure 6-8 shows the I2C transfer sequence. The serial clock is generated by the master. The following definitions are used for the bit states: * Start bit (S) * Data bit * Acknowledge (A) bit (driven low) / No Acknowledge (A) bit (not driven low) * Repeated Start bit (Sr) * Stop bit (P) 6.2.1.1 2nd Bit SCL S FIGURE 6-2: 6.2.1.2 Start Bit. Data Bit The SDA signal may change state while the SCL signal is Low. While the SCL signal is High, the SDA signal MUST be stable (see Figure 6-5). SDA 1st Bit SCL DS22265A-page 54 SCL FIGURE 6-4: 2nd Bit Data Bit. D0 A 8 9 Acknowledge Waveform. Not A (A) Response The A bit has the SDA signal high. Table 6-1 shows some of the conditions where the Slave Device will issue a Not A (A). If an error condition occurs (such as an A instead of A), then an START bit must be issued to reset the command state machine. MCP45XX/MCP46XX A / A RESPONSES Acknowledge Bit Response Comment General Call A Slave Address valid A Slave Address not valid A Device Memory Address and specified command (AD3:AD0 and C1:C0) are an invalid combination A After device has received address and command Communication during EEPROM write cycle A After device has received address and command, and valid conditions for EEPROM write N.A. I2C Module Resets, or a "Don't Care" if the collision occurs on the Master's "Start bit" Bus Collision Data Bit FIGURE 6-3: SDA Event The Start bit (see Figure 6-2) indicates the beginning of a data transfer sequence. The Start bit is defined as the SDA signal falling when the SCL signal is "High". 1st Bit The A bit (see Figure 6-4) is typically a response from the receiving device to the transmitting device. Depending on the context of the transfer sequence, the A bit may indicate different things. Typically the Slave device will supply an A response after the Start bit and 8 "data" bits have been received. an A bit has the SDA signal low. TABLE 6-1: Start Bit SDA Acknowledge (A) Bit Only if GCEN bit is set (c) 2010 Microchip Technology Inc. MCP444X/446X 6.2.1.4 6.2.1.5 Repeated Start Bit The Repeated Start bit (see Figure 6-5) indicates the current Master Device wishes to continue communicating with the current Slave Device without releasing the I2C bus. The Repeated Start condition is the same as the Start condition, except that the Repeated Start bit follows a Start bit (with the Data bits + A bit) and not a Stop bit. The Stop bit (see Figure 6-6) Indicates the end of the I2C Data Transfer Sequence. The Stop bit is defined as the SDA signal rising when the SCL signal is "High". A Stop bit resets the I2C interface of all MCP44XX devices. SDA A / A The Start bit is the beginning of a data transfer sequence and is defined as the SDA signal falling when the SCL signal is "High". SCL P Note 1: A bus collision during the Repeated Start condition occurs if: FIGURE 6-6: Transmit Mode. * SDA is sampled low when SCL goes from low to high. 6.2.2 * SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data "1". CLOCK STRETCHING The MCP44XX will not stretch the clock signal (SCL) since memory read access occur fast enough. 6.2.3 ABORTING A TRANSMISSION If any part of the I2C transmission does not meet the command format, it is aborted. This can be intentionally accomplished with a START or STOP condition. This is done so that noisy transmissions (usually an extra START or STOP condition) are aborted before they corrupt the device. SCL Sr = Repeated Start FIGURE 6-5: Waveform. Stop Condition Receive or "Clock Stretching" is something that the receiving Device can do, to allow additional time to "respond" to the "data" that has been received. 1st Bit SDA Stop Bit Repeat Start Condition SDA SCL S FIGURE 6-7: 1st Bit 2nd Bit 3rd Bit 4th Bit 5th Bit 6th Bit 7th Bit 8th Bit A/A P Typical 8-Bit I2C Waveform Format. SDA SCL START Condition FIGURE 6-8: Data allowed to change Data or A valid STOP Condition I2C Data States and Bit Sequence. (c) 2010 Microchip Technology Inc. DS22265A-page 55 MCP444X/446X 6.2.4 ADDRESSING The address byte is the first byte received following the START condition from the master device. The address contains four (or more) fixed bits and (up to) three user defined hardware address bits (pins A1 and A0). These 7-bits address the desired I2C device. The A6:A2 address bits are fixed to "01011" and the device appends the value of following two address pins (A1 and A0). Since there are address bits controlled by hardware pins, there may be up to four MCP44XX devices on the same I2C bus. Figure 6-9 shows the slave address byte format, which contains the seven address bits. There is also a read/ write (R/W) bit. Table 6-2 shows the fixed address for device. Hardware Address Pins The hardware address bits (A1, and A0) correspond to the logic level on the associated address pins. This allows up to eight devices on the bus. Slave Address S A6 A5 A4 A3 A2 A1 A0 R/W "0" "1" "0" "1" "1" See Table 6-2 Start bit A/A R/W bit R/W = 0 = write R/W = 1 = read A bit (controlled by slave device) A = 0 = Slave Device Acknowledges byte A = 1 = Slave Device does not Acknowledge byte FIGURE 6-9: I2C Control Byte. TABLE 6-2: Slave Address Bits in the DEVICE SLAVE ADDRESSES Device Address MCP44XX `0101 1'b + A1:A0 Note 1: Comment Supports up to 4 devices. (Note 1) A0 is used for High-Voltage commands (HVC/A0) and the value is latched at POR/BOR. These pins have a weak pull-up enabled when the VDD < VBOR. The weak pull-up utilizes the "smart" pull-up technology and exhibits the same characteristics as the High-voltage tolerant I/O structure. 6.2.5 The state of the A0 address pin is latch on POR/BOR. This is required since High Voltage commands force this pin (HVC/A0) to the VIHH level. As the device transitions from HS mode to FS mode, the slope control parameter will change from the HS specification to the FS specification. SLOPE CONTROL The MCP44XX implements slope control on the SDA output. For Fast (FS) and High-Speed (HS) modes, the device has a spike suppression and a Schmidt trigger at SDA and SCL inputs. DS22265A-page 56 (c) 2010 Microchip Technology Inc. MCP444X/446X 6.2.6 HS MODE After switching to the High-Speed mode, the next transferred byte is the I2C control byte, which specifies the device to communicate with, and any number of data bytes plus acknowledgements. The Master Device can then either issue a Repeated Start bit to address a different device (at High-Speed) or a Stop bit to return to Fast/Standard bus speed. After the Stop bit, any other Master Device (in a Multi-Master system) can arbitrate for the I2C bus. 2 The I C specification requires that a high-speed mode device must be `activated' to operate in high-speed (3.4 Mbit/s) mode. This is done by the Master sending a special address byte following the START bit. This byte is referred to as the high-speed Master Mode Code (HSMMC). The MCP44XX device does not acknowledge this byte. However, upon receiving this command, the device switches to HS mode. The device can now communicate at up to 3.4 Mbit/s on SDA and SCL lines. The device will switch out of the HS mode on the next STOP condition. See Figure 6-10 for illustration of HS mode command sequence. For more information on the HS mode, or other I2C modes, please refer to the Phillips I2C specification. The master code is sent as follows: 1. 2. 3. 6.2.6.1 START condition (S) High-Speed Master Mode Code (0000 1XXX), The XXX bits are unique to the high-speed (HS) mode Master. No Acknowledge (A) Slope Control The slope control on the SDA output is different between the Fast/Standard Speed and the High-Speed clock modes of the interface. 6.2.6.2 Pulse Gobbler The pulse gobbler on the SCL pin is automatically adjusted to suppress spikes < 10 ns during HS mode. F/S-mode HS-mode S `0 0 0 0 1 X X X'b P A Sr `Slave Address' R/W A HS Select Byte Control Byte "Data" Command/Data Byte(s) S = Start bit Sr = Repeated Start bit A = Acknowledge bit A = Not Acknowledge bit R/W = Read/Write bit P = Stop bit (Stop condition terminates HS Mode) FIGURE 6-10: A/A F/S-mode HS-mode continues Sr `Slave Address' R/W A Control Byte HS Mode Sequence. (c) 2010 Microchip Technology Inc. DS22265A-page 57 MCP444X/446X 6.2.7 GENERAL CALL The General Call is a method that the "Master" device can communicate with all other "Slave" devices. In a Multi-Master application, the other Master devices are operating in Slave mode. The General Call address has two documented formats. These are shown in Figure 6-11. We have added a MCP44XX format in this figure as well. This will allow customers to have multiple I2C Digital Potentiometers on the bus and have them operate in a synchronous fashion (analogous to the DAC Sync pin functionality). If these MCP44XX 7-bit commands conflict with other I2C devices on the bus, then the customer will need two I2C busses and ensure that the devices are on the correct bus for their desired application functionality. Dual Pot devices can not update both Pot0 and Pot1 from a single command. To address this, there are General Call commands for the Wiper 0, Wiper 1, and the TCON registers. Table 6-3 shows the General Call Commands. Three commands are specified by the I2C specification and are not applicable to the MCP44XX (so command is Not Acknowledged) The MCP44XX General Call Commands are Acknowledge. Any other command is Not Acknowledged. Note: Only one General Call command per issue of the General Call control byte. Any additional General Call commands are ignored and Not Acknowledged. DS22265A-page 58 TABLE 6-3: 7-bit Command GENERAL CALL COMMANDS Comment (1, 2, 3) `1000 00d'b Write Next Byte (Third Byte) to Volatile Wiper 0 Register `1001 00d'b Write Next Byte (Third Byte) to Volatile Wiper 1 Register `1100 00d'b Write Next Byte (Third Byte) to TCON Register `1000 010'b Increment Wiper 0 Register or `1000 011'b `1001 010'b Increment Wiper 1 Register or `1001 011'b `1000 100'b Decrement Wiper 0 Register or `1000 101'b `1001 100'b Decrement Wiper 1 Register or `1001 101'b Note 1: 2: 3: Any other code is Not Acknowledged. These codes may be used by other devices on the I2C bus. The 7-bit command always appends a "0" to form 8-bits. "d" is the D8 bit for the 9-bit write value. (c) 2010 Microchip Technology Inc. MCP444X/446X Second Byte S 0 0 0 0 0 0 0 0 A X X X X X General Call Address X X 0 A P "7-bit Command" Reserved 7-bit Commands (By I2C Specification - Philips # 9398 393 40011, Ver. 2.1 January 2000) `0000 011'b - Reset and write programmable part of slave address by hardware. `0000 010'b - Write programmable part of slave address by hardware. `0000 000'b - NOT Allowed MCP44XX 7-bit Commands `1000 01x'b - Increment Wiper 0 Register. `1001 01x'b - Increment Wiper 1 Register. `1000 10x'b - Decrement Wiper 0 Register. `1001 10x'b - Decrement Wiper 1 Register. The Following is a Microchip Extension to this General Call Format Second Byte S 0 0 0 0 0 0 0 0 A X X X X X General Call Address X d 0 Third Byte A d "7-bit Command" d d d d d d d A P "0" for General Call Command MCP44XX 7-bit Commands `1000 00d'b - Write Next Byte (Third Byte) to Volatile Wiper 0 Register. `1001 00d'b - Write Next Byte (Third Byte) to Volatile Wiper 1 Register. `1100 00d'b - Write Next Byte (Third Byte) to TCON Register. The Following is a "Hardware General Call" Format Second Byte S 0 0 0 0 0 0 0 General Call Address FIGURE 6-11: 0 A X X X X X "7-bit Command" X n occurrences of (Data + A) X 1 A X X X X X X X X A P This indicates a "Hardware General Call" MCP44XX will ignore this byte and all following bytes (and A), until a Stop bit (P) is encountered. General Call Formats. (c) 2010 Microchip Technology Inc. DS22265A-page 59 MCP444X/446X NOTES: DS22265A-page 60 (c) 2010 Microchip Technology Inc. MCP444X/446X 7.0 DEVICE COMMANDS The MCP44XX's I2C command formats are specified in this section. The I2C protocol does not specify how commands are formatted. The MCP44XX supports four basic commands. The location accessed determines the commands that are supported. For the Volatile Wiper Registers, these commands are: * * * * For the Nonvolatile wiper EEPROM, general purpose data EEPROM, and the TCON Register, these commands are: * Write Data * Read Data These commands have formats for both a single command or continuous commands. These commands are shown in Table 7-1. Each command has two operational states. The operational state determines if the device commands control the special features (Write Protect and WiperLock Technology). These operational states are referred to as: * Normal Serial Commands * High-Voltage Serial Commands I2C COMMANDS Command Operation Mode Write Data Single Read Data Single Continuous # of Bit Clocks (1) 29 18n + 11 29 Random Continuous (3) Continuous Decrement (3) 2: 3: Operates on Volatile/ Nonvolatile memory Both Volatile Only Both Both Both (2) 20 Volatile Only 9n + 11 Volatile Only 20 Volatile Only 9n + 11 Volatile Only Single Continuous Note 1: 48 18n + 11 Single Increment Additionally, there are two commands used to enable or disable the special features (Write Protect and Wiper Lock Technology) of the device. The commands are special cases of the Increment and Decrement High-Voltage Serial Command. Table 7-2 shows the supported commands for each memory location. Write Data Read Data Increment Data Decrement Data TABLE 7-1: Normal serial commands are those where the HVC pin is driven to VIH or VIL. With High-Voltage Serial Commands, the HVC pin is driven to VIHH. In each mode, there are four possible commands. "n" indicates the number of times the command operation is to be repeated. This command is useful to determine if a nonvolatile memory write cycle has completed. High Voltage Increment and Decrement commands on select nonvolatile memory locations enable/disable WiperLock Technology and the software Write Protect feature. (c) 2010 Microchip Technology Inc. Table 7-3 shows an overview of all the device commands and their interaction with other device features. 7.1 Command Byte The MCP44XX's Command Byte has three fields: the Address, the Command Operation, and 2 Data bits (see Figure 7-1). Currently only one of the data bits is defined (D8). The device memory is accessed when the Master sends a proper Command Byte to select the desired operation. The memory location getting accessed is contained in the Command Byte's AD3:AD0 bits. The action desired is contained in the Command Byte's C1:C0 bits, see Figure 7-1. C1:C0 determines if the desired memory location will be read, written, Incremented (wiper setting +1) or Decremented (wiper setting -1). The Increment and Decrement commands are only valid on the volatile wiper registers, and in High Voltage commands to enable/disable WiperLock Technology and Software Write Protect. If the Address bits and Command bits are not a valid combination, then the MCP44XX will generate a Not Acknowledge pulse to indicate the invalid combination. The I2C Master device must then force a Start Condition to reset the MCP44XX's I2C module. D9 and D8 are the most significant bits for the digital potentiometer's wiper setting. The 8-bit devices utilize D8 as their MSb while the 7-bit devices utilize D7 (from the data byte) as their MSb. COMMAND BYTE A A A A A C C D D A D D D D 1 0 9 8 3 2 1 0 MSbits (Data) MCP4XXX Memory Address Command Operation bits 00 = Write Data 01 = Increment 10 = Decrement 11 = Read Data FIGURE 7-1: Command Byte Format. DS22265A-page 61 MCP444X/446X TABLE 7-2: MEMORY MAP AND THE SUPPORTED COMMANDS Address Function Volatile Wiper 0 Value 00h Command Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn Increment Wiper Decrement Wiper 01h Volatile Wiper 1 NV Wiper 0 03h NV Wiper 1 -- nn nnnn nnnn Read Data (3) nn nnnn nnnn Decrement Wiper -- -- Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn High Voltage Increment -- Wiper Lock 0 Disable (4) High Voltage Decrement -- Wiper Lock 0 Enable (5) Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn High Voltage Increment -- Wiper Lock 1 Disable (4) High Voltage Decrement -- Wiper Lock 1 Enable (5) 04h (2) Volatile TCON 0 Register Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn 05h (2) Read Data (3) nn nnnn nnnn Write Data Read Data (3) nn nnnn nnnn nn nnnn nnnn Status Register Volatile Wiper 2 06h Increment Wiper Decrement Wiper 07h Volatile Wiper 3 Write Data Read Data (3) Increment Wiper Decrement Wiper 08h NV Wiper 2 Write Data Read Data (3) High Voltage Increment High Voltage Decrement 09h NV Wiper 3 0Ah (2) Volatile TCON 1 Register 0Bh (2) Data EEPROM Write Data Read Data (3) -- -- nn nnnn nnnn nn nnnn nnnn -- -- nn nnnn nnnn nn nnnn nnnn -- Wiper Lock 2 Disable (4) -- Wiper Lock 2 Enable (5) nn nnnn nnnn nn nnnn nnnn High Voltage Increment -- Wiper Lock 3 Disable (4) High Voltage Decrement -- Wiper Lock 3 Enable (5) Write Data Read Data (3) nn nnnn nnnn nn nnnn nnnn Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn 0Ch (2) Data EEPROM Write Data Read Data (3) nn nnnn nnnn nn nnnn nnnn 0Dh (2) Data EEPROM Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn Write Data Read Data (3) nn nnnn nnnn nn nnnn nnnn 0Eh (2) Data EEPROM 0Fh Note Data EEPROM 1: 2: 3: 4: 5: Comment -- Write Data Increment Wiper 02h Data (10-bits) (1) Write Data nn nnnn nnnn Read Data (3) nn nnnn nnnn High Voltage Increment -- Write Protect Disable (4) High Voltage Decrement -- Write Protect Enable (5) The Data Memory is only 9-bits wide, so the MSb is ignored by the device. Increment or Decrement commands are invalid for these addresses. I2C read operation will read 2 bytes, of which the 10-bits of data are contained within. Disables WiperLock Technology for wiper 0, wiper 1, wiper 2, wiper3, or disables Write Protect. Enables WiperLock Technology for wiper 0, wiper 1, wiper 2, wiper3, or enables Write Protect. DS22265A-page 62 (c) 2010 Microchip Technology Inc. MCP444X/446X 7.2 Data Byte 7.3 Only the Read Command and the Write Command have Data Byte(s). The Write command concatenates the 8 bits of the Data Byte with the one data bit (D8) contained in the Command Byte to form 9 bits of data (D8:D0). The Command Byte format supports up to 9 bits of data so that the 8-bit resistor network can be set to Full-Scale (100h or greater). This allows wiper connections to Terminal A and to Terminal B. The D9 bit is currently unused. Error Condition If the four address bits received (AD3:AD0) and the two command bits received (C1:C0) are a valid combination, the MCP44XX will Acknowledge the I2C bus. If the address bits and command bits are an invalid combination, then the MCP44XX will Not Acknowledge the I2C bus. Once an error condition has occurred, any following commands are ignored until the I2C bus is reset with a Start Condition. 7.3.1 ABORTING A TRANSMISSION A Restart or Stop condition in the expected data bit position will abort the current command sequence and data will not be written to the MCP44XX. TABLE 7-3: COMMANDS Command Name Writes Operates on Volatile/ Value in Nonvolatile memory EEPROM High Voltage (VIHH) on HVC pin? Impact on WiperLock or Write Protect Works when Wiper is "locked"? Write Data Yes (1) Both -- unlocked (1) No Read Data -- Both -- unlocked (1) No (1) No No Increment Wiper -- Volatile Only -- unlocked Decrement Wiper -- Volatile Only -- unlocked (1) High Voltage Write Data Yes Both Yes unchanged No High Voltage Read Data -- Both Yes unchanged Yes High Voltage Increment Wiper -- Volatile Only Yes unchanged No High Voltage Decrement Wiper -- Volatile Only Yes unchanged No Modify Write Protect or WiperLock Technology (High Voltage) - Enable -- (2) Nonvolatile Only (2) Yes locked/ protected (2) Yes Modify Write Protect or WiperLock Technology (High Voltage) - Disable -- (3) Nonvolatile Only (3) Yes unlocked/ unprotected (3) Yes Note 1: 2: 3: This command will only complete, if wiper is "unlocked" (WiperLock Technology is Disabled). If the command is executed using address 02h, 03h 08h, or 09h; that corresponding wiper is locked or if with address 0Fh, then Write Protect is enabled. If the command is executed using with address 02h, 03h 08h, or 09h; that corresponding wiper is unlocked or if with address 0Fh, then Write Protect is disabled. (c) 2010 Microchip Technology Inc. DS22265A-page 63 MCP444X/446X 7.4 Write Data Normal and High Voltage The Write Command can be issued to both the Volatile and Nonvolatile memory locations. The format of the command, see Figure 7-2, includes the I2C Control Byte, an A bit, the MCP44XX Command Byte, an A bit, the MCP44XX Data Byte, an A bit, and a Stop (or Restart) condition. The MCP44XX generates the A / A bits. A Write command to a Volatile memory location changes that location after a properly formatted Write Command and the A / A clock have been received. A Write command to a Nonvolatile memory location will only start a write cycle after a properly formatted Write Command have been received and the Stop condition has occurred. Note: 7.4.1 Writes to certain memory locations will be dependant on the state of the WiperLock Technology bits and the Write Protect bit. SINGLE WRITE TO VOLATILE MEMORY For volatile memory locations, data is written to the MCP44XX after every byte transfer (during the Acknowledge). If a Stop or Restart condition is generated during a data transfer (before the A), the data will not be written to the MCP44XX. After the A bit, the master can initiate the next sequence with a Stop or Restart condition. 7.4.3 CONTINUOUS WRITES TO VOLATILE MEMORY A continuous write mode of operation is possible when writing to the volatile memory registers (address 00h, 01h, 04h, 06h, 07h, and 0Ah). This continuous write mode allows writes without a Stop or Restart condition or repeated transmissions of the I2C Control Byte. Figure 7-3 shows the sequence for three continuous writes. The writes do not need to be to the same volatile memory address. The sequence ends with the master sending a STOP or RESTART condition. 7.4.4 CONTINUOUS WRITES TO NONVOLATILE MEMORY If a continuous write is attempted on Nonvolatile memory, the missing Stop condition will cause the command to be an error condition (A). A Start bit is required to reset the command state machine. 7.4.5 THE HIGH VOLTAGE COMMAND (HVC) SIGNAL The High Voltage Command (HVC) signal is multiplexed with Address 0 (A0) and is used to indicate that the command, or sequence of commands, are in the High Voltage operational state. High Voltage commands allow the device's WiperLock Technology and write protect features to be enabled and disabled. The HVC pin has an internal resistor connection to the MCP44XXs internal VDD signal. Refer to Figure 7-2 for the byte write sequence. 7.4.2 SINGLE WRITE TO NONVOLATILE MEMORY The sequence to write to a single nonvolatile memory location is the same as a single write to volatile memory with the exception that the EEPROM write cycle (twc) is started after a properly formatted command, including the Stop bit, is received. After the Stop condition occurs, the serial interface may immediately be re-enabled by initiating a Start condition. During an EEPROM write cycle, access to the volatile memory (addresses 00h, 01h, 04h, 05h, 06h, 07h, and 0Ah) is allowed when using the appropriate command sequence. Commands that address nonvolatile memory are ignored until the EEPROM write cycle (twc) completes. This allows the Host Controller to operate on the Volatile Wiper registers, the TCON register, and to Read the Status Register. The EEWA bit in the Status register indicates the status of an EEPROM Write Cycle. Once a write command to a Nonvolatile memory location has been received, no other commands should be received before the Stop condition occurs. Figure 7-2 shows the waveform for a single write. DS22265A-page 64 (c) 2010 Microchip Technology Inc. MCP444X/446X Write bit Variable Address Fixed Address S 0 1 0 1 1 A1 A0 0 A Device Memory Address AD AD AD AD 3 2 1 0 0 0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A P WRITE Command Control Byte Write bit Variable Address Fixed Address 1 0 1 1 A1 A0 0 A Device Memory Address 0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A WRITE Command AD AD AD AD 3 2 1 0 0 Write Data bits 0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A WRITE Command AD AD AD AD 3 2 1 0 0 Write Data bits STOP bit 0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A P WRITE Command FIGURE 7-3: Write "Data" bits Command AD AD AD AD 3 2 1 0 0 Control Byte Note: Write Data bits I2C Write Sequence. FIGURE 7-2: S 0 Write "Data" bits Command Write Data bits Only functions when writing the volatile wiper registers (AD3:AD0 = 00h, 01h, 06h, and 07h) or the TCON registers (AD3:AD0 = 04h and 0Ah) I2C Continuous Volatile Wiper Write. (c) 2010 Microchip Technology Inc. DS22265A-page 65 MCP444X/446X 7.5 Read Data Normal and High Voltage The Read Command can be issued to both the Volatile and Nonvolatile memory locations. The format of the command (see Figure 7-4), includes the Start condition, I2C Control Byte (with R/W bit set to "0"), A bit, MCP44XX Command Byte, A bit, followed by a Repeated Start bit, I2C Control Byte (with R/W bit set to "1"), and the MCP44XX transmitting the requested Data High Byte, and A bit, the Data Low Byte, the Master generating the A, and Stop condition. The I2C Control Byte requires the R/W bit equal to a logic one (R/W = 1) to generate a read sequence. The memory location read will be the last address contained in a valid write MCP44XX Command Byte or address 00h if no write operations have occurred since the device was reset (Power-on Reset or Brown-out Reset). During a write cycle (Write or High Voltage Write to a Nonvolatile memory location) the Read command can only read the Volatile memory locations. By reading the Status Register (05h), the Host Controller can determine when the write cycle has completed (via the state of the EEWA bit). Read operations initially include the same address byte sequence as the write sequence (shown in Figure 6-9). This sequence is followed by another control byte (including the Start condition and Acknowledge) with the R/W bit equal to a logic one (R/W = 1) to indicate a read. The MCP44XX will then transmit the data contained in the addressed register. This is followed by the master generating an A bit in preparation for more data, or an A bit followed by a Stop. The sequence is ended with the master generating a Stop or Restart condition. 7.5.2 CONTINUOUS READS Continuous reads allows the devices memory to be read quickly. Continuous reads are possible to all memory locations. If a nonvolatile memory write cycle is occurring, then Read commands may only access the volatile memory locations. Figure 7-6 shows the sequence for three continuous reads. For continuous reads, instead of transmitting a Stop or Restart condition after the data transfer, the master reads the next data byte. The sequence ends with the master Not Acknowledging and then sending a Stop or Restart. 7.5.3 THE HIGH VOLTAGE COMMAND (HVC) SIGNAL The High Voltage Command (HVC) signal is multiplexed with Address 0 (A0) and is used to indicate that the command, or sequence of commands, are in the High Voltage mode. High Voltage commands allow the device's WiperLock Technology and write protect features to be enabled and disabled. The HVC pin has an internal resistor connection to the MCP44XX's internal VDD signal. 7.5.4 IGNORING AN I2C TRANSMISSION AND "FALLING OFF" THE BUS The MCP44XX expects to receive complete, valid I2C commands and will assume any command not defined as a valid command is due to a bus corruption and will enter a passive high condition on the SDA signal. All signals will be ignored until the next valid Start condition and Control Byte are received. The internal address pointer is maintained. If this address pointer is for a nonvolatile memory address and the read control byte addresses the device during a Nonvolatile Write Cycle (tWC) the device will respond with an A bit. 7.5.1 SINGLE READ Figure 7-4 show the waveforms for a single read. For single reads the master sends a STOP or RESTART condition after the data byte is sent from the slave. 7.5.1.1 Random Read Figure 7-5 shows the sequence for a Random Reads. Refer to Figure 7-5 for the random byte read sequence. DS22265A-page 66 (c) 2010 Microchip Technology Inc. MCP444X/446X Read bit S 0 1 STOP bit Variable Address Fixed Address 0 1 Read Data bits 1 A1 A0 1 A 0 0 0 0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A2 0 0 0 P Read bits Control Byte Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP44XX will abort this transfer and release the bus. 2: The Master Device will Not Acknowledge, and the MCP44XX will release the bus so the Master Device can generate a Stop or Repeated Start condition. 3: The MCP44XX retains the last "Device Memory Address" that it has received. This is the MCP44XX does not "corrupt" the "Device Memory Address" after Repeated Start or Stop conditions. 4: The Device Memory Address pointer defaults to 00h on POR and BOR conditions. I2C Read (Last Memory Address Accessed). FIGURE 7-4: Write bit Variable Address Fixed Address S 0 1 0 1 1 A1 A0 0 Repeated Start bit Device Memory Address A Command AD AD AD AD 3 2 1 0 1 1 x X A Sr READ Command Control Byte STOP bit Read bit 0 1 0 1 1 A1 A0 1 A 0 Control Byte Read Data bits 0 0 0 0 0 0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A2 P Read bits Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP44XX will abort this transfer and release the bus. 2: The Master Device will Not Acknowledge, and the MCP44XX will release the bus so the Master Device can generate a Stop or Repeated Start condition. 3: The MCP44XX retains the last "Device Memory Address" that it has received. This is the MCP44XX does not "corrupt" the "Device Memory Address" after Repeated Start or Stop conditions. FIGURE 7-5: I2C Random Read. (c) 2010 Microchip Technology Inc. DS22265A-page 67 MCP444X/446X Read bit Variable Address Fixed Address S 0 1 0 1 Read Data bits 0 1 A1 A0 1 A 0 0 0 0 0 0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A1 Read bits Control Byte Read Data bits 0 0 0 0 0 0 0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A1 STOP bit Read Data bits 0 0 0 0 0 0 0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A2 P Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP44XX will abort this transfer and release the bus. 2: The Master Device will Not Acknowledge, and the MCP44XX will release the bus so the Master Device can generate a Stop or Repeated Start condition. FIGURE 7-6: DS22265A-page 68 I2C Continuos Reads. (c) 2010 Microchip Technology Inc. MCP444X/446X 7.6 The advantage of using an Increment Command instead of a read-modify-write series of commands is speed and simplicity. The wiper will transition after each Command Acknowledge when accessing the volatile wiper registers. Increment Wiper Normal and High Voltage The Increment Command provides a quick and easy method to modify the potentiometer's wiper by +1 with minimal overhead. The Increment Command will only function on the volatile wiper setting memory locations 00h, 01h, 06h and 07h. The Increment Command to Nonvolatile addresses will be ignored and will generate a A. TABLE 7-4: Current Wiper Setting Table 7-4 shows the valid addresses for the Increment Wiper command. Other addresses are invalid. Note: INCREMENT OPERATION VS. VOLATILE WIPER VALUE Increment Command Operates? Wiper (W) Properties 7-bit Pot 8-bit Pot When executing an Increment Command, the volatile wiper setting will be altered from n to n+1 for each Increment Command received. The value will increment up to 100h max on 8-bit devices and 80h on 7-bit devices. If multiple Increment Commands are received after the value has reached 100h (or 80h), the value will not be incremented further. Table 7-4 shows the Increment Command versus the current volatile wiper value. 3FFh 081h 3FFh 101h Reserved No (Full-Scale (W = A)) 080h 100h Full-Scale (W = A) 07Fh 041h 0FFh 081 W=N 040h 080h W = N (Mid-Scale) 03Fh 001h 07Fh 001 W=N The Increment Command will most commonly be performed on the Volatile Wiper locations until a desired condition is met. The value in the Volatile Wiper register would need to be read using a Read operation in order to write the new setting to the corresponding Nonvolatile wiper memory using a Write operation. The MCP44XX is responsible for generating the A bits. 000h 000h Zero Scale (W = B) Yes 7.6.1 Note: The command sequence can go from an increment to any other valid command for the specified address. Issuing an increment or decrement to a nonvolatile location will cause an error condition (A will be generated). Fixed Address S 0 1 0 1 Write bit Variable Address 1 A1 A0 0 Control Byte A Device Memory Address Yes THE HIGH VOLTAGE COMMAND (HVC) SIGNAL The High Voltage Command (HVC) signal is multiplexed with Address 0 (A0) and is used to indicate that the command, or sequence of commands, are in the High Voltage mode. Signals > VIHH (~8.5V) on the HVC/A0 pin puts MCP44XX devices into High Voltage mode. High Voltage commands allow the device's WiperLock Technology and write protect features to be enabled and disabled. Refer to Figure 7-7 for the Increment Command sequence. The sequence is terminated by the Stop condition. So when executing a continuous command string, the Increment command can be followed by any other valid command. This means that writes do not need to be to the same volatile memory address. Note: No There is a required delay after the HVC pin is driven to the VIHH level to the 1st edge of the SCL pin. The HVC pin has an internal resistor connection to the MCP44XX's internal VDD signal. Command AD AD AD AD 3 2 1 0 0 1 x AD AD AD AD X A 4 3 2 1 0 INCR Command (n+1) 1 x X A P (2) INCR Command (n+2) Note1: Increment Command (INCR) only functions when accessing the volatile wiper registers (AD3:AD0 = 00h, 01h, 06h, and 07h). 2: This command sequence does not need to terminate (using the Stop bit) and can change to any other desired command sequence (Increment, Read, or Write). FIGURE 7-7: I2C Increment Command Sequence. (c) 2010 Microchip Technology Inc. DS22265A-page 69 MCP444X/446X 7.7 Decrement Wiper Normal and High Voltage The Decrement Command provides a quick and easy method to modify the potentiometer's wiper by -1 with minimal overhead. The Decrement Command will only function on the volatile wiper setting memory locations 00h and 01h. Decrement Commands to Nonvolatile addresses will be ignored and will generate an A bit. Note: The advantage of using a Decrement Command instead of a read-modify-write series of commands is speed and simplicity. The wiper will transition after each Command Acknowledge when accessing the volatile wiper registers. TABLE 7-5: Current Wiper Setting Table 7-5 shows the valid addresses for the Decrement Wiper command. Other addresses are invalid. When executing a Decrement Command, the volatile wiper setting will be altered from n to n-1 for each Decrement Command received. The value will decrement down to 000h min. If multiple Decrement Commands are received after the value has reached 000h, the value will not be decremented further. Table 7-5 shows the Increment Command versus the current volatile wiper value. The Decrement Command will most commonly be performed on the Volatile Wiper locations until a desired condition is met. The value in the Volatile Wiper register would need to be read using a Read operation in order to write the new setting to the corresponding Nonvolatile wiper memory using a Write operation. The MCP44XX is responsible for generating the A bits. Refer to Figure 7-8 for the Decrement Command sequence. The sequence is terminated by the Stop condition. So when executing a continuous command string, the Increment command can be followed by any other valid command. This means that writes do not need to be to the same volatile memory address. Note: The command sequence can go from an increment to any other valid command for the specified address. Issuing an increment or decrement to a nonvolatile location will cause an error condition (A will be generated). Fixed Address S 0 1 0 1 Write bit Variable Address 1 A1 A0 0 A Control Byte DECREMENT OPERATION VS. VOLATILE WIPER VALUE Wiper (W) Properties Decrement Command Operates? 7-bit Pot 8-bit Pot 3FFh 081h 3FFh 101h Reserved No (Full-Scale (W = A)) 080h 100h Full-Scale (W = A) 07Fh 041h 0FFh 081 W=N 040h 080h W = N (Mid-Scale) 03Fh 001h 07Fh 001 W=N 000h 000h Zero Scale (W = B) No 7.7.1 Yes Yes THE HIGH VOLTAGE COMMAND (HVC) SIGNAL The High Voltage Command (HVC) signal is multiplexed with Address 0 (A0) and is used to indicate that the command, or sequence of commands, are in the High Voltage mode. Signals > VIHH (~8.5V) on the HVC/A0 pin puts MCP44XX devices into High Voltage mode. High Voltage commands allow the device's WiperLock Technology and write protect features to be enabled and disabled. Note: There is a required delay after the HVC pin is driven to the VIHH level to the 1st edge of the SCL pin. The HVC pin has an internal resistor connection to the MCP44XX's internal VDD signal. Device Memory Address Command AD AD AD AD 3 2 1 0 1 AD AD AD AD 0 X X A 4 3 2 1 1 DECR Command (n-1) 0 X X A P (2) DECR Command (n-2) Note1: Decrement Command (DECR) only functions when accessing the volatile wiper registers (AD3:AD0 = 00h, 01h, 06h, and 07h). 2: This command sequence does not need to terminate (using the Stop bit) and can change to any other desired command sequence (INCR, Read, or Write). FIGURE 7-8: DS22265A-page 70 I2C Decrement Command Sequence. (c) 2010 Microchip Technology Inc. MCP444X/446X 7.8 Modify Write Protect or WiperLock Technology (High Voltage) Enable and Disable These commands are special cases of the High Voltage Decrement Wiper and the High Voltage Increment Wiper commands to the nonvolatile memory locations 02h, 03h, 08h, 09h, and 0Fh. This command is used to enable or disable either the software Write Protect, wiper 0 WiperLock Technology, wiper 1 WiperLock Technology, wiper 2 WiperLock Technology, or wiper 3 WiperLock Technology. Table 76 shows the memory addresses, the High Voltage command and the result of those commands on the nonvolatile WP, WL0, or WL1 bits. TABLE 7-6: 7.8.1 SINGLE MODIFY (ENABLE OR DISABLE) WRITE PROTECT OR WIPERLOCK TECHNOLOGY (HIGH VOLTAGE) Figure 7-9 (Disable) and Figure 7-10 (Enable) show the formats for a single Modify Write Protect or Wiper-Lock Technology command. A Modify Write Protect or WiperLock Technology Command will only start an EEPROM write cycle (twc) after a properly formatted Command has been received and the Stop condition occurs. During an EEPROM write cycle, only serial commands to Volatile memory (addresses 00h, 01h, 04h, and 05h) are accepted. All other serial commands are ignored until the EEPROM write cycle (twc) completes. This allows the Host Controller to operate on the Volatile Wiper registers and the TCON register, and to Read the Status Register. The EEWA bit in the Status register indicates the status of an EEPROM Write Cycle. ADDRESS MAP TO MODIFY WRITE PROTECT AND WIPERLOCK TECHNOLOGY Commands and Results Memory Address High Voltage Decrement Wiper High Voltage Increment Wiper 00h Wiper 0 register is decremented Wiper 0 register is incremented 01h Wiper 1 register is decremented Wiper 1 register is incremented 02h WL0 is enabled WL0 is disabled 03h WL1 is enabled WL1 is disabled TCON0 register not changed TCON0 register not changed STATUS register not changed STATUS register not changed 06h Wiper 2 register is decremented Wiper 2 register is incremented 07h Wiper 3 register is decremented Wiper 3 register is incremented 08h WL2 is enabled WL2 is disabled 09h WL3 is enabled WL3 is disabled TCON1 register not changed TCON1 register not changed Reserved Reserved WP is enabled WP is disabled 04h (1) 05h 0Ah (1) (1) 0Bh - 0Eh (1) 0Fh Note 1: Reserved addresses: Increment or Decrement commands are invalid for these addresses. (c) 2010 Microchip Technology Inc. DS22265A-page 71 MCP444X/446X Write bit Variable Address Fixed Address S 0 1 0 1 1 A1 A0 0 A Device Memory Address AD AD AD AD 3 2 1 0 0 FIGURE 7-9: Disable Command Sequence. Write bit Variable Address Fixed Address S 0 1 0 1 1 A1 A0 0 A Device Memory Address DS22265A-page 72 Command (Decrement) AD AD AD AD 3 2 1 0 1 Control Byte FIGURE 7-10: 1 X X A P Disable Command Control Byte I2C Command (Increment) 0 X X A P Enable Command 2 I C Enable Command Sequence. (c) 2010 Microchip Technology Inc. MCP444X/446X 8.0 APPLICATIONS EXAMPLES Nonvolatile digital potentiometers have a multitude of practical uses in modern electronic circuits. The most popular uses include precision calibration of set point thresholds, sensor trimming, LCD bias trimming, audio attenuation, adjustable power supplies, motor control overcurrent trip setting, adjustable gain amplifiers and offset trimming. The MCP44XX devices can be used to replace the common mechanical trim pot in applications where the operating and terminal voltages are within CMOS process limitations (VDD = 2.7V to 5.5V). 8.1 Techniques to Force the HVC/A0 Pin to VIHH The circuit in Figure 8-1 shows a method using the TC1240A doubling charge pump. When the SHDN pin is high, the TC1240A is off, and the level on the HVC/ A0 pin is controlled by the PIC(R) microcontrollers (MCUs) IO2 pin. When the SHDN pin is low, the TC1240A is on and the VOUT voltage is 2 * VDD. The resistor R1 allows the HVC/A0 pin to go higher than the voltage such that the PIC MCU's IO2 pin "clamps" at approximately VDD. PIC MCU TC1240A C+ VIN CSHDN IO2 R1 GP0 is a general purpose I/O pin, while GP2 can either be a general purpose I/O pin or it can output the internal clock. For the serial commands, configure the GP2 pin as an input (high impedance). The output state of the GP0 pin will determine the voltage on the HVC/A0 pin (VIL or VIH). For high-voltage serial commands, force the GP0 output pin to output a high level (VOH) and configure the GP2 pin to output the internal clock. This will form a charge pump and increase the voltage on the CS pin (when the system voltage is approximately 5V). PIC10F206 R1 GP0 MCP4XXX C1 VOUT IO1 The circuit in Figure 8-2 shows the method used on the MCP402X Nonvolatile Digital Potentiometer Evaluation Board (Part Number: MCP402XEV). This method requires that the system voltage be approximately 5V. This ensures that when the PIC10F206 enters a brownout condition, there is an insufficient voltage level on the HVC/A0 pin to change the stored value of the wiper. The MCP402X Nonvolatile Digital Potentiometer Evaluation Board User's Guide (DS51546) contains a complete schematic. GP2 HVC/A0 C1 MCP4XXX HVC/A0 C2 C2 FIGURE 8-2: MCP4XXX Nonvolatile Digital Potentiometer Evaluation Board (MCP402XEV) implementation to generate the VIHH voltage. FIGURE 8-1: Using the TC1240A to Generate the VIHH Voltage. (c) 2010 Microchip Technology Inc. DS22265A-page 73 MCP444X/446X 8.2 Using Shutdown Modes Figure 8-3 shows a possible application circuit where the independent terminals could be used. Disconnecting the wiper allows the transistor input to be taken to the Bias voltage level (disconnecting A and or B may be desired to reduce system current). Disconnecting Terminal A modifies the transistor input by the RBW rheostat value to the Common B. Disconnecting Terminal B modifies the transistor input by the RAW rheostat value to the Common A. The Common A and Common B connections could be connected to VDD and VSS. 8.3 Software Reset Sequence Note: This technique is documented in AN1028. At times, it may become necessary to perform a Software Reset Sequence to ensure the MCP44XX device is in a correct and known I2C Interface state. This technique only resets the I2C state machine. This is useful if the MCP44XX device powers up in an incorrect state (due to excessive bus noise, etc), or if the Master Device is reset during communication. Figure 8-4 shows the communication sequence to software reset the device. S `1' `1' `1' `1' `1' `1' `1' `1' S P Common A Nine bits of `1' Start bit Start bit Input A Stop bit FIGURE 8-4: Format. To base of Transistor (or Amplifier) W B Input Common B Balance Bias FIGURE 8-3: Example Application Circuit using Terminal Disconnects. Software Reset Sequence The 1st Start bit will cause the device to reset from a state in which it is expecting to receive data from the Master Device. In this mode, the device is monitoring the data bus in Receive mode and can detect the Start bit forces an internal Reset. The nine bits of `1' are used to force a Reset of those devices that could not be reset by the previous Start bit. This occurs only if the MCP44XX is driving an A bit on the I2C bus, or is in output mode (from a Read command) and is driving a data bit of `0' onto the I2C bus. In both of these cases, the previous Start bit could not be generated due to the MCP44XX holding the bus low. By sending out nine `1' bits, it is ensured that the device will see a A bit (the Master Device does not drive the I2C bus low to acknowledge the data sent by the MCP44XX), which also forces the MCP44XX to reset. The 2nd Start bit is sent to address the rare possibility of an erroneous write. This could occur if the Master Device was reset while sending a Write command to the MCP44XX, AND then as the Master Device returns to normal operation and issues a Start condition while the MCP44XX is issuing an Acknowledge. In this case, if the 2nd Start bit is not sent (and the Stop bit was sent) the MCP44XX could initiate a write cycle. Note: The potential for this erroneous write ONLY occurs if the Master Device is reset while sending a Write command to the MCP44XX. The Stop bit terminates the current I2C bus activity. The MCP44XX waits to detect the next Start condition. This sequence does not effect any other I2C devices which may be on the bus, as they should disregard this as an invalid command. DS22265A-page 74 (c) 2010 Microchip Technology Inc. MCP444X/446X 8.4 Figure 8-5 shows two I2C bus configurations. In many cases, the single I2C bus configuration will be adequate. For applications that do not want all the MCP44XX devices to do General Call support or have a conflict with General Call commands, the multiple I2C bus configuration would be used. Using the General Call Command The use of the General Call Address Increment, Decrement, or Write commands is analogous to the "Load" feature (LDAC pin) on some DACs (such as the MCP4921). This allows all the devices to "Update" the output level "at the same time". For some applications, the ability to update the wiper values "at the same time" may be a requirement, since they delay from writing to one wiper value and then the next may cause application issues. A possible example would be a "tuned" circuit that uses several MCP44XX in rheostat configuration. As the system condition changes (temperature, load, etc.) these devices need to be changed (incremented/decremented) to adjust for the system change. These changes will either be in the same direction or in opposite directions. With the Potentiometer device, the customer can either select the PxB terminals (same direction) or the PxA terminal(s) (opposite direction). Single I2C Bus Configuration Device 1 Host Controller Device 4 Device 2 Multiple I2C Bus Configuration Device 1a Device 3a Device na Host Bus a Controller Figure 8-6 shows that the update of six devices takes 6*TI2CDLY time in "normal" operation, but only 1*TI2CDLY time in "General Call" operation. Note: Device n Device 3 Device 4a Device 2a The application system may need to partition the I2C bus into multiple busses to ensure that the MCP44XX General Call commands do not conflict with the General Call commands that the other I2C devices may have defined. Also if only a portion of the MCP44XX devices are to require this synchronous operation, then the devices that should not receive these commands should be on the second I2C bus. Device 1b Device 3b Device nb Bus b Device 4b Device 2b Device 1n Device 3n Device nn Bus n Device 2n FIGURE 8-5: Configurations. Device 4n Typical Application I2C Bus Normal Operation INC POT01 TI2CDLY INC POT02 TI2CDLY INC POT03 TI2CDLY INC POT04 TI2CDLY INC POT05 TI2CDLY INC POT06 TI2CDLY General Call Operation INC POTs 01-06 TI2CDLY INC POTs 01-06 TI2CDLY INC POTs 01-06 TI2CDLY INC POTs 01-06 TI2CDLY INC POTs 01-06 TI2CDLY INC POTs 01-06 TI2CDLY TI2CDLY = Time from one I2C command completed to completing the next I2C command. FIGURE 8-6: Updates. Example Comparison of "Normal Operation" vs. "General Call Operation" Wiper (c) 2010 Microchip Technology Inc. DS22265A-page 75 MCP444X/446X 8.5 Implementing Log Steps with a Linear Digital Potentiometer In audio volume control applications, the use of logarithmic steps is desirable since the human ear hears in a logarithmic manner. The use of a linear potentiometer can approximate a log potentiometer, but with fewer steps. An 8-bit potentiometer can achieve fourteen 3 dB log steps plus a 100% (0 dB) and a mute setting. Figure 8-7 shows a block diagram of one of the MCP44x1 resistor networks being used to attenuate an input signal. In this case, the attenuation will be ground referenced. Terminal B can be connected to a common mode voltage, but the voltages on the A, B and Wiper terminals must not exceed the MCP44x1's VDD/VSS voltage limits. MCP44X1 P0A P0W EQUATION 8-1: dB CALCULATIONS (VOLTAGE) L = 20 * log10 (VOUT / VIN) dB -3 -2 -1 EQUATION 8-2: VOUT / VIN Ratio 0.70795 0.79433 0.89125 dB CALCULATIONS (RESISTANCE) - CASE 1 Terminal B connected to Ground (see Figure 8-7) L = 20 * log10 (RBW / RAB) EQUATION 8-3: dB CALCULATIONS (RESISTANCE) - CASE 2 Terminal B through RB2GND to Ground L = 20 * log10 ( (RBW + RB2GND) / (RAB + RB2GND) ) P0B FIGURE 8-7: Signal Attenuation Block Diagram - Ground Referenced. Equation 8-1 shows the equation to calculate voltage dB gain ratios for the digital potentiometer, while Equation 8-2 shows the equation to calculate resistance dB gain ratios. These two equations assume that the B terminal is connected to ground. If terminal B is not directly resistively connected to ground, then this terminal B to ground resistance (RB2GND) must be included into the calculation. Equation 8-3 shows this equation. DS22265A-page 76 Table 8-1 shows the codes that can be used for 8-bit digital potentiometers to implement the log attenuation. The table shows the wiper codes for -3 dB, -2 dB, and -1 dB attenuation steps. This table also shows the calculated attenuation based on the wiper code's linear step. Calculated attenuation values less than the desired attenuation are shown with red text. At lower wiper code values, the attenuation may skip a step, if this occurs the next attenuation value is colored magenta to highlight that a skip occurred. For example, in the -3 dB column the -48 dB value is highlighted since the -45 dB step could not be implemented (there are no wiper codes between 2 and 1). (c) 2010 Microchip Technology Inc. MCP444X/446X TABLE 8-1: LINEAR TO LOG ATTENUATION FOR 8-BIT DIGITAL POTENTIOMETERS -3 dB Steps # of Steps -2 dB Steps -1 dB Steps Calculated Calculated Calculated Desired Wiper Desired Wiper Desired Wiper Attenuation Attenuation Attenuation Attenuation Code Attenuation Code Attenuation Code (1) (1) (1) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Note 1: 0 dB -3 dB -6 dB -9dB -12 dB -15 dB -18 dB -21 dB -24 dB -27 dB -30 dB -33 dB -36 dB -39 dB -42 dB -48 dB Mute 256 181 128 91 64 46 32 23 16 11 8 6 4 3 2 1 0 0 dB 256 0 dB -1 dB 228 -1.006 dB -2 dB 203 -2.015 dB -3 dB 181 -3.011 dB -4 dB 162 -3.975 dB -5 dB 144 -4.998 dB -6 dB 128 -6.021 dB -7 dB 114 -7.027 dB -8 dB 102 -7.993 dB -9 dB 91 -8.984 dB -10 dB 81 -9.995 dB -11 dB 72 -11.018 dB -12 dB 64 -12.041 dB -13 dB 57 -13.047 dB -14 dB 51 -14.013 dB -15 dB 46 - 14.910 dB -16 dB 41 -15.909 dB -17 dB 36 -17.039 dB -18 dB 32 -18.062 dB -19 dB 29 -18.917 dB -20 dB 26 -19.865 dB -21 dB 23 - 20.930 dB -22 dB 20 -22.144 dB -23 dB 18 -23.059 dB -24 dB 16 -24.082 dB -25 dB 14 -25.242 dB -26 dB 13 -25.886 dB -27dB 11 -27.337 dB -28 dB 10 -28.165 dB -29 dB 9 -29.080 dB -30 dB 8 -30.103 dB -31 dB 7 -31.263 dB -33 dB 6 -32.602 dB -34 dB 5 -34.185 dB -36 dB 4 -36.124 dB -39 dB 3 -38.622 dB -42 dB 2 -42.144 dB -48 dB 1 -48.165 dB Mute 0 Mute Attenuation values do not include errors from Digital Potentiometer errors, such as Full Scale Error or Zero Scale Error. (c) 2010 Microchip Technology Inc. 0 dB -3.011 dB -6.021 dB -8.984 dB -12.041 dB -14.910 dB -18.062 dB -20.930 dB -24.082 dB -27.337 dB -30.103 dB -32.602 dB -36.124 dB -38.622 dB -42.144 dB -48.165 dB Mute 0 dB -2 dB -4 dB -6 dB -8 dB -10 dB -12 dB -14 dB -16 dB -18 dB -20 dB -22 dB -24 dB -26 dB -28 dB -30 dB -32 dB -34 dB -36 dB -38 dB -42 dB -48 dB Mute 256 203 162 128 102 81 64 51 41 32 26 20 16 13 10 8 6 5 4 3 2 1 0 0 dB -2.015 dB -3.975 dB -6.021 dB -7.993 dB -9.995 dB -12.041 dB -14.013 dB -15.909 dB -18.062 dB -19.865 dB -22.144 dB -24.082 dB -25.886 dB -28.165 dB -30.103 dB -32.602 dB -34.185 dB -36.124 dB -38.622 dB -42.144 dB -48.165 dB Mute DS22265A-page 77 MCP444X/446X 8.6 8.6.2 Design Considerations In the design of a system with the MCP44XX devices, the following considerations should be taken into account: LAYOUT CONSIDERATIONS Several layout considerations may be applicable to your application. These may include: * Power Supply Considerations * Layout Considerations * Noise * Footprint Compatibility * PCB Area Requirements 8.6.1 8.6.2.1 POWER SUPPLY CONSIDERATIONS The typical application will require a bypass capacitor in order to filter high-frequency noise, which can be induced onto the power supply's traces. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 8-8 illustrates an appropriate bypass strategy. In this example, the recommended bypass capacitor value is 0.1 F. This capacitor should be placed as close (within 4 mm) to the device power pin (VDD) as possible. The power source supplying these devices should be as clean as possible. If the application circuit has separate digital and analog power supplies, VDD and VSS should reside on the analog plane. VDD Noise Inductively-coupled AC transients and digital switching noise can degrade the input and output signal integrity, potentially masking the MCP44XX's performance. Careful board layout minimizes these effects and increases the Signal-to-Noise Ratio (SNR). Multi-layer boards utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. Particularly harsh environments may require shielding of critical signals. If low noise is desired, breadboards and wire-wrapped boards are not recommended. 8.6.2.2 Footprint Compatibility The specification of the MCP44XX pinouts was done to allow systems to be designed to easily support the use of either the dual (MCP46XX) or quad (MCP44XX) device. Figure 8-9 shows how the dual pinout devices fit on the quad device footprint. For the Rheostat devices, the dual device is in the MSOP package, so the footprints would need to be offset from each other. 0.1 F VDD W B MCP444X/446X A VSS FIGURE 8-8: Connections. SCL SDA HVC/A0 A1 PICTM Microcontroller MCP44X1 Quad Potentiometers 0.1 F VSS Typical Microcontroller P3A P3W P3B HVC/A0 SCL SDA VSS P1B P1W P1A 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 12 12 11 P2A P2W P2B VDD A1 RESET WP P0B P0W P0A MCP42X1 Pinout (1) TSSOP MCP44X2 Quad Rheostat P3W P3B HVC/A0 SCL SDA VSS P1B 1 2 3 4 5 6 7 14 13 12 11 10 9 8 P2W P2B VDD A1 P0B P0W P1W MCP42X2 Pinout TSSOP Note 1: Pin 15 (RESET) is the Address A2 (A2) pin on the MCP46x1 device. FIGURE 8-9: Quad Pinout (TSSOP Package) vs. Dual Pinout. DS22265A-page 78 (c) 2010 Microchip Technology Inc. MCP444X/446X MCP44X1 In some applications, PCB area is a criteria for device selection. Table 8-2 shows the package dimensions and area for the different package options. The table also shows the relative area factor compared to the smallest area. For space critical applications, the QFN package would be the suggested package. PACKAGE FOOTPRINT (1) TABLE 8-2: Package Pins MCP46X1 PCB Area Requirements Package Footprint Dimensions (mm) Type Code X Rheostat Devices MCP46X2 MCP44X2 14 TSSOP ST 5.10 QFN ML 4.00 20 TSSOP ST 6.60 Note 1: Does not include pattern dimensions. 8.6.3 FIGURE 8-10: Dual Devices. Layout to Support Quad and Y Relative Area Potentiometers Devices 8.6.2.3 Area (mm2) Figure 8-10 shows possible layout implementations for an application to support the quad and dual options on the same PCB. 6.40 32.64 2.04 4.00 16.00 1 6.40 42.24 2.64 recommended land RESISTOR TEMPCO Characterization curves of the resistor temperature coefficient (Tempco) are shown in Figure 2-10, Figure 2-26, Figure 2-41, and Figure 2-56. These curves show that the resistor network is designed to correct for the change in resistance as temperature increases. This technique reduces the end to end change is RAB resistance. 8.6.4 HIGH VOLTAGE TOLERANT PINS High Voltage support (VIHH) on the Serial Interface pins supports two features. These are: * In-Circuit Accommodation of split rail applications and power supply sync issues * User configuration of the Nonvolatile EEPROM, Write Protect, and WiperLock feature Note: (c) 2010 Microchip Technology Inc. In many applications, the High Voltage will only be present at the manufacturing stage so as to "lock" the Nonvolatile wiper value (after calibration) and the contents of the EEPROM. This ensures that since High Voltage is not present under normal operating conditions, these values can not be modified. DS22265A-page 79 MCP444X/446X 9.0 DEVELOPMENT SUPPORT 9.1 Development Tools 9.2 Technical Documentation Several additional technical documents are available to assist you in your design and development. These technical documents include Application Notes, Technical Briefs, and Design Guides. Table 9-2 shows some of these documents. Several development tools are available to assist in your design and evaluation of the MCP44XX devices. The currently available tools are shown in Table 9-1. These boards may be purchased directly from the Microchip web site at www.microchip.com. TABLE 9-1: DEVELOPMENT TOOLS Board Name Part # Supported Devices 20-pin TSSOP and SSOP Evaluation Board TSSOP20EV MCP44XX MCP46XX Digital Potentiometer PICtail Plus Demo MCP46XXDM-PTPLS Board (1, 2) MCP46XX MCP46XX Digital Potentiometer Evaluation Board (2) MCP46XXEV MCP46X1 Note 1: Requires a PICDEM Demo board. See the User's Guide for additional information and requirements. 2: Requires a PICkit Serial Analyzer. See the User's Guide for additional information and requirements. TABLE 9-2: TECHNICAL DOCUMENTATION Application Note Number Title Literature # AN1316 Using Digital Potentiometers for Programmable Amplifier Gain DS01316 AN1080 Understanding Digital Potentiometers Resistor Variations DS01080 AN737 Using Digital Potentiometers to Design Low-Pass Adjustable Filters DS00737 AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692 AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691 AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219 -- Digital Potentiometer Design Guide DS22017 -- Signal Chain Design Guide DS21825 DS22265A-page 80 (c) 2010 Microchip Technology Inc. MCP444X/446X 10.0 PACKAGING INFORMATION 10.1 Package Marking Information 14-Lead TSSOP Example 4462502E XXXXXXXX 1035 YYWW NNN 256 20-Lead QFN (4x4) 4461 502EML 3 1035 e ^^ 256 XXXXX XXXXXX XXXXXX YYWWNNN Example 20-Lead TSSOP XXXXXXXX 4461502 XXXXX NNN YYWW EST ^^ e3 256 1035 Legend: XX...X Y YY WW NNN e3 * Note: Example Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2010 Microchip Technology Inc. DS22265A-page 81 MCP444X/446X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22265A-page 82 (c) 2010 Microchip Technology Inc. MCP444X/446X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging (c) 2010 Microchip Technology Inc. DS22265A-page 83 MCP444X/446X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22265A-page 84 (c) 2010 Microchip Technology Inc. MCP444X/446X % !" #$ > & ' !&" & +# *!( !!& + %& &#& && =??***' '? + D D2 EXPOSED PAD e E2 2 E b 2 1 1 K N N NOTE 1 TOP VIEW L BOTTOM VIEW A A1 A3 @&! '! A'&! G"') %! AA6 6 G G GH J & H K & L &# %% 8 < && +!! 5 H N#& 6 6$ 6 !##N#& H A& 6$ !##A& 8;< 6> ;< O L ;< O L < &&N#& ) L 8 5 < &&A& A 5 8 Q R R < &&& 6$ !## % !"#$%&" ' ()"&'"!&) &#*& & & # +!!*!"&# 5 '! #& 678 ;<= ;!'! &$&"! **& "&& ! 6>= % '! ("!"*& "&& (% % '& " !! (c) 2010 Microchip Technology Inc. * <O; DS22265A-page 85 MCP444X/446X % > & ' !&" & +# *!( !!& + %& &#& && =??***' '? + DS22265A-page 86 (c) 2010 Microchip Technology Inc. MCP444X/446X % &'( )'*( ) + ( )& !" #&))+ $ > & ' !&" & +# *!( !!& + %& &#& && =??***' '? + D N E E1 NOTE 1 1 2 e b c A2 A A1 L L1 @&! '! A'&! G"') %! AA6 6 G G GH J & H K & R R L 8 8 R 8 ##+ +!! &# %% O8;< H N#& 6 ##+N#& 6 5 ##+A& O O8 OO > &A& A 8 O 8 > & & A > & A# +!! O;< 8 6> I U R LU R A#N#& ) R 5 % !"#$%&" ' ()"&'"!&) &#*& & & # '! !#6# &"#' #%! & "! ! #%! & "! !! &$#8'' !# 5 '! #& 678 ;<= ;!'! &$&"! **& "&& ! 6>= % '! ("!"*& "&& (% % '& " !! (c) 2010 Microchip Technology Inc. * <LL; DS22265A-page 87 MCP444X/446X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22265A-page 88 (c) 2010 Microchip Technology Inc. MCP444X/446X APPENDIX A: REVISION HISTORY Revision A (September 2010) * Original Release of this Document. (c) 2010 Microchip Technology Inc. DS22265A-page 89 MCP444X/446X NOTES: DS22265A-page 90 (c) 2010 Microchip Technology Inc. MCP444X/446X CHARACTERIZATION DATA ANALYSIS Some designers may want to understand the device operational characteristics outside of the specified operating conditions of the device. Applications where the knowledge of the resistor network characteristics could be useful include battery powered devices and applications that experience brown-out conditions. In battery applications, the application voltage decays over time until new batteries are installed. As the voltage decays, the system will continue to operate. At some voltage level, the application will be below its specified operating voltage range. This is dependent on the individual components used in the design. It is still useful to understand the device characteristics to expect when this low-voltage range is encountered. Unlike a microcontroller, which can use an external supervisor device to force the controller into the Reset state, a digital potentiometer's resistance characteristic is not specified. But understanding the operational characteristics can be important in the design of the applications circuit for this low-voltage condition. Other application system scenarios where understanding the low-voltage characteristics of the resistor network could be important is for system brown out conditions. For the MCP444X/446X devices, the analog operation is specified at a minimum of 2.7V. Device testing has Terminal A connected to the device VDD (for the potentiometer configuration only) and Terminal B connected to VSS. B.1 Low-Voltage Operation This appendix gives an overview of CMOS semiconductor characteristics at lower voltages. This is important so that the 1.8V resistor network characterization graphs of the MCP444X/446X devices can be better understood. For this discussion, we will use the 5 k device data. This data was chosen since the variations of wiper resistance have much greater implications for devices with smaller RAB resistances. Figure B-1 shows the worst case RBW error from the average RBW as a percentage, while Figure B-2 shows the RBW resistance versus the wiper code graph. Non-linear behavior occurs at approximately wiper code 160. This is better shown in Figure B-2, where the RBW resistance changes from a linear slope. This change is due to the change in the wiper resistance. 2.00% 1.00% 0.00% -1.00% Error % APPENDIX B: -2.00% -3.00% -4.00% -40C +25C +85C +125C -5.00% -6.00% -7.00% 0 32 64 96 128 160 192 224 256 Wiper Code FIGURE B-1: 1.8V Worst Case RBW Error from Average RBW (RBW0-RBW3) vs. Wiper Code and Temperature (VDD = 1.8V, IW = 190 A). 7000 Resistance () 6000 5000 4000 3000 -40C +25C +85C +125C 2000 1000 0 0 32 64 96 128 160 Wiper Code 192 224 256 FIGURE B-2: RBW vs. Wiper Code And Temperature (VDD = 1.8V, IW = 190 A). (c) 2010 Microchip Technology Inc. DS22265A-page 91 MCP444X/446X Figure B-3 and Figure B-4 show the wiper resistance for VDD voltages of 5.5, 3.0, 1.8 Volts. These graphs show that as the resistor ladder wiper node voltage (VWCn) approaches the VDD/2 voltage, the wiper resistance increases. These graphs also show the different resistance characteristics of the NMOS and PMOS transistors that make up the wiper switch. This is demonstrated by the wiper code resistance curve, which does not mirror itself around the mid-scale code (wiper code = 128). So why are the RW graphs showing the maximum resistance at about mid-scale (wiper code = 128) and the RBW graphs showing the issue at code 160? This requires understanding low-voltage transistor characteristics as well as how the data was measured. 220 200 Resistance () 180 -40C @ 3.0V +25C @ 3.0V +85C @ 3.0V +125C @ 3.0V -40C @5.5V +25C @ 5.5V +85C @ 5.5V +125C @ 5.5V 160 floating VA A 120 VW W IW B 140 VB RBW = VW/IW RW = (VW-VA)/IW 100 80 FIGURE B-5: 60 40 20 0 64 128 192 256 Wiper Code FIGURE B-3: Wiper Resistance (RW) vs. Wiper Code and Temperature (VDD = 5.5V, IW = 900 A; VDD = 3.0V, IW = 480 A). 2020 +25C @ 1.8V 1520 +125C @ 1.8V 1020 520 20 0 64 128 192 256 Wiper Code FIGURE B-4: Wiper Resistance (RW) vs. Wiper Code and Temperature (VDD = 1.8V, IW = 260 A). DS22265A-page 92 RBW and RW Measurement. Figure B-6 shows a block diagram of the resistor network where the RAB resistor is a series of 256 RS resistors. These resistors are polysilicon devices. Each wiper switch is an analog switch made up of an NMOS and PMOS transistor. A more detailed figure of the wiper switch is shown in Figure B-7. The wiper resistance is influenced by the voltage on the wiper switches nodes (VG, VW and VWCn). Temperature also influences the characteristics of the wiper switch, see Figure B-4. The NMOS transistor and PMOS transistor have different characteristics. These characteristics, as well as the wiper switch node voltages, determine the RW resistance at each wiper code. The variation of each wiper switch's characteristics in the resistor network is greater then the variation of the RS resistors. -40C @ 1.8V +85C @ 1.8V Resistance () The method in which the data was collected is important to understand. Figure B-5 shows the technique that was used to measure the RBW and RW resistance. In this technique, Terminal A is floating and Terminal B is connected to ground. A fixed current is then forced into the wiper (IW) and the corresponding wiper voltage (VW) is measured. Forcing a known current through RBW (IW) and then measuring the voltage difference between the wiper (VW) and Terminal A (VA), the wiper resistance (RW) can be calculated, see Figure B-5. Changes in IW current will change the wiper voltage (VW). This may affect the device's wiper resistance (RW). The voltage on the resistor network node (VWCn) is dependent upon the wiper code selected and the voltages applied to VA, VB and VW. The wiper switch VG voltage to VW or VWCn voltage determines how strongly the transistor is turned on. When the transistor is weakly turned on, the wiper resistance RW will be high. When the transistor is strongly turned on, the wiper resistance (RW) will be in the typical range. (c) 2010 Microchip Technology Inc. MCP444X/446X So looking at the wiper voltage (VW) for the 3.0V and 1.8V data gives the graphs in Figure B-8 and Figure B-9. In the 1.8V graph, as the VW approaches 0.8V, the voltage increases nonlinearly. Since V = I * R, and the current (IW) is constant, it means that the device resistance increased nonlinearly at around wiper code 160. A VA RS RW (1) Nn-1 DVG RW (1) RS Nn-2 RS VWC(n-2) RAB Nn-3 1.2 1.0 NMOS PMOS RW (1) VW W Wiper Voltage (V) Nn 0.8 0.6 0.4 -40C +25C +85C +125C 0.2 0.0 RS RW (1) RW (1) N0 B Note 1: 0 32 64 96 128 160 Wiper Code 192 224 256 FIGURE B-8: Wiper Voltage (VW) vs. Wiper Code (VDD = 3.0V, IW = 190 A). 1.4 VB 1.2 The wiper resistance is dependent on several factors including, wiper code, device VDD, Terminal voltages (on A, B and W), and temperature. FIGURE B-6: Diagram. Resistor Network Block Wiper Voltage (V) N1 1.0 0.8 0.6 -40C +25C +85C +125C 0.4 0.2 The characteristics of the wiper are determined by the characteristics of the wiper switch at each of the resistor networks tap points. Figure B-7 shows an example of a wiper switch. As the device operational voltage becomes lower, the characteristics of the wiper switch change due to a lower voltage on the VG signal. 0.0 0 32 64 96 128 160 Wiper Code 192 224 256 FIGURE B-9: Wiper Voltage (VW) vs. Wiper Code (VDD = 1.8V, IW = 190 A). Figure B-7 shows an implementation of a wiper switch. When the transistor is turned off, the switch resistance is in the Giga s. When the transistor is turned on, the switch resistance is dependent on the VG, VW and VWCn voltages. This resistance is referred to as RW. RW (1) VG (VDD/VSS) "gate" NMOS NWC VWCn PMOS Wiper VW "gate" Note 1: Wiper Resistance (RW) depends on the voltages at the wiper switch nodes (VG, VW and VWCn). FIGURE B-7: Wiper Switch. (c) 2010 Microchip Technology Inc. DS22265A-page 93 MCP444X/446X RW RPMOS 140 RW 120 5.00E+09 100 4.00E+09 3.00E+09 80 NMOS PMOS Theshold Theshold 2.00E+09 60 40 1.00E+09 20 0.00E+00 0 0.0 0.6 1.2 1.8 VIN Voltage 2.4 3.0 FIGURE B-12: NMOS and PMOS Transistor Resistance (RNMOS, RPMOS) and Wiper Resistance (RW) VS. VIN (VDD = 1.8V). 300 NMOS 250 Resistance () VOUT PMOS "gate" FIGURE B-10: 6.00E+09 VG (VDD/VSS) "gate" VIN 160 RNMOS Wiper Resistance () 7.00E+09 NMOS and PMOS Resistance () Using the simulation models of the NMOS and PMOS devices for the MCP44XX analog switch (Figure B-10), we plot the device resistance when the devices are turned on. Figure B-11 and Figure B-12 show the resistances of the NMOS and PMOS devices as the VIN voltage is increased. The wiper resistance (RW) is simply the parallel resistance on the NMOS and PMOS devices (RW = RNMOS || RPMOS). Below the threshold voltage for the NMOS ad PMOS devices, the resistance becomes very large (Gigaohms). In the transistors active region, the resistance is much lower. For these graphs, the resistances are on different scales. Figure B-13 and Figure B-14 only plot the NMOS and PMOS device resistance for their active region and the resulting wiper resistance. For these graphs, all resistances are on the same scale. Analog Switch. 200 RNMOS RPMOS 150 100 RW 50 RW 2500 RNMOS 0 2.50E+10 2000 RPMOS 2.00E+10 1500 1.50E+10 1000 1.00E+10 NMOS 500 Theshold PMOS Theshold 5.00E+09 0.00E+00 0.0 Wiper Resistance () NMOS and PMOS Resistance () 3.00E+10 0.3 0.6 0.9 1.2 VIN Voltage 1.5 1.2 1.8 VIN Voltage 2.4 3.0 FIGURE B-13: NMOS and PMOS Transistor Resistance (RNMOS, RPMOS) and Wiper Resistance (RW) VS. VIN (VDD = 3.0V). 0 0.0 0.6 5000 1.8 4500 Resistance () 4000 FIGURE B-11: NMOS and PMOS Transistor Resistance (RNMOS, RPMOS) and Wiper Resistance (RW) VS. VIN (VDD = 3.0V). 3500 3000 RNMOS 2500 RPMOS 2000 RW 1500 1000 500 0 0.0 0.3 0.6 0.9 1.2 VIN Voltage 1.5 1.8 FIGURE B-14: NMOS and PMOS Transistor Resistance (RNMOS, RPMOS) and Wiper Resistance (RW) VS. VIN (VDD = 1.8V). DS22265A-page 94 (c) 2010 Microchip Technology Inc. MCP444X/446X B.2 Optimizing Circuit Design for Low-Voltage Characteristics R1 The low-voltage nonlinear characteristics can be minimized by application design. The section will show two application circuits that can be used to control a programmable reference voltage (VOUT). A In example implementation #1 (Figure B-15), we window the digital potentiometer using resistors R1 and R2. When the wiper code is at full scale, the VOUT voltage will be 0.6 * VDD, and when the wiper code is at zero scale the VOUT voltage will be 0.5 * VDD. Remember that the digital potentiometers RAB variation must be included. Table B-1 shows that the VOUT voltage can be selected to be between 0.455 * VDD and 0.727 * VDD, which includes the desired range. With respect to the voltages on the resistor network node, at 1.8V the VA voltage would range from 1.29V to 1.31V while the VB voltage would range from 0.82V to 0.86V. These voltages cause the wiper resistance to be in the nonlinear region (see Figure B-12). In Potentiometer mode, the variation of the wiper resistance is typically not an issue, as shown by the INL/DNL graph (Figure 2-7). VW W Minimizing the low-voltage nonlinear characteristics is done by keeping the voltages on the wiper switch nodes at a voltage where either the NMOS or PMOS transistor is turned on. An example of this is if we are using a digital potentiometer for a voltage reference (VOUT). Let's say that we want VOUT to range from 0.5 * VDD to 0.6 * VDD. VA B VOUT VB R2 FIGURE B-15: TABLE B-1: Example Implementation #1. EXAMPLE #1 VOLTAGE CALCULATIONS Variation Min Typ Max R1 12,000 12,000 12,000 R2 20,000 20,000 20,000 RAB 8,000 10,000 12,000 VOUT (@ FS) 0.714 VDD VOUT (@ ZS) 0.476 VDD 0.70 VDD 0.727 VDD 0.50 VDD 0.455 VDD VA 0.714 VDD 0.70 VDD 0.727 VDD VB 0.476 VDD 0.50 VDD 0.455 VDD Legend: FS - Full Scale, ZS - Zero Scale In example implementation #2 (Figure B-16) we use the digital potentiometer in Rheostat mode. The resistor ladder uses resistors R1 and R2 with RBW at the bottom of the ladder. When the wiper code is at full scale, the VOUT voltage will be 0.6 * VDD and when the wiper code is at full scale the VOUT voltage will be 0.5 * VDD. Remember that the digital potentiometers RAB variation must be included. Table B-2 shows that the VOUT voltage can be selected to be between 0.50 * VDD and 0.687 * VDD, which includes the desired range. With respect to the voltages on the resistor network node, at 1.8V the VW voltage would range from 0.29V to 0.38V. These voltages cause the wiper resistance to be in the linear region (see Figure B-12). (c) 2010 Microchip Technology Inc. DS22265A-page 95 MCP444X/446X R1 VOUT R2 A VA W B FIGURE B-16: TABLE B-2: VW VB Example Implementation #2. EXAMPLE #2 VOLTAGE CALCULATIONS Variation Min Typ Max R1 10,000 10,000 10,000 R2 10,000 10,000 10,000 RBW (max) 8,000 10,000 12,000 VOUT (@ FS) 0.667 VDD VOUT(@ ZS) 0.50 VDD 0.643 VDD 0.687 VDD 0.50 VDD 0.50 VDD VW (@ FS) 0.333 VDD 0.286 VDD 0.375 VDD VW (@ ZS) VSS VSS VSS Legend: FS - Full Scale, ZS - Zero Scale DS22265A-page 96 (c) 2010 Microchip Technology Inc. MCP444X/446X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -XXX X /XX Device Resistance Version Temperature Range Package Device MCP4441: MCP4441T: MCP4442: MCP4442T: MCP4461: MCP4461T: MCP4462: MCP4462T: Quad Nonvolatile 7-bit Potentiometer Quad Nonvolatile 7-bit Potentiometer (Tape and Reel) Quad Nonvolatile 7-bit Rheostat Quad Nonvolatile 7-bit Rheostat (Tape and Reel) Quad Nonvolatile 8-bit Potentiometer Quad Nonvolatile 8-bit Potentiometer (Tape and Reel) Quad Nonvolatile 8-bit Rheostat Quad Nonvolatile 8-bit Rheostat (Tape and Reel) Resistance Version: 502 103 503 104 = = = = 5 k 10 k 50 k 100 k Temperature Range E = -40C to +125C (Extended) Package ST = Plastic Thin Shrink Small Outline (TSSOP), 14/20-lead ML = Plastic Quad Flat No-lead (4x4 QFN), 20-lead (c) 2010 Microchip Technology Inc. Examples: a) b) c) d) e) f) g) h) MCP4441-502E/XX: MCP4441T-502E/XX: MCP4441-103E/XX: MCP4441T-103E/XX: MCP4441-503E/XX: MCP4441T-503E/XX: MCP4441-104E/XX: MCP4441T-104E/XX: 5 k, 20-LD Device T/R, 5 k, 20-LD Device 10 k, 20-LD Device T/R, 10 k, 20-LD Device 50 k, 20-LD Device T/R, 50 k, 20-LD Device 100 k, 20-LD Device T/R, 100 k, 20-LD Device a) b) c) d) e) f) g) h) MCP4442-502E/XX: MCP4442T-502E/XX: MCP4442-103E/XX: MCP4442T-103E/XX: MCP4442-503E/XX: MCP4442T-503E/XX: MCP4442-104E/XX: MCP4442T-104E/XX: 5 k, 14-LD Device T/R, 5 k, 14-LD Device 10 k, 14-LD Device T/R, 10 k, 14-LD Device 50 k, 8LD Device T/R, 50 k, 14-LD Device 100 k, 14-LD Device T/R, 100 k, 14-LD Device a) b) c) d) e) f) g) h) MCP4461-502E/XX: MCP4461T-502E/XX: MCP4461-103E/XX: MCP4461T-103E/XX: MCP4461-503E/XX: MCP4461T-503E/XX: MCP4461-104E/XX: MCP4461T-104E/XX: 5 k, 20-LD Device T/R, 5 k, 20-LD Device 10 k, 20-LD Device T/R, 10 k, 20-LD Device 50 k, 20-LD Device T/R, 50 k, 20-LD Device 100 k, 20-LD Device T/R, 100 k, 20-LD Device a) b) c) d) e) f) g) h) MCP4462-502E/XX: MCP4462T-502E/XX: MCP4462-103E/XX: MCP4462T-103E/XX: MCP4462-503E/XX: MCP4462T-503E/XX: MCP4462-104E/XX: MCP4462T-104E/XX: 5 k, 14-LD Device T/R, 5 k, 14-LD Device 10 k, 14-LD Device T/R, 10 k, 14-LD Device 50 k, 14-LD Device T/R, 50 k, 14-LD Device 100 k, 14-LD Device T/R, 100 k, 14-LD Device XX = ST for 14/20-lead TSSOP = ML for 20-lead QFN DS22265A-page 97 MCP444X/446X NOTES: DS22265A-page 98 (c) 2010 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. 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Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-533-6 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2010 Microchip Technology Inc. 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