AD8233CB-EBZ - ANALOG DEVICES

50 µA, 2 mm × 1.7 mm WLCSP, Low Noise,

Heart Rate Monitor for Wearable Products

Data Sheet

AD8233

Rev. D Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice.

No license is granted by implication or otherwise under any patent or patent rights of Analog

Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

Fully integrated, single-lead ECG front end

Low quiescent supply current: 50 µA (typical)

Leads on/off detection while in shutdown (<1 µA)

Common-mode rejection ratio: 80 dB (dc to 60 Hz)

2-electrode and 3-electrode configurations

High signal gain (G = 100) with dc blocking capabilities

2-pole adjustable high-pass filter

Accepts up to ±300 mV of half cell potential

Fast restore feature improves filter settling

Uncommitted op amp

3-pole adjustable low-pass filter with adjustable gain

Integrated RLD amplifier with shutdown

Single-supply operation: 1.7 V to 3.5 V

Integrated reference buffer generates virtual ground

Rail-to-rail output

Internal RFI filter

8 kV HBM ESD rating

Shutdown pin

2 mm × 1.7 mm WLCSP package

APPLICATIONS

Fitness and activity heart rate monitors

Portable ECG

Wearable and remote health monitors

Gaming peripherals

Biopotential signal acquisition, such as EMG or EEG

GENERAL DESCRIPTION

The AD8233 is an integrated signal conditioning block for

electrocardiogram (ECG) and other biopotential measurement

applications. It is designed to extract, amplify, and filter small

biopotential signals in the presence of noisy conditions, such as

those created by motion or remote electrode placement. This

design allows an ultralow power analog-to-digital converter

(ADC) or an embedded microcontroller to easily acquire the

output signal.

The AD8233 implements a two-pole, high-pass filter for

eliminating motion artifacts and the electrode half cell potential.

This filter is tightly coupled with the instrumentation amplifier

architecture to allow both large gain and high-pass filtering in a

single stage, thereby saving space and cost.

An uncommitted operational amplifier enables the AD8233 to

create a three-pole, low-pass filter to remove additional noise.

The user can select the frequency cutoff of all filters to suit

different types of applications.

FUNCTIONAL BLOCK DIAGRAM

LOD

AD8233

+VSGND

OPAMP– OUTREFOUTOPAMP+SW

REFINIAOUT

HPSENSE

HPDRIVE

+IN

–IN

RLD

RLDFB

SDN

AC/DC

LEADS OFF

DETECTION

10kΩ

150kΩ

B4 A3 A2 A1

D4 D3 C3 D2 D1

RLD S DN

13737-001

Figure 1. 20-Ball WLCSP

To improve the common-mode rejection of the line frequencies

in the system and other undesired interferences, the AD8233

includes a right leg drive (RLD) amplifier for driven electrode

applications.

The AD8233 includes a fast restore function that reduces the

duration of the otherwise long settling tails of the high-pass

filters. After an abrupt signal change that rails the amplifier

(such as a leads off condition), the AD8233 automatically adjusts

to a higher filter cutoff. This feature allows the AD8233 to

recover quickly, and therefore, to take valid measurements

soon after connecting the electrodes to the subject.

The AD8233 is available in a 2 mm × 1.7 mm, 20-ball WLCSP

package and a 150 μm thin die for height constrained applications.

Performance is specified from 0°C to 70°C and is operational

from −40°C to +85°C.

The AD8233 has several improvements over the AD8232,

which are detailed in Table 1.

Table 1. AD8232 vs. AD8233 Comparison

Parameter AD8232 AD8233

Supply Current 170 µA 50 µA

Peak-to-Peak Voltage Noise

(f = 0.5 Hz to 40 Hz)

14 µV p-p 8.5 µV

Leads On or Off Detection

in Shutdown

Not included Included

Right Leg Drive Shutdown Not included Included

Package Size 4 mm × 4 mm ×

0.75 mm

2 mm × 1.7 mm ×

0.5 mm or 0.15 mm

AD8233 Data Sheet

Rev. D | Page 2 of 32

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ...................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications .................................................................................... 3

Absolute Maximum Ratings ........................................................... 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

Instrumentation Amplifier Performance Characteristics ...... 8

Operational Amplifier Performance Characteristics ............ 11

RLD Amplifier Performance Characteristics ......................... 14

Reference Buffer Performance Characteristics ...................... 15

System Performance Characteristics ....................................... 16

Theory of Operation ...................................................................... 17

Architecture Overview .............................................................. 17

Instrumentation Amplifier ....................................................... 17

Operational Amplifier ............................................................... 17

RLD Amplifier ............................................................................ 17

Reference Buffer ......................................................................... 18

Fast Restore Circuit .................................................................... 18

Leads On or Off Detection ........................................................ 19

Standby Operation ..................................................................... 20

Input Protection ......................................................................... 20

Radio Frequency Interference .................................................. 21

Power Supply Regulation and Bypassing ................................ 21

Input Referred Offsets ............................................................... 21

Layout Recommendations ........................................................ 21

Application Information ............................................................... 22

Eliminating Electrode Offsets ................................................... 22

High-Pass Filtering .................................................................... 22

Low-Pass Filtering and Gain .................................................... 24

Driven Electrode ........................................................................ 25

Measuring Surface Electromyography (EMG) or

Electroencephalography (EEG) ................................................ 25

Application Circuits ................................................................... 25

Using AD5940, AD8232, and AD8233 for Bioimpedance and

Electrocardiogram (ECG) Measurements ................................. 29

Die Information .............................................................................. 30

Outline Dimensions ....................................................................... 31

Ordering Guide .......................................................................... 32

REVISION HISTORY

3/2020—Rev. C to Rev. D

Changes to Low-Pass Filtering and Gain Section and Table 7 ..... 24

8/2019—Rev. B to Rev. C

Change to Table 4 ............................................................................. 6

Changes to Ordering Guide .......................................................... 32

3/2019—Rev. A to Rev. B

Changes to Table 7 ......................................................................... 24

Added Using AD5940, AD8232, and AD8233 for

Bioimpedance and Electrocardiogram (ECG) Measurements

Section .............................................................................................. 30

Added Figure 79; Renumbered Sequentially .............................. 30

10/2018—Rev. 0 to Rev. A

Added 20-Pad Bare Die ...................................................... Universal

Changes to Features Section and General Description Section ...... 1

Change to Table 1 ............................................................................. 1

Changes to Specifications Section and Table 2 ............................ 3

Change to Typical Performance Characteristics .......................... 9

Changes to Figure 13 ..................................................................... 10

Changes to Figure 28 ..................................................................... 13

Changes to Table 7 ......................................................................... 25

Added Measuring Surface Electromyography (EMG) or

Electroencephalography (EEG) Section ...................................... 26

Added Figure 77 ............................................................................. 28

Added Portable Heart Rate and Activity Monitor System

Section .............................................................................................. 29

Renamed Synchronized ECG and PPG Measurement Section to

Synchronous ECG and Photoplethysmography (PPG)

Measurement Using Transimpedance Amplifier (TIA) ADC

Mode Using the ADPD1080 Section ........................................... 29

Changes to Synchronous ECG and Photoplethysmography

(PPG) Measurement Using Transimpedance Amplifier (TIA)

ADC Mode Using the ADPD1080 Section ................................. 29

Changes to Figure 79 Caption ...................................................... 29

Added Die Information Section, Figure 80, and Table 8,

Renumbered Sequentially ............................................................. 30

Updated Outline Dimensions ...................................................... 31

Changes to Ordering Guide .......................................................... 32

8/2016—Revision 0: Initial Version

Data Sheet AD8233

Rev. D | Page 3 of 32

SPECIFICATIONS

+VS = 1.8 V to 3 V ± 5.5%, voltage at REFIN pin (VREF) = +VS/2, VCM = +VS/2, TA = 25°C, FR = low, SDN = high, AC/DC = low, RLD SDN =

low, unless otherwise noted. The AD8233C-DF is only characterized at 25°C.

Table 2.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

INSTRUMENTATION AMPLIFIER

Common-Mode Rejection Ratio, DC to

60 Hz

CMRR Input common-mode voltage (VCM) =

0.35 V to +VS − 150 mV, dc differential

input range (VDIFF) = 0 V

80 86 dB

VCM = 0.35 V to +VS − 150 mV, VDIFF = ±0.3 V 80 dB

Power Supply Rejection Ratio PSRR +VS = 1.8 V to 3.5 V 76 90 dB

Offset Voltage (Referred to Input (RTI)) VOS

Instrumentation Amplifier Inputs 1 6 mV

DC Blocking Input1 25 µV

Average Offset Drift

Instrumentation Amplifier Inputs 2 µV/°C

DC Blocking Input1 0.05 µV/°C

Input Bias Current IB 50 200 pA

TA = 0°C to 70°C 1 nA

Input Offset Current IOS 25 100 pA

TA = 0°C to 70°C 1 nA

Input Impedance

Differential 10||7.5 GΩ||pF

Common Mode 5||15 GΩ||pF

Input Voltage Noise (RTI)

Spectral Noise Density f = 1 kHz 150 nV/√Hz

Peak-to-Peak Voltage Noise f = 0.1 Hz to 10 Hz 10 µV p-p

f = 0.5 Hz to 40 Hz 8.5 µV p-p

Input Voltage Range TA = 0°C to 70°C 0.2 +VS V

DC Differential Input Range VDIFF −300 +300 mV

Output

Output Swing Output load resistor (RL) = 50 kΩ 0.1 +VS − 0.1 V

Short-Circuit Current IOUT 6.3 mA

Gain AV 100 V/V

Gain Error VDIFF = 0 V 0.4 %

VDIFF = −300 mV to +300 mV 1 4 %

Average Gain Drift TA = 0°C to 70°C 12 ppm/°C

Bandwidth BW 1 kHz

Radio Frequency Interference (RFI)

Filter Cutoff (Each Input)

1 MHz

OPERATIONAL AMPLIFIER (A1)

Offset Voltage VOS 1 5 mV

Average Temperature Coefficient TC TA = 0°C to 70°C 1 µV/°C

Input Bias Current IB 100 pA

TA = 0°C to 70°C 1 nA

Input Offset Current IOS 100 pA

TA = 0°C to 70°C 1 nA

Input Voltage Range 0.1 +VS − 0.1 V

Common-Mode Rejection Ratio CMRR VCM = 0.5 V to +VS − 0.5 V 100 dB

Power Supply Rejection Ratio PSRR 100 dB

Large Signal Voltage Gain AVO 110 dB

Output Voltage Range RL = 50 kΩ 0.1 +VS − 0.1 V

Short-Circuit Current Limit IOUT 12 mA

AD8233 Data Sheet

Rev. D | Page 4 of 32

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

Gain Bandwidth Product GBP 15 kHz

Slew Rate SR 0.01 V/µs

Voltage Noise Density (RTI) en f = 1 kHz 120 nV/√Hz

Peak-to-Peak Voltage Noise (RTI) en p-p f = 0.1 Hz to 10 Hz 7 µV p-p

f = 0.5 Hz to 40 Hz 9 µV p-p

RIGHT LEG DRIVE AMPLIFIER (A2)

Quiescent Supply Current 7.5 10 µA

Output Swing RL = 50 kΩ 0.1 +VS − 0.1 V

Short-Circuit Current IOUT 11 mA

Integrator Input Resistor 120 150 180 kΩ

Gain Bandwidth Product GDP 20 kHz

REFERENCE BUFFER (A3)

Offset Error VOS RL > 50 kΩ 1 mV

Input Bias Current IB 100 pA

Short-Circuit Current Limit IOUT 12 mA

Voltage Range RL = 50 kΩ 0.1 +VS − 0.7 V

DC LEADS OFF COMPARATORS

Threshold Voltage +VS − 0.27 V

Hysteresis 125 mV

Propagation Delay 1.5 µs

AC LEADS OFF DETECTOR

Square Wave Frequency fAC 50 100 175 kHz

Square Wave Amplitude IAC 200 nA p-p

Input Currents in Shutdown Mode2 IDC +IN, SDN = low 250 nA

−IN, SDN = low −300 nA

Impedance Threshold Between +IN and −IN, SDN = high 10 20 MΩ

Detection Delay 100 μs

FAST RESTORE CIRCUIT

Switches S1 and S2

On Resistance RON 8 10 12 kΩ

Off Leakage 100 pA

Window Comparator

Threshold Voltage From either rail 100 mV

Propagation Delay 2 µs

Switch Timing Characteristics

Feedback Recovery Switch On Time tS1 +VS = 3 V 160 ms

+VS = 1.8 V 80

Filter Recovery Switch On Time tS2 +VS = 3 V 80 ms

+VS = 1.8 V 40

Fast Restore Reset tRST +VS = 3 V 3 µs

+VS = 1.8 V 1.5

Data Sheet AD8233

Rev. D | Page 5 of 32

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

LOGIC INTERFACE

Input Characteristics

Input Voltage (AC/DC, FR, and

RLD SDN)

Low VIL 0.41 × +VS V

High VIH 0.45 × +VS V

Input Voltage (SDN)

Low VIL 0.6 × + VS V

High VIH 0.3 × + VS V

Output Characteristics LOD terminal

Output Voltage RL = 100 kΩ

Low VOL 0.05 V

High VOH +VS − 0.05 V

SYSTEM SPECIFICATIONS

Quiescent Supply Current 50 70 µA

TA = 0°C to 70°C 60 µA

Wakeup Current SDN = low, LOD = low 0.65 1.5 µA

TA = 0°C to 70°C 0.75 µA

Shutdown Current SDN = low, LOD = high 0.5 1 µA

TA = 0°C to 70°C 0.6 µA

Peak-to-Peak Voltage Noise (RTI) VDIFF = 0 V

f = 0.5 Hz to 40 Hz 9 µV p-p

f = 0.05 Hz to 150 Hz 15 µV p-p

VDIFF = ±0.3 V

f = 0.5 Hz to 40 Hz 11 µV p-p

f = 0.05 Hz to 150 Hz 21 µV p-p

Supply Range 1.7 3.5 V

Specified Temperature Range 0 70 °C

Operational Temperature Range −40 +85 °C

1 Offset is referred to the input of the instrumentation amplifier inputs.

2 In ac leads off and shutdown mode, the dc leads off comparator at the +IN pin trips the LOD pin.

AD8233 Data Sheet

Rev. D | Page 6 of 32

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage 3.6 V

Output Short-Circuit Current Duration Indefinite

Maximum Voltage, Any Terminal1 +VS + 0.3 V

Minimum Voltage, Any Terminal1 −0.3 V

Storage Temperature Range −65°C to +125°C

Operating Temperature Range −40°C to +85°C

Maximum Junction Temperature 140°C

Electrostatic Discharge (ESD) Rating

Human Body Model (HBM) 8 kV

Field Induced Charged Device Model

(FICDM)

1 kV

1 This level or the maximum specified supply voltage, whichever is the lesser,

indicates the superior voltage limit for any terminal. If input voltages beyond

the specified minimum or maximum voltages are expected, place resistors in

series with the inputs to limit the current to less than 5 mA.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the

operational section of this specification is not implied.

Operation beyond the maximum operating conditions for

extended periods may affect product reliability.

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required.

Table 4. Thermal Resistance

Package

Type PCB Power (W)

θJA (°C/W) θJC

(°C/W)

0 ms 1 ms 2 ms

CB-20-13 1S0P1 0.25 108.5 89.0 82.3 0.6

1.25 101.1 87.3 87.3 0.6

2S2P2 0.25 47.9 43.4 42.1 0.7

1.25 46.8 43.3 42.1 0.7

1 Simulated thermal numbers per JESD51-9: 1-layer PCB (1S0P), low effective

thermal conductivity test board.

2 4-layer PCB (2S2P), high effective thermal conductivity test board.

ESD CAUTION

Data Sheet AD8233

Rev. D | Page 7 of 32

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TOP VIEW

(BAL L SI DE DOW N)

Not t o Scal e

AD8233

2 3 4

BALL A1

INDICATOR

GND +V

REFIN HPSENSE HPDRIVE

SDN AC/DC FR IAOUT +IN

LOD RLD SDN REFOUT RLDFB –IN

OUT OPAMP– OPAMP+ SW RLD

13737-002

Figure 2. 20-Ball WLCSP Pin Configuration

Table 5. 20-Ball WLCSP Pin Function Descriptions

Ball No. Mnemonic Description

A1 GND Power Supply Ground.

A2 +VS Power Supply Terminal.

A3 REFIN Reference Buffer Input. Use REFIN, a high impedance input terminal, to set the level of the reference buffer.

A4 HPSENSE High-Pass Sense Input for Instrumentation Amplifier. Connect HPSENSE to the junction of R and C that sets the

corner frequency of the dc blocking circuit.

A5 HPDRIVE High-Pass Driver Output. Connect HPDRIVE to the capacitor in the first high-pass filter. The AD8233 drives this pin

to keep HPSENSE at the same level as the reference voltage.

B1 SDN Shutdown Control Input. Drive SDN low to enter the low power shutdown mode.

B2 AC/DC Leads Off Mode Control Input. Drive the AC/DC pin low for dc leads off mode. Drive the AC/DC pin high for ac

leads off mode.

B3 FR Fast Restore Control Input. Drive FR high to enable fast recovery mode. Otherwise, drive it low.

B4 IAOUT Instrumentation Amplifier Output Terminal.

B5 +IN Instrumentation Amplifier, Positive Input. +IN is typically connected to the left arm (LA) electrode.

C1 LOD Leads Off Detection Comparator Output.

C2 RLD SDN Right Leg Drive Shutdown Control Input. Drive RLD SDN low to power down the RLD amplifier.

C3 REFOUT Reference Buffer Output. The instrumentation amplifier output is referenced to this potential. Use REFOUT as a

virtual ground for any point in the circuit that requires a signal reference.

C4 RLDFB Right Leg Drive Feedback Input. RLDFB is the feedback terminal for the right leg drive circuit.

C5 −IN Instrumentation Amplifier, Negative Input. −IN is typically connected to the right arm (RA) electrode.

D1 OUT Operational Amplifier Output. The fully conditioned heart rate signal is present at this output. OUT can be

connected to the input of an ADC.

D2 OPAMP− Operational Amplifier Inverting Input.

D3 OPAMP+ Operational Amplifier Noninverting Input.

D4 SW Fast Restore Switch Terminal. Connect this terminal to the output of the second high-pass filter.

D5 RLD Right Leg Drive Output. Connect the driven electrode (typically right leg) to the RLD pin.

AD8233 Data Sheet

Rev. D | Page 8 of 32

TYPICAL PERFORMANCE CHARACTERISTICS

+VS = 3 V, VREF = 1.5 V, VCM = 1.5 V, TA = 25°C, unless otherwise noted. All typical performance characteristics are measured for the

WLCSP package.

INSTRUMENTATION AMPLIFIER PERFORMANCE CHARACTERISTICS

2100

1750

350

700

1050

1400

–120 –90 90

6030

0–60 –30 120

UNITS

CMRR (µV/V)

13737-003

Figure 3. CMRR Distribution

3500

3000

500

1000

1500

2500

–2.0 –1.5 1.51.00.50–1.0 –0.5 2.0

UNITS

GAI N E RROR (%)

13737-004

Figure 4. Gain Error Distribution

3.5

3.0

–0.5

0.5

1.0

1.5

2.0

2.5

00.5 1.0 3.53.02.52.01.5

INPUT COMMON-MODE VOLT AGE (V)

OUTPUT VOLTAGE (V)

13737-005

Figure 5. Input Common-Mode Voltage vs. Output Voltage

100

–100 00.5 1.0 3.53.02.52.01.5

INPUT BI AS CURRE NT (pA)

INPUT COMMON-MODE VOLT AGE (V)

–80

–60

–40

–20

13737-006

Figure 6. Input Bias Current vs. Input Common-Mode Voltage

–10 1100k10k1k10010

GAI N (dB)

FRE Q UE NCY ( Hz )

NO DC OFFSET

300mV OFF S E T

13737-007

Figure 7. Gain vs. Frequency

120

100

2010 100k10k1k100

CMRR RT I (d B)

FRE Q UE NCY ( Hz )

NO DC OFFSET

+300mV O FF S E T

–300mV OFF S E T

13737-008

Figure 8. CMRR RTI vs. Frequency

Data Sheet AD8233

Rev. D | Page 9 of 32

100

00.1 110 100k10k1k100

PSRR RT I (dB)

FRE Q UE NCY ( Hz )

13737-009

Figure 9. PSRR RTI vs. Frequency

10k

100

100.1 110 100k

10k1k100

NOISE (nV/√Hz)

FRE Q UE NCY ( Hz )

13737-010

Figure 10. Voltage Noise Spectral Density (RTI)

5µV/DIV

1s/DIV

13737-011

Figure 11. 0.1 Hz to 10 Hz Noise (RTI)

5µV/DIV

200ms/DIV

13737-012

Figure 12. 0.5 Hz to 40 Hz Noise (RTI)

1.0

0050 300250200150100

GAI N E RROR (%)

DC OFFSET (mV)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

13737-013

Figure 13. Gain Error vs. DC Offset

50mV/DIV

400µs/DIV

22pF

470pF

1nF

13737-014

Figure 14. Small Signal Pulse Response

AD8233 Data Sheet

Rev. D | Page 10 of 32

400µs/DIV 0.5V/DIV

13737-015

Figure 15. Large Signal Pulse Response

1.5

1.0

0.5

–0.5

–1.0

–1.5

100 1M

100k10k

OUTPUT VOLTAGE SWING (V)

LOAD (Ω)

–40°C

+25°C

+85°C

13737-016

Figure 16. Output Voltage Swing vs. Load

0.4

–0.4

–40 –20 020 40 60 10080

DC BLOCKING INPUT OFFSET (mV)

TEMPERATURE (°C)

–0.3

–0.2

–0.1

0.1

0.2

0.3

13737-017

Figure 17. DC Blocking Input Offset Drift on Multiple Parts

4.0

–1.0

–40 –20 020 40 60 80 100

INPUT BI AS CURRE NT (I

) (nA)

INPUT O FF S E T CURRENT (I

) (pA)

TEMPERATURE (°C)

–20

–10

–0.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5 I

13737-018

Figure 18. Input Bias Current (IB) and Input Offset Current (IOS) vs.

Temperature

0.5

–0.5

–40 –20 010080604020

GAI N E RROR (%)

TEMPERATURE (°C)

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

13737-019

Figure 19. Gain Error vs. Temperature

–10

–40 –20 010080604020

CMRR (µV/V)

TEMPERATURE (°C)

–8

–6

–4

–2

13737-020

Figure 20. CMRR vs. Temperature

Data Sheet AD8233

Rev. D | Page 11 of 32

OPERATIONAL AMPLIFIER PERFORMANCE CHARACTERISTICS

1000

200

400

600

800

0–4 –2 0 42

UNITS

OFFSET VOLTAGE (mV)

13737-021

Figure 21. Offset Distribution

120

–60

0.1 110 100k10k1k100

OPEN-LOOP GAIN (dB)

FRE Q UE NCY ( Hz )

–40

–20

100

–180

PHASE M ARGI N ( Degrees)

–160

–140

–120

–100

–80

–60

–40

–20

GAIN

PHASE M ARGI N

13737-022

Figure 22. Open-Loop Gain and Phase Margin vs. Frequency

20mV/DIV

100µs/DIV

22pF

470pF

1nF

13737-023

Figure 23. Small Signal Response for Various Capacitive Loads

0.5V/DIV

13737-024

400µs/DIV

Figure 24. Large Signal Transient Response

10k

100

100.1 110 100k10k1k100

VOLTAGE NOISE SPECTRAL DENSITY (nV/√Hz)

FRE Q UE NCY ( Hz )

13737-025

Figure 25. Voltage Noise Spectral Density vs. Frequency

5µV/DIV

1s/DIV

13737-026

Figure 26. 0.1 Hz to 10 Hz Noise

AD8233 Data Sheet

Rev. D | Page 12 of 32

5µV/DIV

200ms/DIV

13737-027

Figure 27. 0.5 Hz to 40 Hz Noise

100

–100 03.5

INPUT BI AS CURRE NT (pA)

INPUT COMMON-MODE VOLT AGE (V)

–80

–60

–40

–20

0.5 1.0 1.5 2.0 2.5 3.0

13737-028

Figure 28. Input Bias Current vs. Input Common-Mode Voltage

1.5

1.0

0.5

–0.5

–1.0

–1.5

100 1M100k10k

OUTPUT VOLTAGE SWING (V)

LOAD (Ω)

–40°C

+25°C

+85°C

13737-029

Figure 29. Output Voltage Swing vs. Load

120

0.1 110 100k10k1k100

PSRR ( dB)

FRE Q UE NCY ( Hz )

100

110

13737-030

Figure 30. Power Supply Rejection Ratio vs. Frequency

Data Sheet AD8233

Rev. D | Page 13 of 32

50mV/DIV

100µs/DIV

13737-031

Figure 31. Load Transient Response (100 μA Load Change)

0.8

–0.8

–40 –20 020 40 60 10080

OFF SET (mV)

TEMPERATURE (°C)

–0.6

–0.4

–0.2

0.2

0.4

0.6

13737-032

Figure 32. Offset vs. Temperature on Multiple Parts

100

0.1

–40 100

INPUT BI AS CURRE NT (pA)

TEMPERATURE (°C)

–20 020 40 60 80

13737-033

Figure 33. Input Bias Current vs. Temperature

AD8233 Data Sheet

Rev. D | Page 14 of 32

RLD AMPLIFIER PERFORMANCE CHARACTERISTICS

140

–400.1 110 100k

10k1k

100

OPEN-LOOP GAIN (dB)

FRE Q UE NCY ( Hz )

–20

100

120

–180

PHASE M ARGI N ( Degrees)

–160

–140

–120

–100

–80

–60

–40

–20

GAIN

PHASE M ARGI N

13737-034

Figure 34. Open-Loop Gain and Phase Margin vs. Frequency

1.5

1.0

0.5

–0.5

–1.0

–1.5

100 1M100k

10k1k

OUTPUT VOLTAGE SWING (V)

LOAD (Ω)

–40°C

+25°C

+85°C

13737-035

Figure 35. Output Voltage Swing vs. Load

10k

100

100.1 110 100k10k1k100

VOLTAGE NOISE SPECTRAL DENSITY (nV/√Hz)

FRE Q UE NCY ( Hz )

13737-036

Figure 36. Voltage Spectral Noise Density vs. Frequency

5µV/DIV

1s/DIV

13737-037

Figure 37. 0.1 Hz to 10 Hz Noise

5µV/DIV

200ms/DIV

13737-038

Figure 38. 0.5 Hz to 40 Hz Noise

–40 100

RLD SUP P LY CURRE NT (µA)

TEMPERATURE (°C)

–20 20040 60 80

= 1.8V

= 3V

= 3.5V

AC/DC = LO W, RLD SDN = HIG H

13737-039

Figure 39. RLD Supply Current vs. Temperature

Data Sheet AD8233

Rev. D | Page 15 of 32

REFERENCE BUFFER PERFORMANCE CHARACTERISTICS

–15

0.01 10

10.1

OUTPUT E RROR (mV )

LOAD CURRENT ( mA)

–10

–5

SOURCE

SINK

13737-040

Figure 40. Load Regulation

50mV/DIV

100µs/DIV

13737-041

Figure 41. Load Transient Response (100 μA Load Change)

100k

10k

100

0.1 110 100k

10k

1k100

OUTPUT IMPEDANCE (Ω)

FRE Q UE NCY ( Hz )

13737-042

Figure 42. Output Impedance vs. Frequency

100

0.1

–40 100

INPUT BI AS CURRE NT (pA)

TEMPERATURE (°C)

–20 020 40 60 80

13737-043

Figure 43. Input Bias Current vs. Temperature

AD8233 Data Sheet

Rev. D | Page 16 of 32

SYSTEM PERFORMANCE CHARACTERISTICS

–40 100

SUPPLY CURRE NT (µA)

TEMPERATURE (°C)

–20 20040 60 80

+VS = 1. 8V

+VS = 3V

+VS = 3. 5V

SDN = HI GH, AC/DC = LO W, RLD SDN = LOW

13737-044

Figure 44. Supply Current vs. Temperature

900

–40 100

SHUT DO WN CURRENT (nA)

TEMPERATURE (°C)

–20 20040 60 80

100

200

300

400

500

600

700

800 SDN = L OW , AC/ DC = LO W

RLD SDN = LOW, LOD = HIGH

= 1.8V

= 3V

= 3.5V

13737-045

Figure 45. Shutdown Current vs. Temperature

900

–40 100

WAKE UP CURRENT (nA)

TEMPERATURE (°C)

–20 20040 60 80

100

200

300

400

500

600

700

800

SDN = L OW , AC/ DC = LO W

RLD SDN = LOW, LOD = LOW

= 1.8V

= 3V

= 3.5V

1000

13737-046

Figure 46. Wakeup Current vs. Temperature

10k

100

100.1 110 100k10k

1k100

VOLTAGE NOISE SPECTRAL DENSITY (nV/√Hz)

FRE Q UE NCY ( Hz )

13737-047

Figure 47. Voltage Noise Spectral Density (RTI), Measured at IAOUT

5µV/DIV

200ms/DIV

13737-048

Figure 48. 0.5 Hz to 40 Hz Noise (RTI), Measured at IAOUT

10µV/DIV

2s/DIV

13737-049

Figure 49. 0.05 Hz to 150 Hz Noise (RTI), Measured at IAOUT

Data Sheet AD8233

Rev. D | Page 17 of 32

THEORY OF OPERATION

ARCHITECTURE OVERVIEW

The AD8233 is an integrated front end for signal conditioning

of cardiac biopotentials for heart rate monitoring. It consists of

a specialized instrumentation amplifier (IA), an operational

amplifier (A1), a right leg drive amplifier (A2), and a

midsupply reference buffer (A3). In addition, the AD8233

includes leads on or off detection circuitry and an automatic

fast restore circuit that restores the signal shortly after leads are

reconnected.

The AD8233 contains a specialized instrumentation amplifier

that amplifies the ECG signal while rejecting the electrode half cell

potential on the same stage. The amplification of the ECG signal

and the rejection of the electrode half cell potential are possible

with an indirect current feedback architecture, which reduces

size and power compared with traditional implementations.

INSTRUMENTATION AMPLIFIER

The instrumentation amplifier shown in Figure 50 is composed

of two well matched transconductance amplifiers (GM1 and

GM2), the dc blocking amplifier (HPA), and an integrator

formed by C1 and an op amp. The transconductance amplifier,

GM1, generates a current that is proportional to the voltage

present at its inputs. When the feedback is satisfied, an equal

voltage appears across the inputs of the transconductance

amplifier, GM2, thereby matching the current generated by

GM1. The difference generates an error current that is integrated

across Capacitor C1. The resulting voltage appears at the

output of the instrumentation amplifier.

The feedback of the amplifier is applied via GM2 through two

separate paths: the two resistors divide the output signal to set

an overall gain of 100, whereas the dc blocking amplifier

integrates any deviation from the reference level. Consequently,

dc offsets as large as ±300 mV across the GM1 inputs appear

inverted and with the same magnitude across the inputs of

GM2, all without saturating the signal of interest.

To increase the common-mode voltage range of the instrumen-

tation amplifier, a charge pump boosts the supply voltage for

the two transconductance amplifiers. This boost in supply

voltage further prevents saturation of the amplifier in the

presence of large common-mode signals, such as line

interference. The charge pump runs from an internal oscillator,

the frequency of which is set around 500 kHz.

OPERATIONAL AMPLIFIER

The general-purpose operational amplifier (A1) is a rail-to-rail

device that can be used for low-pass filtering and to add

additional gain. The following sections provide details and

example circuits that use this amplifier.

RLD AMPLIFIER

The RLD amplifier inverts the common-mode signal that is

present at the instrumentation amplifier inputs. When the right

leg drive output current is injected into the subject, it

counteracts common-mode voltage variations, thus improving

the common-mode rejection of the system.

10kΩ

IAOUTHPSENSEHPDRIVE

GM1 GM2

99R

+VS

0.7V

INST RUMENTAT IO N AMPLIFIER (IA)

+VS – 0.1V

0.1V

REFOUTREFIN

–IN

+IN

VCM

RLD SDN LOD

+VS – 0.27V

SW OPAMP+ OPAMP–

OUT

RLD

RLDFB

GND

150kΩ

10kΩ

HPA

+VS

= REF OUT

CHARGE

PUMP

SYNC

RECTIFIER

SWITCH

TIMING

AC/DC

SDN

D4 D3 D2

A5 A4

*ALL SWITCHES SHOWN IN DC LEADS OFF DETECTION POSITION AND FAST RESTORE DISABLED

RFI

FILTER

13737-050

Figure 50. Simplified Schematic Diagram

AD8233 Data Sheet

Rev. D | Page 18 of 32

The common-mode signal that is present across the inputs of the

instrumentation amplifier is derived from the transconductance

amplifier, GM1. It is then connected to the inverting input of

A2 through a 150 kΩ resistor.

An integrator can be built by connecting a capacitor between

the RLD FB and RLD terminals. A good starting point is a 1 nF

capacitor, which places the crossover frequency at about 1 kHz

(the frequency at which the amplifier has an inverting unity

gain). This configuration results in about 26 dB of loop gain

available at a frequency range from 50 Hz to 60 Hz for

common-mode line rejection. Higher capacitor values reduce

the crossover frequency, thereby reducing the gain that is

available for rejection and, consequently, increasing the line

noise. Lower capacitor values move the crossover frequency to

higher frequencies, allowing increased gain. However, when

using higher gain, the system can become unstable and saturate

the output of the right leg amplifier.

When using this amplifier to drive an electrode, place a resistor

in series with the output to limit the current to be always less

than 10 µA, even in fault conditions. For example, if the supply

used is 3.0 V, ensure that the resistor is greater than 330 kΩ to

account for component and supply variations.

RLD

1nF

*LIMI T CURRENT T O L E S S THAN 10µA.

RLDFB

REFOUT

TO DRIVEN

ELECTRODE

150kΩV

13737-051

Figure 51. Typical Configuration of Right Leg Drive Circuit

In two electrode configurations, A2 can be shut down by setting

RLD SDN low for additional power savings. If left in shutdown,

it is recommended to leave both RLD and RLDFB floating.

Alternatively, RLD can be used to bias the inputs through

10 MΩ resistors, as described in the Leads On or Off Detection

section. When the AD8233 is in shutdown and dc leads off

detection mode, RLD pulls down towards ground. This pull-

down acts as an LOD wake-up function, pulling the inputs

down when the electrodes are reconnected.

REFERENCE BUFFER

The AD8233 operates from a single supply. To simplify the

design of single-supply applications, the AD8233 includes a

reference buffer to create a virtual ground between the supply

voltage and the system ground. The signals present at the

output of the instrumentation amplifier are referenced around

this voltage. For example, if there is zero differential input

voltage, the voltage at the output of the instrumentation

amplifier is this reference voltage.

The reference voltage level is set at the REFIN pin. It can be set

with a voltage divider or by driving the REFIN pin from some

other point in the circuit (for example, from the ADC reference).

The voltage is available at the REFOUT pin for the filtering circuits

or for an ADC input.

REFIN A3

R2 C1

+VS

13737-052

Figure 52. Setting the Internal Reference

To limit the power consumption of the voltage divider, the use

of large resistors is recommended, such as 10 MΩ. The designer

must keep in mind that high resistor values make it easier for

interfering signals to appear at the input of the reference buffer.

To minimize noise pickup, it is recommended to place the

resistors close to each other and as near as possible to the

REFIN terminal. Furthermore, use a capacitor in parallel with

the lower resistor on the divider for additional filtering, as

shown in Figure 52. A large capacitor results in better noise

filtering but takes longer to settle the reference after power-up.

The total time the reference takes to settle within 1% can be

estimated with the formula

tSETTLE_REFERENCE =

5R1 R2 C1

R1 R2

××

Disabling the AD8233 with the shutdown terminal does not

discharge this capacitor.

FAST RESTORE CIRCUIT

Because of the low cutoff frequency used in high-pass filters in

ECG applications, signals may require several seconds to settle.

This settling time can result in a delay for the user after a step

response, such as when the electrodes are first connected.

This fast restore function is implemented internally, as shown

in Figure 53. The output of the instrumentation amplifier is

connected to a window comparator. The window comparator

detects a saturation condition at the output of the instrumentation

amplifier when its voltage approaches 0.1 V from either supply

rail.

SWITCH

TIMING

LOD

IAOUT 0.1V

+IN

–IN

– 0.1V

13737-053

Figure 53. Fast Restore Circuit

Data Sheet AD8233

Rev. D | Page 19 of 32

LEADS OFF LEADS O N

SAT URATION DETECTED NO SATURAT IO N

RST

13737-054

Figure 54. Timing Diagram for Fast Restore Switches (Time Base Not to Scale)

If this saturation condition is present when both input

electrodes are attached to the subject, the comparator triggers a

timing circuit that automatically closes Switch S1 and Switch

S2. See Figure 54 for the fast restore switches timing diagram.

These two switches (S1 and S2) enable two different 10 kΩ

resistor paths: one between HPSENSE and IAOUT, and

another between SW and REFOUT. During the time Switch S1

and Switch S2 are enabled, the internal resistors appear in

parallel with their corresponding external resistors, forming

high-pass filters. The result is that the equivalent lower

resistance shifts the pole to a higher frequency, delivering a

quicker settling time. The fast restore settling time depends on

how quickly the internal 10 kΩ resistors of the AD8233 can

drain the capacitors in the high-pass circuit. Smaller capacitor

values result in a shorter settling time.

If, by the end of the timing, the saturation condition persists,

the cycle repeats. Otherwise, the AD8233 returns to its normal

operation. If either of the leads off comparator outputs

indicates that an electrode is disconnected, the timing circuit is

prevented from triggering because it is assumed that no valid

signal is present. To disable fast restore, drive the FR pin low or

tie it permanently to GND.

LEADS ON OR OFF DETECTION

The AD8233 includes leads off detection. The AD8233 features

ac and dc detection modes that both work with two and three

electrode configurations. Ultralow power comparators allow

the leads on or off detection to remain functional in shutdown

mode, creating power savings at the system level when the LOD

output is used as a wake-up signal for the microcontroller.

DC Leads On or Off Detection

The dc leads off detection mode can be used in two or three

electrode configurations. This mode works by sensing when

either instrumentation amplifier input voltage is within 0.27 V

from the positive rail. The lowest power use case for the

AD8233 is two electrode dc mode. A pull-up resistor on +IN

and a pull-down resistor on −IN create a voltage divider when

the electrodes are connected, setting the input common mode

to midsupply. When the electrodes disconnect, the comparator

monitoring +IN sets LOD high when the input pulls to +VS.

10MΩ

+VS

13737-055

Figure 55. Circuit Configuration for Two Electrode DC Leads Off Detection

For three electrode dc mode, each input must have a pull-up

resistor connected to the positive supply. During normal

operation, the potential of the subject must be inside the

common-mode range of the instrumentation amplifier, which

is only possible if a third electrode is connected to the output of

the right leg drive amplifier.

RLD

10MΩ 10MΩ

TO DRIVEN

ELECTRODE

13737-056

Figure 56. Circuit Configuration for Three Electrode DC Leads Off Detection

The AD8233 indicates when any electrode is disconnected by

setting the LOD pin high. To use this mode, connect the

AC/DC pin to ground.

AC Leads On or Off Detection

The ac leads off detection mode is useful when using two

electrodes. A conduction path must exist between the two

electrodes, which is usually formed by two resistors, as shown

in Figure 57.

These resistors also provide a path for bias return on each

input. Connect each resistor to REFOUT or RLD to maintain the

inputs within the common-mode range of the instrumentation

amplifier.

AD8233 Data Sheet

Rev. D | Page 20 of 32

REFOUT

10MΩ 10MΩ

13737-057

Figure 57. Circuit Configuration for Two Electrode AC Leads Off Detection

The AD8233 detects when an electrode is disconnected by

forcing a 100 kHz current into the input terminals. This current

flows through the external resistors from IN+ to IN− and

develops a differential voltage across the inputs, which is then

synchronously detected and compared to an internal threshold.

The recommended value for these external resistors is 10 MΩ.

Low resistance values make the differential drop too low to be

detected and lower the input impedance of the amplifier. When

the electrodes are attached to the subject, the impedance of this

path must be less than 3 MΩ to maintain the drop below the

threshold of the comparator.

To use the ac leads off mode, tie the AC/DC pin to the positive

supply rail. Although REFOUT is at a constant voltage value,

using the RLD output as the input bias may be more effective in

rejecting common-mode interference at the expense of

additional power.

In three electrode ac leads off detection mode, shown in Figure 58,

pull-up resistors are not required, which improves the input

impedance of the circuit. This mode is beneficial for dry electrode

applications. The ac mode currents contribute flicker noise (1/f

noise) to the system. Depending on the application, use ac leads

off detection as a spot check and then switching to dc mode for

improved ECG acquisition.

RLD

TO DRIVEN

ELECTRODE

13737-058

Figure 58. Circuit Configuration for Three Electrode AC Leads Off Detection

The ac leads off detection mode continues to function in

shutdown mode as well. To keep the power under 1 µA, the

clock is disabled and the ac currents become dc currents. The

current source on +IN is 250 nA, while the current sink on –IN

is −300 nA. The stronger pull-down current on −IN acts as a

wake-up function, pulling LOD low when the electrodes are

reconnected.

STANDBY OPERATION

The AD8233 includes a shutdown pin (SDN) that further

enhances the flexibility and ease of use in portable applications

where low power consumption is critical. A logic level signal

can be applied to this pin to switch to shutdown mode.

Driving the SDN pin low places the AD8233 in shutdown mode

and draws less than 1 µA of supply current, offering considerable

power savings. To enter normal operation, drive SDN high. When

not using this feature, permanently tie SDN to +VS.

During shutdown operation, the AD8233 cannot maintain the

REFOUT voltage, but it does not drain the REFIN voltage,

thereby maintaining this additional conduction path from the

supply to ground.

When emerging from a shutdown condition, the charge stored

in the capacitors on the high-pass filters can saturate the instru-

mentation amplifier and subsequent stages. The use of the fast

restore feature helps reduce the recovery time and, therefore,

minimize the amount of time powered on in power sensitive

applications.

Using leads on or off detection in shutdown mode allows

system level power saving. The microcontroller enters sleep

mode when the electrodes are disconnected, and the LOD signal

acts as an interrupt to wake up the microcontroller. An example

of this functionality is shown in Figure 59.

1 -

AT LEAST ONE ELECTRODE I S OFF

AND THEREFORE LOD OUTPUT IS HIGH.

MCU IS OFF AND S DN IS LOW .

(AD8 23 3 SHUT DOWN CURRE NT < 1µA)

2 -

LOD GOES LOW WHEN BOTH

ELECTRODES ARE CONNECTED.

A FALLING E DGE AT LOD W AKES UP

THE M CU.

3 -

MCU W AKES UP

AND SETS SDN HIG H.

4 -

AD8233 IS ACTIVE (~ 50µ A)

AND MONITORI NG ECG.

250mV/DIV

400ms/DIV

OUT

SDN

LOD

13737-059

Figure 59. Electrode Connection and System Wakeup Sequence

INPUT PROTECTION

All terminals of the AD8233 are protected against ESD. In

addition, the input structure allows dc overload conditions that

are a diode drop above the positive supply and a diode drop

below the negative supply. Voltages beyond a diode drop of the

supplies cause the ESD diodes to conduct and enable current to

flow through the diode. Use an external resistor in series with

each of the inputs to limit current for voltages beyond the

supplies. In either scenario, the AD8233 safely handles a

continuous 5 mA current at room temperature.

For applications where the AD8233 encounters extreme over-

load voltages, such as in cardiac defibrillators, use external

series resistors and gas discharge tubes (GDTs). Neon lamps

are commonly used as an inexpensive alternative to GDTs.

Data Sheet AD8233

Rev. D | Page 21 of 32

These devices can handle the application of large voltages but

do not maintain the voltage below the absolute maximum

ratings for the AD8233. A complete solution includes further

clamping to either supply using additional resistors and low

leakage diode clamps, such as BAV199 or FJH1100.

As a safety measure, place a resistor between the input pin and

the electrode that is connected to the subject to ensure that the

current flow never exceeds 10 µA. Calculate the value of this

resistor to be equal to the supply voltage across the AD8233

divided by 10 µA.

RADIO FREQUENCY INTERFERENCE

Radio frequency (RF) rectification is often a problem in

applications where there are large RF signals. The problem

appears as a dc offset voltage at the output. The AD8233 has a

15 pF gate capacitance and 10 kΩ resistors at each input. This

forms a low-pass filter on each input that reduces rectification

at high frequency (see Figure 60) without the addition of

external elements.

AD8233

IAOUT

+IN

–IN

10kΩ

13737-060

Figure 60. RFI Filter Without External Capacitors

For increased filtering, additional resistors can be added in

series with each input. They must be placed as close as possible

to the instrumentation amplifier inputs. These can be the same

resistors used for overload and patient protection.

POWER SUPPLY REGULATION AND BYPASSING

The AD8233 is designed to be powered directly from a single

3 V battery, such as a CR2032. The AD8233 can also operate

from rechargeable Li-Ion batteries, but the designer must take

into account that the voltage during a charge cycle may exceed

the absolute maximum ratings of the AD8233. To avoid

damage to the device, use a power switch or a low power, low

dropout regulator, such as the ADP150 or ADP160.

In addition, excessive noise on the supply pins can adversely

affect performance. As in all linear circuits, bypass capacitors

must be used to decouple the chip power supplies. Place a

0.1 μF capacitor close to the supply pin. A 1 μF capacitor can be

used farther away from the device. In most cases, the capacitor

can be shared by other integrated circuits. Excessive decoupling

capacitance increases power dissipation during power cycling.

INPUT REFERRED OFFSETS

Because of its internal architecture, the instrumentation

amplifier must always be used with the dc blocking amplifier,

labeled HPA in Figure 50.

The dc blocking amplifier attenuates the input referred offsets

present at the inputs of the instrumentation amplifier, as

described in the Theory of Operation section. However, this

attenuation only occurs when the dc blocking amplifier is used

as an integrator. In this case, the input offsets from the dc

blocking amplifier are dominant and appear directly at the

output of the instrumentation amplifier.

If the dc blocking amplifier is used as a follower instead of its

intended function as an integrator, the input referred offsets of

the in-amp are amplified by a factor of 100.

LAYOUT RECOMMENDATIONS

It is important to follow good layout practices to optimize

system performance. In low power applications, most resistors

are of a high value to minimize additional supply current. The

challenge of using high value resistors is that high impedance

nodes become even more susceptible to noise pickup and board

parasitics, such as capacitance and surface leakages. Keep all of

the connections between high impedance nodes as short as

possible to avoid introducing additional noise and errors from

corrupting the signal.

To maintain high CMRR over frequency, keep the input traces

symmetrical and length matched. Place safety and input bias

resistors in the same position relative to each input. In addition,

the use of a ground plane significantly improves the noise

rejection of the system.

For WLCSP layout best practices, refer to the AN-617

Application Note.

AD8233 Data Sheet

Rev. D | Page 22 of 32

APPLICATION INFORMATION

ELIMINATING ELECTRODE OFFSETS

The instrumentation amplifier in the AD8233 is designed to

apply gain and to filter out near dc signals simultaneously. This

capability allows the device to amplify a small ECG signal by a

factor of 100 while rejecting electrode offsets as large as ±300 mV.

To achieve offset rejection, connect a resistor/capacitor (RC)

network between the output of the instrumentation amplifier

(HPSENSE) and HPDRIVE, as shown in Figure 61.

10kΩ

IAOUTHPSENSEHPDRIVE

GM1 GM2

99R

IN+

IN– V

ELECTRODE

OFFSETS

= REF OUT

A5 A4

13737-061

Figure 61. Eliminating Electrode Offsets

This RC network forms an integrator that feeds any dc signals

that are not filtered back into the instrumentation amplifier,

thus eliminating the offsets without saturating any node and

maintaining high signal gain.

In addition to blocking offsets present across the inputs of the

instrumentation amplifier, this integrator also works as a high-pass

filter that minimizes the effect of slow moving signals, such as

baseline wander. The cutoff frequency of the filter is given by

the following equation:

fC =

100

2RCπ

where:

R is in Ω.

C is in farads.

The filter cutoff is 100 times higher than is typically expected

from a single-pole filter. Because of the feedback architecture of

the instrumentation amplifier, the typical filter cutoff equation

is modified by a gain of 100 from the instrumentation

amplifier.

0.01 1001010.1

MAG NITUDE ( dB)

FREQUENCY ( Hz )

20dB PE R

DECADE

13737-062

Figure 62. Frequency Response of a Single-Pole DC Blocking Circuit

As with any high-pass filter with low frequency cutoff, a fast

change in dc offset requires a long time to settle. If such a change

saturates the instrumentation amplifier output, the S1 switch

briefly enables the 10 kΩ resistor path, thus moving the cutoff

frequency to

fC =

100( 10 )

2 (10 )

For values of R greater than 100 kΩ, this expression can be

approximated by

fC =

π200

This higher cutoff frequency reduces the settling time and

enables faster recovery of the ECG signal. For more

information, see the Fast Restore Circuit section.

HIGH-PASS FILTERING

The AD8233 can implement higher order high-pass filters. A

higher filter order yields better artifact rejection, but increased

signal distortion and more passive components on the PCB.

Two-Pole High-Pass Filter

A two-pole architecture can be implemented by adding a

simple ac coupling RC at the output of the instrumentation

amplifier, as shown in Figure 63.

10kΩ

IAOUT

HPSENSEHPDRIVE

+IN

–IN

HPA

10kΩ

REFOUT

TO NEXT

STAGE

= REF OUT

A5 A4

C1 C2

13737-063

Figure 63. Schematic for a Two-Pole High-Pass Filter

Data Sheet AD8233

Rev. D | Page 23 of 32

The right side of C2 connects to the SW terminal. As with S1,

S2 reduces the recovery time for the ac coupling network by

placing 10 kΩ in parallel with R2. See the Fast Restore Circuit

section for additional details on switch timing and trigger

conditions.

If the passive network is not buffered, the network exhibits

higher output impedance at the input of a subsequent low-pass

filter, as with Sallen-Key filter topologies. Careful component

selection results in reliable performance without a buffer. See

the Low-Pass Filtering and Gain section for additional

information on component selection.

Additional High-Pass Filtering Options

In addition to the topologies explained in previous sections, an

additional pole may be added to the dc blocking circuit for the

rejection of low frequency signals. This configuration is shown

in Figure 64.

10kΩ

IAOUT

HPSENSE

HPDRIVE

+IN

–IN

HPA

10kΩ

REFOUT C3

TO NEXT

STAGE

= REF OUT

A5 A4

C1 R1 R2

RCOMP

13737-064

Figure 64. Schematic for an Alternative Two-Pole, High-Pass Filter

An extra benefit of this circuit topology is that it allows a lower

cutoff frequency with lower R and C values. The resistor, RCOMP,

can also be used to control the quality factor (Q) of the filter to

achieve narrow band-pass filters (for heart rate detection) or

maximum pass-band flatness (for cardiac monitoring).

With this circuit topology, the filter attenuation reverts to a

single-pole roll-off at very low frequencies. Because the initial

roll-off is 40 dB per decade, this reversion to 20 dB per decade

has little impact on the ability of the filter to reject out-of-band

low frequency signals.

The designer may choose different values to achieve the desired

filter performance. To simplify the design process, use the

following recommendations as a starting point for component

value selection.

R1 = R2 ≥ 100 kΩ

C1 = C2

RCOMP = 0.14 × R1

The cutoff frequency is located at

fC =

C2R2C1R1 ×××π2

The selection of RCOMP to be 0.14 times the value of the other

two resistors optimizes the filter for a maximally flat pass band.

Reduce the value of RCOMP to increase the Q and, consequently,

the peaking of the filter. A very low RCOMP value may result in

an unstable circuit. The selection of values based on these criteria

results in a transfer function similar to what is shown in Figure 66.

When additional low frequency rejection is desired, a high-

order, high-pass filter can be implemented by adding an ac

coupling network at the output of the instrumentation amplifier,

as shown in Figure 65. The SW terminal is connected to the ac

coupling network to obtain the best settling time response

when fast restore engages.

10kΩ

IAOUTHPSENSEHPDRIVE

+IN

–IN

HPA

10kΩ

REFOUT

TO NEXT

STAGE

= REF OUT

A5 A4

C1 C3

R1 R2

COMP

C2 R3

13737-065

Figure 65. Schematic for a Three-Pole, High-Pass Filter

–20

–40

–60

0.01 1001010.1

MAG NITUDE ( dB)

FRE Q UE NCY ( Hz )

THREE-POLE FILTER

TWO-POLE FILTER

40dB P ER

DECADE

40dB P ER

DECADE

20dB P ER

DECADE 60d B PE R

DECADE

13737-066

Figure 66. Frequency Response of the Circuits Shown in Figure 64 and

Figure 65

Careful analysis and adjustment of all of the component values in

practice is recommended to optimize the filter characteristics. To

reduce the value of RCOMP, increase the peaking of the active filter to

overcome the additional roll-off introduced by the ac coupling

network. Proper adjustment yields the best pass-band flatness.

AD8233 Data Sheet

Rev. D | Page 24 of 32

Table 6. Comparison of High-Pass Filtering Options

Figure to Reference

Filter

Order Component Count Low Frequency Rejection

Capacitor

Sizes/Values

Signal

Distortion1

Output

Impedance2

Figure 61 1 2 Good Large Low Low

Figure 63 2 4 Better Large Medium Higher

Figure 64 2 5 Better Smaller Medium Low

Figure 65 3 7 Best Smaller Highest Higher

1 The signal distortion is for the equivalent corner frequency location.

2 Output impedance refers to the drive capability of the high-pass filter before the low-pass filter. Low output impedance is desirable to allow flexibility in the selection

of values for a low-pass filter, as explained in the Low-Pass Filtering and Gain section.

The design of the high-pass filter involves trade-offs between

signal distortion, component count, low frequency rejection,

and component size. For example, a single-pole, high-pass filter

results in the least distortion to the signal, but the associated

rejection of low frequency artifacts is the lowest of the available

filter options. Table 6 compares the recommended filtering

options.

LOW-PASS FILTERING AND GAIN

The AD8233 includes an uncommitted op amp that can be

used for extra gain and filtering. For applications that do not

require a high order filter, a simple RC low-pass filter is

sufficient, and the op amp can buffer or further amplify the signal.

REFOUT

FILTERED

SIGNAL

FRO M IN-AM P

STAGE

13737-067

Figure 67. Schematic for a Single-Pole, Low-Pass Filter and Additional Gain

A Sallen-Key filter topology can be implemented for

applications that require a steeper roll-off or a sharper cutoff

frequency, as shown in Figure 68.

REFOUT

FILTERED

SIGNAL

FROM I N- AM P

STAGE

13737-068

Figure 68. Schematic for a Two-Pole, Low-Pass Filter

The following equations describe the low-pass cutoff frequency

(fC), gain, and Q:

fC =

2 112 2RCR Cπ ×× ×

Gain = 1 + R3/R4

Q =

(1 )

R1 C1 R2 C2

R1 C2 R2 C2 R1 C1 Gain

×××

×+×+× −

Changing the gain has an effect on Q and vice versa. Common

values for Q are 0.5, to avoid peaking, or 0.7 for maximum

flatness and a sharp cutoff frequency. Use a high Q value in

narrow-band applications to increase peaking and the

selectivity of the band-pass filter.

A common design procedure is to set R1 = R2 = R and C1 = C2 =

C, simplifying the expressions for the cutoff frequency and Q to

fC = 1/(2πRC)

Q =

Gain−

Q can be controlled by setting the gain with R3 and R4, but this

setting limits the gain to be less than 3. The circuit becomes

unstable for gain values equal to or greater than 3. A simple

modification that allows higher gains is to make the value of C2

at least four times larger than C1.

These design equations only hold true in a case where the

output impedance of the previous stage is much lower than the

input impedance of the Sallen-Key filter. The design equations

do not hold true when using an ac coupling network between

the instrumentation amplifier output and the input of the low-

pass filter without a buffer.

To connect these two filtering stages properly without a buffer,

make the value of R1 at least 10 times larger than the resistor of

the ac coupling network (labeled as R2 in Figure 63).

Driving ADCs

The ability of AD8233 to drive capacitive loads makes it ideal

for driving an ADC without an additional buffer. However,

depending on the input architecture of the ADC, a simple, low-

pass RC network may be required to decouple the transients

from the switched capacitor input that are typical of modern

ADCs. This RC network also acts as an additional filter that can

help reduce noise and aliasing. Follow the recommended

guidelines from the ADC in use for the selection of proper R

and C values. Table 7 lists compatible ADCs by category.

Table 7. Compatible ADCs by Category

ADCs Microcontrollers

Optical/

Bio-Z Sensors Accelerometers

AD7091 ADuCM350 ADPD1081 ADXL363

AD7988-1 ADuCM3029 ADPD188GG

AD7682 ADuCM4050 ADPD1080

AD7689 ADPD4000

AD5940

Data Sheet AD8233

Rev. D | Page 25 of 32

RADC

AD8233

13737-069

Figure 69. Driving an ADC

DRIVEN ELECTRODE

A driven electrode (or reference electrode) is often used to

minimize the effects of common-mode voltages induced by the

power line and other interfering sources. The AD8233 extracts

the common-mode voltage from the instrumentation amplifier

inputs and makes it available through the RLD amplifier to

drive an opposing signal into the patient. This functionality

maintains the voltage between the patient and the AD8233 at a

near constant, greatly improving the CMRR.

As a safety measure, place a resistor between the RLD pin and

the electrode connected to the subject to ensure that current

flow never exceeds 10 µA. Calculate the value of this resistor to be

equal to the supply voltage across the AD8233 divided by 10 µA.

The AD8233 implements an integrator formed by an internal

150 kΩ resistor and an external capacitor to drive this

electrode. The choice of the integrator capacitor is a trade-off

between line rejection capability and stability. It is recommended

that the capacitor be small to maintain as much loop gain as

possible, around 50 Hz and 60 Hz, which is typical for line

frequencies. For stability, it is recommended that the gain of the

integrator be less than unity gain at the frequency of any other

poles in the loop, such as those formed by the capacitance and

the safety resistors of the patient. The suggested application circuits

use a 1 nF capacitor, which results in a loop gain of about 20 at

line frequencies, with a crossover frequency of about 1 kHz.

In a 2-lead configuration, the RLD pin amplifier can be shut down

or used to drive the bias current resistors on the inputs. Although

not as effective as a true driven electrode, this configuration can

provide some common-mode rejection improvement if the sense

electrode impedance is small and well matched.

MEASURING SURFACE ELECTROMYOGRAPHY

(EMG) OR ELECTROENCEPHALOGRAPHY (EEG)

Due to its flexible architecture, the AD8233 filters can be

configured to measure other biopotential signals, such as

surface EMG or nondiagnostic EEG (alpha or beta waves). The

frequency range of signals for surface EMG is typically 2 Hz to

500 Hz for skeletal muscles and 0.01 Hz to 1 Hz for smooth

muscles. When measuring wider bandwidth signals inclusive of

50 Hz or 60 Hz, consider lower gain settings. EEG signals have a

shared frequency range with ECG signals. However, the amplitude

for EEG signals is about 10 times smaller than those for ECG, and

as such, require a lower noise solution. Alpha waves (8 Hz to 13

Hz) and beta waves (14 Hz to 40 Hz) can be measured with the

AD8233 by setting the high-pass filter at 7 Hz, similar to ECG

measurement at the hands (see Figure 72). The 7 Hz cutoff

frequency helps remove additional 1/f noise, which lowers the

noise floor for the EEG measurement.

APPLICATION CIRCUITS

Heart Rate Measurement (HRM) Next to the Heart

For wearable exercise devices, the AD8233 is typically placed in

a pod near the heart. The two sense electrodes are placed under

the pectoral muscles, and no driven electrode is used. Because

the distance from the heart to the AD8233 is small, the heart

signal is strong and there is less muscle artifact interference.

In this wearable device configuration, space is at a premium. By

using as few external components as possible, the circuit shown

in Figure 70 is optimized for size.

+IN

–IN

HPDRIVE

HPSENSE

IAOUT

REFIN

GND

AC/DC

RLD SDN

SDN

LOD

RLD

RLDFB

OUT

OPAMP+

OPAMP–

REFOUT

AD8233

180kΩ

10MΩ

10MΩ 0.1µF

10MΩ

1nF

10MΩ

ELECTRODE

INTERFACE

0.1µF

0.22µF

TO DIGITAL

INTERFACE

SIGNAL

OUTPUT

10MΩ

13737-070

Figure 70. Circuit for HRM Next to the Heart

A shorter distance from the AD8233 to the heart makes this

application less vulnerable to common-mode interference.

However, because RLD is not used to drive an electrode, it can

be used to improve the common-mode rejection by main-

taining the midscale voltage through the 10 MΩ bias resistors.

Alternatively, tie RLD SDN low to save power, and tie the bias

resistors to REFOUT.

A single-pole, high-pass filter is set at 7 Hz, and there is no low-

pass filter. No gain is used on the output op amp, which reduces

the number of resistors for a total system gain of 100, as shown in

Figure 71.

0.1 10k

MAG NITUDE ( dB)

FRE Q UE NCY ( Hz )

110 100 1k

13737-071

Figure 71. Frequency Response for HRM Next to the Heart Circuit

AD8233 Data Sheet

Rev. D | Page 26 of 32

The input terminals in this configuration use two 180 kΩ

resistors to protect the user from fault conditions. Two 10 MΩ

resistors provide input bias. Use higher values for electrodes

with high output impedance, such as cloth electrodes.

Figure 70 also shows two 10 MΩ resistors to set the midscale

reference voltage. If there is already a reference voltage available,

it can be driven into the REFIN input to eliminate these two

10 MΩ resistors.

Exercise Application, HRM at the Hands

In this application, the heart rate signal is measured at the

hands with stainless steel electrodes. The arm and upper body

movement of the user create large motion artifacts, and the

long lead length makes the system susceptible to common-

mode interference. A very narrow band-pass characteristic is

required to separate the heart signal from interference.

+VS

+IN

–IN

HPDRIVE

+VS

HPSENSE

IAOUT

REFIN

GND

AC/DC

RLD SDN

LOD

RLD

RLDFB

OUT

OPAMP+

OPAMP–

REFOUT

AD8233

22nF

1MΩ

100kΩ

3.3nF

100kΩ

180kΩ

1MΩ

10MΩ

10MΩ 0.1µF

10MΩ

1nF

10MΩ

0.1µF

360kΩ

0.22µF

TO DIGITAL

INTERFACE

SIGNAL OUTPUT

0.22µF

SDN

+VS

13737-072

Figure 72. Circuit for HRM at Hands

The circuit shown in Figure 72 uses a two-pole, high-pass filter

set at 7 Hz. A two-pole, low-pass filter at 24 Hz follows the

high-pass filters to eliminate any other artifacts and line noise.

0.1 1k

MAG NI TUDE ( dB)

FRE Q UE NCY ( Hz )

110 100

13737-073

Figure 73. Frequency Response for HRM Circuit Taken at the Hands

The overall narrow-band nature of the two-pole, low-pass filter

combination distorts the ECG waveform significantly. Therefore,

it is only suitable to determine the heart rate, and not to analyze the

ECG signal characteristics.

The low-pass filter stage also includes a gain of 11, bringing the

total system gain close to 1100. Because the ECG signal is

measured at the hands, it is weaker than when measured closer

to the heart.

The RLD circuit drives to the third electrode, which can also be

located at the hands, to cancel common-mode interference.

Holter Monitor Configuration

The circuit in Figure 75 is designed for monitoring the shape of

the ECG waveform.

To obtain an ECG waveform with minimal distortion, the

AD8233 is configured with a 0.5 Hz, single-pole, high-pass

filter, followed by a two-pole, 40 Hz, low-pass filter. A third

electrode is driven for optimum common-mode rejection.

0.01 1k

MAG NITUDE ( dB)

FRE Q UE NCY ( Hz )

0.1 110 100

13737-075

Figure 74. Frequency Response of Holter Monitor Circuit

In addition to 40 Hz filtering, the op amp stage is configured

for a gain of 2, resulting in a total system gain of 200. Keeping

the gain lower helps with any motion artifacts picked up in

band. To optimize the dynamic range of the system, the gain

level is adjustable, depending on the input signal amplitude

(which may vary with electrode placement) and ADC input range.

Data Sheet AD8233

Rev. D | Page 27 of 32

+VS

HPSENSE

IAOUT

+VS

REFIN

GND

AC/DC

SDN

LOD

+IN

–IN

HPDRIVE

RLD

RLDFB

OUT

OPAMP+

OPAMP–

REFOUT

AD8233

5.6nF

499kΩ

1MΩ

5.6nF

150kΩ

1MΩ

10MΩ

10MΩ 0.1µF

10MΩ

0.1µF

300kΩ

3.3µF

+VS

(= + 2.5V)

ELECTRODE

INTERFACE

... TO 11- 13 E NOB ADC

RLD S DN

10MΩ

+VS

1nF

10MΩ

+VS

10MΩ

...TO MCU

0.5Hz TO 40Hz

GAIN = × 200

13737-074

Figure 75. Holter Monitor Circuit

HPSENSE

IAOUT

+VS

REFIN

GND

AC/DC

SDN

LOD

+IN

–IN

HPDRIVE

RLD

RLDFB

OUT

OPAMP+

OPAMP–

REFOUT

AD8233

22nF

100kΩ

1MΩ

100kΩ

11nF

150kΩ

1MΩ

10MΩ

10MΩ 0.1µF

10MΩ

0.1µF

0.22µF

1µF 1µF VBATT

ADXL362

VDDI/O

GND

TO HOST,

MEMORY

DISPLAY

1.8V TO 3.5V

CLK

ELECTRODE

INTERFACE

SPI1_CLK_GPIO22

SPI1_MOSI_GPIO23

SPI1_MISO_GPIO24

SPI2_CLK_GPIO18

SPI2_MOSI_GPIO19

SPI2_MISO_GPIO20

SPI2_CS0_GPIO21

XINT0_WAKE0/GPIO15

SPI1_CS0_GPIO25

VDCDC_OUT

VLDO_OUT

ADuCM3029

ADP150

GND VINVOUT

SCLK

INT2

MOSI

MISO

ADC0_VIN0

SPI0_RDY/GPIO30

XINT0_WAKE1/GPIO16

RLD S DN

10MΩ 1nF

4.7µF

VREF_ADC

GND_VREFADC

0.1µF

1µF GND_ANA

VBAT_ADC

VBAT_ANA1

VBAT_ANA2

VBAT_DIG1

VBAT_DIG2

GND_DIG

0.1µF

0.47µF

SEL E CT VRE F_ADC = 2.5V

+VS+VS

+VS

150kΩ

0.22µF

10MΩ

7Hz T O 26Hz

GAI N = × 1100

+VS

13737-076

Figure 76. Portable Heart Rate and Activity Monitor Circuit

AD8233 Data Sheet

Rev. D | Page 28 of 32

Portable Heart Rate and Activity Monitor System

The circuit in Figure 76 shows the AD8233 configured as an

HRM circuit for two electrode applications. The AD8233

implements a two-pole, low-pass filter with a cutoff frequency

of 7 Hz, and a two-pole, low-pass filter with a cutoff frequency

of 26 Hz. The total signal gain in the pass band is 1,100.

The output of this HRM circuit is sampled by the 12-bit ADC

embedded in the ADuCM3029, an ultralow power (<38 µA/MHz,

<750 nA in hibernate mode) Arm® Cortex™ M3 microcontroller.

The ADXL362 is a micropower (1.8 µA at 100 SPS), 3-axis

accelerometer that monitors user activity and features an output

that serves as the basis for motion-based applications, such as

pedometers, calorie burn estimation, and activity tracking. The

ADXL362 also features a deep first in, first out (FIFO) that

stores samples and allows the system to sleep for long periods of

time, minimizing the system power.

Synchronous ECG and Photoplethysmography (PPG)

Measurement Using Transimpedance Amplifier (TIA)

ADC Mode Using the ADPD1080

In wearable devices developed for monitoring the health care of

patients, it is often necessary to have synchronized measurements

of biomedical signals. For example, a synchronous measurement

of patient ECG and PPG can determine the pulse wave transit time

(PWTT), which can then estimate blood pressure.

The circuit shown in Figure 78 shows a synchronous ECG and

PPG measurement using the AD8233 and the ADPD1080. The

AD8233 implements a two-pole high-pass filter (HPF) with a

cutoff frequency at 0.3 Hz, and a two-pole low-pass filter (LPF)

with a cutoff frequency of 37 Hz. The output of the AD8233 is fed

to one of the current inputs of the ADPD1080 through a 200 kΩ

resistor to convert the voltage output of the AD8233 into a current.

The ADPD1080 is configured to alternately measure the

photodiode signal and the ECG signal from the AD8233 on

consecutive timeslots to provide fully synchronized PPG and

ECG measurements. Data can be read out of the on-chip FIFO

or straight from data registers. The ADPD1080 channel used to

process the ECG signal is set up in TIA ADC mode, and the

input bias voltage must be set to the 0.90 V setting using Bits[5:4]

of Register 0x42 if the ECG signal is on Time Slot A, or

optimize the dynamic range of the signal path. The channel used to

process the PPG signal is configured in its normal operating

mode. Figure 77 shows a plot of a synchronized ECG and PPG

measurement using the AD8233 with the ADPD1080.

6000

6500

7000

7500

8000

8500

9000

9500

10000

50000

50500

51000

51500

52000

109

127

145

163

181

199

217

235

253

271

289

307

325

343

ECG (LSBs)

PPG (LSBs)

PPG

ECG

SAMPLE RATE (ms)

13737-149

Figure 77. Plot of Synchronized ECG and PPG Waveforms

1.8V

+IN

–IN

HPDRIVE

HPSENSE

IAOUT

REFIN

GND

AC/DC

SDN

LOD

RLD

RLDFB

OUT

OPAMP+

OPAMP–

REFOUT

AD8233

6.8nF

1MΩ

250kΩ

2.7nF

100kΩ

180kΩ

1MΩ

10MΩ

10MΩ 0.1µF

10MΩ

1nF

10MΩ

0.1µF

360kΩ

4.7µF

TO DIGITAL

INTERFACE

4.7µF

RLD SDN

1.8V

200kΩ

PD5

PD1

PDC

LEDX1

VLED

VREF

1µF

AGND

DGND

LGND

0.1µF 0.1µF

DVDD

AVDD

1.8V

10kΩ 10kΩ

1.8V

SCL

SDA

GPIO0

GPIO1

TO DIGITAL

INTERFACE

ADPD1080

13737-148

Figure 78. Synchronized PPG and ECG Measurement Using the ADPD1080 with the AD8233

Data Sheet AD8233

Rev. D | Page 29 of 32

USING AD5940, AD8232, AND AD8233 FOR

BIOIMPEDANCE AND ELECTROCARDIOGRAM (ECG)

MEASUREMENTS

The AD5940 can be used in conjunction with the AD8232 and

the AD8233 to perform bioimpedance and ECG measurements.

The same electrodes can be used to facilitate both measurements.

When a bioimpedance measurement (for example, body

composition, hydration, and electrodermal activity (EDA)) is

required, the AD8232 and AD8233 are put into shutdown (the

SDN pin on the AD8232 and the AD8233 is controlled by the

AD5940 GPIOx pin) and the AD5940 switch matrix

disconnects the AD8232 and the AD8233 from the electrodes.

When an ECG measurement is required, the AD5940 switch

matrix disconnects the AD5940 AFE from the electrodes and

connects the AD8233 front end. The AD8233 analog output is

connected to the high performance, 16-bit ADC on the

AD5940 through an AINx pin. The measurement data is stored

in the AD5940 data FIFO to be read by the host controller.

For more information, refer to the AN-1557 Application Note.

E1 E2

LIMIT

ISO

ISOBIA

LIMITECG

ISO

LIMITECG

TIABIA

LIMITECG

LIMIT

HPDRIVE HPSENSE

IAOUT

REFIN

HOST/

AD5940

AD8233

GND

AC/DC

RLD SDN

SDN

LOD

+IN

–IN

RLD

RLDFB

OPAMP+

REFOUT

OPAMP–

OUT

AAF

VBIAS

AIN1

AIN2

CE0

AIN1

RE0

DE0

SE0

AIN4

AIN3

AIN0

MUX

10MΩ

ADC

COARSE

OFFSET

CORRECTION

HSTIA

LPTIA

VREF2V5

RF = 0Ω

RTIA = INFΩ

AIN4

AMP

HSDAC

EXCITATION

BUFFER

VBIAS0 VZERO0

CE0

AIN0 L P DUAL

OUTPUT

DAC

AIN6

AFE3

AFE2

SW2_1

AD5940

13737-079

Figure 79. Body Composition and ECG System Solution Using the AD5940 with the AD8232 and AD8233

AD8233 Data Sheet

Rev. D | Page 30 of 32

DIE INFORMATION

Die size: 2.080 mm × 1.745 mm

Die thickness: 150 µm

Bond Pad 16A and Pad 16B to GND. Bond Pad 17A and Pad 17B to +VS.

13737-179

HPDRIVE

+IN

–IN

RLDFB

RLD

LOD

SW OPAMP+ REFOUT OPAMP– OUT

6 7 8 9 10

GND

REFIN

IAOUTHPSENSE

16A16B

17A17B

181920

SDN

RLD SDN

AC/DC

Figure 80. 20-Pad Bare Die Bond Pad Diagram

Table 8. Bond Pad Information

Pad No. Mnemonic

Pad Coordinates1

X (µm) Y (µm)

1 HPDRIVE –630.5 +557

2 +IN –630.5 +176.4

3 −IN –630.5 −62.8

4 RLDFB –630.5 −261.2

5 RLD –630.5 −475.1

6 SW –356 −758

7 OPAMP+ −98.45 –758

8 REFOUT +127.95 –758

9 OPAMP− +515.95 –758

10 OUT +742.35 –758

11 LOD +925.5 −575.45

12 RLD SDN +925.5 −359.05

13 SDN +925.5 +28

14 AC/DC +925.5 +279.7

15 FR +925.5 +490.6

16A GND +821.9 +765.5

16B GND +631.9 +765.5

17A +VS +467.8 +752.5

17B +VS +272.9 +752.5

REFIN

+45.35

+758

19 IAOUT −181.05 +758

20 HPSENSE −391.95 +758

1 The pad coordinates indicate the center of each pad, referenced to the center of the die. The die orientation is indicated by the logo, as shown in Figure 80.

Data Sheet AD8233

Rev. D | Page 31 of 32

OUTLINE DIMENSIONS

2.080

2.040

2.000

1.745

1.705

1.665

BOTTOM VIEW

(BALL SI DE UP)

TOP VIEW

(BALL SI DE DOW N)

BALLA1

IDENTIFIER

0.560

0.500

0.440

0.330

0.300

0.270

SIDE VIEW

0.230

0.200

0.170

0.300

0.260

0.220

COPLANARITY

0.04

SEATING

PLANE

12-10-2015-A

PKG-003315

1.20

REF

1.60 REF

0.40

BSC

0.252

REF

0.18 REF 0.26

REF

Figure 81. 20-Ball, Backside-Coated, Wafer Level Chip Scale Package [WLCSP]

(CB-20-13)

Dimensions shown in millimeters

09-24-2018-A

1.745

2.080

0.4678

0.6319

0.8219

0.630 0.39195

0.18105 0.04535

0.2729

TOP VIEW

(CIRCUIT SIDE) SIDE VIEW

0.059 ×0.059

678910

16A

16B

17A

17B

0.15

0.557

0.1764

0.0628

0.2612

0.4751

0.356

0.09845 0.12795

0.758

0.51595 0.74235

0.9255

0.57545

0.35905

0.4906

0.2797

0.028

Figure 82. 20-Pad Bare Die [CHIP]

(C-20-3)

Dimensions shown in millimeters

AD8233 Data Sheet

Rev. D | Page 32 of 32

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD8233ACBZ-R7 −40°C to +85°C 20-Ball, Backside-Coated, Wafer Level Chip Scale Package [WLCSP] CB-20-13

AD8233C-DF −40°C to +85°C 20-Pad Bare Die [CHIP], Die on Film Frame C-20-3

AD8233C-WP −40°C to +85°C 20-Pad Bare Die [CHIP], Waffle Pack C-20-3

AD8233CB-EBZ Evaluation Board

1 Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D13737-3/20(D)