Q68000-A8906 - OSRAM OPTO SEMICONDUCTORS

RoHS Compliant - By Exemption (see page 15)

Yellow IPD2131

High Efficiency Red IPD2132

High Efficiency Green IPD2133

0.200’’ 8-Character 5x7 Dot Matrix X-Y Stackable

Alphanumeric Programmable Display™

2006-04-04 1

DESCRIPTION

The IPD2131 (yellow), IPD2132 (High Efficiency Red)

and IPD2133 (High Efficien cy Green) are eig ht- digit high

reliability 5 x 7 dot matrix Programmable Displays that

are aimed at satisfying the most demandin g di splay

requirements. They are designed for use in extremely

harsh environment s where only the most reliable parts

are acceptable. The devices are constructed in ceramic

packages with eight 4.85 mm (0.200’’) high 5 x 7 dot

matrix digits. The de vices incorporate the latest in CMOS

technology which is the heart of the device intelligence.

The CMOS IC is controlled by a user supplied eight-bit

data word on a bidirectional BUS. The ASCI I data and

attribute data ar e w ord driven. This approach allows the

displays to interface using similar techniques as a micro-

processor peripheral.

Applications include: control panels, night viewing applica-

tions, cockpit monitors, portable and vehicle technology as

well as industrial controllers.

ESD Warning: Standard precautions for CMOS

handling should be observed.

FEATURES

• Eight 4.85 mm (0.200") Dot Matrix Characters in a

Ceramic Package

• True Hermetic Glass Flat Seal for all Colors

• Internal ROM with 128 ASCII Characters

• Internal RAM for up to 16 User Defina ble Characte rs

• Programmable Control W ord Allows User to Select

from 8 Brightness Levels, Display Blink, Character

Flash, Self Test, or Clear Funct i ons

• Internal or External Clock Capability

• 8 Bit Bidirectional Data Bus Allows for Read/Write

Capability

• Contains all Display Drive and Multiplexing Circuitry

• Reset Pin for Display Initialization, Multiple Display

Blinking and Flashing Synchronization

• TTL Compatible

• Operating Temperature Range: –55° to +100°C

• Storage Temperature: –65° to +125°C

• Categorized for Luminous Intensity and Color

• X-Y Stackable

2006-04-04 2

IPD2131, IPD2132, IPD2133

Package Outlines Dimensions in mm (inch)

Ordering Information

Type Color of Emission Character Height

mm (inch) Ordering Code

IPD2131 yellow 4.85 (0.200) Q68000A8904

IPD2132 high efficiency red Q68000A8836

IPD2133 high efficiency green Q68000A8906

IDOD5204

OSRAM

IPD213X YYWW V Z

2.7 (0.105) 5.3 (0.210) 2.8 (0.111)

42.7 (1.680) max.

42.4 (1.669) min.

0.8 (0.030)

4.8 (0.191)

4.9 (0.195)

1.1 (0.045)

9.9 (0.390)

Intensity Code

EIA Date Code

Hue Category

2.3 (0.090) typ. 2.54 (0.100) typ.

Non cum.

12.7 (0.500) 0.5 (0.020) typ.

1.3 (0.050) typ.

6.3 (0.250) max.

1.8 (0.070) typ.

6.0 (0.240)

Seating

Plane

5.3 (0.210) ref.

4.6 (0.180)

0.4 (0.015) typ.

7.6 (0.300)

Tolerance: ±0.30 (0.015)

IPD2131, IPD2132, IPD2133

2006-04-04 3

Maximum Ratings (TA=25°C)

Parameter Symbol Value Unit

Operating temperatur e range Top – 55 … + 100 °C

Storage temperature range Tstg – 65 … + 125 °C

DC Supply Voltage, VCC to GND

(max. voltage with no LEDs on) VCC -0.3 to + 7.0 V

Input Voltage Levels, All Inputs -0.3 to (VCC + 0.3) V

Operating Voltage, VCC to GND

(max. voltage with 20 dots/digits on) 5.5 V

Solder Temperature

1.59 mm (0.063“) below seating plane, t < 5.0 s TS260 °C

Relative Humidity (non-condensing) 85 %

ESD (100 pF, 1.5 kΩ), each pin VZ4.0 kV

Optical Characteristics at 25°C

(VCC=5.0 V at 100% brightness level

Description Symbol Values Unit

Yellow

IPD2131

High

Efficiency

Red

IPD2132

High

Efficiency

Green

IPD2133

Luminous Intensity (min.)

(typ.) IV125

205 125

350 150

500 µcd/dot

µcd/dot

Peak Wavelength (typ.) λpeak 583 635 568 nm

Dominant Wavelength (typ.) λdom 585 626 574 nm

Notes:

1) ICC is an average value.

2) ICC is measured with the display at full brightness. Peak ICC= 28/15 ICC average (#displayed).

IPD2131, IPD2132, IPD2133

2006-04-04 4

Enlarged Character Font Dimensions in inch (mm)

Maximum Power Dissipation vs. Ambient

Temperature Derating Based on TJ

max=125°C

IDOD5205

C1 C2 C3 C4 C5 R1

2.85 (0.112)

0.76 (0.030) typ.

0.65 (0.026) typ.

4.81 (0.189)

IDDG5322

˚C

35 45 55 65 75 85 105

1.0

2.0

3.0

4.0

J-A = 30 ˚C/W

Switching Specifications

(over operating temperature range and VCC=4.5V to 5.5V)

Symbol Description Min. Units

Tacc Display Access Time—Write 210 ns

Tacc Display Access Time—Read 230 ns

Tacs Address Setup Time to CE 10 ns

Tce Chip Enable Active Time—Write 140 ns

Tce Chip Enable Active Time—Read 160 ns

Tach Address Hold Time to CE 20 ns

Tcer Chip Enable Recovery Time 60 ns

Tces Chip Enable Active Prior to

Rising Edge—Write 140 ns

Tces Chip Enable Active Prior to

Rising Edge—Read 160 ns

Tceh Chip Enable Hold to Rising Edge of

Read/Wri te Si gn al 0ns

TwWrite Active Time 100 ns

Twd Data Valid Prior to

Rising Edge of Write Signal 50 ns

Tdh Data Write Time 20 ns

TrChip Enable Active Prior to Valid Data 160 ns

Trd Read Active Prior to Valid Data 95 ns

Tdf Read Data Float Delay 10 ns

Trc Reset Active Time 300 ns

Oscillator, Refresh, Flash and Self Test Characteristics

Parameters Min. Typ. Max. Units Conditions

Clock I/O Frequency 28 57.34 81.14 kHz VCC=4.5 V to 5.5 V

External Clock Frequency 25 —640 kHz VCC=4.5 V to 5.5 V

FM, Digit Multiplex Frequency 125 256 362.5 Hz VCC=4.5 V to 5.5 V

Blinking Rate 0.98 2.0 2.83 Hz —

Clock I/O Bus Loading — — 2.40 pF —

Clock Out Rise Time — — 500 nsec VCC=4.5 V, VOH=2.4 V

Clock Out Fall Time — — 500 nsec VCC=4.5 V, VOH=0.4 V

IPD2131, IPD2132, IPD2133

2006-04-04 5

Write Cycle Timing Diagram

Read Cycle Timing Diagram

Tacc

Twd Tdh

Tces

Tcer

Tceh

Tacs Tach Tacs

0-A3

Tce

0-D7

nput pulse levels —0.6 V to 2.4 v

Tacc

Trd Tdf

TrTces

Tcer

Tceh

Tacs Tach Tacs

0-A3

Tce

0-D7

2006-04-04 6

IPD2131, IPD2132, IPD2133

Electrical Characteristics at 25°C

Parameters Limits Conditions

Min. Typ. Max. Units

VCC 4.5 5.0 5.5 V —

ICC Blank —0.5 1.0 mA VCC=5.0 V, VIN=5.0 V

ICC 12 dots/digit on (1) (2) —200 255 mA VCC=5.0 V, “V” in all 8 digits

ICC 20 dots/digit on (1) (2) —300 370 mA VCC=5.0 V, “#” in all 8 digits

IILP (with pull-up)

Input Leakage –1.0 –11 –18 µAVCC=5.0 V, VN=0 V to VCC

(WR, CE, FL, RST, RD, CLKSEL)

IIL (no pull-up)

Input Leakage –1.0 —+1.0 µAVCC=5.0 V, VIN=0–5.0 V

(CLK, A0–A4, D0–D7)

VIH

Input Voltage High 2.0 —VCC

+0.3 VVCC=4.5 V to 5.5 V

VIL

Input Voltage Low GND

–0.3 —0.8 VVCC=4.5 V to 5.5 V

VOL (D0–D7), Output Voltage Low ——0.4 VVCC=4.5 V, IOL=1.6 mA

VOL (CLK), Output Voltag e Low ——0.4 VVCC=4.5 V, IOL=40 µA

VOH Output Voltage High 2.4 ——V VCC=4.5 V, IOH=–40 µA

θJC Thermal Resistance,

Junction to Case —15 —°C/W —

Recommended Operating Conditions (TA= – 55°C to + 100°C)

Parameter Symbol Min. Max. Units

Supply Voltage VCC 4.5 5.5 V

Input Voltage Low VIL —0.8 V

Input Voltage High VIH 2.0 — V

Output Voltage Low VOL —0.4 V

Output Voltage High VOH 2.4 — V

IPD2131, IPD2132, IPD2133

2006-04-04 7

Pin Description

Pin No. Function Description Explanation

1CLS Clock Select Selects an internal or external clock source. CLS=1 the internal clock selected

(master clock), CLS=0 then external clock selected (slave operation).

2CLK Clock I/O Inputs or outputs the clock as determined by the CLS pin.

3WR Write Writes data into the display when WR=0 and CE=0.

4CE Chip Enable Enables the read/write access when low.

5RST Reset Initializes the display; clears the Character RAM (20 Hex), Flash RAM

(00 Hex), Control Word (00 Hex) and resets the internal counters. UDC Address

6RD Read Outputs data from the display when RD=0 and CE=0.

7No Pin — —

11 D0 Data Bus 8 bit bidirectional data bus. Character RAM and Control Word uses D7–D0, UDC

Address Register uses D3–D0, UDC RAM uses D4–D0, and Flash RAM uses D0.

12 D1

13 D2

14 D3

15 NC — —

16 VCC —Positive power supply.

17 GND Supply Analog ground for the LED drivers.

18 GND Logic Digital ground for the logic circuitry.

19 D4 Data Bus 8 bit bidirectional data bus. Character RAM and Control Word uses D7-D0, UDC

Address Register uses D3-D0, UDC RAM uses D4-D0, and Flash RAM uses D0.

20 D5

21 D6

22 D7

23 No Pin — —

27 FL Flash Accesses the Flash RAM. Address inputs, A2–A0, select the digit address while

data bit D0 sets (D0=1) or resets (D0=0) the Flash bit. A4 and A3 are ignored.

28 A0 Address Inputs A4 and A3 select a section of the display’s memory. A2–A0 select specific locations

in the different sections. If FL is low the Flash RAM is accessed regardless of the

status of A4 and A3.

29 A1

30 A2

31 A3

32 A4

2006-04-04 8

IPD2131, IPD2132, IPD2133

Character Set

Notes: 1. Upon power up, the device will initialize in a random state. 2. X=don’t care.

Cascading Diagram

Cascading Displays

The display’s oscillator is designed to drive up to 16 other display’s with input loading of 15 pF each.

The following are the gen eral requirements for cascading 16 displays together:

• Determine the correct address for each display.

• Use CE from an address decoder t o select the correct display.

• Select one of the Displays to provide the Clock for the other

displa ys. Connect CLKSEL to VCC for this display.

• Tie CLKSEL to ground on other displays.

• Use RST to synchronize the blinking between the displays.

IDCS5086

ASCII

CODE

HEX

D4D5D7

LLL

HLL

LHL

LHH

LLL

LLH

LHL

LHH

HXXX

8UDC

0UDC

1UDC

2UDC

3UDC

4UDC

5UDC

6UDC

7UDC

8UDC

9UDC

10 UDC

11 UDC

12 UDC

14 UDC

1513

UDC

IDCD5031

RD WR FL CLK CLK

Display

D0-D7 A0-A4 CE

Up to 14 more

displays in between

I/O SEL

Display

D0-D7 A0-A4

Data I/O

Address

Decoder

Address Address Decode Chip 1 to 14

RST

RSTRD WR FL CLK

SEL

CLK

I/O

IPD2131, IPD2132, IPD2133

2006-04-04 9

Block Diagram

Functional Description

The displa y's user inte rface is orga ni zed into fiv e memory areas.

They are accessed using the Flash Input, FL , and address lines,

A3 and A4. All the listed RAMs and Registers may be read or writ-

ten through the data bus. See Table „Memory Selection“

(page 10). Each input pin is described in Pin Definitions.

RST can be used to initialize display operation upon power up or

during normal operati on . Wh en ac ti vated, RST will clear the Flash

RAM and Control Word Register (00H) and reset the internal

counter. All eight display memory locations will be set to 20H to

show blanks in all digits.

FL pin enables access to the Fl ash R AM. Th e Flash RAM will set

(D0=1) or reset (D0 =0) fla shi n g of the ch aracter addresse d by A0–

A2.

The 1 x 8 bit Contr ol W or d Register is loaded with attribu te data if

A3=0.

The Control Word Logic decodes attribute data for proper imple-

mentation.

Character ROM is designed for 128 ASCII characters. The ROM

is Mask Programmable for custom fonts.

The Cloc k Source could either be the internal oscillator

(CLKSEL=1) of the device or an external clock (CLKSEL=0) could

be an input from another IPD213X display for synchronizing blink-

ing for multiple displays.

The Displa y Multiplexer controls the Row Drivers so no additional

logic is required for a display system.

The Display has eight digits. Each digit has 35 LEDs.

IDBD5064

OSC

Counter Counter

8 Digit Display

Drivers

Counter

128

Counter

Decode

RAM

Character

RAM

D Latch

Holding

Word

ROM

for Display

Decode

Character

(Read/Write)

Character

Decode

Address

UDC

Bus

Row

ROM

4RAM

16 UDC

Column

Latch

Master

Slave

5 25

and

Controls

Cursor

Display

MUX

Word

Control

Test

Self Flash

RAM

Drivers

Column

Data

Five Basic Memory Areas

Character RAM Stores either ASCII (Katakana)

character data or an UDC RAM

address

Flash RAM 1 x 8 RAM which stores Flash data

User-Defined

Character RAM

(UDC RAM)

Stores dot pattern for custom

characters

User-Defined Address

Provides addr ess to UDC RAM

when user is writing or reading

custom character

Control Word

brightness, flash individual charac-

ters, blink, self test or clearing

the display

IPD2131, IPD2132, IPD2133

2006-04-04 10

Theory of Operation

The IPD213X Display is designed to work with all major micropro-

cessors. Data entry is via an eight bit parallel bus. Three bits of

address route the data to the proper digit location in the RAM.

Standard control signals like WR and CE allow the data to be writ-

ten into the display.

D0–D7 data bits are used for both Character RAM and control

word data input. A3 acts as the mode selector.

If A3=1, character RAM is selected. Then input data bit D7 will

determine whether input data bits D0–D6 is ASCII coded data

(D7=0) or UDC data (D7=1 ). See section on „UDC Address Regi s-

ter and UDC RAM“ (page 11).

For normal operation FL pin should be held high. When FL is held

low, Flash RAM is accessed to set character blinking.

The seven bit ASCII code is de coded by the Characte r ROM to

generate Column data. Twenty columns worth of data is sent out

each display cycle , and it tak es f ourteen display cycles to write into

eight digits.

The rows are multiplexed in two sets of seven rows each. The

inter nal t imi ng an d co ntro l lo gic sy nc hron izes th e tu rning on o f

rows and presentation of column data to assure proper display

operation.

Power Up Sequence

Upon power up the display will come on at random. Thus the dis-

play should be reset on power-up. Reset will clear the Flash

RAM, Control Word Register and reset the internal counter. All

the digits will show blanks and display brightness level will be

100%.

The display must not be accesse d un til three clock pulses (110 µs

minimum using the internal clock) after the rising edge of the reset

line.

Microprocessor Interface

The interface to a microprocessor is through the 8-bit data bus

(D0–D7), the 4-bit address bus (A0–A3) and control lines FL , CE

and WR.

To write data (ASCII/ Co ntr o l Word ) i nt o the display CE should be

held low, address and data signals stable and WR should be

brought low. The data is written on the low to high transition of

WR.

The Control Word is decoded by the Control Word Decode Logic.

Each code has a d iff erent functi on. The code f or displa y brightness

changes the duty cycle for the column drivers. The peak LED cur-

rent stays the same but the average LED current diminishes

depending on the intensity level.

The character Flash Enable causes 2.0 Hz coming out of the

counter to be ANDED with the column drive signal to make the col-

umn driver cycle at 2.0 Hz. Thus the character flashes at 2.0 Hz.

The display Blink works the same way as the Flash Enable but

causes all twen ty column driv ers to cycle at 2.0 Hz th ereb y making

all eight digits blink at 2.0 Hz.

The Self Test function of the IC consists of two internal routines

which exercise major portions of the IC and illuminates all the

LEDs.

Clear bit clears the character RAM and writes a blank into the dis-

play memory. It however does not clear the control word.

ASCII Data or Control Word Data can be written into the display

at this point. For multiple display operation, CLK I/O must be

properly selected. CLK I/O will output t he internal clock if CLK-

SEL=1, or will allow input from an external clock if CLKSEL=0.

Memory Selection

FL A4 A3 Section of Memory A2–A0 Data Bits Used

0XX Flash RAM Character Address D0

100 UDC Address Register Don’t Care D3–D0

101 UDC RAM Row Address D4–D0

111 Character RAM Character Address D7–D0

110 Control Word Register Don’t Care D7–D0

IPD2131, IPD2132, IPD2133

2006-04-04 11

Character RAM

The Character RAM is selected when FL , A4 and A3 are set to

1,1,1 during a read or write cycle. The Character RAM is a 8 by 8

bit RAM wit h each of th e eight lo cations correspo nding to a digit on

the displa y. Digit 0 is on the left side of the display and digit 7 is on

the right side of t he display. Address lines, A2–A0 select the digit

address with A2 being the most significant bit and A0 being the

least significant bit. The two types of data stored in the Character

RAM are the ASCII coded data and the UDC Address Data. The

type of data stored in the Character R AM is determined by da ta bit,

D7. If D7 is low, then ASCII coded data is stored in data bits D6–

D0. If D7 is high, then UDC Address Data is stored in data bit D3–

D0.

The ASCII coded data is a 7 bit code used to select one of 128

ASCII characters permanently stored in the ASCII ROM.

The UDC Addres s data is a 4 bit c ode used to se lect one of the

UDC characters in the UDC RAM. Ther e are up to 16 characters

available. See Table „Character RAM Access Logic“ (page 11).

UDC Address Register and UDC RAM

The UDC Address Registe r and UD C RA M al lows the user to gen -

erate and store up to 16 custom characters. Each custom charac-

ter is defined in 5 x 7 dot matrix pattern. It takes 8 write cycles to

define a custom character, one cycle to load the UDC Address

UDC Address Registe r will store the 4 bit addre ss for on e of the 16

UDC RAM locations. The UDC RAM is used to store the custom

character.

UDC Address Register

The UDC Address Register is selected by setting FL=1, A4=0,

A3=0. It is a 4 bit register and uses data bits, D3–D0 to store the

4 bit address code (D7–D4 are ignored). The address code

selects one of 16 UDC RAM locations for custom character gen-

eration.

UDC RAM

The UDC RAM is selected b y setting FL=1, A4=0, A3=1. The RAM

is comprised of a 7 x 5 bit RAM. As shown in Table „UDC Charac-

ter Map“ (page 12), address lines, A2-A0 select one of the 7 rows

of the custom character. Data bits, D4-D0 determine the 5 bits of

column data in each row. Each data bit corresponds to a LED. If

the data bit is high, then the LED is on. If the data bit is low, the

LED is off. To create a character, each of the 7 rows of column

data need to be defined. See Tables „UDC Address Register and

UDC RAM“ (page 11) and „UDC Character Map“ (page 12) for

logic.

Flash RAM

The Flash RAM all ows the d isplay to flash one o r more of the cha r-

acters being displayed. The Fla s h Ram is acce ssed b y settin g FL

low. A4 and A3 are ignored. The Flash R AM is a 8 x 1 bit R AM with

each bit correspo nd i ng to a di g i t ad dr ess. Digit 0 is o n t he left side

of the displa y an d digit 7 is on th e right side of the di spla y. Address

lines, A2–A 0 select the digit ad dress wi th A2 bein g the most si gnif -

icant digit and A0 being the least significant digit. Data bit, D0, sets

and resets the fl ash bit f or each di git. When D0 is high, th e flash bit

is set; and when D0 is low, it is reset. See Table „Flash RAM

Access Logic“ (page 12).

Character RAM Access Logic

RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 1 1 1 1 Character Address for

Digits 0–7 0 7 bit ASCII code for a Write Cycle

1 0 1 0 1 1 1 Character Address for

Digits 0–7 0 7 bit ASCII co de read durin g a Read Cycle

1 0 0 1 1 0 0 Character Address for

Digits 0–7 1 D3–D0=UDC address for a Write Cycle

1 0 1 0 1 0 0 Character Address for

Digits 0–7 1 D3–D0=UDC address for Read Data

UDC Address Register and UDC Character RAM

RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 1 1 0 0 Not used for UDC

Address Register D3–D0=UDC RAM Address Code

for Write Cycle

UDC

Address

1 0 1 0 1 0 0 Not used for UDC

Address Register D3–D0=UDC RAM Address Code

for Read Cycle

1 0 0 1 1 0 1 A2–A0=Character

Row Address D4–D0=Character Co lumn Data

for Write Cycle

UDC

RAM

1 0 1 0 1 0 1 A2–A0=Character

Row Address D4–D0=Character Co lumn Data

read during a Read Cycle

IPD2131, IPD2132, IPD2133

2006-04-04 12

Control Word

The Control Word is used to set up the attributes required by the

user. It is addressed by setting FL=1, A4=1, A3=0. The Control

Word i s a n 8 b it r egiste r an d i s a ccesse d usi ng da ta bi ts, D7–D0.

See Table „Control Word Access Logic“ (page 12) and Figure

„Control Word Data Definition“ ( page 13) for the logic and attrib-

uted control. The Control Word has 5 functions. They are bright-

ness control, flashing character enable, blinking character

enable, self test, and clear (Flash and Character RAMS only).

Brightness Control

Control Word bits, D2–D0, control the brightness of the display

with a binary code of 000 being 100% brightness and 111 being

display blank. See Figure „Control Word Data Definition“

(page 13) f o r brightness le vel v ersus binary code. The a v er age ICC

can be calculated by multiplying the 100% brightness level ICC

value by the display’s brightness level. For example, a display set

to 80% brightness with a 100% aver a ge ICC value of 200 mA will

have an average ICC val ue of 200 mA x 80%=160 mA.

Flash Fu nc tion

Control Word bit, D3, enables or disables the Flash Function.

When D3 is 1, the Flash Function is enabled and any digit with its

corresponding bit set in the Flash RAM will flash at approximately

2.0 Hz. When using an external clock, the flash rate can be deter-

mined by dividing the clock rate by 28,672. When D3 is 0, the

Flash Function is disabled and the contents of the Fl ash RAM is

ignored. For synchronized flashing on mul tipl e di splays , see the

Reset Section (page 13).

Blink Function

Control W ord bit, D4, enable s or disab les the Blink Funct ion. When

D4 is 1, the Blin k Functi on is e nab led and al l char acte rs on th e di s-

play will blink at approximately 2.0 Hz. The Blink Function will over-

ride the Flash Function if both functions are enabled. When D4 is

0, the Blink Function is d isabled. Whe n using an e xternal clock, the

blink rate can be determined by dividing the clock rate by 28,672.

For synchronized blinking on multiple displays, see the Reset Sec-

tion (page 13).

Self Test

Control Word bits, D6 and D5, are used for the Self Test Function.

When D6 is 1, the Self Test is initiated. Results of the Self Test are

stored in bit D5. Control Word bit, D5, is a read only bit. When D5

is 1, Self Test has passed. When D5 is 0, Self Test failed is indi-

cated. The Self Test function of the IC consists of two internal rou-

tines which exercise major portions of the IC and illuminates all of

the LEDs. The first routine cycles the ASCII de coder ROM through

all states and performs a check sum on the out-put. If the check

sum is correct, D5 is set to a 1 (Pass).

The second routine provides a visual test of the LEDs. This is

accomplished by writing checkered and inversed checkered pat-

terns to the display. Each pattern is displayed for approximately

2.0 sec. During the self test function the display must not be

accessed. The time needed to execute the self test function is cal-

culated by multiplying the clock time by 262,144 (typical

time ≈ 4.6 sec.). At the end of the self test, the Character RAM is

loaded with blanks; the Control Word Register is set to zeroes

except D 5; th e Flash RA M is clear e d an d the UD C Ad dr ess R eg is-

ter is set to all 1.0s.

UDC Character Map

Row Data

A2 A1 A0 Row #

Column Data

C1 C2 C3 C4 C5

D4 D3 D2 D1 D0

0001

5 x 7

Dot Matrix

Pattern

0012

0103

0114

1005

1016

1107

Flash RAM Access Logic

RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 1 0 X X Flash RAM Address

for Digits 0–7 D0=Flash Data, 0=Flash Off and 1=Flash On

(Write Cycle)

1 0 1 0 0 X X Flash RAM Address

for Digits 0–7 D0=Flash Data, 0=Flash Off and 1=Flash On

(Read Cycle)

Control Word Access Logic

RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 1 1 1 0 Not used for Control

Word Control Word data for a Write Cycle,

see Figure „Control Word Data Definition“

(page 13)

1 0 1 0 1 1 0 Not used for Control

Word Control Word data for a Read during a

Read Cycle

IPD2131, IPD2132, IPD2133

2006-04-04 13

Clear Function (see Figure „Control Word Data Definition“

(page 13) and Table „Clear Function“ (page 13))

Control Word bit, D7 clears the character RAM to 20 hex and the

flash RAM to all zeroes. The RAMs are cleared within three clock

cycles (110 µs minimum, using the internal clock) when D7 is set

to 1. During the clear time the display must not be accessed.

When the clear function is finished, bit 7 of the Co ntrol Word RAM

will be reset to a “0”.

Control Word Data Definition

Reset Function

The display should be reset on power up of the display

(RST=LO W). When th e displa y i s reset, the Char acter RAM , Flash

RAM, and Control Word Register are cleared.

The display's internal counters are reset. Reset cycle takes three

clock cycles (110 µs minimum using the internal clock). The dis-

play must not be accessed dur ing this ti me.

To synchronize the flashing and blinking of multiple displays, it is

necessary for the display to use a commo n cloc k source and reset

all the displays at the same time to start the internal counters at

the same place.

While RST is low, the display must not be accessed by RD nor

WR.

Key

C C l e ar F u nction

ST Self test

BL Blink function

FL Flash function

Br Brightness control

IDCW5161

Function

Blink

Self Test

Function Brightness Control

D7 D6 D5 D4 D3 D2 D1 D0

D1 D0 Brightness Control

100% Brightness0080% Brightness01

1 53% Brightness0

1 40% Brightness1

Disabled

Flash FunctionD3

0Enabled1

Enabled (overrides Flash Function)

Disabled

Blink Function

Normal Operation (X = bit ignored)

XRun Self Test, R = Test Result (1 = pass, 0 = fail)

Self Test

Clear Flash RAM & Character RAM (Character RAM = 20 Hex)

Normal Operation0

Clear FunctionD7

Clear Flash

Function

27% Brightness

Blank Display11

0 20% Brightness

13% Brightness

Clear Function

CE WR FL A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation

XClear disabled

Clear user RAM, flash RAM

and display

X=don’t care

2006-04-04 14

IPD2131, IPD2132, IPD2133

Display Cycle Using Built -in RO M Exa mple

Display message “Showtime.” Dig it 0 is leftmost—closest to pin 1.

Logic levels: 0=Low, 1=High, X=Don’t care.

RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation Display

0 X1 11XXXXXXXXXXXXXReset. No

Read/Write

Within 3 Clock

Cycles

All Blank

1 00 1110XXX00X0001153% Brightness

Selected All Blank

1 00 111100001010011Write “S” to Digit 0 S

1 00 111100101001000Write “H” to Digit 1 SH

1 00 111101001001111Write “O” to Digit 2 SHO

1 00 111101101010111Write “W” to Digit 3 SHOW

1 00 111110001010100Write “T” to Digit 4 SHOWT

1 00 111110101001001Write “I” to Digit 5 SHOWTI

1 00 111111001001101Write “M” to Digit 6 SHOWTIM

1 00 111111101000101Write “E” to Digit 7 SHOWTIME

Displaying User Defined Char act e r Example

Load character “A” into UDC-5 and then display it in digit 2.

Logic levels: 0=Low, 1=High, X=Don‘t care

RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation Display

0 X1 11XXXXXXXXXXXXXReset. No

Read/Write

Within 3 Clock

Cycles

All Blank

1 0 0 1 1 0 0 X X X X X X X 0 1 0 1 Select UDC-5 All Blank

1 00 1101000XXX01110Write into Row 1 of

UDC-5 All Blank

1 00 1101001XXX10001Write into Row 2 of

UDC-5 All Blank

1 00 1101010XXX10001Write into Row 3 of

UDC-5 All Blank

1 00 1101011XXX11111Write into Row 4 of

UDC-5 All Blank

1 00 1101100XXX10001Write into Row 5 of

UDC-5 All Blank

1 00 1101101XXX10001Write into Row 6 of

UDC-5 All Blank

1 00 1101110XXX10001Write into Row 7 of

UDC-5 All Blank

1 00 11110101XXX0101Write UDC-5 into

Digit 2 (Digit 2) A

IPD2131, IPD2132, IPD2133

2006-04-04 15

Electrical and Mechanical Considerations

Voltage Transient Suppression

For best results power the display and the components that inter-

face with the display to avoid logic inputs higher than VCC. Addi-

tionally, the LEDs may cause transients in the power supply line

while they change display states. The common practice is to place

a parallel combin ation of a 0.01 µF an d a 22 µF capacitor between

VCC and GND for all display packages.

ESD Protection

The input protection structure of the IPD2131X provides significant

protection against ESD damage. It is capable of withstanding dis-

charges greater than 4.0 kV. Take all the sta ndard pr ecaut io ns nor -

mal for CMOS components. These include properly grounding

personnel, tools, tables, and transport carriers that come in con-

tact with unshi elded parts. If these condi tions are not, or cannot be

met, keep the leads of the device shorted together or the parts in

anti-static packaging.

Soldering Considerations

The IPD213X can be hand soldered with SN63 solder using a

grounded iron set to 260°C.

Wave soldering is also possible. Use water soluble organic acid

flux or resin based RMA flux.

A wave temperature of 245°C ±5°C with a dwell between 1.5 sec.

to 3.0 sec. can be used. Exposure to the wave should not exceed

temperatures above 260°C for five seconds at 1.59 mm (0.063")

below the seating plane. The packages should not be immersed in

the wave.

Po st Solder Cl eaning Procedures

The least offensive cleaning solution is hot D.I. water (60 °C) for

less than 15 minutes. Addition of mild saponifiers is acceptable.

Do not use commercial dishwasher detergents.

For faster cleaning, solvents may be used. Suggested solvents

include Genesolv DE-15, Genesolv DI-15, and Genesolv DES.

An alternative to soldering and cleaning the display modules is to

use sockets. Multiple display assemblies are best handled by

longer SIP sockets or DIP so ckets when available for uniform

package alignment. Socket manufacturers are Aries Electronics,

Inc., Frenchtown, NJ; Garry Manufacturing, New Brunsw i ck, NJ;

Robinson-Nugent, New Albany, IN; and Samtec Electronic Hard-

ward, New Albany, IN.

For furth er information refer to Appnote 22 at www.osram-os.com

Optical Considerations

The 4.85 m m (0.2 0 0" ) hig h ch aract er of the IP D213 X gives read-

ability up to e ight f eet. Proper filter selection en hances read ability

over this distance.

Using filters emphasizes the contrast ratio between a lit LED and

the character background. This will increase the discriminati on of

different characters. The only limitation is cost. Take into consider-

ation the ambient lighting environment for the best cost/benefit

ratio for filters .

Incandescent (with almost no green) or fluorescent (with almost no

red) lights do not have the flat spectral response of sunlight. Plas-

tic band-pass filters are an inexpensive and effective way to

strengthen contrast ratios. The high efficiency red displays should

be matched with a long wavelength pass filter in the 570 nm to

590 nm range. The IPD2133 should be matched with a yel-

low-green band-pass filter that peaks at 565 nm. For displays of

multiple colors, neutral density grey filters offer the best compro-

mise.

Additional contrast enhancement is gained by shading the dis-

plays. Plastic band-pass filters with built-in louvers offer the next

step up in contrast improvement. Plastic filters can be improved

further with anti-refle ctive coatings to re duce glare . The trad e-off is

fuzzy characters. Mounting the filters close to the display reduces

this effect. Take care not to ov erheat the plastic filter by allowing f or

proper air flow.

Optimal filter enhancements are gained by using circular polarized,

anti-reflecti ve, band-pass filters. The circula r polarizing further

enhances contr ast b y red ucing th e light that t ra v els th rough t he filter

and reflects bac k o ff t he display to le ss than 1%.

Several filter manufacturers supply quality filter materials. Some of

them are: Panelgraphic Corporation, W. Caldwell, NJ; SGL Homa-

lite, Wilmington, DE; 3M Company, Visual Products Division, St.

Paul, MN; Polaroid Corporation, Polarizer Division, Cambridge,

MA; Marks Polarized Corporation, Deer Park, NY, Hoya Optics,

Inc., Fremont, CA.

One last note on mounting filters: recessing displays and bezel

assemblies is an inexpensive way to provide a shading effect in

overhead lighting situations. Several bezel manufacturers are:

R.M.F. Products, Batavia, IL; Nobex Components, Griffith Plastic

Corp., Burlingame, CA; Photo Chemical Prod ucts of Califor nia,

Santa Monica, CA; I.E.E.-Atlas, Van Nuys, CA.

RoHS Compliance

The IPD2132, IPD2131, IPD2133 Intelligent DisplaysTM are her-

metically sealed displays using a ceramic and glass con structio n.

These compone nts are n ot lead (Pb) free but are RoHS C omplia nt

based on the RoHS Compliance Directive's Annex, paragraphs 5

and 7. These exemption s all ow for lea d (Pb) in glass a nd ceram ic

electronic components. Refer to the following excerpts from the

RoHS Compliance Directive Annex:

Applications of lead, mercury, cadmium and hexavalent chromium,

which are ex empted fr om the requirements of Article 4(1)

5. Lead in glass of cathode ray tubes, electronic components and

fluorescent tubes.

7. Lead in electronic ceramic parts (e.g. piezoelectronic devices).

2006-04-04 16

IPD2131, IPD2132, IPD2133

Published by

OSRAM Opto Semiconductors GmbH

Wernerwerkstrasse 2, D-93049 Regensburg

www.osram-os.com

Attention please!

The information describes the type of component and shall not be considered as assured ch aracteristics.

Terms of delivery and rights to change design reserved. Due to technical requirements components may contain

dangerous substances. For information on the types in question please contact our Sales Organization.

If printed or downloaded, please find the latest version in the Internet.

Packing

Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office.

By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing

material that is retu rned to us unsorted or which we are not obliged to a ccept, we shall have t o invoice you for any costs

incurred.

Components used in life-support devices or systems must be expressly authorized for such purpose! Critical

components1) may only be used in life-support devices or systems2) with the express written approval of OSRAM OS.

1) A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safety or the effectiveness of that device or system.

2) Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain

human life. If they fail, it is reasonable to assume that the health and the life of the user may be endangered.

Revision History: 2006-04-04

Previous Version: 2004-11-11

Page Subjects (major changes since last revision) Date of change

all RoHS Compliant - By Exemption 2006-03-03