0.1 GHz to 33 GHz,1 dB LSB, 5-Bit, GaAs Digital Attenuator HMC939ALP4E Data Sheet P1 P2 P3 P4 NIC FUNCTIONAL BLOCK DIAGRAM Attenuation range: 1 dB LSB steps to 31 dB Insertion loss: 6 dB typical at 33 GHz Attenuation accuracy: 0.5 dB typical Input linearity 0.1 dB compression (P0.1dB): 24 dBm typical Third-order intercept (IP3): 40 dBm typical Power handling: 27 dBm Dual-supply operation: 5 V CMOS-/TTL-compatible parallel control 24-lead, 4 mm x 4 mm LFCSP package P0 FEATURES 24 23 22 21 20 19 VSS 1 18 VDD NIC 2 17 NIC NIC 3 16 NIC NIC 4 15 NIC RF1 5 14 RF2 NIC 6 13 NIC DRIVER 2dB 4dB 8dB 16dB 8 9 10 11 12 NIC NIC NIC NIC PACKAGE BASE GND NIC = NO INTERNAL CONNECTION 13920-001 7 NIC Test instrumentation Microwave radios and very small aperture terminals (VSATs) Military radios, radars, electronic counter measures (ECMs) Broadband telecommunications systems NIC APPLICATIONS Figure 1. GENERAL DESCRIPTION The HMC939ALP4E is a 5-bit digital attenuator with a 31 dB attenuation control range in 1 dB steps. The HMC939ALP4E offers optimum insertion loss, attenuation accuracy, and input linearity over the specified frequency range from 100 MHz to 33 GHz. Rev. D The HMC939ALP4E requires dual supply voltages, VDD = +5 V and VSS = -5 V, and provides CMOS-/TTL-compatible parallel control interface by incorporating an on-chip driver. The HMC939ALP4E comes in a RoHS compliant, compact, 4 mm x 4 mm LFCSP package. See HMC939A-DIE for the die version of HMC939ALP4E. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com HMC939ALP4E Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Insertion Loss, Return Loss, State Error, Step Error, and Relative Phase ................................................................................6 Functional Block Diagram .............................................................. 1 Input Power Compression and Third-Order Intercept ............8 General Description ......................................................................... 1 Theory of Operation .........................................................................9 Revision History ............................................................................... 2 Power Supply..................................................................................9 Specifications..................................................................................... 3 RF Input and Output ....................................................................9 Absolute Maximum Ratings............................................................ 4 Applications Information .............................................................. 10 Thermal Resistance ...................................................................... 4 Evaluation Board ........................................................................ 10 ESD Caution .................................................................................. 4 Outline Dimensions ....................................................................... 11 Pin Configuration and Function Descriptions ............................. 5 Ordering Guide .......................................................................... 11 Interface Schematics..................................................................... 5 Typical Performance Characteristics ............................................. 6 REVISION HISTORY 5/2018--Rev. C to Rev. D Changed + 27 V to 27 dBm in Rating Column, Table 2 .............. 4 Change to Ordering Guide ............................................................ 11 Added Theory of Operation Section, RF Input and Output Section, and Power Supply Section ........................................................................ 9 Changes to Figure 22 ............................................................................... 10 Changes to Ordering Guide ................................................................... 11 8/2017--Rev. 02.0417 to Rev. C This Hittite Microwave Products data sheet has been reformatted to meet the styles and standards of Analog Devices, Inc. Changed N/C to NIC ............................................................ Throughout Changes to Features Section, Applications Section, and General Description Section ................................................................................... 1 Changes to Table 1 ..................................................................................... 3 Changes to Table 2 and Added Thermal Resistance Section ............ 4 Added Table 3; Renumbered Sequentially ............................................ 4 Changes to Table 4 ..................................................................................... 5 Changes to Figure 5 Caption through Figure 10 Caption ................. 6 Changes to Figure 11 Caption through Figure 14 Caption ............... 7 Changes to Figure 15 Caption through Figure 20 Caption ............... 8 Rev. D | Page 2 of 11 Data Sheet HMC939ALP4E SPECIFICATIONS VDD = 5 V, VSS = -5 V, VCTL = 0 V or VDD, TCASE = 25C, 50 system, unless otherwise noted. Table 1. Parameter FREQUENCY RANGE INSERTION LOSS Symbol ATTENUATION Range Step Size Step Error State Error RETURN LOSS RELATIVE PHASE SWITCHING CHARACTERISTICS Rise and Fall Time On and Off Time INPUT LINEARITY 0.1 dB Compression Third-Order Intercept SUPPLY CURRENT Positive Negative DIGITAL CONTROL INPUTS Voltage Low High Current Low and High tRISE, tFALL tON, tOFF P0.1dB IP3 Test Conditions/Comments Min 0.1 Typ Max 33 5.5 7.0 8.0 Unit GHz dB dB dB 0.1 GHz to 18 GHz 18 GHz to 26.5 GHz 26.5 GHz to 33 GHz 4.5 5.5 6.0 Between minimum and maximum attenuation states, 0.1 GHz to 33 GHz Between any successive attenuation states, 0.1 GHz to 33 GHz Between any successive attenuation states, 0.1 GHz to 33 GHz Referenced to insertion loss state 1 dB to 15 dB attenuation states, 0.1 GHz to 33 GHz 16 dB to 31 dB attenuation states, 0.1 GHz to 20 GHz 16 dB to 31 dB attenuation states, 20 GHz to 33 GHz RF1 and RF2 pins, all attenuation states, 0.1 GHz to 33 GHz Between minimum and maximum attenuation states 0.1 GHz to 18 GHz 18 GHz to 26.5 GHz 26.5 GHz to 33 GHz Between all attenuation states 10% to 90% of RF output 50% VCTL to 90% of RF output All attenuation states 0.1 GHz to 0.5 GHz 0.5 GHz to 33 GHz 8 dBm per tone, 1 MHz spacing 0.1 GHz to 0.5 GHz 0.5 GHz to 33 GHz 31 dB 1 dB 0.5 dB IDD ISS -(0.5 + 5% of attenuation state) -(0.5 + 5% of attenuation state) -(0.6 + 8% of attenuation state) 2.5 -7.0 +(0.5 + 5% of attenuation state) +(0.5 + 5% of attenuation state) +(0.6 + 8% of attenuation state) dB dB dB 10 dB 45 60 80 Degrees Degrees Degrees 45 60 ns ns 20 24 dBm dBm 43 40 dBm dBm 4.5 -5.5 6.5 -3.0 mA mA 0.8 5.0 V V P0 to P5 pins VINL VINH 0 2.0 IINL, IINH <1 Rev. D | Page 3 of 11 A HMC939ALP4E Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter Supply Voltage Positive Negative Digital Control Input Voltage RF Input Power (All Attenuation States, f = 0.1 GHz to 33 GHz, TCASE = 85C) Continuous Power Dissipation, PDISS (TCASE = 85C) Temperature Junction, TJ Storage Reflow1 ((Moisture Sensitivity Level 3 (MSL3) Rating) ESD Sensitivity Human Body Model (HBM) 1 Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Rating +7 V -7 V VDD + 0.5 V 27 dBm Table 3. Thermal Resistance 0.453 W Package Type CP-24-161 JC is the junction to case thermal resistance. JC 143.52 Unit C/W 1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board with nine thermal vias. See JEDEC JESD51. 150C -65C to +150C 260C 2 The device is set to maximum attenuation state. ESD CAUTION 250 V (Class 1A) See the Ordering Guide for more information. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Only one absolute maximum rating can be applied at any one time. Rev. D | Page 4 of 11 Data Sheet HMC939ALP4E P1 P2 P3 P4 NIC 24 23 22 21 20 19 VSS 1 18 VDD NIC 2 17 NIC NIC 3 16 NIC 15 NIC HMC939ALP4E TOP VIEW (Not to Scale) NIC 6 13 NIC 7 8 9 10 11 12 NIC RF2 NIC 14 NIC 5 NIC RF1 NIC 4 NIC NIC PACKAGE BASE GND NOTES 1. NIC = NO INTERNAL CONNECTION 2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. 13920-002 P0 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 to 4, 6 to 13, 15 to 17, 19 5 Mnemonic VSS NIC Description Negative Supply Voltage. These pins are not internally connected; however, all data shown herein was measured when these pins connected to the RF/DC ground of evaluation board. RF1 14 RF2 18 20 to 24 VDD P4 to P0 This pin can be used as RF input or output of attenuator. This pin is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is necessary when the RF line potential is equal to 0 V dc. This pin can be used as RF input or output of attenuator. This pin is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is necessary when the RF line potential is equal to 0 V dc. Positive Supply Voltage. Parallel Control Voltage Inputs. These pins select the required attenuation (see Table 6). There is no internal pull-up or pull-down resistor on these pins; therefore, they must always be kept at a valid logic level (VIH or VIL) and not be left floating. Exposed Pad. The exposed pad must be connected to ground for proper operation. EPAD INTERFACE SCHEMATICS RF1 RF2 13920-003 VDD VDD 13920-004 P0 TO P4 500 Figure 3. RF1, RF2 Interface Schematic Figure 4. Digital Control Input Interface Rev. D | Page 5 of 11 HMC939ALP4E Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS INSERTION LOSS, RETURN LOSS, STATE ERROR, STEP ERROR, AND RELATIVE PHASE 0 0 -1 NORMALIZED ATTENUATION (dB) -4 -5 -6 -7 +85C +25C -40C -9 -10 0 5 10 15 20 25 30 35 40 FREQUENCY (GHz) Figure 5. Insertion Loss vs. Frequency over Temperature 0 0dB 1dB 2dB 4dB -15 -20 8dB 16dB 31dB -30 -35 0 5 10 15 20 25 30 35 40 FREQUENCY (GHz) Figure 8. Normalized Attenuation vs. Frequency over Major Attenuation States 0 8dB 16dB 31dB 0dB 1dB 2dB 4dB -10 -20 -30 8dB 16dB 31dB -20 -30 0 5 10 15 20 25 30 35 40 FREQUENCY (GHz) -50 13920-006 -50 0 15 20 25 30 35 40 Figure 9. RF2 Return Loss vs. Frequency over Major Attenuation States 2.0 5GHz 10GHz 18GHz 26.5GHz 33GHz 1.5 10 FREQUENCY (GHz) Figure 6. RF1 Return Loss vs. Frequency over Major Attenuation States 2.0 5 13920-009 -40 -40 0dB 1dB 2dB 4dB 1.5 1.0 8dB 16dB 31dB STATE ERROR (dB) 1.0 0 -0.5 0.5 0 -0.5 -1.0 -1.0 -1.5 -1.5 -2.0 0 4 8 12 16 20 24 28 ATTENUATION STATE (dB) Figure 7. State Error vs. Attenuation State over Frequency 32 -2.0 0 5 10 15 20 25 30 35 40 FREQUENCY (GHz) Figure 10. State Error vs. Frequency over Major Attenuation States Rev. D | Page 6 of 11 13920-010 0.5 13920-007 STATE ERROR (dB) 0dB 1dB 2dB 4dB -25 RETURN LOSS (dB) RETURN LOSS (dB) -10 -10 13920-008 -3 -8 -5 13920-005 INSERTION LOSS (dB) -2 Data Sheet 1.0 STEP ERROR (dB) 1.0 0.5 0 -0.5 -1.0 0 -0.5 -1.0 0 4 8 12 16 20 24 28 32 ATTENUATION STATE (dB) 0 10 15 20 25 30 35 40 Figure 13. Step Error vs. Frequency over Major Attenuation States 100 5GHz 10GHz 18GHz 26.5GHz 33GHz 0dB 1dB 2dB 4dB 80 RELATIVE PHASE (Degrees) 80 5 8dB 16dB 31dB FREQUENCY (GHz) Figure 11. Step Error vs. Attenuation State over Frequency 100 0dB 1dB 2dB 4dB -1.5 13920-011 -1.5 60 40 20 0 8dB 16dB 31dB 60 40 20 0 -20 0 4 8 12 16 20 24 28 32 ATTENUATION STATE (dB) Figure 12. Relative Phase vs. Attenuation State over Frequency -20 13920-012 RELATIVE PHASE (Degrees) 0.5 0 5 10 15 20 25 FREQUENCY (GHz) 30 35 40 13920-014 STEP ERROR (dB) 1.5 5GHz 10GHz 18GHz 26.5GHz 33GHz 13920-013 1.5 HMC939ALP4E Figure 14. Relative Phase vs. Frequency over Major Attenuation States Rev. D | Page 7 of 11 HMC939ALP4E Data Sheet INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT 70 +85C +25C -40C 30 60 25 50 IP3 (dBm) 20 5 10 15 20 25 30 FREQUENCY (GHz) 20 0 10 15 20 25 30 FREQUENCY (GHz) Figure 15. Input P0.1dB vs. Frequency at Minimum Attenuation State over Temperature 35 5 13920-018 0 13920-015 10 Figure 18. Input IP3 vs. Frequency at Minimum Attenuation State over Temperature 70 +85C +25C -40C +85C +25C -40C 30 60 25 50 IP3 (dBm) 20 40 30 15 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 FREQUENCY (GHz) 20 13920-016 10 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 FREQUENCY (GHz) Figure 16. Input P0.1dB vs. Frequency at Minimum Attenuation State over Temperature (Low Frequency Detail) Figure 19. Input IP3 vs. Frequency at Minimum Attenuation State over Temperature (Low Frequency Detail) 70 30 60 25 50 IP3 (dBm) 35 20 0.1 13920-019 P0.1dB (dBm) 40 30 15 P0.1dB (dBm) +85C +25C -40C 15 40 30 4dB 8dB 16dB 0dB 1dB 2dB 10 0 5 10 15 20 FREQUENCY (GHz) 25 30 4dB 8dB 16dB 20 13920-017 0dB 1dB 2dB 0 5 10 15 20 25 30 FREQUENCY (GHz) Figure 17. Input P0.1dB vs. Frequency over Major Attenuation States Figure 20. Input IP3 vs. Frequency over Major Attenuation States Rev. D | Page 8 of 11 13920-020 P0.1dB (dBm) 35 Data Sheet HMC939ALP4E THEORY OF OPERATION The HMC939ALP4E incorporates a 5-bit attenuator die that offers an attenuation range of 31 dB in 1 dB steps and a driver for CMOS-/TTL-compatible parallel control of the 5-bit attenuator. See Table 5 for the truth table. Table 5. P4 to P0 Truth Table P4 High High High High High Low Low 1 Digital Control Input1 P3 P2 P1 High High High High High High High High Low High Low High Low High High High High High Low Low Low P0 High Low High High High High Low Attenuation State (dB) 0 dB (reference) 1 dB 2 dB 4 dB 8 dB 16 dB 31 dB Any combination of the control voltage input states shown in Table 5 provides an attenuation equal to the sum of the bits selected. POWER SUPPLY The HMC939ALP4E requires dual supply voltages, VDD = +5 V and VSS = -5 V, and CMOS/TTL-compatible control voltages applied to the P0 to P4 pins. The ideal power-up sequence is as follows: 1. 2. 3. 4. Connect the ground reference. Power up VDD and VSS. The relative order is not important. Apply the digital control inputs. The relative order of the digital control inputs is not important. Apply an RF input signal to RF1 or RF2. The power-down sequence is the reverse of the power-up sequence. RF INPUT AND OUTPUT The HMC939ALP4E is bidirectional. The RF1 and RF2 pins are internally matched to 50 and dc-coupled to 0 V; therefore, they do not require external matching components and dc blocking capacitors when the RF line potential is equal to 0 V. Rev. D | Page 9 of 11 HMC939ALP4E Data Sheet APPLICATIONS INFORMATION The RF1 and RF2 ports are connected through 50 transmission lines to the RF connectors, J1 and J2, respectively. A thru calibration line connects J4 and J5; this transmission line is used to estimate the loss of the PCB over the environmental conditions being evaluated. Figure 22 and Table 6 show the evaluation board schematic and bill of materials, respectively. VSS J3 Figure 21 shows the top view of the populated HMC939ALP4E evaluation board, available from Analog Devices, Inc., upon request (see the Ordering Guide section). C1 1NF VDD GND GND 1 VSS VDD J3 RF1 2 3 4 5 6 VSS VDD NIC NIC U1 NIC NIC HMC939ALP4E NIC NIC RF1 RF2 NIC NIC 18 17 16 15 14 13 RF2 J2 7 8 9 10 11 12 C2 C1 J1 J6 J2 XXXX RF1 THRU CAL J4 939A U1 RF2 NIC = NO INTERNAL CONNECTION 13920-022 P4 P2 P3 P0 P1 NIC NIC NIC NIC NIC NIC J1 C2 1NF 24 23 22 21 20 19 The HMC939ALP4E uses a 4-layer evaluation board. The copper thickness is 0.5 oz (0.7 mil) on each layer. The top dielectric material is 10 mil Rogers RO4350 for optimal high frequency performance. The middle and bottom dielectric materials are FR-4 type materials to achieve an overall board thickness of 62 mil. RF traces are routed on the top copper layer and the bottom layer is grounded plane that provide a solid ground for the RF transmission lines. The RF transmission lines are designed using a coplanar waveguide (CPWG) model with a width of 16 mil and ground spacing of 13 mil to have a characteristic impedance of 50 . For enhanced RF and thermal grounding, as many plated through vias as possible are arranged around transmission lines and under the exposed pad of the package. The evaluation board is grounded from the 2 x 5-pin header, J3. All the supply and digital control pins are also connected to the J3. A 1 nF decoupling capacitors are placed on the supply traces to filter high frequency noise. P0 P1 P2 P3 P4 NIC EVALUATION BOARD Figure 22. Evaluation Board Schematic THRU CAL Table 6. List of Materials for EV1HMC939ALP4 131909-1 Figure 21. Populated Evaluation Board--Top View 13920-021 J5 J4 Item J1, J2 J3, J4, J5 C1, C2 U1 PCB Rev. D | Page 10 of 11 Description PCB mount, 2.9 mm RF connector 2 x 5-pin header PCB mount, 2.9 mm RF connector, do not insert 1 nF capacitor, 0402 package HMC939ALP4E digital attenuator 131909-1 evaluation PCB Data Sheet HMC939ALP4E OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 0.30 0.25 0.18 1 18 0.50 BSC 2.80 2.70 SQ 2.60 EXPOSED PAD 13 0.50 0.40 0.30 TOP VIEW PKG-004926/004942 0.90 0.85 0.80 6 12 7 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 24 19 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8 12-12-2017-C PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 23. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm x 4 mm Body and 0.85 mm Package Height (CP-24-16) Dimensions shown in millimeters ORDERING GUIDE Model1 HMC939ALP4E HMC939ALP4ETR EV1HMC939ALP4 1 2 Temperature Range -40C to +85C -40C to +85C MSL Rating2 MSL3 MSL3 Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP] 24-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board All models are RoHS compliant. See the Absolute Maximum Ratings section. (c)2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13920-0-5/18(D) Rev. D | Page 11 of 11 Package Option CP-24-16 CP-24-16