AD7124-4TRUZ-EP-R7 - ANALOG DEVICES

4-Channel, Low Noise, Low Power, 24-Bit,

Sigma-Delta ADC with PGA and Reference

Enhanced Product AD7124-4-EP

Rev. 0 Document Feedback

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FEATURES

3 power modes

RMS noise

Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 μA typical)

Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 μA typical)

Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 μA typical)

Up to 22 noise free bits in all power modes (gain = 1)

Output data rate

Full power: 9.38 SPS to 19,200 SPS

Mid power: 2.34 SPS to 4800 SPS

Low power: 1.17 SPS to 2400 SPS

Rail-to-rail analog inputs for gains > 1

Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle

settling)

Diagnostic functions (which aid safe integrity level (SIL)

certification)

Crosspoint multiplexed analog inputs

4 differential/7 pseudo differential inputs

Programmable gain (1 to 128)

Band gap reference with 10 ppm/°C drift maximum (70 μA)

Matched programmable excitation currents

Internal clock oscillator and temperature sensor

On-chip bias voltage generator

Low-side power switch

Multiple filter options

Sensor burnout detection

Automatic channel sequencer

Per channel configuration

Power-down current: 5 μA maximum

24-lead TSSOP

3-wire or 4-wire serial interface

SPI, QSPI, MICROWIRE, and DSP compatible

Schmitt trigger on SCLK

ENHANCED PRODUCT FEATURES

Supports defense and aerospace applications (AQEC standard)

Full military temperature range: −55°C to +125°C

Controlled manufacturing baseline

1 assembly/test site

1 fabrication site

Product change notification

Qualification data available on request

APPLICATIONS

Military and space

Avionics

Pressure measurement

Instrumentation

FUNCTIONAL BLOCK DIAGRAM

TEMPERATURE

SENSOR

BANDGAP

REF

BIAS

SERIAL

INTERFACE

AND

CONTROL

LOGIC

INTERNAL

CLOCK CLK

SCLK

DIN

SYNC

REGCAPD

IOV

AD7124-4-EP

DGND

24-BIT

Σ-∆ ADC

X-MUX

REFIN1(+)

REFOUT

PSW

VARIABLE

DIGITAL

FILTER

DIAGNOSTICS

COMMUNICATIONS

POWER SUPPLY

SIGNAL CHAIN

DIGITAL

REFIN1(–)

REFIN2(+)

REFIN2(–)

BURNOUT

DETECT

EXCITATION

CURRENTS

POWER

SWITCH

GPOs

CHANNEL

SEQUENCER

CROSSPOINT

MUX

REGCAP

1.9V

LDO

DIAGNOSTICS

DOUT/RDY

1.8V

LDO

ANALOG

BUFFERS

REFERENCE

BUFFERS

BUF

PGA2PGA1

AIN0/IOUT/VBIAS

AIN1/IOUT/VBIAS

AIN2/IOUT/VBIAS/P1

AIN3/IOUT/VBIAS/P2

AIN4/IOUT/VBIAS

AIN5/IOUT/VBIAS

AIN6/IOUT/VBIAS/REFIN2(+)

AIN7/IOUT/VBIAS/REFIN2(–)

20190-001

Figure 1.

AD7124-4-EP Enhanced Product

Rev. 0 | Page 2 of 17

TABLE OF CONTENTS

Features .............................................................................................. 1

Enhanced Product Features ............................................................ 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Specifications ..................................................................................... 4 

Absolute Maximum Ratings .......................................................... 10

Thermal Resistance .................................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions ........................... 11

Typical Performance Characteristics ........................................... 13

Outline Dimensions ....................................................................... 17

Ordering Guide .......................................................................... 17

REVISION HISTORY

4/2019—Revision 0: Initial Version

Enhanced Product AD7124-4-EP

Rev. 0 | Page 3 of 17

GENERAL DESCRIPTION

The AD7124-4-EP is a low power, low noise, completely

integrated analog front end for high precision measurement

applications. The device contains a low noise, 24-bit Σ-Δ analog-

to-digital converter (ADC), and can be configured to have four

differential inputs or seven single-ended or pseudo differential

inputs. The on-chip low gain stage ensures that signals of small

amplitude can be interfaced directly to the ADC.

One of the major advantages of the AD7124-4-EP is that it gives

the user the flexibility to employ one of three integrated power

modes. The current consumption, range of output data rates,

and rms noise can be tailored with the power mode selected.

The device also offers a multitude of filter options, ensuring that

the user has the highest degree of flexibility.

The AD7124-4-EP can achieve simultaneous 50 Hz and 60 Hz

rejection when operating at an output data rate of 25 SPS (single

cycle settling), with rejection in excess of 80 dB achieved at lower

output data rates.

The AD7124-4-EP establishes the highest degree of signal chain

integration. The device contains a precision, low noise, low

drift internal band gap reference, and also accepts an external

differential reference, which can be internally buffered. Other

key integrated features include programmable low drift excitation

current sources, burnout currents, and a bias voltage generator,

which sets the common-mode voltage of a channel to AVDD/2.

The low-side power switch enables the user to power down

bridge sensors between conversions, ensuring the absolute

minimal power consumption of the system. The device also

allows the user the option of operating with either an internal

clock or an external clock.

The integrated channel sequencer allows several channels to be

enabled simultaneously, and the AD7124-4-EP sequentially

converts on each enabled channel, simplifying communication

with the device. As many as 16 channels can be enabled at any

time; a channel being defined as an analog input or a diagnostic

such as a power supply check or a reference check. This unique

feature allows diagnostics to be interleaved with conversions.

The AD7124-4-EP also supports per channel configuration.

The device allows eight configurations or setups. Each

configuration consists of gain, filter type, output data rate,

buffering, and reference source. The user can assign any of

these setups on a channel by channel basis.

The AD7124-4-EP also has extensive diagnostic functionality

integrated as part of its comprehensive feature set. These

diagnostics include a cyclic redundancy check (CRC), signal

chain checks, and serial interface checks, which lead to a more

robust solution. These diagnostics reduce the need for external

components to implement diagnostics, resulting in reduced

board space needs, reduced design cycle times, and cost savings.

The failure modes effects and diagnostic analysis (FMEDA) of a

typical application has shown a safe failure fraction (SFF) greater

than 90% according to IEC 61508.

The device operates with a single analog power supply from 2.7 V

to 3.6 V or a dual 1.8 V power supply. The digital supply has a

range of 1.65 V to 3.6 V. It is specified for the full military

temperature range of −55°C to +125°C. The AD7124-4-EP is

housed in a 24-lead TSSOP package.

Note that, throughout this data sheet, multifunction pins, such

as DOUT/RDY, are referred to either by the entire pin name or

by a single function of the pin, for example, RDY, when only

that function is relevant.

Additional application and technical information can be found

in the AD7124-4 data sheet.

AD7124-4-EP Enhanced Product

Rev. 0 | Page 4 of 17

SPECIFICATIONS

AVDD = 2.9 V to 3.6 V (full power mode), 2.7 V to 3.6 V (mid and low power mode), IOVDD = 1.65 V to 3.6 V, AVSS = DGND = 0 V,

REFINx(+) = 2.5 V, REFINx(−) = AVSS, master clock = 614.4 kHz, all specifications TMIN to TMAX, unless otherwise noted.

Table 1.

Parameter1 Min Typ Max Unit Test Conditions/Comments

ADC

Output Data Rate, fADC

Low Power Mode 1.17 2400 SPS

Mid Power Mode 2.34 4800 SPS

Full Power Mode 9.38 19,200 SPS

No Missing Codes2 24 Bits FS3 > 2, sinc4 filter

24 Bits FS3 > 8, sinc3 filter

Resolution

RMS Noise and Update Rates

Integral Nonlinearity (INL) −4 ±1 +4 ppm of FSR Gain = 12

−15 ±2 +15 ppm of FSR Gain > 14

Offset Error5

Before Calibration ±15 μV Gain = 1 to 8

200/gain μV Gain = 16 to 128

After Internal Calibration/System

Calibration

In order of

noise

Offset Error Drift vs. Temperature6

Low Power Mode 10 nV/°C Gain = 1 or gain > 16

80 nV/°C Gain = 2 to 8

40 nV/°C Gain = 16

Mid Power Mode 10 nV/°C Gain = 1 or gain > 16

40 nV/°C Gain = 2 to 8

20 nV/°C Gain = 16

Full Power Mode 10 nV/°C

Gain Error5, 7

Before Internal Calibration −0.0025 +0.0025 % Gain = 1, TA = 25°C

−0.3 % Gain > 1

After Internal Calibration −0.016 +0.004 +0.016 % Gain = 2 to 8, TA = 25°C

±0.025 % Gain = 16 to 128

After System Calibration In order of

noise

Gain Error Drift vs. Temperature 1 2 ppm/°C

Power Supply Rejection AIN = 1 V/gain, external reference

Low Power Mode 87 dB Gain = 2 to 16

96 dB Gain = 1 or gain > 16

Mid Power Mode2 92 dB Gain = 2 to 16

100 dB Gain = 1 or gain > 16

Full Power Mode 99 dB

Common-Mode Rejection8

At DC2 85 90 dB AIN = 1 V, gain = 1

105 115 dB AIN = 1 V/gain, gain 2 or 4

1029, 2 dB AIN = 1 V/gain, gain 2 or 4

115 120 dB AIN = 1 V/gain, gain ≥ 8

1059, 2 dB AIN = 1 V/gain, gain ≥ 8

Sinc3, Sinc4 Filter2

At 50 Hz, 60 Hz 120 dB 10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz

At 50 Hz 120 dB 50 SPS, 50 Hz ± 1 Hz

At 60 Hz 120 dB 60 SPS, 60 Hz ± 1 Hz

Enhanced Product AD7124-4-EP

Rev. 0 | Page 5 of 17

Parameter1 Min Typ Max Unit Test Conditions/Comments

Fast Settling Filters2

At 50 Hz 115 dB First notch at 50 Hz, 50 Hz ± 1 Hz

At 60 Hz 115 dB First notch at 60 Hz, 60 Hz ± 1 Hz

Post Filters2

At 50 Hz, 60 Hz 130 dB 20 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz

130 dB 25 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz

Normal Mode Rejection2

Sinc4 Filter

External Clock

At 50 Hz, 60 Hz 120 dB 10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz

80 dB 50 SPS, REJ6010=1, 50 Hz ± 1 Hz,

60 Hz ± 1 Hz

At 50 Hz 120 dB 50 SPS, 50 Hz ± 1 Hz

At 60 Hz 120 dB 60 SPS, 60 Hz ± 1 Hz

Internal Clock

At 50 Hz, 60 Hz 98 dB 10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz

66 dB 50 SPS, REJ6010 = 1, 50 Hz ± 1 Hz,

60 Hz ± 1 Hz

At 50 Hz 92 dB 50 SPS, 50 Hz ± 1 Hz

At 60 Hz 92 dB 60 SPS, 60 Hz ± 1 Hz

Sinc3 Filter

External Clock

At 50 Hz, 60 Hz 100 dB 10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz

65 dB 50 SPS, REJ6010 = 1, 50 Hz ± 1 Hz,

60 Hz ± 1 Hz

At 50 Hz 100 dB 50 SPS, 50 Hz ± 1 Hz

At 60 Hz 100 dB 60 SPS, 60 Hz ± 1 Hz

Internal Clock

At 50 Hz, 60 Hz 73 dB 10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz

52 dB 50 SPS, REJ6010 = 1, 50 Hz ± 1 Hz,

60 Hz ± 1 Hz

At 50 Hz 68 dB 50 SPS, 50 Hz ± 1 Hz

At 60 Hz 68 dB 60 SPS, 60 Hz ± 1 Hz

Fast Settling Filters

External Clock

At 50 Hz 40 dB First notch at 50 Hz, 50 Hz ± 0.5 Hz

At 60 Hz 40 dB First notch at 60 Hz, 60 Hz ± 0.5 Hz

Internal Clock

At 50 Hz 24.5 dB First notch at 50 Hz, 50 Hz ± 0.5 Hz

At 60 Hz 24.5 dB First notch at 60 Hz, 60 Hz ± 0.5 Hz

Post Filters

External Clock

At 50 Hz, 60 Hz 86 dB 20 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz

62 dB 25 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz

Internal Clock

At 50 Hz, 60 Hz 67 dB 20 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz

50 dB 25 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz

AD7124-4-EP Enhanced Product

Rev. 0 | Page 6 of 17

Parameter1 Min Typ Max Unit Test Conditions/Comments

ANALOG INPUTS11

Differential Input Voltage Ranges12 ±VREF/gain V VREF = REFINx(+) − REFINx(−), or

internal reference

Absolute AIN Voltage Limits2

Gain = 1 (Unbuffered) AVSS − 0.05 AVDD + 0.05 V

Gain = 1 (Buffered) AVSS + 0.1 AVDD − 0.1 V

Gain > 1 AVSS − 0.05 AVDD + 0.05 V

Analog Input Current

Gain > 1 or Gain = 1 (Buffered)

Low Power Mode

Absolute Input Current ±1 nA

Differential Input Current ±0.2 nA

Analog Input Current Drift 25 pA/°C

Mid Power Mode

Absolute Input Current ±1.2 nA

Differential Input Current ±0.4 nA

Analog Input Current Drift 25 pA/°C

Full Power Mode

Absolute Input Current ±3.3 nA

Differential Input Current ±1.5 nA

Analog Input Current Drift 25 pA/°C

Gain = 1 (Unbuffered) Current varies with input voltage

Absolute Input Current ±2.65 μA/V

Analog Input Current Drift 1.1 nA/V/°C

REFERENCE INPUT

Internal Reference

Initial Accuracy 2.5 − 0.2% 2.5 2.5 + 0.2% V TA = 25°C

Drift 2 10 ppm/°C

Output Current 10 mA

Load Regulation 50 μV/mA

Power Supply Rejection 85 dB

External Reference

External REFIN Voltage2 0.5 2.5 AVDD V REFIN = REFINx(+) − REFINx(−)

Absolute REFIN Voltage Limits2 AVSS − 0.05 AVDD + 0.05 V Unbuffered

AVSS + 0.1 AVDD − 0.1 V Buffered

Reference Input Current

Buffered

Low Power Mode

Absolute Input Current ±0.5 nA

Reference Input Current Drift 10 pA/°C

Mid Power Mode

Absolute Input Current ±1 nA

Reference Input Current Drift 10 pA/°C

Full Power Mode

Absolute Input Current ±3 nA

Reference Input Current Drift 10 pA/°C

Unbuffered

Absolute Input Current ±12 μA

Reference Input Current Drift 6 nA/°C

Normal Mode Rejection Same as for analog inputs

Common-Mode Rejection 100 dB

Enhanced Product AD7124-4-EP

Rev. 0 | Page 7 of 17

Parameter1 Min Typ Max Unit Test Conditions/Comments

EXCITATION CURRENT SOURCES (IOUT0/IOUT1) Available on any analog input pin

Output Current 50/100/250/

500/750/1000

μA

Initial Tolerance ±4 % TA = 25°C

Drift 50 ppm/°C

Current Matching ±0.5 % Matching between IOUT0 and

IOUT1, VOUT = 0 V

Drift Matching2 5 30 ppm/°C

Line Regulation (AVDD) 2 %/V AVDD = 3 V ± 5%

Load Regulation 0.2 %/V

Output Compliance2 AVSS − 0.05 AVDD − 0.37 V 50 μA/100 μA/250 μA/500 μA

current sources, 2% accuracy

AVSS − 0.05 AVDD − 0.48 V 750 μA and 1000 μA current

sources, 2% accuracy

BIAS VOLTAGE (VBIAS) GENERATOR Available on any analog input pin

VBIAS AVSS + (AVDD −

AVSS)/2

VBIAS Generator Start-Up Time 6.7 μs/nF Dependent on the capacitance

connected to AINx

TEMPERATURE SENSOR

Accuracy ±0.5 °C

Sensitivity 13,584 Codes/°C

LOW-SIDE POWER SWITCH

On Resistance (RON) 7 10 Ω

Allowable Current2 30 mA Continuous current

BURNOUT CURRENTS

AIN Current 0.5/2/4 μA Analog inputs must be buffered

DIGITAL OUTPUTS (P1 AND P2)

Output Voltage

High, VOH AVDD − 0.6 V ISOURCE = 100 μA

Low, VOL 0.4 V ISINK = 100 μA

DIAGNOSTICS

Power Supply Monitor Detect Level

Analog Low Dropout Regulator (ALDO) 1.6 V AVDD − AVSS ≥ 2.7 V

Digital LDO (DLDO) 1.55 V IOVDD ≥ 1.75 V

Reference Detect Level 0.7 1 V REF_DET_ERR bit active if VREF < 0.7 V

AINM/AINP Overvoltage Detect Level AVDD + 0.04 V

AINM/AINP Undervoltage Detect Level AVSS − 0.04 V

INTERNAL/EXTERNAL CLOCK

Internal Clock

Frequency 614.4 − 5% 614.4 614.4 + 5% kHz

Duty Cycle 50:50 %

External Clock

Frequency 2.4576 MHz Internal divide by 4

Duty Cycle Range 45:55 to 55:45 %

LOGIC INPUTS2

Input Voltage

Low, VINL 0.3 × IOVDD V 1.65 V ≤ IOVDD < 1.9 V

0.35 × IOVDD V 1.9 V ≤ IOVDD < 2.3 V

0.7 V 2.3 V ≤ IOVDD ≤ 3.6 V

High, VINH 0.7 × IOVDD V 1.65 V ≤ IOVDD < 1.9 V

0.65 × IOVDD V 1.9 V ≤ IOVDD < 2.3 V

1.7 V 2.3 V ≤ IOVDD < 2.7 V

2 V 2.7 V ≤ IOVDD ≤ 3.6 V

Hysteresis 0.2 0.6 V 1.65 V ≤ IOVDD ≤ 3.6 V

Input Currents −1 +1 μA VIN = IOVDD or GND

Input Capacitance 10 pF All digital inputs

AD7124-4-EP Enhanced Product

Rev. 0 | Page 8 of 17

Parameter1 Min Typ Max Unit Test Conditions/Comments

LOGIC OUTPUTS (INCLUDING CLK)

Output Voltage2

High, VOH IOVDD − 0.35 V ISOURCE = 100 μA

Low, VOL 0.4 V ISINK = 100 μA

Floating State Leakage Current −1 +1 μA

Floating State Output Capacitance 10 pF

Data Output Coding Offset binary

SYSTEM CALIBRATION2

Calibration Limit

Full Scale (FS) 1.05 × FS V

Zero Scale −1.05 × FS V

Input Span 0.8 × FS 2.1 × FS V

POWER SUPPLY VOLTAGES FOR ALL POWER

MODES

AVDD to AVSS

Low Power Mode 2.7 3.6 V

Mid Power Mode 2.7 3.6 V

Full Power Mode 2.9 3.6 V

IOVDD to GND 1.65 3.6 V

AVSS to GND −1.8 0 V

IOVDD to AVSS 5.4 V

POWER SUPPLY CURRENTS11, 13

IAVDD, External Reference

Low Power Mode

Gain = 12 125 140 μA All buffers off

Gain = 1 IAVDD Increase per AINx Buffer2 15 25 μA

Gain = 2 to 8 205 250 μA

Gain = 16 to 128 235 300 μA

IAVDD Increase per Reference Buffer2 10 20 μA All gains

Mid Power Mode

Gain = 12 150 170 μA All buffers off

Gain = 1 IAVDD Increase per AINx Buffer2 30 40 μA

Gain = 2 to 8 275 345 μA

Gain = 16 to 128 330 430 μA

IAVDD Increase per Reference Buffer2 20 30 μA All gains

Full Power Mode

Gain = 12 315 350 μA All buffers off

Gain = 1 IAVDD Increase per AINx Buffer2 90 135 μA

Gain = 2 to 8 660 830 μA

Gain = 16 to 128 875 1200 μA

IAVDD Increase per Reference Buffer2 85 120 μA All gains

IAVDD Increase

Due to Internal Reference2 50 70 μA Independent of power mode; the

reference buffers are not required

when using this reference

Due to VBIAS2 15 20 μA Independent of power mode

Due to Diagnostics2 4 5 μA

IIOVDD

Low Power Mode 20 35 μA

Mid Power Mode 25 40 μA

Full Power Mode 55 80 μA

Enhanced Product AD7124-4-EP

Rev. 0 | Page 9 of 17

Parameter1 Min Typ Max Unit Test Conditions/Comments

POWER-DOWN CURRENTS13 Independent of power mode

Standby Current

IAVDD 7 15 μA LDOs on only

IIOVDD 8 20 μA

Power-Down Current

IAVDD 1 3 μA

IIOVDD 1 2 μA

1 Temperature range = −55°C to +125°C.

2 These specifications are not production tested but are supported by characterization data at the initial product release.

3 FS is the decimal equivalent of the FS[10:0] bits in the filter registers.

4 The integral nonlinearity is production tested in full power mode only. For other power modes, the specification is supported by characterization data at the initial

product release.

5 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full-

scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.

6 Recalibration at any temperature removes these errors.

7 Gain error applies to both positive and negative full-scale. A factory calibration is performed at gain = 1, TA = 25°C.

8 When gain > 1, the common-mode voltage is between (AVSS + 0.1 + 0.5/gain) and (AVDD − 0.1 − 0.5/gain).

9 Specification is for a wider common-mode voltage between (AVSS − 0.05 + 0.5/gain) and (AVDD − 0.1 − 0.5/gain).

10 REJ60 is a bit in the filter registers. When the first notch of the sinc filter is at 50 Hz, a notch is placed at 60 Hz when REJ60 is set to 1. This gives simultaneous 50 Hz and

60 Hz rejection.

11 When the gain is greater than 1, the analog input buffers are enabled automatically. The buffers can only be disabled when the gain equals 1.

12 When VREF = (AVDD − AVSS), the typical differential input equals 0.92 × VREF/gain for the low and mid power modes and 0.86 × VREF/gain for full power mode when gain > 1.

13 The digital inputs are equal to IOVDD or DGND with excitation currents and bias voltage generator disabled.

AD7124-4-EP Enhanced Product

Rev. 0 | Page 10 of 17

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 2.

Parameter Rating

AVDD to AVSS −0.3 V to +3.96 V

IOVDD to DGND −0.3 V to +3.96 V

IOVDD to AVSS −0.3 V to +5.94 V

AVSS to DGND −1.98 V to +0.3 V

Analog Input Voltage to AVSS −0.3 V to AVDD + 0.3 V

Reference Input Voltage to AVSS −0.3 V to AVDD + 0.3 V

Digital Input Voltage to DGND −0.3 V to IOVDD + 0.3 V

Digital Output Voltage to DGND −0.3 V to IOVDD + 0.3 V

AINx/Digital Input Current 10 mA

Operating Temperature Range −55°C to +125°C

Storage Temperature Range −65°C to +150°C

Maximum Junction Temperature 150°C

Lead Temperature, Soldering

Reflow 260°C

ESD Ratings

Human Body Model (HBM) 4 kV

Field-Induced Charged Device

Model (FICDM)

1250 V

Machine Model 400 V

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required.

θJA is the natural convection, junction to ambient thermal

resistance measured in a one cubic foot sealed enclosure.

θJC is the junction to case thermal resistance.

Table 3. Thermal Resistance

Package Type1 θ

JA θ

JC Unit

RU-24 128 42 °C/W

1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal

test board. See JEDEC JESD51.

ESD CAUTION

Enhanced Product AD7124-4-EP

Rev. 0 | Page 11 of 17

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SCLK

CLK

DGND

IOVDD

REGCAPD

DIN

SYNC

AVDD

PSW

REFOUT

AVSS

REGCAPA

AIN0/IOUT/VBIAS

AIN1/IOUT/VBIAS

REFIN1(+)

AIN3/IOUT/VBIAS/P2

AIN2/IOUT/VBIAS/P1

AIN7/IOUT/VBIAS/REFIN2(–)

AIN6/IOUT/VBIAS/REFIN2(+)

REFIN1(–)

AIN4/IOUT/VBIAS

AIN5/IOUT/VBIAS

DOUT/RDY

AD7124-4-EP

TOP VIEW

(Not to Scale)

20190-002

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 DIN Serial Data Input to the Input Shift Register on the ADC. Data in the input shift register is transferred to

the control registers within the ADC, with the register selection bits of the communications register

identifying the appropriate register.

2 SCLK Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK pin has a Schmitt-

triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous

with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock

with the information being transmitted to or from the ADC in smaller batches of data.

3 CLK Clock Input/Clock Output. The internal clock can be made available at this pin. Alternatively, the internal

clock can be disabled, and the ADC can be driven by an external clock. This allows several ADCs to be

driven from a common clock, allowing simultaneous conversions to be performed.

4 CS Chip Select Input. This is an active low logic input that selects the ADC. Use CS to select the ADC in systems

with more than one device on the serial bus or as a frame synchronization signal in communicating with the

device. CS can be hardwired low if the serial peripheral interface (SPI) diagnostics are unused, allowing the

ADC to operate in 3-wire mode with SCLK, DIN, and DOUT interfacing with the device.

5 REGCAPD Digital LDO Regulator Output. Decouple this pin to DGND with a 0.1 μF capacitor.

6 IOVDD Serial Interface Supply Voltage, 1.65 V to 3.6 V. IOVDD is independent of AVDD. Therefore, the serial

interface can operate at 1.65 V with AVDD at 3.6 V, for example.

7 DGND Digital Ground Reference Point.

8 AIN0/IOUT/VBIAS

Analog Input 0/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via

the configuration registers to be the positive or negative terminal of a differential or pseudo differential

input. Alternatively, the internal programmable excitation current source can be made available at this pin.

Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power

supply rails can be generated at this pin.

9 AIN1/IOUT/VBIAS

Analog Input 1/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via

the configuration registers to be the positive or negative terminal of a differential or pseudo differential

input. Alternatively, the internal programmable excitation current source can be made available at this pin.

Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power

supply rails can be generated at this pin.

10 AIN2/IOUT/VBIAS/P1

Analog Input 2/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 1. This

input pin is configured via the configuration registers to be the positive or negative terminal of a

differential or pseudo differential input. Alternatively, the internal programmable excitation current source

can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin. This pin can also be configured

as a general-purpose output bit, referenced between AVSS and AVDD.

AD7124-4-EP Enhanced Product

Rev. 0 | Page 12 of 17

Pin No. Mnemonic Description

11 AIN3/IOUT/VBIAS/P2

Analog Input 3/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 2. This

input pin is configured via the configuration registers to be the positive or negative terminal of a

differential or pseudo differential input. Alternatively, the internal programmable excitation current source

can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin. This pin can also be configured

as a general-purpose output bit, referenced between AVSS and AVDD.

12 REFIN1(+) Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−).

REFIN1(+) can be anywhere between AVDD and AVSS + 0.5 V. The nominal reference voltage (REFIN1(+) −

REFIN1(−)) is 2.5 V, but the device functions with a reference from 0.5 V to AVDD.

13 REFIN1(−) Negative Reference Input. This reference input can be anywhere between AVSS and

AVDD – 0.5 V.

14 AIN4/IOUT/VBIAS

Analog Input 4/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the

configuration registers to be the positive or negative terminal of a differential or pseudo differential input.

Alternatively, the internal programmable excitation current source can be made available at this pin. Either

IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply

rails can be generated at this pin.

15 AIN5/IOUT/VBIAS

Analog Input 5/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the

configuration registers to be the positive or negative terminal of a differential or pseudo differential input.

Alternatively, the internal programmable excitation current source can be made available at this pin. Either

IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply

rails can be generated at this pin.

16 AIN6/IOUT/VBIAS/

REFIN2(+)

Analog Input 6/Output of Internal Excitation Current Source/Bias Voltage/Positive Reference Input. This

input pin is configured via the configuration registers to be the positive or negative terminal of a differential or

pseudo differential input. Alternatively, the internal programmable excitation current source can be made

available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between

the analog power supply rails can be generated at this pin. This pin also functions as a positive reference

input for REFIN2(±). REFIN2(+) can be anywhere between AVDD and AVSS + 0.5 V. The nominal reference

voltage (REFIN2(+) to REFIN2(−)) is 2.5 V, but the device functions with a reference from 0.5 V to AVDD.

17 AIN7/IOUT/VBIAS/

REFIN2(−)

Analog Input 7/Output of Internal Excitation Current Source/Bias Voltage/Negative Reference Input. This

input pin is configured via the configuration registers to be the positive or negative terminal of a differential or

pseudo differential input. Alternatively, the internal programmable excitation current source can be made

available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between

the analog power supply rails can be generated at this pin. This pin also functions as the negative reference

input for REFIN2(±). This reference input can be anywhere between AVSS and AVDD – 0.5 V.

18 REFOUT Internal Reference Output. The buffered output of the internal 2.5 V voltage reference is available on this pin.

19 AVSS Analog Supply Voltage. The voltage on AVDD is referenced to AVSS. The differential between AVDD and AVSS

must be between 2.7 V and 3.6 V in mid or low power mode and between 2.9 V and 3.6 V in full power

mode. AVSS can be taken below 0 V to provide a dual power supply to the AD7124-4-EP. For example, AVSS

can be tied to −1.8 V and AVDD can be tied to +1.8 V, providing a ±1.8 V supply to the ADC.

20 REGCAPA Analog LDO Regulator Output. Decouple this pin to AVSS with a 0.1 μF capacitor.

21 PSW Low-Side Power Switch to AVSS.

22 AVDD Analog Supply Voltage, Relative to AVSS.

23 SYNC Synchronization Input. This pin is a logic input that allows synchronization of the digital filters and analog

modulators when using a number of AD7124-4-EP devices. When SYNC is low, the nodes of the digital

filter, the filter control logic, and the calibration control logic are reset, and the analog modulator is held

in a reset state. SYNC does not affect the digital interface but does reset RDY to a high state if it is low.

24 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY functions as a serial data output pin to access the

output shift register of the ADC. The output shift register can contain data from any of the on-chip data

or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion

of a conversion. If the data is not read after the conversion, the pin goes high before the next update

occurs. The DOUT/RDY falling edge can also be used as an interrupt to a processor, indicating that valid

data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. When CS is

low, the data/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is

valid on the SCLK rising edge.

Enhanced Product AD7124-4-EP

Rev. 0 | Page 13 of 17

TYPICAL PERFORMANCE CHARACTERISTICS

–60

–40

–20

–55 –40 –25 –10 5 20 35 50 65 80 95 110 125

INPUT REFERRED OFFSET ERROR (µV)

TEMPERATURE (°C)

15 UNITS

20190-003

Figure 3. Input Referred Offset Error vs. Temperature (Gain = 8, Full Power Mode)

–60

–40

–20

–55 –40 –25 –10 5 20 35 50 65 80 95 110 125

INPUT REFERRED OFFSET ERROR (µV)

TEMPERATURE (°C)

15 UNITS

20190-004

Figure 4. Input Referred Offset Error vs. Temperature (Gain = 8, Mid Power Mode)

–60

–40

–20

–55 –40 –25 –10 5 20 35 50 65 80 95 110 125

INPUT REFERRED OFFSET ERROR (µV)

TEMPERATURE (°C)

15 UNITS

20190-005

Figure 5. Input Referred Offset Error vs. Temperature (Gain = 8, Low Power Mode)

–60

–40

–20

–55 –40 –25 –10 5 20 35 50 65 80 95 110 125

INPUT REFERRED OFFSET ERROR (µV)

TEMPERATURE (°C)

15 UNITS

20190-006

Figure 6. Input Referred Offset Error vs. Temperature (Gain = 16, Full Power Mode)

–60

–40

–20

–55 –40 –25 –10 5 20 35 50 65 80 95 110 125

INPUT REFERRED OFFSET ERROR (µV)

TEMPERATURE (°C)

15 UNITS

20190-007

Figure 7. Input Referred Offset Error vs. Temperature (Gain = 16, Mid Power Mode)

–60

–40

–20

–55 –40 –25 –10 5 20 35 50 65 80 95 110 125

INPUT REFERRED OFFSET ERROR (µV)

TEMPERATURE (°C)

15 UNITS

20190-008

Figure 8. Input Referred Offset Error vs. Temperature (Gain = 16, Low Power Mode)

AD7124-4-EP Enhanced Product

Rev. 0 | Page 14 of 17

–60

–40

–20

–55 –40 –25 –10 5 20 35 50 65 80 95 110 125

INPUT REFERRED OFFSET ERROR (µV)

TEMPERATURE (°C)

15 UNITS

20190-009

Figure 9. Input Referred Offset Error vs. Temperature (Gain = 1, Analog Input

Buffers Enabled)

–0.0015

–0.0010

–0.0005

0.0005

0.0010

0.0015

–55–40–25–105 203550658095110125

INPUT REFERRED OFFSET ERROR (%)

TEMPERATURE (°C)

15 UNITS

20190-010

Figure 10. Input Referred Gain Error vs. Temperature (Gain = 1)

–0.015

–0.010

–0.005

0.005

0.010

0.015

–55–40–25–105 203550658095110125

INPUT REFERRED OFFSET ERROR (%)

TEMPERATURE (°C)

15 UNITS

20190-011

Figure 11. Input Referred Gain Error vs. Temperature (Gain = 8)

–0.015

–0.010

–0.005

0.005

0.010

0.015

0.020

0.025

0.030

0.035

0.040

–55–40–25–105 203550658095110125

INPUT REFERRED OFFSET ERROR (%)

TEMPERATURE (°C)

15 UNITS

20190-012

Figure 12. Input Referred Gain Error vs. Temperature (Gain = 16)

–55–40–25–105 203550658095110125

INTERNAL REFERENCE VOLTAGE (V)

TEMPERATURE (°C)

15 UNITS

2.4965

2.4970

2.4975

2.4980

2.4985

2.4990

2.4995

2.5000

2.5005

2.5010

2.5015

2.5020

20190-013

Figure 13. Internal Reference Voltage vs. Temperature

–55–40–25–105 203550658095110125

EXCITATION CURRENT DRIVE (µA)

TEMPERATURE (°C)

15 UNITS

470

475

480

485

490

495

500

505

510

20190-014

Figure 14. Excitation Current Drift (500 μA)

Enhanced Product AD7124-4-EP

Rev. 0 | Page 15 of 17

–55–40–25–105 203550658095110125

EXCITATION CURRENT MISMATCH (%)

TEMPERATURE (°C)

15 UNITS

–1.2

–1.0

–0.8

–0.6

–0.4

–0.2

20190-015

Figure 15. Excitation Current Drift Matching (500 μA)

–55–40–25–105 203550658095110125

ANALOG CURRENT (µA)

TEMPERATURE (°C)

200

400

600

800

1000

1200

GAIN = 1, AIN BUFFERS OFF

GAIN = 2 TO 8

GAIN = 1, AIN BUFFERS ON

GAIN = 16 TO 128

20190-016

Figure 16. Analog Current vs. Temperature (Full Power Mode)

–55–40–25–105 203550658095110125

ANALOG CURRENT (µA)

TEMPERATURE (°C)

450

400

350

300

250

200

150

100

GAIN = 1, AIN BUFFERS OFF

GAIN = 2 TO 8

GAIN = 1, AIN BUFFERS ON

GAIN = 16 TO 128

20190-017

Figure 17. Analog Current vs. Temperature (Mid Power Mode)

–55–40–25–105 203550658095110125

ANALOG CURRENT (µA)

TEMPERATURE (°C)

350

300

250

200

150

100

GAIN = 1, AIN BUFFERS OFF

GAIN = 2 TO 8

GAIN = 1, AIN BUFFERS ON

GAIN = 16 TO 128

20190-018

Figure 18. Analog Current vs. Temperature (Low Power Mode)

AD7124-4-EP Enhanced Product

Rev. 0 | Page 16 of 17

–55–40–25–105 203550658095110125

DIGITAL CURRENT (µA)

TEMPERATURE (°C)

FULL POWER

MID POWER

LOW POWER

20190-019

Figure 19. Digital Current vs. Temperature

–55–40–25–105 203550658095110125

TEMPERATURE SENSOR ERROR (%)

TEMPERATURE (°C)

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

1.0

1.2 6 UNITS

20190-027

Figure 20. Temperature Sensor Accuracy

–55–40–25–105 203550658095110125

INTERNAL OSCILLATOR ERROR (%)

TEMPERATURE (°C)

–3

–2

–1

315 UNITS

20190-028

Figure 21. Internal Oscillator Error vs. Temperature

Enhanced Product AD7124-4-EP

Rev. 0 | Page 17 of 17

OUTLINE DIMENSIONS

24 13

121

6.40 BSC

4.50

4.40

4.30

PIN 1

7.90

7.80

7.70

0.15

0.05

0.30

0.19

0.65

BSC 1.20

MAX

0.20

0.09

0.75

0.60

0.45

8°

0°

SEATING

PLANE

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AD

Figure 22. 24-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-24)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD7124-4TRUZ-EP −55°C to +125°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24

AD7124-4TRUZ-EP-R7 −55°C to +125°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24

1 Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D20190-0-4/19(0)