(R) RT7736 SmartJitterTM PWM Flyback Controller General Description Features The RT7736 series is a high performance enhanced PWM flyback controller with proprietary SmartJitterTM technology. The innovative SmartJitterTM technology not only reduces EMI emissions of SMPS when the system enters burst switching green mode, but also eliminates output jittering ripple. The RT7736 is a current mode PWM controller including built-in slope compensation, internal Leading Edge Blanking (LEB) and cycle-by-cycle current limit. It provides excellent green power performance, especially under light load and no load conditions. It allows for simpler design and reduces external component count. The RT7736 is a cost-effective and compact solution for NB adaptor applications. It is available in the SOT-23-6 package. Reducing EMI Emissions of SMPS Output Jittering Ripple Elimination No Load Input Power Under 100mW (RT7736G/R/L/E) Accurate Over Load Protection UVLO 9V/14.5V PRO Pin for External Arbitrary OVP/OTP IC ON/OFF Control (RT7736G/R/L) BNO Pin for Brown-In/Out (RT7736B/D/F) Soft Driving for EMI Noise Reduction Driver Capability : 300mA/- -300mA High Noise Immunity RoHS Compliant and Halogen Free This controller integrates comprehensive safety protection functions for robust designs including input Under-Voltage Lockout (UVLO), Over-Voltage Protection (OVP), OverLoad Protection (OLP), Secondary Rectifier Short Protection (SRSP), CS pin open protection and cycle-bycycle current limit. Proprietary SmartJitterTM Technology Applications Switching AC/DC Adaptor DVD Open Frame Power Supply Set-Top Box (STB) ATX Standby Power TV/Monitor Standby Power PC Peripherals NB Adaptor Simplified Application Circuit Vo+ + + AC Mains (90V to 265V) Vo- PRO COMP VDD GATE RT7736 CS GND Copyright (c) 2014 Richtek Technology Corporation. All rights reserved. DS7736-04 September 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT7736 Ordering Information RT7736 Package Type E : SOT-23-6 Note : Richtek products are : Lead Plating System G : Green (Halogen Free and Pb Free) RT7736 Version (Refer to Version Table) RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. Marking Information RT7736RGE RT7736GGE IFF= : Product Code IFF=DNN 2B= : Product Code 2B=DNN DNN : Date Code RT7736EGE RT7736LGE 09= : Product Code 09=DNN 0F= : Product Code 0F=DNN DNN : Date Code DNN : Date Code RT7736DGE RT7736BGE 0N= : Product Code 00= : Product Code 00=DNN DNN : Date Code 0N=DNN DNN : Date Code DNN : Date Code RT7736FGE 0P= : Product Code 0P=DNN DNN : Date Code RT7736 Version Table Version RT7736G RT7736R RT7736L RT7736E RT7736B RT7736D RT7736F Frequency 65kHz 65kHz 65kHz 65kHz 65kHz 65kHz 65kHz OLP Delay Time 56ms 56ms 56ms 56ms 56ms 88ms 64ms Internal OVP Auto Recovery Auto Recovery Latch Latch Auto Recovery Auto Recovery Auto Recovery OLP & SRSP Auto Recovery Auto Recovery Auto Recovery Auto Recovery Auto Recovery Auto Recovery Auto Recovery PRO Pin High Latch Auto Recovery Latch Latch X X X PRO Pin Low Auto Recovery Auto Recovery Auto Recovery Latch X X X External OTP by PRO Auto Recovery Auto Recovery Latch Latch X X X External Brown-In/Out X X X X Copyright (c) 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS7736-04 September 2014 RT7736 Pin Configurations (TOP VIEW) GATE VDD CS 6 5 4 2 3 GATE VDD CS 6 5 4 2 3 GND COMP PRO GND COMP BNO RT7736G/R/L/E RT7736B/D/F SOT-23-6 SOT-23-6 Functional Pin Description Pin No. Pin Name Pin Function 1 GND Ground of the Controller. 2 COMP Feedback Voltage Input. Connect an opto-coupler to close the control loop and achieve output voltage regulation. PRO Protection Input for OVP, OTP or ON/OFF Control. (RT7736G/R/L/E) BNO Brown-In/Out Detection Input for RT7736B/D/F Only. 4 CS Current Sense Input. The current sense resistor between this pin and GND is used for current limit setting. 5 VDD Supply Voltage Input. The controller will be enabled when VDD exceeds VTH_ON (14.5V typ.) and disabled when VDD decreases lower than VTH_OFF (9V typ.) 6 GATE Gate Driver Output for External Power MOSFET. 3 Copyright (c) 2014 Richtek Technology Corporation. All rights reserved. DS7736-04 September 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT7736 Function Block Diagram VDD + IBias VTH_H - VTH_OTP + PRO OVP - VTH_L + - 27V + - 2V Secondary Rectifier Short Protection - Shutdown Logic OTP POR UVLO + + - Counter COMP Open Sensing OLP Bias & Bandgap Oscillator TOLP : 56ms Constant Power Dmax 5.2V Soft Driver S COMP Slope Ramp CS 9V/14.5V + PWM Comparator Q COMP Burst Switching Green Mode LEB GATE R X3 VBURL VBURH VDD GND Figure 1. Block Diagram for RT7736G, RT7736R, RT7736L and RT7736E Copyright (c) 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS7736-04 September 2014 RT7736 VDD OVP VBIN_TH/VBNO_TH BNO + + - 27V - 2V Secondary Rectifier Short Protection + OTP Shutdown Logic POR UVLO + - OLP Bias & Bandgap TOLP : 56ms (RT7736B) TOLP : 88ms (RT7736D) TOLP : 64ms (RT7736F) Oscillator Dmax Constant Power 5.2V Soft Driver S COMP Slope Ramp CS + PWM Comparator Q GATE R COMP Burst Switching Green Mode LEB 9V/14.5V Counter COMP Open Sensing X3 VBURL VBURH VDD GND Figure 2. Block Diagram for RT7736B, RT7736D and RT7736F Operation The burst mode is designed to reduce switching loss. When the output load reduces, and the VCOMP drops and reaches VBURL, the controller will cease switching. After output voltage decreases and the VCOMP goes up to VBURH, the switching will be resumed. then force switching at a very low level to supply energy to VDD pin. VDD holdup mode is also improved to hold up VDD by less switching cycles. This mode is very useful for reducing start-up resistor loss and keeping start-up time within specification. This function makes bias winding design and transient design easier. VDD Holdup Mode Oscillator Under very light load conditions, the VDD may drop down to turn-off threshold voltage. To avoid this situation when VDD drops to a set threshold, VDD_ET, the hysteresis comparator will bypass PWM and burst mode loop, and The oscillator runs at 65kHz and features frequency jittering function. Its jittering depth is f with about TJIT envelope frequency at fOSC. It also generates slope compensation saw-tooth, maximum duty cycle pulse and overload protection slope. Burst Switching Green Mode Copyright (c) 2014 Richtek Technology Corporation. All rights reserved. DS7736-04 September 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT7736 Leading Edge Blanking (LEB) Feedback Open and Opto-Coupler Short To prevent unexpectedly gate switching interruption from the initial spike on CS pin, the LEB delay is designed to block this spike at the beginning of gate switching. If the output voltage feedback loop is open or the optocoupler is shorted, the OVP/OLP function will be triggered depending on which one occurs first. Gate Driver Secondary Rectifier Short Protection A totem pole gate driver is designed to meet both EMI and efficiency requirements in low power applications. An internal pull-low circuit is activated after pretty low VDD to prevent external MOSFET from accidentally turning on during UVLO. The current spike during secondary rectifier short test is extremely high because of the saturated main transformer. Meanwhile, the transformer acts like a leakage inductance. During high line, the current in power MOSFET is sometimes too high for OLP delay time. To offer better and easier protection design, the RT7736 will shut down after a few of cycles before fuse is impacted. PRO Pin (RT7736G/R/L/E) The RT7736G/R/L/E features a PRO pin, and it can be applied for external arbitrary OVP or OTP applications (RT7736G/R/L/E), and also can be applied for IC ON/OFF control (RT7736G/R/L). BNO Pin (RT7736B/D/F) Output Short Protection The RT7736 implements output short protection by detecting GATE width with delay time. It could minimize the power loss and temperature during output short, especially at high line input voltage. The RT7736B/D/F features a BNO pin, and it can be applied for external arbitrary brown-in/out. The BNO pin is connected to the AC line input or bulk capacitor with a resistive divider to achieve brown-in/out protection. Cycle-by-Cycle Current Limit This is a basic but very useful function and it can be implemented easily in current mode controller. Over-Load Protection In over load conditions, long time current limit will lead to system thermal stress problem. To further protect the system, the RT7736 is designed with a proprietary prolonged turn-off period during hiccup. The power loss and temperature during OLP will be averaged to an acceptable level over the ON/OFF cycle. CS Pin Open Protection When the CS pin is opened, the controller will shut down after a few cycles. Over-Voltage Protection Output voltage can be roughly sensed by the VDD pin. If the sensed voltage reaches VOVP threshold, the controller will shut down after deglitch delay. The controller will resume once the fault is removed. Copyright (c) 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 is a registered trademark of Richtek Technology Corporation. DS7736-04 September 2014 RT7736 Absolute Maximum Ratings (Note 1) Supply Input Voltage, VDD to GND ------------------------------------------------------------------------------------GATE to GND -------------------------------------------------------------------------------------------------------------- PRO, BNO, COMP, CS to GND --------------------------------------------------------------------------------------- Power Dissipation, PD @ TA = 25C SOT-23-6 -------------------------------------------------------------------------------------------------------------------- Package Thermal Resistance (Note 2) SOT-23-6, JA --------------------------------------------------------------------------------------------------------------- Junction Temperature ----------------------------------------------------------------------------------------------------- Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------- Storage Temperature Range -------------------------------------------------------------------------------------------- ESD Susceptibility (Note 3) HBM (Human Body Model) ----------------------------------------------------------------------------------------------MM (Machine Model) ----------------------------------------------------------------------------------------------------- Recommended Operating Conditions -0.3V to 30V -0.3V to 16.5V -0.3V to 6.5V 0.38W 260.7C/W 150C 260C -65C to 150C 3kV 250V (Note 4) Supply Input Voltage, VDD ----------------------------------------------------------------------------------------------- 12V to 25V Junction Temperature Range --------------------------------------------------------------------------------------------- -40C to 125C Ambient Temperature Range --------------------------------------------------------------------------------------------- -40C to 85C Electrical Characteristics (VDD = 15V, TA = 25C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit V DD Over-Voltage Protection Level VOVP 26 27 28 V V DD Zener Clamp VZ 29 -- -- V On Threshold Voltage VTH_ON 13.5 14.5 15.5 V Off Threshold Voltage VTH_OFF 8.5 9 9.5 V Disable Brown-in Detection to Avoid Start-up Failed VDD_BNI 11 12 13 V VDD Holdup Mode Entry Point VDD_ET VCOMP < 1.3V 9.5 10 10.5 V VDD Holdup Mode Ending Point VDD_ED VCOMP < 1.3V 10 10.5 11 V Latch-off Clamping Voltage VDD_LH -- 5.5 -- V Threshold Voltage for Latch-off Release VLH_OFF -- 5 -- V Start-up Current IDD_ST VDD < V TH_ON 0.1V, TA = 40C to 80C -- 5 10 A Latch-off Operating Current IDD_LH TA = 40C to 80C 2 -- 10 A Operating Supply Current IDD_OP1 VDD = 15V, GATE pin open, VCOMP = 2.5V -- 1 -- mA Operating Supply Current IDD_OP2 VDD = 15V, GATE pin open, VCOMP = 1.7V -- 0.9 -- mA IDD Sinking Current of Waiting Brown-in After Start-up IDD_BNI For RT7736B/D/F ; V DD = 15V, GATE and COMP pin open 100 150 200 A VDD Section Copyright (c) 2014 Richtek Technology Corporation. All rights reserved. DS7736-04 September 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT7736 Parameter Symbol Test Conditions Min Typ Max Unit IDD_ARP During entering auto recovery protection 300 400 500 A Normal PWM Frequency fOSC VCOMP > VBS_ET 60 65 70 kHz Maximum Duty Cycle DCYMAX 70 75 80 % Minimum Burst Switching Green Mode Frequency f BS_MIN 18.5 22 25.5 kHz PWM Frequency Jittering Range f -- 6 -- % PWM Frequency Jittering Period TJIT -- 16 -- ms Frequency Variation Versus VDD Deviation f DV VDD = 9V to 23V -- -- 2 % Frequency Variation Versus Temperature Deviation f DT TA = 30C to105C -- -- 5 % 5 5.2 5.4 V 0.24 0.29 0.34 mA -- 56 -- fOSC = 65kHz RT7736D -- 88 -- RT7736F -- 64 -- Burst Switching Green Mode Entry VBS_ET Voltage 2.3 2.35 2.4 V Burst Switching Green Mode Ending Voltage VBS_ED 2.1 2.15 2.2 V Delay Time of Output Short Protection TD_OSP fOSC = 65kHz, RT7736G/R/L/E/B -- 8 -- ms Maximum Current Limit VCS_MAX (Note 5) 1.05 1.1 1.15 V Leading Edge Blanking Time TLEB (Note 5) 150 250 350 ns Internal Propagation Delay Time TPD (Note 5) -- 100 -- ns Minimum On-Time TON_MIN 250 350 450 ns 0.7 1.1 1.5 s IDD Sinking Current Oscillator Section COMP Input Section Open Loop Voltage VCOMP_OP COMP pin open Short Circuit Current of COMP IZERO Delay Time of COMP Open-loop Protection VCOMP = 0V RT7736G/R/L/E/B TOLP ms Current Sense Section Detection On-Time of Output Short TON_OSP Protection fOSC = 65kHz, RT7736G/R/L/E/B (Note 6) GATE Section Rising Time TR VDD = 15V, CL = 1nF -- 60 -- ns Falling Time TF VDD = 15V, CL = 1nF -- 40 -- ns Gate Output Clamping Voltage VCLAMP VDD = 23V -- 13.5 -- V PRO Interface Section (RT7736G/R/L/E) Pull High Threshold VTH_H 1.75 1.8 1.85 V Pull Low OTP Threshold VTH_OTP 0.47 0.5 0.53 V Pull Low Threshold VTH_L 0.25 0.3 0.35 V Copyright (c) 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 is a registered trademark of Richtek Technology Corporation. DS7736-04 September 2014 RT7736 Parameter Symbol Test Conditions Min Typ Max Unit -- 1.3 -- V Open Loop Voltage VPRO_OP Internal Bias Current IBIAS 90 100 110 A Pull High Sinking Current ISIN -- -- 500 A Delay Time of OTP by PRO T D_OTP -- 56 -- ms PRO pin open f OSC = 65kHz BNO Interface Section (RT7736B/D/F) Brown-In Threshold VBNI_TH 0.96 1 1.04 V Brown-Out Threshold VBNO_TH 0.81 0.85 0.89 V RT7736B -- 56 -- RT7736D -- 88 -- RT7736F -- 24 -- (Note 6) -- 140 -- De-bounce Time of VBNO_TH T D_BNO f OSC = 65kHz ms Over-Temperature Protection (OTP) Section Over-Temperature Protection T OTP On Chip OTP C Note 1. Stresses beyond those listed "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. JA is measured in natural convection (still air) at TA = 25C with the component mounted on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Leading edge blanking time and internal propagation delay time are guaranteed by design. Note 6. Guaranteed by design. Copyright (c) 2014 Richtek Technology Corporation. All rights reserved. DS7736-04 September 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT7736 Typical Application Circuit Vo+ + + AC Mains (90V to 265V) Vo- 3 2 PRO 5 VDD (Optional) GATE 6 COMP RT7736G/R/L/E CS 4 GND 1 Figure 3. Application Circuit For RT7736G, RT7736R, RT7736L and RT7736E Vo+ + + AC Mains (90V to 265V) Vo- 5 VDD (Optional) 3 BNO GATE 6 2 COMP RT7736B/D/F CS 4 GND 1 Figure 4. Application Circuit for RT7736B, RT7736D and RT7736F Copyright (c) 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 is a registered trademark of Richtek Technology Corporation. DS7736-04 September 2014 RT7736 Typical Operating Characteristics IDD_ST vs. VDD IDD_ST vs. Temperature 6 10 5 4 I DD_ST (A) I DD_ST (A) 8 3 2 6 4 1 0 2 0 3 6 VDD (V) 9 12 15 -50 -25 0 25 50 75 100 125 Temperature (C) VTH_ON vs. Temperature VTH_OFF vs. Temperature 10.0 16.0 15.5 15.0 VTH_OFF (V) VTH_ON (V) 9.5 14.5 14.0 9.0 8.5 13.5 8.0 13.0 -50 -25 0 25 50 75 100 -50 125 -25 0 Temperature (C) 25 50 75 100 125 100 125 Temperature (C) VDD_LH & VLH_OFF vs. Temperature VOVP vs. Temperature 28.00 5.8 5.6 27.50 5.4 VOVP (V) VDD_LH & VLH_OFF (V) 27.75 VDD_LH 5.2 27.00 26.75 26.50 VLH_OFF 5.0 27.25 26.25 26.00 4.8 -50 -25 0 25 50 75 100 Temperature (C) Copyright (c) 2014 Richtek Technology Corporation. All rights reserved. DS7736-04 September 2014 125 -50 -25 0 25 50 75 Temperature (C) is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT7736 fOSC vs. VDD fOSC vs. Temperature 67.0 68 66.5 66 65.5 f OSC (kHz) f OSC (kHz) 66.0 65.0 64.5 64 62 64.0 60 63.5 63.0 58 10 13 16 19 22 25 -50 -25 0 VDD (V) 25 50 75 100 125 100 125 100 125 Temperature (C) fBS_MIN vs. Temperature IDD_LH vs. Temperature 26 8 7 I DD_LH (A) f BS_MIN (kHz) 24 22 6 5 4 20 3 18 2 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (C) 50 75 Temperature (C) IDD_BNI vs. Temperature IDD_ARP vs. Temperature 200 425 180 400 I DD_ARP (A) I DD_BNI (A) 25 160 140 375 350 120 -50 -25 0 25 50 75 100 Temperature (C) Copyright (c) 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 125 325 -50 -25 0 25 50 75 Temperature (C) is a registered trademark of Richtek Technology Corporation. DS7736-04 September 2014 RT7736 IDD_OP2 vs. Temperature 850 800 800 I DD_OP2 (A) I DD_OP1 (A) IDD_OP1 vs. Temperature 850 750 750 700 700 650 650 -50 -25 0 25 50 75 100 -50 125 -25 0 Temperature (C) 75 100 125 100 125 IZERO vs. Temperature 310 5.3 300 I ZERO (A) VCOMP_OP (V) VCOMP_OP vs. Temperature 5.2 290 280 5.1 270 5 -50 -25 0 25 50 75 100 -50 125 -25 0 50 75 TOLP vs. Temperature TOLP vs. Temperature 62 25 Temperature (C) Temperature (C) 94 RT7736G/R/L/E/B RT7736D 92 TOLP (ms) 60 TOLP (ms) 50 Temperature (C) 5.4 58 56 90 88 86 84 54 -50 -25 0 25 50 75 100 Temperature (C) Copyright (c) 2014 Richtek Technology Corporation. All rights reserved. DS7736-04 25 September 2014 125 -50 -25 0 25 50 75 100 125 Temperature (C) is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT7736 TD_BNO vs. Temperature TOLP vs. Temperature 70 30 RT7736F 28 TD_BNO (ms) 68 TOLP (ms) RT7736F 66 64 26 24 22 62 20 60 -50 -25 0 25 50 75 100 -50 125 -25 0 Temperature (C) VCLAMP vs. Temperature 75 100 125 100 125 100 125 tR vs. Temperature 80 70 tR (ns) 14.5 VCLAMP (V) 50 Temperature (C) 15.5 13.5 12.5 60 50 40 11.5 30 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (C) 25 50 75 Temperature (C) tF vs. Temperature IBIAS vs. Temperature 60 106 50 102 40 I BIAS (A) tF (ns) 25 30 98 94 20 10 90 -50 -25 0 25 50 75 100 Temperature (C) Copyright (c) 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 125 -50 -25 0 25 50 75 Temperature (C) is a registered trademark of Richtek Technology Corporation. DS7736-04 September 2014 RT7736 VTH_OTP vs. Temperature 0.60 1.85 0.55 VTH_OTP (V) VTH_H (V) VTH_H vs. Temperature 1.90 1.80 1.75 0.50 0.45 1.70 0.40 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (C) VTH_L vs. Temperature 50 75 100 125 100 125 VBNI_TH vs. Temperature 0.40 1.10 0.35 1.05 VBNI_TH (V) VTH_L (V) 25 Temperature (C) 0.30 0.25 1.00 0.95 0.20 0.90 -50 -25 0 25 50 75 100 125 Temperature (C) -50 -25 0 25 50 75 Temperature (C) VBNO_TH vs. Temperature 0.95 VBNO_TH (V) 0.90 0.85 0.80 0.75 -50 -25 0 25 50 75 100 125 Temperature (C) Copyright (c) 2014 Richtek Technology Corporation. All rights reserved. DS7736-04 September 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 15 RT7736 Application Information SmartJitterTM Technology The RT7736 series applies RICHTEK proprietary SmartJitterTM technology. In order to reduce switching loss for lower power consumption during light load or no load, general PWM controllers have green mode function according to the feedback voltage VCOMP. The output power equation is : 2 x V Po_DCM (VCOMP ) = 1 Lp 1 COMP fs (VCOMP ) 2 RCS Where LP is the magnetizing inductance of the transformer, RCS is the current sense resistor, VCOMP is the feedback voltage of the COMP pin. fS is the switching frequency of the power switch, is the conversion efficiency, and x1 is a constant coefficient. Output power is a function of feedback voltage VCOMP. Frequency jittering technique is typically used to improve EMI problems in general PWM controllers, and the frequency jittering period is based on PWM switching frequency. Jittering Freq. General PWM Controller Normal Operating The innovative SmartJitterTM technology not only helps reduce EMI emissions of SMPS when the system entering green mode, but also eliminates output jittering ripple. Accurate Over-Load Protection and Tight Current Limit Tolerance Generally, the saw current limit is applied to low cost flyback controllers because of simple design. The RT7736 series applies with RICHTEK proprietary technology through well foundry control, design and test/trim mode in final test. Therefore, the current limit tolerance is tight enough to make design and mass production easier, and it provides accurate over-load protection. RT7736 Jittering Freq. Normal Operating fs mean = 64.85kHz Jittering Range = Jittering Freq. When the system enters green mode, a output power relationship is formed between the feedback voltage VCOMP and the PWM switching frequency, and a new stable equilibrium point is eventually reached after back-and-forth adjustments. It limits the frequency jittering range is limited and the improving EMI function is poor, as shown in Figure 5. fs mean = 64.61kHz Jittering Range = 6.3% General PWM Controller Green Mode 6.0% RT7736 Jittering Freq. Green Mode fs mean = 42.99kHz Jittering Range = 3.3% fs mean = 42.58kHz Jittering Range = 7.7% Figure 5. Frequency Jittering Range During Green Mode : General PWM Controller vs. RT7736 Copyright (c) 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 16 is a registered trademark of Richtek Technology Corporation. DS7736-04 September 2014 RT7736 Start-Up Circuit VDD Discharge Time in Auto Recovery Mode To minimize power loss, it's recommended to connect the start-up circuit to the bleeding resistors. It's power saving and also could reset latch mode protection quickly. Figure 6 shows IDD_Avg vs. RBleeding curve. Users can apply this curve to design the adequate bleeding resistors. Figure 7 shows the VDD and VGATE waveforms during an auto recovery protection (e.g., OLP). In this mode, the start-up resistors, VDD sinking current and VDD decoupling capacitor will affect the restart time. The discharge time tD_Discharge of VDD voltage can be calculated by using the following equation : In order to prolong turn-off period and minimize the power loss and thermal rising during hiccup, the controller is designed to have smaller sinking current during entering auto-recovery protection, IDD_ARP. Therefore, the start-up current at maximum AC line input voltage must be smaller than IDD_ARP (IDD_ARP(min) = 300A). Otherwise, when the controller enters auto-recovery protection, the VDD capacitor won't be dropped down to VTH_OFF by IC's sinking current and then restart. The controller behaves like latch protection or triggers the SCR of VDD. The RT7736 implemented brown-in detected function (RT7736B/D/F) as described in "BNO Pin Application" section. In order to avoid start-up failure, the controller is designed to have smaller sinking current after start-up and then wait for brown-in, IDD_BNI. Therefore, the start-up tD_Discharge CVDD (VDD_DIS VTH_OFF ) IDD_ARP IST Where the CVDD is the VDD decoupling capacitor, the VDD_DIS is the initial VDD voltage after entering the auto recovery mode, the VTH_OFF (9V typ.) is the falling UVLO voltage threshold of the controller, the IDD_ARP (300A typ.) is the sinking current of the VDD pin in the auto recovery mode, and IST is the start-up current of the power system. Please note that the start-up current at high input voltage must be smaller than the IDD_ARP. Otherwise, the VDD voltage can't reach the VTH_OFF to activate the next startup process after an auto recovery protection. Therefore, the system behavior resembles the behavior of latch mode. VDD VDD_DIS VTH_ON VTH_OFF current at brown-in voltage of AC line input must be smaller than IDD_BNI (IDD_BN (min) = 100A). Otherwise, the VDD voltage will rise up continuously and then trigger the SCR of VDD. t VGATE OLP Delay Time tD_Discharge t Figure 7. Auto Recovery Mode (e.g., OLP) IDD_Avg vs. RBleeding Curve IDD_Avg vs. RBleeding Curve 250 80 RBleeding 70 RBleeding 60 IDD_Avg I DD_Avg (A) I DD_Avg (A) 90 VDD 50 90Vac 85Vac 80Vac 40 30 225 RBleeding 200 RBleeding 175 VDD 150 125 265Vac 230Vac 100 20 IDD_Avg 75 10 50 0.6 1.0 1.4 1.8 2.2 2.6 3.0 0.6 1.0 1.4 1.8 2.2 2.6 3.0 RBleeding (M) RBleeding (M ) Figure 6. IDD_Avg vs. RBleeding Curve Copyright (c) 2014 Richtek Technology Corporation. All rights reserved. DS7736-04 September 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 17 RT7736 VDD Holdup Mode The VDD holdup mode is only designed to prevent VDD from decreasing to the turn-off threshold voltage under light load or load transient. Relative to burst mode, the VDD holdup mode brings higher switching. Hence, it is highly recommended that the system should avoid operating at this mode during light load or no load conditions, normally. BNO Pin Application (RT7736B/D/F) The RT7736 features a BNO pin (RT7736B/D/F), and it can be applied for external arbitrary brown-in/out. The BNO pin is connected to the AC line input or bulk capacitor by resistive divider to achieve brown-in/out function. Comparing the BNO pin connected to the AC line input with bulk capacitor, the advantage of the BNO pin connected to the AC line input is having brown-in/out function regardless of output loads. Figure 8 shows the application circuit of the BNO pin connected to AC line input with resistive divider. The resistive divider (RA and RB) can be calculated by the following equations : R VBrown-in_AC_rms 2 VBNI_TH 1 A RB R VBrown-out_AC_rms 2 VBNO_TH 1 A RB The sum of resistor values (RA and RB) should be smaller than 1.5M because parasitic capacitors of bridge of diode may make hysteresis of brown-in/out function invalid. The Brown-in/out detected from bulk capacitor is shown in Figure 9, and the resistive divider (RC and RD) can be calculated by the following equations : R VBulk_Brown-in VBNI_TH 1 C RD R VBulk_Brown-out VBNO_TH 1 C RD The BNO pin application from bulk capacitor can use higher resistance on the divider for power saving, but this method can't have brown-in/out function at light load because bulk capacitor still has energy stored when AC line input is turned off. The recommended bypass capacitor CBNO is smaller than 1nF. To avoid start-up failure, the RT7736 implements brownin detected function, as shown in Figure 10. When VDD is greater than VTH_ON, the controller starts to operate and waits for brown-in signal. If brown-in signal is not enabled before VDD falls below VDD_BNI, the controller will be shut down and then re-start. If the brown-in signal VBNO is higher than VBNI_TH, the controller will be enabled. AC Mains (90V to 265V) CBulk RC BNO RT7736 CBNO RD GND Figure 9. Brown-in/out Detected from Bulk Capacitor AC Mains (90V to 265V) RA BNO RB CBNO RT7736 GND Figure 8. Brown-in/out Detected from AC Line Input Copyright (c) 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 18 is a registered trademark of Richtek Technology Corporation. DS7736-04 September 2014 RT7736 VTH_ON VDD Brown-in VDD_BNI Detection VTH_OFF VBNO < VBNI_TH VBNO < VBNI_TH 1.6mA (typ.) Operating Current IDD_ARP IDD_BNI IDD_ST VAC VBNO > VBNI_TH Entering Auto Recovery Protection (Ex : OLP) IDD Brown-in (VBNO > VBNI_TH) GATE Figure 10. RT7736 Brown-in Detected Function PRO Pin Application (RT7736G/R/L/E) + The RT7736 provides a PRO pin for external arbitrary OVP/ OTP or IC ON/OFF applications as shown in Figure 12 to Figure 15. In Figure 11, when the voltage of the PRO pin is between VTH_OTP and VTH_H, the controller is enabled for normal operation. If the voltage of the PRO pin is lower than VTH_OTP and higher than VTH_L after delay time TD_OTP, the controller will be shut down and cease switching. If the voltage of the PRO pin is higher than VTH_H or lower than VTH_L, the controller will be shut down and cease switching after deglitch delay. When the voltage of the PRO pin is pulled above VTH_H, the supply current of the PRO pin must be higher than 500A and be limited below 5mA. When IC enters latch mode, VDD will be clamped at latched voltage VDD_LH, and it will be released until VDD falls to latched reset voltage VLH_OFF. When the PRO pin is open, it is set at 1.3V internally. Leave the PRO pin open if it is not used. If designer needs to apply a bypass capacitor on the PRO pin, the capacitance should be less than 1nF. The internal bias current of the PRO pin is 100A (typ.). Copyright (c) 2014 Richtek Technology Corporation. All rights reserved. DS7736-04 September 2014 VTH_H - VTH_OTP + PRO - VTH_L + Deglitch Auto Recovery Latch 56ms Delay Time Deglitch Auto Recovery Latch Auto Recovery - Latch VPRO Auto Recovery/Latch VTH_H Normal Operating VTH_OTP Auto Recovery/Latch VTH_L Auto Recovery/Latch Figure 11. PRO Pin Diagram is a registered trademark of Richtek Technology Corporation. www.richtek.com 19 RT7736 Because it is hard to distinguish the difference between output short and big capacitance load, circuit design must be careful to make sure GATE width is larger than TON_OSP (tON > tON_OSP(MAX)) after delay time TD_OSP during startup. PRO (Option) NTC Resistors on GATE Pin In Figure 16, RG is applied to alleviate ringing spike of gate drive loop in typical application circuits. The value of RG must be considered carefully with respect to EMI and efficiency for the system. Figure 12. External OTP VDD The built-in internal discharge resistor RID in parallel with GATE pin prevents the MOSFET from any uncertain conditions. If the connection between the GATE pin and the Gate of the MOSFET is disconnected, the MOSFET will be false triggered by the residual energy through the Gate-to-Drain parasitic capacitor CGD of the MOSFET and the system will be damaged. Therefore, it's highly recommended to add an external discharge-resistor RED connected between the Gate of MOSFET and GND terminals. The energy through the CGD is discharged by the external discharge-resistor to avoid MOSFET false triggering. PRO (Option) Figure 13. OVP for VDD VDD PRO (Option) AC Mains (90V to 265V) Figure 14. OVP for VDD PRO Vo+ The built-in internal discharge-resistor prevents the MOSFET from any uncertain conditions. CGD RT7736 (Option) (Option) Soft Driver GATE RG RID Figure 15. OVP for Output Voltage RED CS GND Output Short Protection (RT7736G/R/L/E/B) The RT7736 implements output short protection (RT7736G/ R/L/E/B) by detecting GATE width with delay time TD_OSP. It can minimize the power loss during output short, especially at high line input voltage. Copyright (c) 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 20 It is recommend to add the external dischargeresistor to avoid MOSFET false triggering. Figure 16. Resistors on Gate Pin is a registered trademark of Richtek Technology Corporation. DS7736-04 September 2014 RT7736 Feedback Resistor In order to enhance light load efficiency, the loss of the feedback resistor in parallel with photo-coupler is reduced, as shown in Figure 17. Due to small feedback resistor current, shunt regulator selection (e.g. TL-431) and minimum regulation current design must be considered carefully to make sure it's able to regulate under low cathode current. AC Mains (90V to 265V) PRO VDD GATE RT7736 COMP Vo+ CS GND + + R-C Filter Vo- Figure 18. R-C Filter on CS Pin Over-Temperature Protection (OTP) Feedback Resistor Figure 17. Feedback Resistor The RT7736 provides an internal OTP function to protect the controller itself from suffering thermal stress and permanent damage. It's not suggested to use the function as precise control of over temperature. Once the junction temperature is higher than the OTP threshold, the controller will shut down until the temperature cools down. Meanwhile, if VDD reaches turn-off threshold voltage VTH_OFF, the controller will hiccup till the over-temperature condition is removed. Negative Voltage Spike on Each Pin Thermal Considerations Negative voltage (< -0.3V) to the controller pins will cause substrate injection and lead to controller damage or circuit false triggering. For example, the negative spike voltage at the CS pin may come from improper PCB layout or inductive current sense resistor. Therefore, it is highly recommended to add an R-C filter to avoid the CS pin damage, as shown in Figure 18. Proper PCB layout and component selection should be considered during circuit design. For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) - TA) / JA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and JA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125C. The junction to ambient thermal resistance, JA, is layout dependent. For Copyright (c) 2014 Richtek Technology Corporation. All rights reserved. DS7736-04 September 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 21 RT7736 SOT-23-6 package, the thermal resistance, JA, is 260.7C/W on a standard JEDEC 51-3 single-layer thermal test board. The maximum power dissipation at TA = 25C can be calculated by the following formula : PD(MAX) = (125C - 25C) / (260.7C/W) = 0.38W for SOT-23-6 package Layout Consideration A proper PCB layout can abate unknown noise interference and EMI issue in the switching power supply. Please refer to the guidelines when you want to design PCB layout for switching power supply : The current path (1) through bulk capacitor, transformer, MOSFET, R CS returns to bulk capacitor is a high frequency current loop. It must be as short as possible to decrease noise coupling and keep away from other low voltage traces, such as IC control circuit paths, especially. The path (2) of the RCD snubber circuit is also a high switching loop. Keep it as small as possible. Separate the ground traces of bulk capacitor(a), MOSFET(b), auxiliary winding(c) and IC control circuit(d) for reducing noise, output ripple and EMI issue. Connect these ground traces together at bulk capacitor ground (a). The areas of these ground traces should be large enough. Place the bypass capacitor as close to the controller as possible. In order to reduce reflected trace inductance and EMI, minimize the area of the loop connecting the secondary winding, output diode and output filter capacitor. In additional, apply sufficient copper area at the anode and cathode terminal of the diode for heatsinking. The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, JA. The derating curve in Figure 19 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. Maximum Power Dissipation (W)1 0.5 Single-Layer PCB 0.4 0.3 0.2 0.1 0.0 0 25 50 75 100 125 Ambient Temperature (C) Figure 19. Derating Curve of Maximum Power Dissipation CBULK AC Mains (90V to 265V) (2) (a) PRO VDD CBULK Ground (a) (c) GATE RT7736 COMP CS (1) Trace IC Ground (d) Trace Auxiliary Ground (c) Trace MOSFET Ground (b) GND (d) (b) Figure 20. PCB Layout Guide Copyright (c) 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 22 is a registered trademark of Richtek Technology Corporation. DS7736-04 September 2014 RT7736 Outline Dimension H D L C B b A A1 e Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.889 1.295 0.031 0.051 A1 0.000 0.152 0.000 0.006 B 1.397 1.803 0.055 0.071 b 0.250 0.560 0.010 0.022 C 2.591 2.997 0.102 0.118 D 2.692 3.099 0.106 0.122 e 0.838 1.041 0.033 0.041 H 0.080 0.254 0.003 0.010 L 0.300 0.610 0.012 0.024 SOT-23-6 Surface Mount Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. DS7736-04 September 2014 www.richtek.com 23