FUJITSU SEMICONDUCTOR DATA SHEET DS04-27270-2E ASSP for Power Management Applications (General-Purpose DC/DC Converter) 2ch DC/DC converter IC with synchronous rectification MB39A138 DESCRIPTION MB39A138 is a 2ch step-down DC/DC converter equipped with a bottom detection comparator and N-ch/ N-ch synchronous rectification. It supports low on-duty operation to allow stable output of low voltages when there is a large difference between input and output voltages. MB39A138 realizes ultra-rapid response and high efficiency with built-in enhanced protection features. FEATURES * * * * High efficiency High accurate reference voltage Input voltage range Output voltage setting range * * * * * * * * * * Built-in diode for boot strap Built-in over voltage protection function Built-in under voltage protection function Built-in over current detection function Built-in over temperature protection function Built-in soft-start circuit without load dependence Built-in discharge control circuit Built-in synchronous rectification type output steps for N-ch MOS FET Standby current : 0 A (Typ) Small package : TSSOP-24 : 1.0% (indoor temperature ) : 6 V to 24 V : CH1 0.7 V to 5.2 V : CH2 2.0 V to 5.2 V APPLICATIONS * * * * * Digital TV Photocopiers STB BD, DVD players/recorders Projectors Various other advanced devices Copyright(c)2009-2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2011.3 MB39A138 PIN ASSIGNMENT (TOP VIEW) CTL1 1 24 CB1 CS1 2 23 DRVH1 FB1 3 22 LX1 VO1 4 21 DRVL1 ILIM1 5 20 VCC GND 6 19 VB CVBLPF 7 18 PGND CTL2 8 17 DRVL2 ILIM2 9 16 LX2 VO2 10 15 DRVH2 FB2 11 14 CB2 CS2 12 13 TEST (FPT-24P-M10) 2 DS04-27270-2E MB39A138 PIN DESCRIPTIONS Pin No. Pin Name I/O 1 CTL1 I CH1 control pin. 2 CS1 I CH1 start time setting capacitor connection pin. 3 FB1 I CH1 feedback pin for DC/DC output voltage. 4 VO1 I CH1 input pin for DC/DC output voltage. 5 ILIM1 I CH1 over current detection level setting voltage input pin. 6 GND 7 CVBLPF I Control circuit bias input pin. 8 CTL2 I CH2 control pin. 9 ILIM2 I CH2 over current detection level setting voltage input pin. 10 VO2 I CH2 input pin for DC/DC output voltage. 11 FB2 I CH2 feedback pin for DC/DC output voltage. 12 CS2 I CH2 soft-start time setting capacitor connection pin. 13 TEST I Pin for IC test. Connect to GND in the DC/DC operation. 14 CB2 CH2 connection pin for boot strap capacitor. 15 DRVH2 O CH2 output pin for external high-side FET drive. 16 LX2 CH2 inductor and external high-side FET source connection pin. 17 DRVL2 O CH2 output pin for external low-side FET gate drive. 18 PGND Ground pin for output circuit. 19 VB O Output circuit bias output pin. 20 VCC I Power supply pin for reference voltage and control circuit. 21 DRVL1 O CH1 output pin for external low-side FET gate drive. 22 LX1 CH1 inductor and external high-side FET source connection pin. 23 DRVH1 O CH1 output pin for external high-side FET gate drive. 24 CB1 CH1 connection pin for boot strap capacitor. DS04-27270-2E Description Ground pin. 3 MB39A138 BLOCK DIAGRAM CTL1 CTL2 VCC 1 8 20 VO1 <CH1> 4 /CTL1 UVP,OTP 5 A FB1 3 VO Control <Error Comp.> - + + R S ILIM1 VB 19 (5.2 V) 5.2 V Reg. REF tON Generator 24 Drv-1 Q INTREF1 CS1 CTL VO1 VCC Drive Logic 22 <ILIM Comp.> LX1 - PGND + /CTL1,/UVLO UVP,OTP - 10 A + 2 Drv-2 INTREF1 x 1.15 V <UVP Comp.> - uvp_q1 + 18 R 50 s delay UVLO R 1.7 ms delay S Q 10 <CH2> 7 PGND CVBLPF H:UVLO release OTP uvp_q2 ovp_q2 bias 14 11 15 16 CB2 DRVH2 LX2 12 17 ILIM2 DRVL1 Q S The configuration of a control circuit is the same as that of CH1. CS2 LX1 bias INTREF1 x 0.7 V FB2 21 DRVH1 5 <OVP Comp.> + ovp_q1 - VO2 23 CB1 DRVL2 9 6 GND 4 DS04-27270-2E MB39A138 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Power supply voltage VVCC CB pin input voltage VCB LX pin input voltage VLX Voltage between CB and LX Control input voltage Unit Min Max 26 V CB1, CB2 pins 32 V LX1, LX2 pins 26 V 7 V CTL1, CTL2 pins 26 V CVBLPF pin VB + 0.3 V VFB FB1, FB2 pins VB + 0.3 V VVO VO1, VO2 pins VB + 0.3 V VCS CS1, CS2 pins VB + 0.3 V VILIM ILIM1, ILIM2 pins VB + 0.3 V VTEST TEST pin VB + 0.3 V VCBLX VI VCVBLPF Input voltage Rating Output current IOUT DRVH1, DRVH2 pins, DRVL1, DRVL2 pins 60 mA Power dissipation PD Ta + 25 C 1333 mW - 55 + 125 C Storage temperature TSTG WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. DS04-27270-2E 5 MB39A138 RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Power supply voltage VVCC CB pin input voltage Value Unit Min Typ Max 6 24 V VCB 30 V Bias output current IVB -1 mA CTL pin input voltage VI CTL1, CTL2 pins 0 24 V CVBLPF pin 0 VB V VFB FB1, FB2 pins 0 VB V VVO VO1, VO2 pins 0 VB V VILIM ILIM1, ILIM2 pins 30 200 mV Peak output current IOUT DRVH1, DRVH2 pins, DRVL1, DRVL2 pins Duty 5% (t = 1/fOSC x Duty) - 1200 + 1200 mA Soft start capacitor CCS 0.018 F CB pin capacitor CCB 0.1 1.0 F Bias voltage output capacitor CVB 2.2 10.0 F Bias voltage input capacitor CCVBLPF 1.0 4.7 F Operating ambient temperature Ta - 30 + 25 + 85 C VCVBLPF Input voltage WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 6 DS04-27270-2E MB39A138 ELECTRICAL CHARACTERISTICS (Ta = + 25 C, VCC pin = 12 V, CTL1, CTL2 pins = 5 V = CVBLPF pin : VB pin connected) Parameter ON/OFF Time Generator Block [tON Generator] Min Typ Max Unit 19 5.04 5.20 5.36 V VCC pin = 6 V to 24 V 10 100 mV LOAD 19 VB pin = 0 A to -1 mA 10 100 mV IOS 19 VB pin = 0 V - 200 - 140 - 100 mA VTLH 7 CVBLPF pin 4.0 4.2 4.4 V VTHL 7 CVBLPF pin 3.4 3.6 3.8 V Hysteresis width VH 7 CVBLPF pin 0.6* V Charge current ICS 2, 12 CS1, CS2 pins = 0 V - 7.1 - 5.0 - 3.8 A Electrical discharge resistance RD 4, 10 CTL1, CTL2 pins = 0 V, VO1, VO2 pins = 0.5 V 35 70 VVOVTH 4, 10 CTL1, CTL2 pins = 0 V, VO1, VO2 pins 0.1 0.2 0.3 V tON11 23 VCC pin = 12 V, VO1 pin = 1.2 V 256 320 384 ns tON12 15 VCC pin = 12 V, VO2 pin = 3.3 V 470 587 704 ns Minimum ON time tONMIN 23, 15 100 ns Minimum OFF time tOFFMIN 23, 15 380 ns VTH1 3 Ta = + 25 C 0.693 0.700 0.707 V VTHT1 3 Ta = 0 C to + 85 C 0.690* 0.710* V VTH2 11 Ta = + 25 C 1.980 2.000 2.020 V VTHT2 11 Ta = 0 C to +85 C 1.970* 2.030* V VTH3 4 Ta = + 25 C 1.202 1.226 1.250 V VTHT3 4 Ta = 0 C to + 85 C 1.196 1.256 V VTH4 10 Ta = + 25 C 3.381 3.450 3.519 V VTHT4 10 Ta = 0 C to + 85 C 3.364 3.536 V IFB 3, 11 FB1, FB2 pins = 0.8 V - 0.1 0 + 0.1 A IVO1 4 VO1 pin = 1.226 V 80 115 A IVO2 10 VO2 pin = 3.450 V 225 325 A Threshold voltage Discharge end voltage ON time Feedback voltage (CH2) Bottom detection voltage (CH1) Bottom detection voltage (CH2) FB pin input current VO pin input current Over-voltage Protection Circuit Block [OVP Comp.] Value 19 Feedback voltage (CH1) Output Voltage Block [VO Control, Error Comp.] Condition VVB Bias Voltage Input stability Block Load stability [VB Reg.] Short-circuit output current Soft-Start/ Discharge Block [Soft-Start, Discharge] Pin No. LINE Output voltage Under voltage Lockout Protection Circuit Block [UVLO] Symbol VCC pin = 12 V, VO1, VO2 pins = 0 V Over-voltage detecting voltage VOVP 3, 11 Error Comp. input (4, 10) Over-voltage detection time tOVP 3, 11 (4, 10) INTREF INTREF INTREF x 1.11 x 1.15 x 1.19 50 V s (Continued) DS04-27270-2E 7 MB39A138 (Ta = + 25 C, VCC pin = 12 V, CTL1, CTL2 pins = 5 V = CVBLPF pin : VB pin connected) Value SymParameter Pin No. Condition Unit bol Min Typ Max Under-volt- Under-volt3, 11 INTREF INTREF INTREF V age Protec- age detect- VUVP (4, 10) Error Comp. input x 0.65 x 0.70 x 0.75 tion Circuit ing voltage Block Under-volt3, 11 [UVP age detectUVP 1.2* 1.7* 2.2* ms (4, 10) Comp.] tion time Over-temTOTPH + 150* C perature Protection Protection temperaCircuit TOTPL + 125* C ture Block [OTP] DRVH1, DRVH2 pins = ROH 23, 15 5 7 High-side -100 mA output onDRVH1, DRVH2 pins = resistance ROL 23, 15 1.5 2.5 100 mA DRVL1, DRVL2 pins = ROH 21, 17 4 6 Low-side -100 mA output onDRVL1, DRVL2 pins = resistance ROL 21, 17 1 2 100 mA LX1, LX2 pins = 0 V, CB1, CB2 pins = VB 23, 15 - 0.4* A DRVH1, DRVH2 pins = 2.5 V Output Duty 5% source ISOURCE LX1, LX2 pins = 0 V, current CB1, CB2 pins = VB 21, 17 - 0.5* A DRVL1, DRVL2 pins = 2.5 V Duty 5% LX1, LX2 pins = 0 V, Output CB1, CB2 pins = VB 23, 15 0.7* A Block DRVH1, DRVH2 pins = 2.5 V Output [DRV] Duty 5% sink ISINK LX1, LX2 pins = 0 V, current CB1, CB2 pins = VB 21, 17 0.9* A DRVL1, DRVL2 pins = 2.5 V Duty 5% LX1, LX2 pins = 0 V, CB1, CB2 pins = VB pin 40 ns DRVL1, DRVL2 pins-low to 23, 21 DRVH1, DRVH2 pins-on Dead time tD 15, 17 LX1, LX2 pins = 0 V, CB1, CB2 pins = VB pin 80 ns DRVH1, DRVH2 pins-low to DRVL1, DRVL2 pins-on Diode VF 24, 14 IF = 10 mA 0.7 0.8 0.9 V voltage CB1, CB2 pins = 30 V, Leak ILEAK 24, 14 LX1, LX2 pins = 24 V 0.1 1 A current Ta = + 25 C (Continued) 8 DS04-27270-2E MB39A138 (Continued) (Ta = + 25 C, VCC pin = 12 V, CTL1, CTL2 pins = 5 V = CVBLPF pin : VB pin connected) Symbol Pin No. Condition ILIM pin source current IILIM 5, 9 ILIM pin source current temperature slope TILIM Over current detection offset voltage Parameter Over Current Detection Block [Current Sense] Control Block [CTL1, CTL2] Unit Min Typ Max ILIM1, ILIM2 pins = 0.1 V, Ta = + 25 C - 12.5 - 10.0 - 8.3 A 5, 9 Ta = + 25 C (reference) 4200* ppm / C VOFFILIM 5, 9 ILIMx - (PGND - LXx) PGND - LXx = 60 mV - 20 0 + 20 mV Over current detection setting range VILIM 5, 9 ILIM pin input range 30 200 mV ON condition VON 1, 8 CTL1, CTL2 pins 2 24 V OFF condition VOFF 1, 8 CTL1, CTL2 pins 0 0.8 V VH 1, 8 CTL1, CTL2 pins 0.4* V ICTLH 1, 8 CTL1, CTL2 pins = 5 V 25 40 A ICTLL 1, 8 CTL1, CTL2 pins = 0 V 0 1 A Standby current ICCS 20 CTL1, CTL2 pins = 0 V 0 10 A Power supply current ICC 20 LX1, LX2 pins = 0 V, FB1, FB2 pins = 1.0 V 1.5 2.0 mA Hysteresis width Input current General Value * : This parameter is not be specified. This should be used as a reference to support designing the circuits. DS04-27270-2E 9 MB39A138 TYPICAL CHARACTERISTICS Power dissipation vs. Operating ambient temperature Power dissipation PD (mW) 2000 1500 1333 1000 500 0 -50 -25 0 +25 +50 +75 +100 +125 Operating ambient temperature Ta ( C) VB bias voltage vs. Operating ambient temperature VB bias voltage vs. VB bias output current 5.40 5.4 Ta = +25 C 5.28 5.24 5.20 5.16 5.08 5.04 5.00 -40 Error Comp.1 Threshold voltage VTHT1 (V) VCC = 12 V IVB = 0 A 5.12 VB bias voltage VVB (V) 5.32 5.3 5.2 VCC = 12 V 5.1 VCC = 6 V VCC = 24 V 5.0 -20 0 +20 +40 +60 0 +80 +100 5 10 15 20 25 30 Operating ambient temperature Ta ( C) VB bias output current (mA) Error Comp.1 Threshold voltage vs. Operating ambient temperature Error Comp.2 Threshold voltage vs. Operating ambient temperature 0.710 Error Comp.2 Threshold voltage VTHT2 (V) VB bias voltage VVB (V ) 5.36 0.708 0.706 0.704 0.702 0.700 0.698 0.696 0.694 0.692 0.690 -40 -20 0 +20 +40 +60 +80 +100 Operating ambient temperature Ta ( C) 2.03 2.02 2.01 2.00 1.99 1.98 1.97 -40 -20 0 +20 +40 +60 +80 +100 Operating ambient temperature Ta ( C) (Continued) 10 DS04-27270-2E MB39A138 (Continued) DRVH2 on time vs. Operating ambient temperature 400 740 380 700 360 340 320 300 VCC = 12 V VO1 = 1.2 V 280 260 -40 -20 0 DRVH2 on time tON12 (ns) DRVH1 on time tON11 (ns) DRVH1 on time vs. Operating ambient temperature 580 540 VCC = 12 V VO2 = 3.3 V 500 -20 0 +20 +40 +60 +80 +100 Operating ambient temperature Ta ( C) Operating ambient temperature Ta ( C) Minimum off time vs. Operating ambient temperature Minimum off time vs. Input voltage 600 VCC = 12 V 550 500 450 400 350 300 250 200 -40 -20 0 +20 +40 +60 Minimum off time tOFFMIN (ns) Minimum off time tOFFMIN (ns) 620 460 -40 +20 +40 +60 +80 +100 600 Ta = +25 C 550 500 450 400 350 300 250 200 +80 +100 5 10 15 20 Operating ambient temperature Ta ( C) Input voltage VIN (V) Dead time vs. Operating ambient temperature Bootstrup diode IF vs. VF 25 30 120 25 t D2 80 LX = 0 V VCB = VB 60 tD 1 40 IF current IF (mA) 100 Dead time (ns) 660 Ta = -30 C 20 Ta = +25 C 15 Ta = +85 C 10 5 20 -40 -20 0 +20 +40 +60 +80 +100 Operating ambient temperature Ta ( C) DS04-27270-2E 0 0.2 0.4 0.6 0.8 1 1.2 VF voltage VF (V) 11 MB39A138 FUNCTION 1. Bottom detection comparator system The bottom detection comparator system uses fixed ON time (tON) and the switching ripple voltage which superimposed the output voltage (VOUT). The tON time is uniquely defined by the power supply voltage (VIN) and the output voltage (VOUT). During the tON period, a current is supplied from the power supply voltage (VIN). This results in an increased inductor current (ILX) and also an increased output voltage (VOUT) due to the parasitic resistance (ESR) of the output capacitor. And when the tOFF period arrives, the energy accumulated in the inductor is supplied to the load to decrease the inductor current (ILX) gradually. Consequently, the output voltage (VOUT), which has been increasing due to the parasitic resistance (ESR) of the output capacitor, also decreases. When the output voltage is below a certain level, RS-FF is set and the tON period arrives again. Switching is repeated as described above. Error Comp. is used to compare the reference voltage (INTREF) with the output period voltage VFB to control the off-duty condition in order to stabilize the output voltage. VOUT VIN Bias Reg. VIN tON generator FB <Error Comp.> - Err out + Hi-side Drive DRVH RS-FF R Q RS out ILX Drive Logic S VOUT Bias Lo-side Drive DRVL ESR INTREF ILX FB INTREF toff RS out ton DRVH 12 DS04-27270-2E MB39A138 (1) Bias Voltage Block (VB Reg.) It outputs 5.2 V (Typ) for setting of the output circuit's power supply and the bootstrap voltage. The bias power supply is supplied from the CVBLPF pin (pin 7) to the control circuit, which is smoothed with the RC filter of the resistor and the capacitor connected outside of the IC. (2) Under Voltage Lockout Protection Circuit Block (UVLO) A bias voltage (VCVBLPF) of the control IC, a transitional state at startup, or a sudden drop leads to malfunction of the control IC, causing system destruction/deterioration. To prevent such malfunction, the under voltage lockout protection circuit detects a voltage drop at the CVBLPF pin (pin 7) and fixes DRVH1 pin (pin 23), DRVH2 pin (pin 15) and DRVL1 pin (pin 21), DRVL2 pin (pin 17) to the "L" level. When voltages at the CVBLPF pin exceed the threshold voltage of the under voltage lockout protection circuit, the system is restored. (3) Soft-start/Discharge Block (Soft-Start, Discharge) The soft-start block is the circuit to prevent a rush current when turning power on. When the CTL1 pin (pin 1) and CTL2 pin (pin 8) are set to the "H" level, the capacitor connected to the CS1 pin (pin 2) and, CS2 pin (pin 12) starts charging and its lamp voltage is input to the error comparator (Error Comp.) of each channel. This allows for the setting of the soft-start time that does not depend on the output load of the DC/DC converter. The discharge block is the circuit to discharge electrical charges stored in an output capacitor at output stop. When setting the CTL1 pin (pin 1) and the CTL2 pin (pin 8) "L" level, FET for discharge (RON = 35 (Typ)) which is connected between the VO1 pin (pin 4), VO2 pin (pin 10), and GNDs will turn on and discharge the output capacitors. When VO1 pin voltage and VO2 pin voltage go down below 0.2 V (Typ) after discharging starts, FET for discharge is turned off and the discharge operation stops. Also, the discharge block works when detecting low voltage at the under-voltage protection circuit block (UVP Comp.) and detecting IC junction temperature increase at the over-temperature protection circuit block (OTP). (4) ON/OFF Time Generator Block (tON Generator) The ON/OFF time generator block (tON generator) contains a capacitor for timing setting and a resistor for timing setting and generates ON time which depends on input voltage and output voltage. ON time for each CH is obtained by the following formula. tON11 (ns) = VVO1 VVCC x 3200 (fOSC1 310 kHz) tON12 (ns) = VVO2 VVCC x 2133 (fOSC2 465 kHz) The oscillation frequency of CH2 is set to 1.5 times that of CH1 to prevent the beat by the frequency difference among channels. DS04-27270-2E 13 MB39A138 (5) Output Voltage Setting Block (VO Control, Error Comp.) The output voltage setting block (VO Control, Error Comp.) detects the bottom value of ripple voltage that superimposed output voltage for DC/DC converter at the error comparator. The optional output voltage can be set by connecting the external output voltage setting resistor to the FB1 pin (pin 3) and the FB2 pin (pin 11). Also, the output setting resistor of the built-in IC can be used by connecting the FB1 pin and the FB2 pin to the CVBLPF pin (pin 7). < VO Control >. VO1 VO2 4 10 SW2 FB1 FB2 3 11 + Comp.1 SW1 - - 2.5 V Error Comp. + INTREF Output Voltage Setting Table Connection state of FB1 and FB2 pins SW state Remarks Connected to an external resistor SW1 : ON SW2 : OFF The DC/DC output voltage can be set freely by the external resistor Connected to CVBLPF pin (pin 7) SW1 : OFF SW2 : ON The external resistor for output voltage setting is unnecessary because DC/DC output voltage setting resistor embedded in the IC is used. Set VO1 = 1.23 V, VO2 = 3.45 V. (6) Over-voltage Protection Circuit Block (OVP Comp.) It compares 1.15 times (Typ) of the internal reference voltage INTREF (CH1/CH2: 0.7V/2.0V) with the feedback voltage that is input to the FB1 pin (pin 3) and the FB2 pin (pin 11). The RS latch is set and the DRVH1 pin (pin 23) and the DRVH2 pin (pin 15) set to "L" level and the DRVL1 pin (pin 21) and the DRVL2 pin (pin 17) set to "H" level, when the feedback voltage detects a higher state at 50 s (Typ) or more. The voltage output stops to fixes the high-side FET to the off-state and the low-side FET to the on-state, of both channels in the DC/DC converter. The over-voltage protection state can be cancelled by setting the IC to standby state first and then resetting the latch using the UVLO signal. (7) Under-voltage Protection Circuit Block (UVP Comp.) It compares 0.7 times (Typ) of the internal reference voltage INTREF (CH1/CH2: 0.7V/2.0V) with the feedback voltage that is input to the FB1 pin (pin 3) and the FB2 pin (pin 11). The RS latch is set and the DRVH1 pin (pin 23) and the DRVH2 pin (pin 15) go to "L" level and the DRVL1 pin (pin 21) and the DRVL2 pin (pin 17) go to "L" level, when the feedback voltage detects a lower state at 1.7 ms (Typ) or more. The discharge function internal in the IC operates and the voltage output of both channels stops, in synchronization with setting the latch of under voltage protection. The under-voltage protection state can be cancelled by setting the IC to standby state first and then resetting the latch using the UVLO signal. 14 DS04-27270-2E MB39A138 (8) Over-temperature Protection Circuit Block (OTP) If the junction temperature reaches +150 C, the over-temperature protection circuit block makes the discharge function internal in the IC operate and makes voltage output of both channels stop. The soft start activates again when the junction temperature goes down to +125 C. (9) Output Block (DRV1, DRV2) The output circuit is configured in CMOS type for both of the high-side and the low-side, allowing the external N-ch MOS FET to drive. (10) Over Current Detection Block (ILIM) The over current detection block (ILIM) compares the difference voltage between the PGND pin (pin 18) and the LX1 pin (pin 22) during the synchronous rectification period with the ILIM1 pin (pin 5) voltage, and compares the difference voltage between the PGND pin and the LX2 pin (pin 16) with the ILIM2 pin (pin 9) voltage, and detects over current at each cycle. The high-side FET remains the off state until the voltage difference between the PGND pin and the LXx pin becomes below the ILIMx pin voltage and ON in the high-side FET is allowed after the voltage difference has been below the ILIMx pin voltage. This protects a circuit from flowing over current. This protection operates to drop the output voltage. The difference voltage between PGND and LXx caused during the synchronous rectification period is described as the voltage waveform by sensing the inductor current, as the ON-resistance of the low-side FET is regarded as the sense resistor. The optional limit value for over current can be set by setting a resistor to the ILIMx pin because IILIM current which is 10 A (Typ) is supplied from the ILIMx pin. As for IILIM current, the temperature slope which is 4200 ppm/ C is set to compensate the temperature dependence characteristics of the low-side FET on-resistance. Note: x is each channel number. (11) Control Block (CTL) On and off for CH1 is set by the CTL1 pin (pin 1) and on and off for CH2 is set by the CTL2 pin (pin 8). If setting CTL1 and CTL2 to "L" level at the same time, this IC turns to the standby state. (The maximum powersupply current at standby is 10 A.) Control Function Table CTL1 CTL2 DC/DC converter (CH1) DC/DC converter (CH2) L L OFF OFF H L ON OFF L H OFF ON H H ON ON DS04-27270-2E 15 MB39A138 PROTECTION FUNCTION TABLE The following table shows the state of DRVH1, DRVH2 pins (pin 23, pin 15) and DRVL1, DRVL2 pins (pin 21, pin 17) when each protection function operates. Output of each pin DC/DC output after detection Protection function Detection condition dropping operation VB DRVHx DRVLx Under Voltage Lockout Protection (UVLO) VCVBLPF < 3.6 V Under Voltage Protection (UVP) L L Electrical discharge by discharge function VFBx < INTREFx x 0.7 V 5.2 V L L Electrical discharge by discharge function Over Voltage Protection (OVP) VFBx > INTREFx x 1.15 V 5.2 V L H 0 V clamping Over Current Protection (ILIM) VPGNDx - VLXx > VILIMx 5.2 V Over Temperature Protection (OTP) Tj > + 150 C 5.2 V L L Electrical discharge by discharge function CONTROL (CTL) CTLx : H L (VOx > 0.2 V) 5.2 V L L Electrical discharge by discharge function switching switching The voltage is dropped by the constant current Note: x is each channel number. 16 DS04-27270-2E MB39A138 I/O PIN EQUIVALENT CIRCUIT DIAGRAM CTL1, CTL2 pins CS1, CS2 pins VCC 20 CVBLPF CTL1, CTL2 1,8 0.1 V ESD protection element CS1, CS2 2,12 + - GND GND 6 FB1, FB2 pins VO1, VO2 pins CVBLPF VO1, VO2 FB1, FB2 4,10 + 3,11 - 2.5 V GND GND ILIM1, ILIM2 pins CVBLPF pin CVBLPF 7 CVBLPF ILIM1, ILIM2 5,9 GND GND (Continued) DS04-27270-2E 17 MB39A138 (Continued) TEST pin DRVH1, DRVH2, CB1, CB2 and LX1, LX2 pins CVBLPF VB 24,14 CB1, CB2 23,15 DRVH1, DRVH2 22,16 LX1, LX2 TEST 13 GND PGND DRVL1, DRVL2 pins VB pin VCC VB 21,17 19 VB DRVL1, DRVL2 CB1, CB2 18 PGND 18 PGND DS04-27270-2E MB39A138 EXAMPLE APPLICATION CIRCUIT VB VCC 12 V CVBLPF C9 7 VIN C7 R7 VCC 20 PGND VB 13 TEST VB 19 VB C8 VCC FB1 R2 3 C1-2 D1 D2 7 8 G 2 Q1 S 1 C1-1 CRVH1 23 C5 R1-1 CB1 24 R1-2 4 VO1 1.2 V, 5 A L1 VO1 LX1 22 R5 DRVL1 21 CS1 MB39A138 C12 2 D1 D2 5 6 G 4 Q1 S 3 C2-3 CTL1 5 ILIM1 C2-1 1 CTL1 VCC FB2 R4 11 DRVH2 15 C3-1 D1 D2 7 8 G 2 Q3 S 1 C6 3.3 V, 5 A L2 VO2 8 CTL2 CTL2 ILIM2 DRVL2 17 R6 9 CS2 C13 12 D1 D2 5 6 G 4 Q3 S 3 C4-3 LX2 16 C4-1 R3-2 CB2 14 C3-2 VO2 R3-1 10 6 DS04-27270-2E GND PGND 18 19 MB39A138 PARTS LIST Component Item Q1 N-ch FET Q3 N-ch FET L1 L2 Specification VDS = 30 V, ID = 8 A, Ron = 21 m VDS = 30 V, ID = 8 A, Ron = 21 m 1.5 H (6.8 m, 9.0 A) 2.2 H (10.2 m, 7.4 A) Inductor Inductor Ceramic C1-1 10 F (25 V) capacitor Ceramic C1-2 10 F (25 V) capacitor C2-1 OS-CON 220 F (6.3 V, 15 m Max) Ceramic C2-3 1000 pF (50 V) capacitor Ceramic C3-1 10 F (25 V) capacitor Ceramic C3-2 10 F (25 V) capacitor C4-1 OS-CON 220 F (6.3 V, 15 m Max) Ceramic C4-3 1000 pF (50 V) capacitor Ceramic C5 0.1 F (50 V) capacitor Ceramic 0.1 F (50 V) C6 capacitor Ceramic C7 0.1 F (50 V) capacitor Ceramic C8 2.2 F (16 V) capacitor Ceramic C9 1.0 F (16 V) capacitor Ceramic C12 0.015 F (50 V) capacitor Ceramic C13 4700 pF (50 V) capacitor R1-1 Resistor 1 k R1-2 Resistor 24 k R2 Resistor 36 k R3-1 Resistor 1.1 k R3-2 Resistor 22 k R4 Resistor 36 k R5 Resistor 18 k R6 Resistor 18 k R7 Resistor 5.6 RENESAS : Renesas Electronics Corporation SANYO : SANYO Electric Co., Ltd. TDK : TDK Corporation SSM : SUSUMU Co.,Ltd. KOA : KOA Corporation 20 Vendor Package Part number Remarks RENESAS SO-8 PA2755 RENESAS SO-8 PA2755 Dual type (2 elements) Dual type (2 elements) TDK TDK VLF10045T-1R5N9R0 VLF10045T-2R2N7R4 TDK 3216 C3216JB1E106K TDK 3216 C3216JB1E106K SANYO C6 6SVPC220MV TDK 1608 C1608CH1H102J TDK 3216 C3216JB1E106K TDK 3216 C3216JB1E106K SANYO C6 6SVPC220MV TDK 1608 C1608CH1H102J TDK 1608 C1608JB1H104K TDK 1608 C1608JB1H104K TDK 1608 C1608JB1H104K TDK 1608 C1608JB1C225K TDK 1608 C1608JB1C105K TDK 1608 C1608JB1H153K TDK 1608 C1608JB1H472K SSM SSM SSM SSM SSM SSM SSM SSM KOA 1608 1608 1608 1608 1608 1608 1608 1608 1608 RR0816P102D RR0816P243D RR0816P363D RR0816P112D RR0816P223D RR0816P363D RR0816P183D RR0816P183D RK73H1JTTD5R6F DS04-27270-2E MB39A138 APPLICATION NOTE 1. Setting Operating Conditions Setting output voltages 1. When the output setting voltages are Vo1 = 1.23 V, Vo2 = 3.45 V: They can be set by the internal preset function. In this case, the smallest number of parts is required for the setting, as it is not necessary to use a resistor to set the output voltage. Pin connection Output voltage setting value (Vo) CH1 FB1 = CVBLPF Vo1 = 1.23 V CH2 FB2 = CVBLPF Vo2 = 3.45 V 2. When the output setting voltages are other Vo1 = 1.23 V, Vo2 = 3.45 V: They can be set by adjusting the ratio of the output voltage setting resistor value. The output setting voltage is calculated by the following formula. VOX = R1 + R2 R2 VOX INTREF VOX x INTREF + VOX 2 : Output setting voltage [V] : Internal reference voltage (CH1/CH2 : 0.7 V/2.0 V) : Output ripple voltage value [V] VOX VOX R1 FBX R2 The output ripple voltage value (VOX) is calculated by the following formula. VOX = ESR x VOX L VIN VOX fOSC VIN-VOX L x VOX VIN x fOSC : Output ripple voltage value [V] : Inductor value [H] : Power supply voltage [V] : Output setting voltage [V] : Oscillation frequency [Hz] (CH1 : 310 kHz, CH2 : 465 kHz) Note: x is each channel number. When not using the following feedback capacitor (CFB), select a resistor value that achieves R1//R2 15 k as a target. Set so that the on-time (tON) is more than 100 ns. (For how to calculate the on-time, see (4) ON/OFF Time Generator Block in " FUNCTION") DS04-27270-2E 21 MB39A138 As the output voltage gets higher, the resistor value ratio of output voltage setting is getting higher. Moreover, the oscillation frequency may become unstable as a result. This occurs because the value of the ripple voltage applied to the FB pin is reduced by the R1/R2 ratio. In this case, a stable oscillation frequency can be achieved by increasing the output ripple voltage or adding a capacitor (CFB) in parallel to R1. Select an additional capacitor using the following formula as a guide. CFB 10 x (R1 + R2) 2 x fosc x R1 x R2 CFB R1, R2 fOSC : Capacitor value of feedback capacitor [F] : Output voltage setting resistor value [] : Oscillation frequency [Hz] VO VO R1 CFB FB R2 Moreover, adding a capacitor increases the output voltage according to the output ripple voltage. The following formula is used to calculate the output voltage value to be increased. Vo_offset = (VO - INTREF) x VO 2 x INTREF Vo_offset VO Vo INTREF : Output setting voltage offset value [V] : Output setting voltage [V] : Output ripple voltage value [V] : Internal reference voltage (CH1/CH2 : 0.7 V/2.0 V) V Vo Vo_offset Vo t Use the following formula to calculate the output setting voltage when considering the output setting voltage offset value. VOX = R1 + R2 R2 VOX INTREF VOX VO_offset x INTREF + VOX 2 + VO_offset : Output setting voltage[V] : Internal reference voltage (CH1/CH2 : 0.7 V/2.0 V) : Output ripple voltage value [V] : Output setting voltage offset value [V] Note: x is each channel number. 22 DS04-27270-2E MB39A138 Consideration of output ripple voltage This device requires an output ripple voltage value as an operating principle. It must secure about 15 mV at the FB pin. Calculate the output ripple voltage required for the output of the DC/DC converter by the following formula. VOX K x 15 mV VOX K : Output ripple voltage value [V] : Coefficient When CFB is used : K = 1; CFB is not used : K = VO INTREF VO INTREF : Output setting voltage [V] : Internal reference voltage (CH1/CH2 : 0.7 V/2.0 V) A stable oscillation frequency can be achieved by increasing the output ripple voltage. The output ripple voltage can be increased by selecting a larger output capacitor's ESR or a smaller inductor value. However, if the output ripple voltage is increased excessively, the slope of the output ripple voltage during the off-period (tOFF) becomes steeper, which affects the bottom detection voltage more. As a result, it affects the output voltage. This become prominent, if it increase on-duty. Ensure that the ripple voltage at the FB pin is not excessively large. DS04-27270-2E 23 MB39A138 Setting soft-start time Calculate the soft-start time by the following formula. ts = INTREF x CCS 5 x 10-6 ts INTREF CCS : Soft-start time [s] (time until output reaches 100%) : Internal reference voltage (CH1/CH2 : 0.7 V/2.0 V) : CS pin capacitor value [F] Calculate the delay time until the soft-start activation by the following formula. td = 30 x (CVB + CCVBLPF) td CVB CCVBLPF : VB voltage delay time [s] : VB capacitor value [F] : CVBLPF capacitor value [F] Time until the soft-start activates td [s] Reference characteristics : Time until the soft-start activates vs. power supply voltage 400 CVB = 2.2 F, CCVBLPF = 1 F 350 300 250 200 150 100 50 0 5 10 15 20 25 Power supply voltage VIN [V] In almost all cases, no delay time is generated when the soft-start activates in the state that one side channel has already activated (UVLO release: VB output already). ts1 ts2 CTL1 CTL2 VO1 VO2 td1 Note : Set the slew rate of 750 V/s or more to the input-signal to CTL1 and CTL2 pins. 24 DS04-27270-2E MB39A138 Setting over current detection value The over current detection value can be set by adjusting the over current detection resistor value connected to the ILIM pin. Calculate the resistor value by the following formula. RON_Sync x (ILIM - RLIM = RLIM ILIM IL RON_Sync VO L IL VO x 260 x 10-9 + ) 2 L 10 x 10-6 : Over current detection value setting resistor [] : Over current detection value [A] : Ripple current peak-to-peak value of inductor [A] : ON resistance of low-side FET [] : Output setting voltage [V] : Inductor value [H] ILIM RLIM Inductor current Value to limit over current ILIM IL IO 0 Time If the rate of inductor saturation current is small, the inductor value decreases and the ripple current of inductor increase when the over-current flows. At that time there is a possibility that the limited output current increases or is not limited, because the bottom of inductor current is detected. It is necessary to use the inductor that has enough large rate of inductor saturation current to prevent the overlap current. DS04-27270-2E 25 MB39A138 The over current limit value is affected by ILIM pin source current and over current detection offset voltage in the IC except for the on resistance of the low-side FET and the inductor value. The variation of dropped over current limit value caused by IC characteristics is calculated by the following formula. ILIM = - 1.7 x 10-6 x RLIM + 0.02 RON_Sync ILIM RLIM RON_Sync : The variation of dropped over current limit value [A] : Resistor to set over current limit [] : Low-side FET on resistance [] Inductor current Over current limit value ILIM ILIM Dropped over current limit value due to ILIM' IC's characteristics IO 0 Time The over current detection value needs to set a sufficient margin against the maximum load current. 26 DS04-27270-2E MB39A138 VB Regulator In the condition for which the potential difference between VCC and VB is insufficient, the decrease in the voltage of VB happens because of power output on-resistance and load current (mean current of all external FET gate driving current and load current of internal IC) of the VB regulator. Stop the switching operation when the voltage of VB decreases and it reaches threshold voltage (VTHL) of the under voltage lockout protection circuit. Therefore, set oscillation frequency or external FET or I/O potential difference of the VB regulator using the following formula as a target when you use this IC. When using it in the condition for which the I/O potential difference is insufficient, check the operation on an actual device carefully during normal operation, startup and shutdown. VIN VB (VTHL) + (Qg x fOSC + ICC) x RVB VB (VTHL) Qg fOSC ICC RVB : Threshold voltage of under-voltage lockout protection circuit = 3.8 [V] Max : Total amount of gate charge of external FET [C] : Oscillation frequency [Hz] : Power supply current = 2 x 10-3 [A] ( Load current of VB (LDO)) : VB Output on-resistance = 75 [] (The reference value at VIN = 6 V) Power dissipation and the thermal design As for this IC, considerations of the power dissipation and thermal design are not necessary in most cases because of its high efficiency. However, they are necessary for the use at the conditions of a high power supply voltage, a high oscillation frequency, high load, and the high temperature. Calculate IC internal loss by the following formula. PIC = VCC x (ICC + Qg1 x fOSC1 + Qg2 x fOSC2) PIC VCC ICC Qg1, Qg2 fOSC1, fOSC2 : IC internal loss [W] : Power supply voltage (VIN) [V] : Power supply current [A] (2 mA Max) : Total quantity of charge for the high-side FET and the low-side FET of each CH [C] (Total at Vgs = VB) : Oscillation frequency of each CH [Hz] Calculate junction temperature (Tj) by the following formula. Tj = Ta + ja x PIC Tj Ta ja PIC DS04-27270-2E : Junction temperature [ C] ( + 125 C Max) : Operation ambient temperature [ C] : TSSOP-24 Package thermal resistance ( + 75 C/W) : IC internal loss [W] 27 MB39A138 Handling of the pins when using a single channel Although this device is a 2-channel DC/DC converter control IC, it is also able to be used as a 1-channel DC/DC converter by handling the pins of the unused channel as shown in the following diagram. VOx CBx "Open" FBx DRVHx "Open" CSx DRVLx "Open" ILIMx "Open" CTLx LXx Note: x is the unused channel number. 28 DS04-27270-2E MB39A138 2. Selecting parts Selection of smoothing inductor The inductor value selects the value that the ripple current peak-to-peak value of the inductor is 50% or less of the maximum load current as a rough standard. Calculate the inductor value in this case by the following formula. L VIN - VO VO LOR x IOMAX x VIN x fOSC L IOMAX LOR VIN VO fOSC : Inductor value [H] : Maximum load current [A] : Ripple current peak-to-peak value of inductor / Maximum load current ratio (=0.5) : Power supply voltage [V] : Output setting voltage [V] : Oscillation frequency [Hz] It is necessary to calculate the maximum current value that flows to the inductor to judge whether the electric current that flows to the inductor is a rated value or less. Calculate the maximum current value of the inductor by the following formula. ILMAX IOMAX + IL = IL 2 VIN - VO L ILMAX IOMAX IL L VIN VO fOSC VO x VIN x fOSC : Maximum current value of inductor [A] : Maximum load current [A] : Ripple current peak-to-peak value of inductor [A] : Inductor value [H] : Power supply voltage[V] : Output setting voltage[V] : Oscillation frequency [Hz] Inductor current ILMAX IOMAX IL Time 0 DS04-27270-2E 29 MB39A138 Selection of Switching FET Select the low-side FET ON resistance from the below range in order to operate the over current limit function normally. 0.03 (ILIM - IL ) 2 RON_Sync 0.2 (ILIM - IL ) 2 RON_Sync : Low-side FET ON resistance [] IL : Ripple current peak-to-peak value of inductor [A] ILIM : Over current detection value [A] The maximum value of the current that flows to the switching FET must be calculated in order to determine whether the current flowing to the switching FET is within the rated value. Calculate the maximum value of the current that flows to the switching FET by the following formula. IL 2 ID = IOMAX + ID IOMAX IL : Drain current [A] : Maximum load current [A] : Ripple current peak-to-peak value of inductor [A] Moreover, it is necessary to calculate the loss of switching FET to judge whether a power dissipation of switching FET is a rated value or less. Calculate the loss on high-side FET by the following formula. PMainFET = PRON_Main + PSW_Main PMainFET PRON_Main PSW_Main : High-side FET loss [W] : High-side FET conduction loss [W] : High-side FET switching loss [W] High-side FET conduction loss PRON_Main = IOMAX2 x PRON_Main IOMAX VIN VO RON_Main VO x RON_Main VIN : High-side FET conduction loss [W] : Maximum load current[A] : Power supply voltage[V] : Output voltage[V] : High-side FET ON resistance [] High-side FET switching loss PSW_Main = VIN x fOSC x (Ibtm x tr + Itop x tf) 2 PSW_Main VIN fOSC Ibtm Itop 30 : Switching loss [W] : Power supply voltage [V] : Oscillation frequency (Hz) : Ripple current bottom value of inductor [A] : Ripple current top value of inductor [A] DS04-27270-2E MB39A138 IL , Itop = IOMAX + 2 Ibtm = IOMAX - IL IOMAX IL 2 : Ripple current peak-to-peak value of inductor [A] : Maximum load current [A] tr : Turn-on time on high-side FET [s] tf : Turn-off time on high-side FET [s] tr and tf is calculated by the following formula. tr = Qgd x 4 , tf = VB - Vgs (on) Qgd Vgs (on) VB Qgd x 1 Vgs (on) : Quantity of charge between gate and drain on high-side FET [C] : Voltage between gate and sources in Qgd on high-side FET [V] : VB voltage [V] The loss of the low-side FET is calculated by the following formula. (The transition voltage of the voltage between drain and source on low-side FET is generally small, and the switching loss is omitted here for the small one as it is possible to disregard it.) PSyncFET = RRon_Sync = IOMAX2 x (1 - PRon_Sync IOMAX VIN VO Ron_Sync VO ) x Ron_Sync VIN : Low-side FET conduction loss [W] : Maximum load current [A] : Power supply voltage [V] : Output voltage [V] : Low-side FET on-resistance [] The gate drive power of switching FET is supplied by LDO in IC, therefore all of the allowable maximum total gate charge (QgTotalMax) of all switching FET for 2 channels is calculated by the following formula. QgTotalMax 140000 fOSC2 QgTotalMax fOSC2 DS04-27270-2E : All of the allowable maximum total gate charge of all switching FET for 2 channels [nC] : CH2 oscillation frequency [kHz] 31 MB39A138 Selection of fly-back diode Fly-back diode is not needed in general. However, it is possible to enhance the conversion efficiency by building in the fly-back diode, thought it is usually unnecessary. The effect is achieved in the condition where the oscillation frequency is high or output voltage is lower. Select schottky barrier diode (SBD) that the forward current is as small as possible. In this DC/DC control IC, the period for the electric current flows to fly-back diode is limited to synchronous rectification period (120 [ns]) because of using the synchronous rectification method. Therefore, select the one that the electric current of fly-back diode does not exceed ratings of forward current surge peak (IFSM).Calculate the forward current surge peak ratings of fly-back diode by the following formula. IL 2 IFSM IOMAX + IFSM IOMAX IL : Forward current surge peak ratings of SBD [A] : Maximum load current [A] : Ripple current peak-to-peak value of inductor [A] Calculate ratings of the fly-back diode by the following formula: VR_Fly > VIN VR_Fly VIN : Reverse voltage of fly-back diode direct current [V] : Power supply voltage [V] Selection of output capacitor A certain level of ESR is required for stable operation of this IC. Use a tantalum capacitor or polymer capacitor as the output capacitor. If using a ceramic capacitor with low ESR, a resistor should be connected in series with it to increase ESR equivalently. Calculate the required ESR for the smoothing capacitor by the following formula. ESR IL VO ESR VO IL : Series resistance of output capacitor [] : Output ripple voltage [V] : Ripple current peak-to-peak value of inductor [A] Select the capacitance of the output capacitor with the following condition to a target. CO 1 4 x fOSC x ESR CO fOSC ESR : Output capacitor value [F] : Oscillation frequency [Hz] : Series resistance of output capacitor [] When using a capacitor where the capacity demanded by the above formula is unfulfilled, use it after intensively operation check that there is no problem with the jitter level. 32 DS04-27270-2E MB39A138 Moreover, the output capacitor values are also derived from the allowable amount of overshoot and undershoot. The following formula is represented as the worst condition in which the shift time for a sudden load change is 0s. For a longer shift time, the smaller amount of output capacitor is acceptable than the value calculated by the following formula. Overshoot condition CO IO2 x L 2 x VO x VO_OVER Undershoot condition CO IO2 x L x (VO + VIN x fOSC x 380 x 109) 2 x VO x VO_UNDER x (VIN - VO - VIN x fOSC x 380 x 109) CO VO_OVER VO_UNDER IO L VIN VO fOSC : Output capacitor value [F] : Allowable amount of output voltage overshoot [V] : Allowable amount of output voltage undershoot [V] : Current difference in sudden load change [A] : Inductor value [H] : Power supply voltage [V] : Output setting voltage[V] : Oscillation frequency [Hz] The capacitor has frequency, operating temperature, and bias voltage characteristics, etc. Therefore, it must be noted that its effective capacitor value may be significantly smaller, depending on the use conditions. Calculate voltage rating of the output capacitor by the following formula. VCO > VO VCO VO : Withstand voltage of the output capacitor [V] : Output voltage [V] Capacitor voltage rating should have a sufficient margin to withstand the output voltage. Calculate the allowable ripple current of the output capacitor by the following formula. Irms IL 2 3 Irms IL DS04-27270-2E : Allowable ripple current (effective value) [A] : Ripple current peak-to-peak value of inductor [A] 33 MB39A138 Selection of input capacitor Select the input capacitor whose ESR is as small as possible. The ceramic capacitor is an ideal. Use the tantalum capacitor and the polymer capacitor of the low ESR when a mass capacitor is needed as the ceramic capacitor can not support. If a inductor is connected as a noise filter between the power supply and the input capacitor, and the cut-off frequency for this inductor and input capacitor is set to a value lower than the oscillation frequency, the ripple voltage by the switching operation of DC/DC is generated. Discuss the lower bound of input capacitor according to an allowable ripple voltage. Calculate the ripple voltage of the power supply from the following formula. VIN = IOMAX CIN VIN IOMAX CIN VIN VO fOSC ESR IL x VO + ESR x (IOMAX + VIN x fOSC IL 2 ) : Power supply ripple voltage peak-to-peak value [V] : Maximum load current value [A] : Input capacitor value [F] : Power supply voltage [V] : Output setting voltage [V] : Oscillation frequency [Hz] : Series resistance component of input capacitor [] : Ripple current peak-to-peak value of inductor [A] Capacitor has frequency characteristic, the temperature characteristic, and the bias voltage characteristic, etc. The effective capacitor value might become extremely small depending on the use conditions. Note the effective capacitor value in the use conditions. Calculate ratings of the input capacitor by the following formula: VCIN > VIN VCIN VIN : Withstand voltage of the input capacitor [V] : Power supply voltage [V] Select the capacitor voltages rating with withstand voltage with margin enough for the input voltage. In addition, use the allowable ripple current with an enough margin, if it has a rating. Calculate an allowable ripple current by the following formula. Irms IOMAX x Irms IOMAX VIN VO 34 VO x (VIN - VO) VIN : Ripple current (effective value) [A] : Maximum load current value [A] : Power supply voltage [V] : Output setting voltage [V] DS04-27270-2E MB39A138 Selection of boot strap capacitor To drive the gate of high-side FET, the bootstrap capacitor must have enough stored charge. Therefore, a minimum value as a target is assumed the capacitor which can store electric charge 10 times that of the Qg on high-side FET. And select the boot strap capacitor. CBOOT 10 x CBOOT Qg VB Qg VB : Boot strap capacitor value [F] : Amount of gate charge on high-side FET [C] : VB voltage [V] Calculate ratings of the boot strap capacitor by the following formula: VCBOOT > VB VCBOOT VB : Withstand voltage of the boot strap capacitor[V] : VB voltage [V] VB pin capacitor 2.2 F is assumed to be a standard, and when Qg of switching FET used is large, it is necessary to adjust it. To drive the gate of high-side FET, the bootstrap capacitor must have enough stored charge. Therefore, a minimum value as a target is assumed the capacitor value which can store electric charge 100 times that of the Qg on switching FET. And select it. Moreover, capacitor change may cause an overshoot when CTL was turned on. Although the overshoot does not affect DC/DC operation, check that the VB pin does not exceed its rating before applying the capacitors. CVB 100 x CVB Qg VB Qg VB : VB pin capacitor value [F] : Total amount of gate charge of high-side FET and low-side FET for 2ch [C] : VB voltage [V] Calculate ratings of the VB pin capacitor by the following formula: VCVB > VB VCVB VB : Withstand voltage of the VB pin capacitor [V] : VB voltage [V] CVBLPF pin capacitor and resistor LPF to power supply from the VB regulator (VB pin) to the control system power supply (CVBLPF pin) is made by the CVBPF pin's capacitor and the resistor between the VB pin and the CVBPF pin. The cut-off frequency is set to one tenth of oscillation frequency as a target (1 F is the standard of the capacitor value). Select as small a value as possible (the recommended value is about 5 ). Because the voltages drop to the control system power supply is occurred when setting the resistor value to extremely large value. DS04-27270-2E 35 MB39A138 3. Layout Consider the points listed below and do the layout design. * Provide the ground plane as much as possible on the IC mounted face. Connect bypass capacitor connected with the VCC and VB pins, and GND pin of the switching system parts with switching system GND (PGND). Connect other GND connection pins with control system GND (AGND), and separate each GND, and try not to pass the heavy current path through the control system GND (AGND) as much as possible. In that case, connect control system GND (AGND) and switching system GND (PGND) at the single point of GND (PGND) in IC. * Connect the switching system parts as much as possible on the surface. Avoid the connection through the through-hole as much as possible. * As for GND pins of the switching system parts, provide the through hole at the proximal place, and connect it with GND of internal layer. * Pay the most attention to the loop composed of input capacitor (CIN), switching FET, and fly-back diode (SBD). Consider making the current loop as small as possible. * Place the boot strap capacitor (CBOOT1, CBOOT2) proximal to CBx and LXx pins of IC as much as possible. * Large electric current flows momentary in the net of DRVHx and DRVLx pins connected with the gate of switching FET. Wire the linewidth of about 0.8 mm to be a standard, as short as possible. * By-pass capacitor (CVBLPF, CVCC, CVB) connected with CVBLPF, VCC, and VB should be placed close to the pin as much as possible. Also connect the GND pin of the bypass capacitor with GND of internal layer in the proximal through-hole. * Pull the feedback line to be connected to the VOx pin of the IC separately from near the output capacitor pin, whenever possible, in order to feed back it to the IC more accurately. It is the ripple voltage which is generated from ESR of the output capacitor. Consider the net connected with VOx and FBx pins to keep away from a switching system parts as much as possible because it is sensitive to the noise. Moreover, place the output voltage setting resistor connected with this net close to the IC as much as possible, and try to make the net as short as possible. In addition, for the internal layer right under the component mounting place, provide the control system GND (AGND) of few ripple and few spike noises, or provide the ground plane of the power supply as much as possible. Switching system parts : Input capacitor (CIN), Switching FET, Fly-back diode (SBD), Inductor (L), Output capacitor (CO) Layout example of IC peripheral 1pin Layout example of switching system parts Through-hole High-side FET High-side FET CBOOT1 VIN CVCC AGND Through-hole CIN Low-side FET CIN Low-side FET CVREF PGND To the LX1 pin CVB Output voltage setting resistor layout CBOOT2 Connect AGND and PGND right under IC Surface 36 Internal layer SBD (option) CO SBD (option) CO L L PGND AGND To the LX2 pin PGND Vo1 Output voltage Vo1 feedback Vo2 Output voltage Vo2 feedback DS04-27270-2E MB39A138 REFERENCE DATA Conversion efficiency vs. Load current Conversion efficiency vs. Load current 100 Conversion efficiency (%) Conversion efficiency (%) 100 90 80 70 VIN =12 V VO1=1.2 V Ta = +25C 60 50 0 1 2 3 4 80 70 VIN = 12 V 60 50 5 VO2 = 3.3 V Ta = +25C Load current IO(A) 1 2 3 Load current IO(A) Oscillation frequency vs. Load current Oscillation frequency vs. Load current 430 0 370 5 310 VIN =12 V 250 VO1 =1.2 V 520 460 VIN = 12 V 400 VO2 = 3.3 V Ta = +25C Ta = +25C 190 0 1 2 3 4 340 5 1 2 3 Load current IO(A) Output voltage vs. Load current Output voltage vs. Load current 4 5 Output voltage VO (V) 3.60 1.25 1.20 VIN = 12 V 1.15 1.10 0 Load current IO(A) 1.30 Output voltage VO (V) 4 580 Oscillation frequency fosc (kHz) Oscillation frequency fosc (kHz) 90 VO1 = 1.2 V Ta = +25C 0 1 2 3 Load current IO(A) 4 5 3.45 3.30 VIN = 12 V 3.15 3.00 VO2 = 3.3 V Ta = +25C 0 1 2 3 Load current IO(A) 4 5 (Continued) DS04-27270-2E 37 MB39A138 Ripple Waveform 2.0 s/div VO1 : 50 mV/div (AC) 1 VO2 : 50 mV/div (AC) 2 VIN = 12 V, VO1 = 1.2 V, IO1 = 5 A, VO2 = 3.3 V, IO2 = 5 A, Ta = + 25 C CH1 Load Sudden Change Waveform CH2 Load Sudden Change Waveform 100 s/div VO1 : 50 mV/div 100 s/div VO2 : 50 mV/div 1 1 5A 5A IO2 : 2 A/div IO1 : 2 A/div 0A 0A 4 4 VIN = 12 V, VO2 = 3.3 V, SR SET = 0.75 A/s 5 A, Ta = + 25 C IO2 = 0 A VIN = 12 V, VO1 = 1.2 V, SR SET = 0.75 A/s IO2 = 0 A 5 A, Ta = + 25 C CH2 CTL Startup Waveform CH1 CTL Startup Waveform 1 ms/div 1 ms/div CTL1 : 5 V/div CTL2 : 5V/div 1 1 VO2 : 1V/div VO1 : 500 mV/div 4 4 VLX1 : 10 V/div 2 VLX2 : 10V/div 2 VIN = 12 V, VO1 = 1.2 V, IO1 = 5 A (0.24 ), Softstart setting time = 2.1 ms, Ta = + 25 C VIN = 12 V, VO2 = 3.3 V, IO2 = 5 A (0.66 ), Softstart setting time = 1.9 ms, Ta = + 25 C (Continued) 38 DS04-27270-2E MB39A138 (Continued) CH2 CTL Shutdown Waveform CH1 CTL Shutdown Waveform 100 s/div 100 s/div CTL1 : 5 V/div 3 CTL2 : 5 V/div 3 VO2 : 1 V/div VO1 : 500 mV/div 1 1 VLX1 : 10 V/div 2 VIN = 12 V, VO1 = 1.2 V, IO1 = 5 A (0.24 ), Ta = + 25 C VLX2 : 10 V/div 2 VIN = 12 V, VO2 = 3.3 V, IO2 = 5 A (0.66 ), Ta = + 25 C CH2 Output Over Current Waveform CH1 Output Over Current Waveform 500 s/div 500 s/div 3 VO2 : 1 V/div VO1 : 500 mV/div 3 lO1 : 10 A/div 4 lO2 : 10 A/div 4 VLX1 : 10 V/div 2 VLX2 : 10 V/div 2 Over current Normal protection operation VIN = 12 V, VO1 = 1.2 V, Ta = + 25C DS04-27270-2E Under voltage protection Normal operation Over current protection Under voltage protection VIN = 12 V, VO2 = 3.3 V, Ta = + 25C 39 MB39A138 USAGE PRECAUTION 1. Do not configure the IC over the maximum ratings. If the IC is used over the maximum ratings, the LSI may be permanently damaged. It is preferable for the device to normally operate within the recommended usage conditions. Usage outside of these conditions can have an adverse effect on the reliability of the LSI. 2. Use the device within the recommended operating conditions. The recommended values guarantee the normal LSI operation under the recommended operating conditions. The electrical ratings are guaranteed when the device is used within the recommended operating conditions and under the conditions stated for each item. 3. Printed circuit board ground lines should be set up with consideration for common impedance. 4. Take appropriate measures against static electricity. * Containers for semiconductor materials should have anti-static protection or be made of conductive material. * After mounting, printed circuit boards should be stored and shipped in conductive bags or containers. * Work platforms, tools, and instruments should be properly grounded. * Working personnel should be grounded with resistance of 250 k to 1 M in serial body and ground. 5. Do not apply negative voltages. The use of negative voltages below -0.3 V may make the parasitic transistor activated to the LSI, and can cause malfunctions. 40 DS04-27270-2E MB39A138 ORDERING INFORMATION Part number Package MB39A138PFT 24-pin plastic TSSOP (FPT-24P-M10) Remarks EV BOARD ORDERING INFORMATION EV board number EV board version No. Remarks MB39A138EVB-01 MB39A138EVB-01 Rev.2.0 TSSOP-24 DS04-27270-2E 41 MB39A138 RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION The LSI products of FUJITSU SEMICONDUCTOR with "E1" are compliant with RoHS Directive, and has observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB) , and polybrominated diphenyl ethers (PBDE) . A product whose part number has trailing characters "E1" is RoHS compliant. MARKING FORMAT (Lead Free version) 39A138 XXXX E1 XXX INDEX 42 Lead Free version DS04-27270-2E MB39A138 LABELING SAMPLE (Lead free version) Lead-free mark JEITA logo MB123456P - 789 - GE1 (3N) 1MB123456P-789-GE1 1000 (3N)2 1561190005 107210 JEDEC logo G Pb QC PASS PCS 1,000 MB123456P - 789 - GE1 2006/03/01 ASSEMBLED IN JAPAN MB123456P - 789 - GE1 1/1 0605 - Z01A 1000 1561190005 The part number of a lead-free product has the trailing characters "E1". DS04-27270-2E 43 MB39A138 MB39A138PFT RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL [FUJITSU SEMICONDUCTOR Recommended Mounting Conditions] Item Condition Mounting Method IR (infrared reflow) , Manual soldering (partial heating method) Mounting times 2 times Storage period Before opening Please use it within two years after Manufacture. From opening to the 2nd reflow Less than 8 days When the storage period after opening was exceeded Please process within 8 days after baking (125 C, 24h) Storage conditions 5 C to 30 C, 70%RH or less (the lowest possible humidity) [Mounting Conditions] (1) IR (infrared reflow) 260C 255C Main heating 170 C to 190 C (b) RT (a) "H" level : 260 C Max (a) Temperature increase gradient (b) Preliminary heating (c) Temperature increase gradient (d) Peak temperature (d') Main heating (e) Cooling (c) (d) (e) (d') : Average 1 C/s to 4 C/s : Temperature 170 C to 190 C, 60 s to 180 s : Average 1 C/s to 4 C/s : Temperature 260 C Max; 255 C or more, 10 s or less : Temperature 230 C or more, 40 s or less or Temperature 225 C or more, 60 s or less or Temperature 220 C or more, 80 s or less : Natural cooling or forced cooling Note: Temperature : on the top of the package body (2) Manual soldering (partial heating method) Temperature at the tip of an soldering iron: 400 C max Time: Five seconds or below per pin 44 DS04-27270-2E MB39A138 PACKAGE DIMENSIONS 24-pin plastic TSSOP Lead pitch 0.65 mm Package width x package length 4.40 mm x 7.80 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.20 mm MAX Weight 0.10 g (FPT-24P-M10) 24-pin plastic TSSOP (FPT-24P-M10) Note 1) Pins width and pins thickness include plating thickness. Note 2) Pins width do not include tie bar cutting remainder. Note 3) #: These dimensions do not include resin protrusion. # 7.800.10(.307.004) +0.06 24 0.13 -0.03 +.002 .005 -.001 13 BTM E-MARK # 4.400.10 (.173.004) INDEX Details of "A" part 6.400.20 (.252.008) 1 12 0.65(.026) +0.07 0.22 -0.02 +.003 .008 -.001 1.20(.047) (Mounting height) MAX 0~8 "A" 0.10(.004) 0.600.15 (.024.006) 0.100.05 (Stand off) (.004.002) 0.10(.004) C 2008-2010 FUJITSU SEMICONDUCTOR LIMITED F24033S-c-1-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ DS04-27270-2E 45 MB39A138 MEMO 46 DS04-27270-2E MB39A138 MEMO DS04-27270-2E 47 MB39A138 FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fss/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fsp/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department