1 of 16 REV: 090407
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
FEATURES
Integrated NV SRAM, Real-Time Clock,
Crystal, Power-Fail Control Circuit, and
Lithium Energy Source
Clock Registers are Accessed Identically to
the Static RAM. These Registers Reside in
the Eight Top RAM Locations.
Century Byte Register
Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power
BCD-Coded Century, Year, Month, Date,
Day, Hours, Minutes, and Seconds with
Automatic Leap Year Compensation Valid
through 2099
Low-Battery-Voltage Level Indicator Flag
Power-Fail Write Protection Allows for ±10%
VCC Power-Supply Tolerance
Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time
DIP Module Only
Standard JEDEC Bytewide 8k x 8 Static
RAM Pinout
PowerCap Module Board Only
Surface-Mountable Package for Direct
Connection to PowerCap Containing
Battery and Crystal
Replaceable Battery (PowerCap)
Power-On Reset Output
Pin-for-Pin Compatible with Other Densities
of DS174XP Timekeeping RAM
Underwriters Laboratories (UL) Recognized
to Prevent Charging of the Internal Lithium
Battery
PIN CONFIGURATIONS
DS1743/DS1743P
Y2K-Compliant, Nonvolatile Timekeeping
RAMs
www.maxim-ic.com
VCC
WE
CE2
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
N.C.
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28-Pin Encapsulated Package
(
28 PIN 740
)
DS1743
1
N.C. 2
3
N.C.
N.C.
R
ST
VCC
W
E
O
E
C
E
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
4
5
6
7
8
9
10
11
12
13
14
15
16
17
N.C.
N.C.
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
N.C.
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34 N.C.
X1 GND VBAT X2
34-Pin PowerCap Module Board
(
Uses DS9034PCX PowerCa
p)
DS1743P
TOP VIEW
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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PIN DESCRIPTION
PIN
PDIP PowerCap
NAME FUNCTION
1 1, 2, 3,
31–34 N.C. No Connection
2 30 A12
3 25 A7
4 24 A6
5 23 A5
6 22 A4
7 21 A3
8 20 A2
9 19 A1
10 18 A0
Address Input
11 16 DQ0
12 15 DQ1
13 14 DQ2
Data Input/
Output
14 17 GND Ground
15 13 DQ3
16 12 DQ4
17 11 DQ5
18 10 DQ6
19 9 DQ7
Data Input/
Output
PIN
PDIP PowerCap
NAME FUNCTION
20 8
CE Chip Enable,
Active Low
21 28 A10 Address Input
22 7
OE Output Enable,
Active Low
23 29 A11
24 27 A9
25 26 A8
Address Input
26 — CE2 Chip Enable 2
27 6
WE Write Enable,
Active Low
28 5 VCC Power-Supply
Input
— 4
RST Power-On Reset
Output, Active
Low
— X1, X2
Crystal
Connection
— VBAT Battery
Connection
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
VOLTAGE
(V) TOP MARK**
DS1743-85 0°C to +70°C 28 EDIP Module 5 DS1743-85
DS1743-100 0°C to +70°C 28 EDIP Module 5 DS1743-100
DS1743-100 IND -40°C to +85°C 28 EDIP Module 5 DS1743-100-IND
DS1743P-85 0°C to +70°C 34 PowerCap* 5 DS1743P-85
DS1743P-100 0°C to +70°C 34 PowerCap* 5 DS1743P-100
DS1743P-100IND -40°C to +85°C 34 PowerCap* 5 DS1743P-100 IND
DS1743W-120 0°C to +70°C 28 EDIP Module 3.3 DS1743W-120
DS1743W-120 IND -40°C to +85°C 28 EDIP Module 3.3 DS1743W-120 IND
DS1743W-150 0°C to +70°C 28 EDIP Module 3.3 DS1743W-150
DS1743W-150 IND -40°C to +85°C 28 EDIP Module 3.3 DS1743W-150 IND
DS1743WP-120 0°C to +70°C 34 PowerCap* 3.3 DS1743WP-120
DS1743WP-120 IND -40°C to +85°C 34 PowerCap* 3.3 DS1743WP-120 IND
DS1743-85+ 0°C to +70°C 28 EDIP Module 5 DS1743-85
DS1743-100+ 0°C to +70°C 28 EDIP Module 5 DS1743-100
DS1743-100 IND+ -40°C to +85°C 28 EDIP Module 5 DS1743-100-IND
DS1743P-85+ 0°C to +70°C 34 PowerCap* 5 DS1743P-85
DS1743P-100+ 0°C to +70°C 34 PowerCap* 5 DS1743P-100
DS1743P-100IND+ -40°C to +85°C 34 PowerCap* 5 DS1743P-100 IND
DS1743W-120+ 0°C to +70°C 28 EDIP Module 3.3 DS1743W-120
DS1743W-120 IND+ -40°C to +85°C 28 EDIP Module 3.3 DS1743W-120 IND
DS1743W-150+ 0°C to +70°C 28 EDIP Module 3.3 DS1743W-150
DS1743W-150 IND+ -40°C to +85°C 28 EDIP Module 3.3 DS1743W-150 IND
DS1743WP-120+ 0°C to +70°C 34 PowerCap* 3.3 DS1743WP-120
DS1743WP-120 IND+ -40°C to +85°C 34 PowerCap* 3.3 DS1743WP-120 IND
DS9034PCX 0°C to +70°C PowerCap — DS9034PC
DS9034I-PCX -40°C to +85°C PowerCap IND — DS9034PCI
DS9034PCX+ 0°C to +70°C PowerCap — DS9034PC
DS9034I-PCX+ -40°C to +85°C PowerCap IND — DS9034PCI
+Denotes a lead(Pb)-free/RoHS-compliant package.
*DS9034PCX required (must be ordered separately).
**A ‘+’ indicates lead(Pb)-free. The top mark will include a ‘+’ symbol on lead(Pb)-free devices.
DESCRIPTION
The DS1743 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and 8k x 8
nonvolatile static RAM. User access to all registers within the DS1743 is accomplished with a bytewide
interface as shown in Figure 1. The RTC information and control bits reside in the eight uppermost RAM
locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in
24-hour binary-coded decimal (BCD) format. Corrections for the day of the month and leap year are made
automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can occur
during clock update cycles. The double-buffered system also prevents time loss as the timekeeping
countdown continues unabated by access to time register data. The DS1743 also contains its own power-
fail circuitry, which deselects the device when the VCC supply is in an out-of-tolerance condition. When
VCC is above VPF, the device is fully accessible. When VCC is below VPF, the internal CE signal is forced
high, preventing any access. When VCC rises above VPF, access remains inhibited for TREC, allowing time
for the system to stabilize. These features prevent loss of data from unpredictable system operation brought
on by low VCC as errant access and update cycles are avoided .
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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PACKAGES
The DS1743 is available in two packages: the 28-pin DIP and the 34-pin PowerCap module. The 28-pin
DIP-style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1743P after the completion of the surface-mount process. Mounting the PowerCap after the surface-
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
TIME AND DATE OPERATION
The time and date information is obtained by reading the appropriate register bytes. Table 2 shows the
RTC registers. The time and date are set or initialized by writing the appropriate register bytes. The
contents of the time and date registers are in the BCD format. The day-of-week register increments at
midnight. Values that correspond to the day of week are user-defined, but must be sequential (i.e., if 1
equals Sunday, then 2 equals Monday and so on). Illogical time and date entries result in undefined
operation.
CLOCK OPERATIONS-READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1743 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, bit 6 of the century register (see Table 2). As long
as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count that
is day, date, and time that was current at the moment the halt command was issued. However, the internal
clock registers of the double-buffered system continue to update so that the clock accuracy is not affected
by the access of data. All the DS1743 registers are updated simultaneously after the internal clock register
updating process has been re-enabled. Updating is within a second after the read bit is written to 0.
The READ bit must be a zero for a minimum of 500s to ensure the external registers are updated.
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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Figure 1. Block Diagram
Table 1. Truth Table
VCC CE CE2 OE WE MODE DQ POWER
VIH X X X Deselect High-Z Standby
X VIL X X Deselect High-Z Standby
VIL V
IH X VIL Write Data In Active
VIL V
IH V
IL V
IH Read Data Out Active
VCC > VPF
VIL V
IH V
IH V
IH Read High-Z Active
VSO < VCC < VPF X X X X Deselect High-Z CMOS Standby
VCC<VSO<VPF X X X X Deselect High-Z Data-Retention
Mode
SETTING THE CLOCK
As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a 1, like the read
bit, halts updates to the DS1743 registers. The user can then load them with the correct day, date and time
data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock
counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers, see
Table 2. Setting it to a 1 stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512Hz frequency as long as conditions for
access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and
stable).
Dallas
Semiconductor
DS1743
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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CLOCK ACCURACY (DIP MODULE)
The DS1743 is guaranteed to keep time accuracy to within 1 minute per month at +25C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require
additional calibration. For this reason, methods of field clock calibration are not available and not
necessary. The electrical environment also affects clock accuracy, so caution should be taken to place the
RTC in the lowest-level EMI section of the PC board layout. For additional information, please refer to
Application Note 58: Crystal Considerations with Dallas Real-Time Clocks.
CLOCK ACCURACY (PowerCap MODULE)
The DS1743 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within 1.53 minutes per month (35ppm) at +25°C. The
electrical environment also affects clock accuracy, so caution should be taken to place the RTC in the
lowest-level EMI section of the PC board layout. For additional information, please refer to Application
Note 58: Crystal Considerations with Dallas Real-Time Clocks.
Table 2. Register Map DATA
ADDRESS B7 B
6 B
5 B
4 B
3 B
2 B
1 B
0 FUNCTION RANGE
1FFF 10 Year Year Year 00–99
1FFE X X X
10
Month Month Month 01–12
1FFD X X 10 Date Date Date 01–31
1FFC BF FT X X X Day Day 01–07
1FFB X X 10 Hour Hour Hour 00–23
1FFA X 10 Minutes Minutes Minutes 00–59
1FF9 OSC 10 Seconds Seconds Seconds 00–59
1FF8 W R 10 Century Century Control 00–39
OSC = STOP BIT R = READ BIT FT = FREQUENCY TEST
W = WRITE BIT X = SEE NOTE BELOW BF = BATTERY FLAG
Note: All indicated “X” bits must be set to “0” when written to ensure proper clock operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1743 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations in
the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is stable,
providing that the, CE and OE access times and states are satisfied. If CE, or OE access times and states
are not met, valid data will be available at the latter of chip enable access (tCEA) or at output enable access
time (tCEA). The state of the data input/output pins (DQ) is controlled by CE and OE. If the outputs are
activated before tAA, the data lines are driven to an intermediate state until tAA. If the address inputs are
changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH) but
will then go indeterminate until the next address access.
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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WRITING DATA TO RAM OR CLOCK
The DS1743 is in the write mode whenever WE, and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE, on CE. The addresses must be held valid throughout the
cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or write
cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a typical
application, the OE signal will be high during a write cycle. However, OE can be active provided that care
is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the data bus
can become active with read data defined by the address inputs. A low transition on WE will then disable
the outputs tWEZ after WE goes active.
DATA-RETENTION MODE
The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF.
However, when VCC is below the power-fail point, VPF, (point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. At this time (PowerCap only) the power-
fail reset-output signal (RST) is driven active and remains active until VCC returns to nominal levels. When
VCC falls below the battery switch point VSO (battery supply level), device power is switched from the VCC
in to the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is
returned to nominal levels.
The 3.3V device is fully accessible and data can be written or read only when VCC is greater than VPF.
When VCC falls below the power-fail point, VPF, access to the device is inhibited. At this time the power-
fail reset-output signal (RST) is driven active and remains active until VCC returns to nominal levels. If VPF
is less than VSO, the device power is switched from VCC to the backup supply (VBAT) when VCC drops
below VPF. If VPF is greater than VSO, the device power is switched from VCC to the backup supply (VBAT)
when VCC drops below VSO. RTC operation and SRAM data are maintained from the battery until VCC is
returned to nominal levels. The RST (PowerCap only) signal is an open-drain output and requires a pullup
resistor. Except for RST, all control, data, and address signals must be powered down when VCC is
powered down.
BATTERY LONGEVITY
The DS1743 has a lithium power source that is designed to provide energy for clock activity and clock and
RAM data retention when the VCC supply is not present. The capability of this internal power supply is
sufficient to power the DS1743 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at +25C with the internal clock oscillator running in
the absence of VCC power. Each DS1743 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than
VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
DS1743 will be longer than 10 years since no lithium battery energy is consumed when VCC is present.
BATTERY MONITOR
The DS1743 constantly monitors the battery voltage of the internal battery. The battery flag bit (bit 7) of
the day register is used to indicate the voltage level range of the battery. This bit is not writeable and
should always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated and
both the contents of the RTC and RAM are questionable.
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………………………………………-0.3V to +6.0V
Operating Temperature Range…………………………………………………………………….-40°C to +85°C
Storage Temperature Range……………………………………………………………………….-40°C to +85°C
Soldering Temperature (EDIP) (leads, 10 seconds)…………………….……………………………..…+260°C
Soldering Temperature…………………………………………..….See J-STD-020 Specification (See Note 8)
This is a stress rating only and functional operation of the device a t these or any ot her conditions above those indicated in the operation sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
OPERATING RANGE
RANGE TEMP RANGE VCC
Commercial 0°C to +70°C 3.3V 10% or 5V 10%
Industrial -40C to +85C 3.3V 10% or 5V 10%
RECOMMENDED DC OPERATING CONDITIONS
(TA = Over the Operating Range.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
VCC = 5V 10% 2.2 VCC
+0.3V V 1
Logic 1 Voltage All Inputs VIH VCC = 3.3V
10% 2.0 VCC
+0.3V V 1
VCC = 5V 10% -0.3 +0.8 V 1
Logic 0 Voltage All Inputs VIL VCC = 3.3V
10% -0.3 +0.6 V 1
DC ELECTRICAL CHARACTERISTICS (5V)
( VCC = 5.0V 10%, TA = Over the Operating Range.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Active Supply Current ICC 15 50 mA 2, 3
TTL Standby Current
(CE = VIH, CE2 = VIL) ICC1 1 3 mA 2, 3
CMOS Standby Current
(CE VCC - 0.2V; CE2 = GND + 0.2V) ICC2 1 3 mA 2, 3
Input Leakage Current (Any Input) IIL -1 +1
A
Output Leakage Current (Any Output) IOL -1 +1
A
Output Logic 1 Voltage
(IOUT = -1.0mA) VOH 2.4 1
Output Logic 0 Voltage
(IOUT = 2.1mA) VOL1 0.4 1
Write-Protection Voltage VPF 4.20 4.50 V 1
Battery Switchover Voltage VSO V
BAT 1, 4
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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DC ELECTRICAL CHARACTERISTICS (3.3V)
(VCC = 3.3V 10%, TA = Over the Operating Range.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Active Supply Current ICC 10 30 mA 2, 3
TTL Standby Current (CE = VIH) ICC1 0.7 2 mA 2, 3
CMOS Standby Current
(CE VCC - 0.2V;
CE2 = GND + 0.2V) ICC2 0.7 2 mA 2, 3
Input Leakage Current
(Any Input) IIL -1 +1
A
Output Leakage Current
(Any Output) IOL -1 +1
A
Output Logic 1 Voltage
(IOUT = -1.0mA) VOH 2.4 1
Output Logic 0 Voltage
(IOUT =2.1mA) VOL1 0.4 1
Write-Protection Voltage VPF 2.75 2.97 V 1
Battery Switchover Voltage VSO
VBAT
or
VPF
V 1, 4
AC CHARACTERISTICS—READ CYCLE (5V)
(VCC = 5.0V 10%, TA = Over the Operating Range.)
ACCESS
70ns 85ns 100ns
PARAMETER SYMBOL
MIN MAX MIN MAX MIN MAX
UNITS NOTES
Read Cycle Time tRC 70 85 100 ns
Address Access Time tAA 70 85 100 ns
CE to CE2 to DQ Low-Z tCEL 5 5 5 ns 5
CE Access Time tCEA 70 85 100 ns 5
CE2 Access Time tCE2A 80 95 105 ns 5
CE and CE2 Data-Off
Time tCEZ 25 30 35 ns
OE to DQ Low-Z tOEL 5 5 5 ns
OE Access Time tOEA 35 45 55 ns
OE Data-Off Time tOEZ 25 30 35 ns
Output Hold from
Address tOH 5 5 5 ns
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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AC CHARACTERISTICS—READ CYCLE (3.3V)
(VCC = 3.3V 10%, TA = Over the Operating Range.) ACCESS
120ns 150ns
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES
Read Cycle Time tRC 120 150 ns
Address Access Time tAA 120 150 ns
CE and CE2 Low to DQ Low-Z tCEL 5 5 ns 5
CE and CE2 Access Time tCEA 120 150 ns 5
CE and CE2 Data-Off time tCEZ 40 50 ns 5
OE Low to DQ Low-Z tOEL 5 5 ns
OE Access Time tOEA 100 130 ns
OE Data-Off Time tOEZ 35 35 ns
Output Hold from Address tOH 5 5 ns
READ CYCLE TIMING DIAGRAM
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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AC CHARACTERISTICS—WRITE CYCLE (5V)
(VCC = 5.0V 10%, TA = Over the Operating Range.) ACCESS
70ns 85ns 100ns
PARAMETER SYMBOL
MIN MAX MIN MAX MIN MAX
UNITS NOTES
Write Cycle Time tWC 70 85 100 ns
Address Setup Time tAS 0 0 0 ns 5
WE Pulse Width tWEW 50 65 70 ns
CE Pulse Width tCEW 60 70 75 ns 5
CE2 Pulse Width tCE2W 65 75 85 ns 5
Data Setup Time tDS 30 35 40 ns 5
Data Hold Time CE tDH 0 0 0 ns 5
Data Hold Time CE2 tDH 8 8 8 ns 5
Address Hold Time tAH 5 5 5 ns 5
WE Data-Off Time tWEZ 25 30 35 ns
Write Recovery Time tWR 10 10 10 ns
AC CHARACTERISTICS—WRITE CYCLE (3.3V)
(VCC = 3.3V 10%, TA = Over the Operating Range.) ACCESS
120ns 150ns
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES
Write Cycle Time tWC 120 150 ns
Address Setup Time tAS 0 0 ns 5
WE Pulse Width tWEW 100 130 ns
CE and CE2 Pulse Width tCEW 110 140 ns 5
Data Setup Time tDS 80 90 ns 5
Data Hold Time CE tDH 0 0 ns 5
Data Hold Time CE2 tDH 10 10 ns 5
Address Hold Time tAH 0 0 ns 5
WE Data-Off Time tWEZ 40 50 ns
Write Recovery Time tWR 10 10 ns
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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WRITE CYCLE TIMING—WRITE-ENABLE CONTROLLED (See Note 5)
WRITE CYCLE TIMING—CE/CE2-CONTROLLED (See Note 5)
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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POWER-UP/DOWN CHARACTERISTICS—5V
(VCC = 5.0V 10%, TA = Over the Operating Range.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CE or WE at VIH, CE2 at VIL, Before
Power-Down tPD 0
s
VCC Fall Time: VPF(MAX) to VPF(MIN) tF 300 s
VCC Fall Time: VPF(MIN) to VSO t
FB 10 s
VCC Rise Time: VPF(MIN) to VPF(MAX) t
R 0
s
Power-Up Recover Time tREC 35 ms
Expected Data-Retention Time
(Oscillator On) tDR 10 years 6, 7
POWER-UP/DOWN TIMING (5V DEVICE)
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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POWER-UP/DOWN CHARACTERISTICS—3.3V
(VCC = 3.3V 10%, TA = Over the Operating Range.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CE or WE at VIH, Before
Power-Down tPD 0 s
VCC Fall Time: VPF(MAX) to VPF(MIN) tF 300 s
VCC Rise Time: VPF(MIN) to VPF(MAX) t
R 0
s
VPF to RST High tREC 35 ms
Expected Data-Retention Time
(Oscillator On) tDR 10 years 6, 7
POWER-UP/DOWN WAVEFORM TIMING (3.3V DEVICE)
CAPACITANCE
(TA = +25C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Capacitance on All Input Pins CIN 7 pF
Capacitance on All Output Pins CO 10 pF
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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AC TEST CONDITIONS
Output Load: 50 pF + 1TTL Gate
Input Pulse Levels: 0 to 3.0V
Timing Measurement Reference Levels:
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
NOTES:
1) Voltages are referenced to ground.
2) Typical values are at +25C and nominal supplies.
3) Outputs are open.
4) Battery switchover occurs at the lower of either the battery terminal voltage or VPF.
5) The CE2 control signal functions the same as the CE signal except that the logic levels for active and
inactive levels are opposite. If CE2 is used to terminate a write, the CE2 data hold time (tDH) applies.
6) Data-retention time is at +25C.
7) Each DS1743 has a built-in switch that disconnects the lithium source until VCC is first applied by the
user. The expected tDR is defined for DIP modules as a cumulative time in the absence of VCC starting
from the time power is first applied by the user.
8) RTC Encapsulated DIP Modules (EDIP) can be successfully processed through conventional wave-
soldering techniques as long as temperatures as long as temperature exposure to the lithium energy
source contained within does not exceed +85C. Post-solder cleaning with water-washing techniques is
acceptable, provided that ultrasonic vibration is not used. See the PowerCap package drawing for
details regarding the PowerCap package.
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
28 EDIP (740) MDF28+2 21-0245
34 PWRCP PC1+2 21-0246
