MCP39F521 I2C Power Monitor with Calculation and Energy Accumulation Features Description * Power Monitoring Accuracy Capable of 0.1% Error Across 4000:1 Dynamic Range * Built-In Calculations on Fast 16-bit Processing Core - Active, Reactive, Apparent Power - True Root Mean Square (RMS) Current, RMS Voltage - Line Frequency, Power Factor * 64-bit Wide Import and Export Active Energy Accumulation Registers * 64-bit Four Quadrant Reactive Energy Accumulation Registers * Signed Active and Reactive Power Outputs * Dedicated Zero Crossing Detection (ZCD) Pin Output with Less than 100 s Latency * Automatic Event Pin Control through Fast Voltage Surge Detection, Less than 5 ms Delay * I2C Interface, up to 400 kHz Clock Rate * Two Independent Registers for Minimum and Maximum Output Quantity Tracking * Fast Calibration Routines and Simplified Command Protocol * 512 Bytes User-Accessible EEPROM through Page Read/Write Commands * Low-Drift Internal Voltage Reference, 10 ppm/C Typical * 28-lead 5 x 5 mm QFN Package * Extended Temperature Range -40C to +125C The MCP39F521 is a highly integrated, complete single-phase power-monitoring device, designed for real-time measurement of input power for AC/DC power supplies, power distribution units, consumer and industrial applications. It includes dual-channel delta-sigma ADCs, a 16-bit calculation engine, EEPROM and a flexible two-wire I2C interface. An integrated low-drift voltage reference with 10 ppm/C in addition to 94.5 dB of signal-to-noise and distortion ratio (SINAD) performance on each measurement channel allows for better than 0.1% accurate designs across a 4000:1 dynamic range. 2015 Microchip Technology Inc. ZCD REFIN+/OUT DVDD DGND MCLR DGND DR 28 27 26 25 24 23 22 EVENT 1 NC 2 21 AGND 20 AN_IN NC 3 19 V1+ EP 29 COMMONB 4 COMMONA 5 18 V117 I116 I1+ OSCI 6 15 A1 OSCO 7 SDA SCL A0 AVDD 8 9 10 11 12 13 14 RESET * Power Monitoring for Home Automation * Industrial Lighting Power Monitoring * Real-Time Measurement of Input Power for AC/DC Supplies * Intelligent Power Distribution Units MCP39F521 5x5 QFN* NC NC Applications Package Types *Includes Exposed Thermal Pad (EP); see Table 3-1. DS20005442A-page 1 MCP39F521 Functional Block Diagram Timing Generation OSCI OSCO V1+ V1- DVDD DGND A1 Internal Oscillator + PGA - 24-bit Delta-Sigma Multi-Level Modulator ADC SINC3 Digital Filter I1- AGND + PGA - 24-bit Delta-Sigma Multi-Level Modulator ADC SINC3 Digital Filter I1+ AVDD AN_IN DS20005442A-page 2 I2C Serial Interface A0 SCL SDA 16-BIT CORE FLASH Calculation Engine (CE) EVENT Digital Outputs ZCD 10-bit SAR ADC 2015 Microchip Technology Inc. MCP39F521 MCP39F521 Typical Application - Single-Phase, Two-Wire Application Schematic 10 1 F LOAD 0.1 F 0.1 F AVDD DVDD RESET 1 k REFIN/OUT+ I1+ + +3.3V 0.1 F 33 nF 2 m - 1 k I133 nF A1 To DVDD or GND, do not float A0 To DVDD or GND, do not float MCP39F521 1 k 3.3 DVDD V133 nF SCL 499 k 499 k 3.3 DVDD V1+ 2 k 33 nF N.C. Leave Floating Connect on PCB to MCU SCL SDA NC NC NC NC DR COMMONA,B Isolation 1 k Isolation 2 k to MCU SDA (OPTIONAL) +3.3V MCP9700A EVENT AN_IN ZCD OSCO 4 MHz OSCI 22 pF DGND AGND 22 pF (OPTIONAL) +3.3V 0.47 F 470 MCP1754 0.01 F N Note: L DGND 470 F AGND The external sensing components shown here, a 2 m shunt, two 499 k and 1 k resistors for the 1000:1 voltage divider, are specifically chosen to match the default values for the calibration registers defined in Section 6.0, Register Descriptions. By choosing low-tolerance components of these values (e.g. 1% tolerance), measurement accuracy in the 2-3% range can be achieved with zero calibration. See Section 8.0, MCP39F521 Calibration for more information. 2015 Microchip Technology Inc. DS20005442A-page 3 MCP39F521 1.0 Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings DVDD .................................................................. -0.3 to +4.5V AVDD .................................................................. -0.3 to +4.0V Digital inputs and outputs w.r.t. AGND ............... -0.3V to +4.0V Analog Inputs (I+,I-,V+,V-) w.r.t. AGND ............... ....-2V to +2V VREF input w.r.t. AGND ........................ ....-0.6V to AVDD +0.6V Maximum Current out of DGND pin..............................300 mA Maximum Current into DVDD pin .................................250 mA Maximum Output Current Sunk by Digital IO ................25 mA Maximum Current Sourced by Digital IO.......................25 mA Storage temperature .....................................-65C to +150C Ambient temperature with power applied......-40C to +125C Soldering temperature of leads (10 seconds) ............. +300C ESD on the analog inputs (HBM,MM) .................4.0 kV, 200V ESD on all other pins (HBM,MM) ........................4.0 kV, 200V 1.1 Specifications TABLE 1-1: ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V, TA = -40C to +125C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Sym. Min. Typ. Max. Units Test Conditions Active Power (Note 1) P -- 0.1 -- % 4000:1 Dynamic Range on Current Channel (Note 2) Reactive Power (Note 1) Q -- 0.1 -- % 4000:1 Dynamic Range on Current Channel (Note 2) Apparent Power (Note 1) S -- 0.1 -- % 4000:1 Dynamic Range on Current Channel (Note 2) Current RMS (Note 1) IRMS -- 0.1 -- % 4000:1 Dynamic Range on Current Channel (Note 2) Voltage RMS (Note 1) VRMS -- 0.1 -- % 4000:1 Dynamic Range on Voltage Channel (Note 2) Power Measurement Power Factor (Note 1) -- 0.1 -- % Line Frequency (Note 1) LF -- 0.1 -- % Note 1: 2: 3: 4: 5: 6: 7: Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 4 line cycles. Specification by design and characterization; not production tested. N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or TCAL = 80 ms for 50 Hz line. Applies to Voltage Sag and Voltage Surge events only. Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0, Typical Performance Curves for typical performance. VIN = 1VPP = 353 mVRMS @ 50/60 Hz. Variation applies to internal clock and I2C only. All calculated output quantities are temperature compensated to the performance listed in the respective specification. DS20005442A-page 4 2015 Microchip Technology Inc. MCP39F521 TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V, TA = -40C to +125C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Sym. Min. Typ. Max. Units Test Conditions -- 2N x (1/fLINE) -- ms Note 3 -- see -- ms Note 4 Calibration, Calculation and Event Detection Times Auto-Calibration Time Minimum Time for Voltage Surge/Sag Detection tCAL tAC_SASU Section 7.0 24-Bit Delta-Sigma ADC Performance Analog Input Absolute Voltage VIN -1 -- +1 V Analog Input Leakage Current AIN -- 1 -- nA -- +600/GAIN mV Differential Input Voltage Range (I1+ - I1-), -600/GAIN (V1+ - V1-) Offset Error VOS Offset Error Drift Gain Error GE -- +1 mV 0.5 -- V/C -4 -- +4 % -- 1 -- ppm/C 232 -- -- k G=1 142 -- -- k G=2 72 -- -- k G=4 38 -- -- k G=8 36 -- -- k G = 16 33 -- -- k G = 32 SINAD 92 94.5 -- dB Note 6 THD -- -106.5 -103 dBc Note 6 Gain Error Drift Differential Input Impedance Signal-to-Noise and Distortion Ratio -1 -- VREF = 1.2V, proportional to VREF ZIN Total Harmonic Distortion Signal-to-Noise Ratio Note 5 SNR 92 95 -- dB Note 6 Spurious Free Dynamic Range SFDR -- 111 -- dB Note 6 Crosstalk CTALK -- -122 -- dB AC Power Supply Rejection Ratio AC PSRR -- -73 -- dB AVDD and DVDD = 3.3V + 0.6VPP, 100 Hz, 120 Hz, 1 kHz DC Power Supply Rejection Ratio DC PSRR -- -73 -- dB AVDD and DVDD = 3 to 3.6V DC Common Mode Rejection Ratio DC CMRR -- -105 -- dB VCM varies from -1V to +1V Note 1: 2: 3: 4: 5: 6: 7: Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 4 line cycles. Specification by design and characterization; not production tested. N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or TCAL = 80 ms for 50 Hz line. Applies to Voltage Sag and Voltage Surge events only. Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0, Typical Performance Curves for typical performance. VIN = 1VPP = 353 mVRMS @ 50/60 Hz. Variation applies to internal clock and I2C only. All calculated output quantities are temperature compensated to the performance listed in the respective specification. 2015 Microchip Technology Inc. DS20005442A-page 5 MCP39F521 TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V, TA = -40C to +125C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Sym. Min. Typ. Max. Units bits Test Conditions 10-Bit SAR ADC Performance for Temperature Measurement Resolution NR -- 10 -- Absolute Input Voltage VIN DGND - 0.3 -- DVDD + 0.3 V Recommended Impedance of Analog Voltage Source RIN -- -- 2.5 k Integral Nonlinearity INL -- 1 2 LSb Differential Nonlinearity DNL -- 1 1.5 LSb GERR -- 1 3 LSb EOFF -- 1 2 LSb -- fLINE/2N -- sps Note 3 fSCL -- -- 400 kHz 100 kHz and 400 kHz I2C modes supported fMCLK -2% 4 +2% MHz Capacitive Loading on OSCO pin COSC2 -- -- 15 pF When an external clock is used to drive the device Internal Oscillator Tolerance fINT_OSC -- 2 -- % -40 to +85C only (Note 7) VREF -2% 1.2 +2% V TCVREF -- 10 -- ZOUTVREF -- 2 -- k AIDDVREF -- 40 -- A -- -- 10 pF AGND + 1.1V -- AGND + 1.3V V Gain Error Offset Error Temperature Measurement Rate Clock and Timings I2C Clock Frequency Master Clock and Crystal Frequency Internal Voltage Reference Internal Voltage Reference Tolerance Temperature Coefficient Output Impedance Current, VREF ppm/C TA = -40C to +85C, VREFEXT = 0 Voltage Reference Input Input Capacitance Absolute Voltage on VREF+ Pin Note 1: 2: 3: 4: 5: 6: 7: VREF+ Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 4 line cycles. Specification by design and characterization; not production tested. N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or TCAL = 80 ms for 50 Hz line. Applies to Voltage Sag and Voltage Surge events only. Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0, Typical Performance Curves for typical performance. VIN = 1VPP = 353 mVRMS @ 50/60 Hz. Variation applies to internal clock and I2C only. All calculated output quantities are temperature compensated to the performance listed in the respective specification. DS20005442A-page 6 2015 Microchip Technology Inc. MCP39F521 TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V, TA = -40C to +125C, MCLK = 4 MHz, PGA GAIN = 1. Characteristic Sym. Min. Typ. Max. Units Operating Voltage AVDD, DVDD 2.7 -- 3.6 V DVDD Start Voltage to Ensure Internal Power-On Reset Signal VPOR DGND -- 0.7 V DVDD Rise Rate to Ensure Internal Power-On Reset Signal SDVDD 0.05 -- -- V/ms AVDD Start Voltage to Ensure Internal Power-On Reset Signal VPOR AGND -- 2.1 V AVDD Rise Rate to Ensure Internal Power On Reset Signal SAVDD 0.042 -- -- V/ms IDD -- 13 -- mA Cell Endurance EPS 100,000 -- -- E/W Self-Timed Write Cycle Time TIWD -- 4 -- ms Number of Total Write/Erase Cycles Before Refresh RREF -- 10,000,000 -- E/W TRETDD 40 -- -- Years IDDPD -- 7 -- mA Test Conditions Power Specifications Operating Current 0 - 3.3V in 0.1s, 0 - 2.5V in 60 ms 0 - 2.4V in 50 ms Data EEPROM Memory Characteristic Retention Supply Current during Programming Note 1: 2: 3: 4: 5: 6: 7: Provided no other specifications are violated Calculated from reading the register values with no averaging, single computation cycle with accumulation interval of 4 line cycles. Specification by design and characterization; not production tested. N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or TCAL = 80 ms for 50 Hz line. Applies to Voltage Sag and Voltage Surge events only. Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0, Typical Performance Curves for typical performance. VIN = 1VPP = 353 mVRMS @ 50/60 Hz. Variation applies to internal clock and I2C only. All calculated output quantities are temperature compensated to the performance listed in the respective specification. 2015 Microchip Technology Inc. DS20005442A-page 7 MCP39F521 TABLE 1-2: SERIAL DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V, TA = -40C to +125C, MCLK = 4 MHz Characteristic Sym. Min. High-Level Input Voltage VIH 0.8 DVDD Low-Level Input Voltage VIL 0 High-Level Output Voltage VOH 3 Low-Level Output Voltage VOL -- ILI Input Leakage Current TABLE 1-3: Typ. Max. Units Test Conditions -- DVDD V -- 0.2 DVDD V -- -- V IOH = -3.0 mA, VDD = 3.6V -- 0.4 V IOL = 4.0 mA, VDD = 3.6V -- -- 1 A -- 0.050 0.100 A Digital Output pins only (ZCD, EVENT) TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V. Parameters Sym. Min. Typ. Max. Units Operating Temperature Range TA -40 -- +125 C Storage Temperature Range TA -65 -- +150 C JA -- 36.9 -- C/W Conditions Temperature Ranges Thermal Package Resistances Thermal Resistance, 28LD 5x5 QFN DS20005442A-page 8 2015 Microchip Technology Inc. MCP39F521 2.0 TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: 0.50% 0.40% 0.30% 0.20% 0.10% 0.00% -0.10% -0.20% -0.30% -0.40% -0.50% 0.01 0.1 1 10 100 1000 Current Channel Input Amplitude (mVPEAK) FIGURE 2-1: Active Power, Gain = 1. 0 fIN = -60 dBFS @ 60 Hz fD = 3.9 ksps 16384 pt FFT OSR = 256 -20 -40 Amplitude (dB) Measurement Error (%) Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V, TA = +25C, GAIN = 1, VIN = -0.5 dBFS at 60 Hz. -60 -80 -100 -120 -140 -160 -180 -200 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency (Hz) FIGURE 2-4: Spectral Response. RMS Current, Gain = 1. 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 1 10 100 1000 10000 -105.8 -105.9 -106.1 -106.2 Total Harmonic Distortion (-dBc) FIGURE 2-5: Total HDrmonic Distortion(dBc) Energy Accumulation Error (%) FIGURE 2-2: 1000 -106.4 1 10 100 Input Voltage RMS (mVPP) -106.5 0.1 -106.7 -0.100% -106.8 -0.050% -107.0 0.000% -107.1 0.050% -107.3 Frequency of Occurrence RMS Current Error (%) 0.100% 100000 THD Histogram. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 G=1 G=8 -50 -25 0 G=2 G = 16 25 50 75 Temperature (C) G=4 G = 32 100 125 150 Energy Accumulation (Watt-Hours) FIGURE 2-3: Energy, Gain = 8. 2015 Microchip Technology Inc. FIGURE 2-6: THD vs. Temperature. DS20005442A-page 9 MCP39F521 Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V, TA = +25C, GAIN = 1, VIN = -0.5 dBFS at 60 Hz. Frequency of Occurrence Internal Voltage Reference (V) 1.2008 94.2 94.3 94.5 94.6 94.8 94.9 95.1 95.2 95.4 95.5 Signal-to-Noise and Distortion Ratio (dB) Signal-to-Noise and Distortion Ratio (dB) FIGURE 2-7: SNR Histogram. 100 90 80 70 60 50 40 30 20 10 0 G=1 G=8 -50 -25 0 FIGURE 2-8: G=2 G = 16 1.2007 1.2006 1.2005 1.2004 1.2003 1.2002 1.2001 1.2000 1.1999 -50 FIGURE 2-10: vs. Temperature. 0 50 100 Temperature (C) 150 Internal Voltage Reference G=4 G = 32 25 50 75 100 125 150 Temperature (C) SINAD vs. Temperature. 5 4 Gain Error (%) 3 2 1 0 -1 -2 -3 G=1 G=8 -4 -5 -50 -25 0 25 G=2 G = 16 50 75 G=4 G = 32 100 125 150 Temperature (C) FIGURE 2-9: DS20005442A-page 10 Gain Error vs. Temperature. 2015 Microchip Technology Inc. MCP39F521 3.0 PIN DESCRIPTION The description of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP39F521 5x5 QFN Symbol Function 1 EVENT 2, 3, 8, 9 NC 4 COMMONB Common pin B, to be connected to COMMONA 5 COMMONA Common pin A, to be connected to COMMONB 3.1 Event Output Pin No Connect (must be left floating) 6 OSCI Oscillator Crystal Connection Pin or External Clock Input Pin 7 OSCO Oscillator Crystal Connection Pin 10 RESET Reset Pin for Delta Sigma ADCs 11 AVDD Analog Power Supply Pin 12 A0 I2C Address Select Pin A0 13 SCL I2C Serial Clock 14 SDA I2C Serial Data 15 A1 I2C Address Select Pin A1 16 I1+ Noninverting Current Channel Input for 24-bit ADC 17 I1- Inverting Current Channel Input for 24-bit ADC 18 V1- Inverting Voltage Channel Input for 24-bit ADC Noninverting Voltage Channel Input for 24-bit ADC 19 V1+ 20 AN_IN Analog Input for SAR ADC 21 AGND Analog Ground Pin, Return Path for internal analog circuitry 22 ZCD Zero Crossing Detection Output 23 REFIN+/OUT Noninverting Voltage Reference Input and Internal Reference Output Pin 24, 27 DGND Digital Ground Pin, Return Path for internal digital circuitry 25 DVDD Digital Power Supply Pin 26 MCLR Master Clear for Device 28 DR Data Ready (must be left floating) 29 EP Exposed Thermal Pad (to be connected to DGND) Event Output Pin (EVENT) This digital output pin can be configured to act as an output flag based on various internal raise conditions. Control is modified through the Event Configuration register. 3.2 Common Pins (COMMONA and COMMONB) The COMMONA and COMMONB pins are internal connections for the MCP39F521. These two pins should be connected together in the application. 2015 Microchip Technology Inc. 3.3 Oscillator Pins (OSCI/OSCO) OSCI and OSCO provide the master clock for the device. Appropriate load capacitance should be connected to these pins for proper operation. An optional 4 MHz crystal can be connected to these pins. If a crystal of external clock source is not detected, the device will clock from the internal 4 MHz oscillator. 3.4 Reset Pin (RESET) This pin is active-low and places the delta-sigma ADCs, PGA, internal VREF and other blocks associated with the analog front-end in a Reset state when pulled low. This input is Schmitt-triggered. DS20005442A-page 11 MCP39F521 3.5 Analog Power Supply Pin (AVDD) AVDD is the power supply pin for the analog circuitry within the MCP39F521. This pin requires appropriate bypass capacitors and should be maintained to 2.7V and 3.6V for specified operation. It is recommended to use 0.1 F ceramic capacitors. 3.6 Chip Address Inputs (A0, A1) 3.10 24-Bit Delta Sigma ADC Differential Voltage Channel Inputs (V1-/V1+) V1- and V1+ are the two fully-differential voltage channel inputs for the Delta-Sigma ADCs. The linear and specified region of the channels are dependent on the PGA gain. This region corresponds to a differential voltage range of 600 mVPEAK/GAIN with VREF = 1.2V. The A0 and A1 inputs are used by the MCP39F521 for multiple device operations. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. The maximum absolute voltage, with respect to AGND, for each VN+/- input pin is 1V with no distortion and 2V, with no breaking after continuous voltage. Up to four devices may be connected to the same bus by using different combinations. These inputs must be connected to VDD or GND and cannot be left floating. 3.11 In most applications, the chip address inputs are hardwired to logic 0 or logic 1. For applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic 0 or logic 1 before normal device operation can proceed. 3.7 I2C Serial Clock (SCL) This input is used to synchronize the data transfer to and from the device. 3.8 I2C Serial Data (SDA) This is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open drain terminal. Therefore, the SDA bus requires a pull-up resistor to DVDD (typical 10k for 100kHz, 2k for 400kHz). Analog Input (AN_IN) This is the input to the analog-to-digital converter that can be used for temperature measurement and compensation. If temperature compensation is required in the application, it is advised to connect the low-power active thermistor IC MCP9700A to this pin. If temperature compensation is not required, this can be used as a general purpose analog-to-digital converter input. 3.12 Analog Ground Pin (AGND) AGND is the ground connection to internal analog circuitry (ADCs, PGA, voltage reference, POR). If an analog ground pin is available on the PCB, it is recommended that this pin be tied to that plane. 3.13 Zero Crossing Detection (ZCD) For normal data transfer, SDA is allowed to change only during SCL low. Change during SCL high is reserved for indicating the Start and Stop conditions. This digital output pin is the output of the Zero Crossing Detection circuit of the IC. The output here will be a logic output with edges that transition at each zero crossing of the voltage channel input. For more information see Section 5.13, Zero Crossing Detection (ZCD). 3.9 3.14 24-Bit Delta Sigma ADC Differential Current Channel Input Pins (I1+/I1-) I1- and I1+ are the two fully-differential current channel inputs for the Delta-Sigma ADCs. The linear and specified region of the channels are dependent on the PGA gain. This region corresponds to a differential voltage range of 600 mVPEAK/GAIN with VREF = 1.2V. The maximum absolute voltage, with respect to AGND, for each In+/- input pin is 1V with no distortion and 6V with no breaking after continuous voltage. DS20005442A-page 12 Noninverting Reference Input/Internal Reference Output Pin (REFIN+/OUT) This pin is the noninverting side of the differential voltage reference input for the delta sigma ADCs or the internal voltage reference output. For optimal performance, bypass capacitances should be connected between this pin and AGND at all times, even when the internal voltage reference is used. However, these capacitors are not mandatory to ensure proper operation. 2015 Microchip Technology Inc. MCP39F521 3.15 Digital Ground Connection Pins (DGND) DGND is the ground connection to internal digital circuitry (SINC filters, oscillator, serial interface). If a digital ground plane is available, it is recommended to tie this pin to the digital plane of the PCB. This plane should also reference all other digital circuitry in the system. 3.16 Digital Power Supply Pin (DVDD) DVDD is the power supply pin for the digital circuitry within the MCP39F521. This pin requires appropriate bypass capacitors and should be maintained between 2.7V and 3.6V for specified operation. It is recommended to use 0.1 F ceramic capacitors. 3.17 Data Ready Pin (DR) The data ready pin indicates if a new delta-sigma A/D conversion result is ready to be processed. This pin is for indication only and should be left floating. After each conversion is finished, a low pulse will take place on the Data Ready pin to indicate that the conversion result is ready and an interrupt is generated in the calculation engine (CE). This pulse is synchronous with the line frequency to ensure an integer number of samples for each line cycle. Note: 3.18 This pin is internally connected to the IRQ of the calculation engine and should be left floating. Exposed Thermal Pad (EP) This pin is the exposed thermal pad. It must be connected to DGND. 2015 Microchip Technology Inc. DS20005442A-page 13 MCP39F521 NOTES: DS20005442A-page 14 2015 Microchip Technology Inc. MCP39F521 4.0 COMMUNICATION PROTOCOL The I2C communication protocol is a frame-based protocol, with a complete communication frame occurring between the I2C start and stop bits. A command frame is a write transmission from the I2C master to the MCP39F521 device. Each command frame consists of a header byte, the number of bytes in the frame, command packet (or command packets) and a checksum. Each response frame consists of either a ACK, NAK, CSFAIL, or ACK+Data with checksum. If a custom communication protocol is desired, please contact a Microchip sales office. Note: A read response frame is read transmission from the I2C master to the MCP39F521. 4.1 COMMUNICATION FRAMES The following two figures represent the command frames and read request frames. Frame Byte 1 Frame Byte 2 Header Byte (0xA5) Number of Bytes Command Frame Frame Byte 3 ... Command Packet1 Command Packet2 Frame Byte N ...Command Packet n Checksum Command BYTE1 BYTE2 BYTE N BYTE0 BYTE N FIGURE 4-1: MCP39F521 Command Write Frame. Frame Byte 1 Frame Byte 2 ACK (0x06) Number of Bytes FIGURE 4-2: Read Response Frame Frame Byte 3 Frame Byte 4 Data Byte 1 Data Byte 2 ... Frame Byte N-1 ...Data Byte N Frame Byte N Checksum MCP39F521 Read Response Frame (ACK with Data). The following two figures represent I2C command frame writes and read frame responses. S Bus Activity T Command A Control Byte Master Frame Byte 1 R T SDA Line A S1 1101A 1000 A Bus Activity C K FIGURE 4-3: 0 A C K 0 A C K Command Frame Byte N 0 A C K S T O P 0P A C K I2C Command Write Frame. S Response Bus Activity T A Control Byte Master Frame Byte 1 R T SDA Line AA S1 11011010 A Bus Activity C K FIGURE 4-4: Command Frame Byte 3 Command Frame Byte 2 Response Frame Byte 2 0 A C K Frame Byte N Frame Byte 3 0 A C K 0 A C K S T O P 1P N O A C K I2C Read Response Frame. 2015 Microchip Technology Inc. DS20005442A-page 15 MCP39F521 This approach allows for single, secure transmission from the host processor to the MCP39F521 with either a single command, or multiple commands. No command in a frame is processed until the frame is complete and the checksum and number of bytes are validated after the stop bit. The number of bytes in an individual command packet depends on the specific command. For example, to set the instruction pointer, three bytes are needed in the packet: the command byte and two bytes for the address you want to set to the pointer. The first byte in a command packet is always the command byte. 4.2 I2C CONTROL BYTE A Control byte is the first byte received following the Start condition from the master device. The Control byte consists of a 4-bit control code. For the MCP39F521 the control code is `1110' for all read and write operations. The following three bits are chip-select address bits, A2, A1, and A0. For the MCP39F521, A2 is always set to binary `1'. A1 and A0 are controlled by the logic pins A1 and A0, which allows up to 4 different devices on the I2C bus. The last bit of the Control byte defines the operation to be performed. When set to `1', a read operation is selected. When set to `0', a write operation is selected. Following a Start condition, the MCP39F521 monitors the SDA bus checking for the 4-bit control code (`1110') and proper address bits. Upon receiving the correct control code and address bits, the slave (MCP39F521) outputs an acknowledge signal on the SDA line, and depending on the state of the R/W bit, will either respond with data or wait to receive additional bytes prior to the Stop condition. The Control byte is defined in the following figure. 4.3 I2C Time Out and Clock Stretching Time out is when an I2C slave resets its interface if the I2C clock is low for longer than a specified time. The MCP39F521 offers a set 2 ms I2C time out that can be disabled through the Time-out Disable bit in the System Configuration Register (Register 6-2). In addition, the device includes a clock stretching feature which allows the master to know when a frame has been processed. Clock stretching is when a slave device can not cooperate with the clock speed or needs to slow down the bus. In the case of the MCP39F521, after a frame is received, the device will hold the clock low until the frame has been processed. The maximum clock stretching duration is less than 10 milliseconds. 4.4 Checksum The checksum is generated using simple byte addition and taking the modulus to find the remainder after dividing the sum of the entire frame by 256. This operation is done to obtain an 8-bit checksum. All the bytes of the frame are included in the checksum, including the header byte and number of bytes. If a frame includes multiple command packets, none of the commands will be issued if the frame checksum fails. In this instance, the MCP39F521 will respond with a CSFAIL response of 0x51. On commands that are requesting data back from the MCP39F521, the frame and checksum are created in the same way, with the header byte becoming an acknowledge (0x06). Communication examples are given in Section 4.6, Example Communication Frames and MCP39F521 Responses. Read/Write Bit Chip Select Bits Control Code S 1 Start Bit FIGURE 4-5: 1 1 0 1 A1 A0 R/W ACK Slave Address Acknowledge Bit MCP39F521 Control Byte Format. DS20005442A-page 16 2015 Microchip Technology Inc. MCP39F521 4.5 Command List The following table is a list of all accepted command bytes for the MCP39F521. There are 10 possible accepted commands for the MCP39F521. TABLE 4-1: MCP39F521 INSTRUCTION SET Command # Command Command ID Instruction Parameter Number of Bytes Successful Response 1 Register Read, N bytes 0x4E Number of Bytes 2 ACK, Data, Checksum 2 Register Write, N bytes 0x4D Number of Bytes 1+N ACK 3 Set Address Pointer 0x41 ADDRESS 3 ACK 4 Save Registers To Flash 0x53 None 2 ACK 5 Page Read EEPROM 0x42 PAGE 2 ACK, Data, Checksum 6 Page Write EEPROM 0x50 PAGE 18 ACK 7 Bulk Erase EEPROM 0x4F None 2 8 Auto-Calibrate Gain 0x5A None 9 Auto-Calibrate Reactive Gain 0x7A None Note 1 10 Auto-Calibrate Frequency 0x76 None Note 1 Note 1: 4.6 ACK Note 1 See Section 8.0, MCP39F521 Calibration for more information on calibration. Example Communication Frames and MCP39F521 Responses Tables 4-2 to 4-11 show exact hexadecimal communication frames as they should be sent to the MCP39F521 from the system MCU. The values here can be used as direct examples for writing your code to communicate to the MCP39F521. TABLE 4-2: REGISTER READ, N BYTES COMMAND (Note 1) Byte # Value Byte Description 1 0xA5 Header Byte 2 0x08 Number of Bytes in Frame 3 0x41 Command (Set Address Pointer) 4 0x00 Address High 5 0x02 Address Low 6 0x4E Command (Register Read, N bytes) 7 0x20 Number of Bytes to Read (32) 8 0x5E Checksum Note 1: Response from MCP39F521 ACK + Number of Bytes (35) + 32 bytes, + Checksum This example Register Read, N bytes frame, as written here, can be used to poll a subset of the output data, starting at the top, address 0x02, and reading 32 data bytes back or 35 bytes total in the frame. 2015 Microchip Technology Inc. DS20005442A-page 17 MCP39F521 TABLE 4-3: REGISTER WRITE, N- BYTES COMMAND (Note 1) Byte # Value Byte Description 1 0xA5 2 0x25 Number of Bytes in Frame 3 0x41 Command (Set Address Pointer) 4 0x00 Address High 5 0x48 Address Low Response from MCP39F521 Header Byte 6 0x4D Command (Register Write, N Bytes) 7 0x1C Number of Bytes to Write (28) 8-36 *Data* Data Bytes (28 total data bytes) 37 Checksum Note 1: Checksum ACK This Register Write, N Bytes frame, as written here, can be used to write the entire set of calibration target data, starting at the top, address 0x7A, and continuing to write until the end of this set of registers, 28 bytes later, register 0x94. Note these are not the calibration registers, but the calibration targets which need to be written prior to issuing the auto-calibration target commands. See Section 8.0, MCP39F521 Calibration for more information. TABLE 4-4: SET ADDRESS POINTER COMMAND (Note 1) Byte # Value Byte Description 1 0xA5 Header Byte 2 0x06 Number of Bytes in Frame 3 0x41 Command (Set Address Pointer) 4 0x00 Address High 5 0x02 Address Low 6 0xEE Checksum Note 1: Response from MCP39F521 ACK The Set Address Pointer command is typically included inside of a frame that includes a read or write command, as shown in Table 4-2 and Table 4-3. There is typically no reason for this command to have its own frame, but is shown here as an example. TABLE 4-5: SAVE TO FLASH COMMAND Byte # Value 1 0xA5 Header Byte 2 0x04 Number of Bytes in Frame 3 0x53 Command (Save To Flash) 4 0xFC Checksum TABLE 4-6: Byte Description Response from MCP39F521 ACK PAGE READ EEPROM COMMAND Byte # Value 1 0xA5 Header Byte 2 0x05 Number of Bytes in Frame 3 0x42 Command (Page Read EEPROM) 4 0x01 Page Number (e.g. 1) 5 0xED Checksum DS20005442A-page 18 Byte Description Response from MCP39F521 ACK + EEPROM Page Data + Checksum 2015 Microchip Technology Inc. MCP39F521 TABLE 4-7: PAGE WRITE EEPROM COMMAND Byte # Value 1 0xA5 Header Byte 2 0x15 Number of Bytes in Frame 3 0x50 Command (Page Write EEPROM) Page Number (e.g. 1) 4 0x01 5-20 *Data* 21 Checksum TABLE 4-8: Byte Description Response from MCP39F521 EEPROM Data (16 bytes/Page) Checksum ACK BULK ERASE EEPROM COMMAND Byte # Value 1 0xA5 Header Byte 2 0x04 Number of Bytes in Frame 3 0x4F Command (Bulk Erase EEPROM) 4 0xF8 Checksum TABLE 4-9: Byte Description ACK AUTO-CALIBRATE GAIN COMMAND Byte # Value 1 0xA5 Header Byte 2 0x04 Number of Bytes in Frame 3 0x5A Command (Auto-Calibrate Gain) 4 0x03 Checksum TABLE 4-10: Byte Description Response from MCP39F521 ACK (or NAK if unable to calibrate), see Section 8.0, MCP39F521 Calibration for more information. AUTO-CALIBRATE REACTIVE GAIN COMMAND Byte # Value Byte Description Response from MCP39F521 1 0xA5 Header Byte 2 0x04 Number of Bytes in Frame 3 0x7A Command (Auto-Calibrate Reactive Gain) 4 0x23 Checksum TABLE 4-11: Response from MCP39F521 ACK (or NAK if unable to calibrate), see Section 8.0, MCP39F521 Calibration for more information. AUTO-CALIBRATE FREQUENCY COMMAND Byte # Value Byte Description 1 0xA5 Header Byte 2 0x04 Number of Bytes in Frame 3 0x76 Command (Auto-Calibrate Frequency) 4 0x1F Checksum 2015 Microchip Technology Inc. Response from MCP39F521 ACK (or NAK if unable to calibrate), see Section 8.0, MCP39F521 Calibration for more information. DS20005442A-page 19 MCP39F521 4.7 4.7.1 Command Descriptions REGISTER READ, N BYTES (0x4E) 4.7.6 PAGE WRITE EEPROM (0x50) The Page Write EEPROM command is expecting 17 additional bytes in the command parameters, which are the EEPROM page plus 16 bytes of data. A more complete description of the memory organization of the EEPROM can be found in Section 9.0, EEPROM The response to this command is an acknowledge. The Register Read, N bytes command returns the N bytes that follow whatever the current address pointer is set to. It should typically follow a Set Address Pointer command and can be used in conjunction with other read commands. An acknowledge, data and checksum is the response for this command. The maximum number of bytes that can be read with this command is 32. If there are other read commands within a frame, the maximum number of bytes that can be read is 32 minus the number of bytes being read in the frame. With this command, the data is returned LSB first. The Bulk Erase EEPROM command will erase the entire EEPROM array and return it to a state of 0xFFFF for each memory location of EEPROM. A more complete description of the memory organization of the EEPROM can be found in Section 9.0, EEPROM. The response to this command is acknowledge. 4.7.2 4.7.8 REGISTER WRITE, N BYTES (0x4D) The Register Write, N bytes command is followed by N bytes that will be written to whatever the current address pointer is set to. It should typically follow a Set Address Pointer command and can be used in conjunction with other write commands. An acknowledge is the response for this command. The maximum number of bytes that can be written with this command is 32. If there are other write commands within a frame, the maximum number of bytes that can be written is 32 minus the number of bytes being written in the frame. With this command, the data is written LSB first. 4.7.3 SET ADDRESS POINTER (0x41) This command is used to set the address pointer for all read and write commands. This command is expecting the address pointer as the command parameter in the following two bytes, address high byte followed by address low byte. The address pointer is two bytes in length. If the address pointer is within the acceptable addresses of the device, an acknowledge will be returned. 4.7.4 SAVE REGISTERS TO FLASH (0x53) The Save Registers To Flash command makes a copy of all the calibration and configuration registers to flash. This includes all R/W registers in the register set. The response to this command is an acknowledge. 4.7.5 4.7.7 BULK ERASE EEPROM (0x4F) AUTO-CALIBRATE GAIN (0x5A) The Auto-Calibrate Gain command initiates the single-point calibration that is all that is typically required for the system. This command calibrates the RMS current, RMS voltage and active power based on the target values written in the corresponding registers. See Section 8.0, MCP39F521 Calibration for more information on device calibration. The response to this command is acknowledge. 4.7.9 AUTO-CALIBRATE REACTIVE GAIN (0X7A) The Auto-Calibrate Reactive Gain command initiates a single-point calibration to match the measured reactive power to the target reactive power. This is typically done at PF = 0.5. See section Section 8.0, MCP39F521 Calibration for more information on device calibration. 4.7.10 AUTO-CALIBRATE FREQUENCY (0x76) For applications not using an external crystal and running the MCP39F521 off the internal oscillator, a gain calibration to the line frequency indication is required. The Gain Line Frequency (0x00AE) register is set such that the frequency indication matches what is set in the Line Frequency Reference (0x0094) register. See Section 8.0, MCP39F521 Calibration for more information on device calibration. PAGE READ EEPROM (0x42) The Read Page EEPROM command returns 16 bytes of data that are stored in an individual page on the MCP39F521. A more complete description of the memory organization of the EEPROM can be found in Section 9.0, EEPROM. This command is expecting the EEPROM page as the command parameter or the following byte. The response to this command is an acknowledge, 16-bytes of data and CRC checksum. DS20005442A-page 20 2015 Microchip Technology Inc. MCP39F521 4.8 Notation for Register Types The following notation has been adopted for describing the various registers used in the MCP39F521: TABLE 4-12: Notation SHORT-HAND NOTATION FOR REGISTER TYPES Description u64 Unsigned, 64-bit register u32 Unsigned, 32-bit register s32 Signed, 32-bit register u16 Unsigned, 16-bit register s16 Signed, 16-bit register b32 32-bit register containing discrete Boolean bit settings 2015 Microchip Technology Inc. DS20005442A-page 21 MCP39F521 5.0 CALCULATION ENGINE (CE) DESCRIPTION 5.1 Computation Cycle Overview The MCP39F521 uses a coherent sampling algorithm to phase lock the sampling rate to the line frequency with an integer number of samples per line cycle, and reports all power output quantities at a 2N number of line cycles. This is defined as a computation cycle and is dependent on the line frequency, so any change in the line frequency will change the update rate of the output power quantities. 5.2 Accumulation Interval Parameter 24-bit ADC Multi-Level Modulator + PGA - I1+ I1- SINC3 Digital Filter The accumulation interval is defined as an 2N number of line cycles, where N is the value in the Accumulation Interval Parameter register. CHANNEL I1 5.3 Raw Voltage and Currents Signal Conditioning The first set of signal conditioning that occurs inside the MCP39F521 is shown in Figure 5-1. All conditions set in this diagram effect all of the output registers (RMS current, RMS voltage, active power, reactive power, apparent power, etc.). The gain of the PGA, the Shutdown and Reset status of the 24-bit ADCs are all controlled through the System Configuration register (Register 6-2). For DC applications, offset can be removed by using the DC Offset Current register. To compensate for any external phase error between the current and voltage channels, the Phase Compensation register can be used. See Section 8.0, MCP39F521 Calibration for more information on device calibration. + + HPF 1 i DC Offset Current:s16 SystemConfiguration:b32 V1- 24-bit ADC Multi-Level Modulator SINC3 + PGA - V1+ Digital Filter PhaseCompensation:s16 CHANNEL V1 Note 1: HPF 1 v High-Pass Filters (HPFs) are automatically disabled in the absence of an AC signal on the voltage channel. FIGURE 5-1: 5.4 Channel I1 and V1 Signal Flow. RMS Current and RMS Voltage The MCP39F521 device provides true RMS measurements. The MCP39F521 device has two simultaneous sampling 24-bit A/D converters for the current and voltage measurements. The root mean square calculations are performed on 2N current and voltage samples, where N is defined by the register Accumulation Interval Parameter. EQUATION 5-1: RMS CURRENT AND VOLTAGE N 2 -1 I RMS = N 2 -1 in 2 n=0 ----------------------------N 2 DS20005442A-page 22 V RMS = vn 2 n=0 -----------------------------N 2 2015 Microchip Technology Inc. MCP39F521 Range:b32 X i 2N-1 0 / 2 N ACCU + X /2RANGE CurrentRMS:u32 + GainCurrentRMS:u16 OffsetCurrentRMS:s32 X ApparentPower:u32 GainVoltageRMS:u16 X v FIGURE 5-2: 5.5 2N-1 0 / 2 X N ACCU /2RANGE VoltageRMS:u16 RMS Current and Voltage Calculation Signal Flow. Power and Energy The MCP39F521 offers signed power numbers for active and reactive power, import and export registers for active energy, and four-quadrant reactive power measurement. For this device, import power or energy is considered positive (power or energy being consumed by the load), and export power or energy is considered negative (power or energy being delivered by the load). The following figure represents the measurements obtained by the MCP39F521. Import Reactive Power Consume, Inductive Generate, Inductive -P, +Q Quadrant II Quadrant I +P, +Q S Q P Import Active Power Export Active Power Quadrant III Generate, Capacitive Quadrant IV Consume, Capacitive +P, -Q -P, -Q Export Reactive Power FIGURE 5-3: The Power Circle and Triangle (S = Apparent, P = Active, Q = Reactive). 2015 Microchip Technology Inc. DS20005442A-page 23 MCP39F521 5.6 Energy Accumulation 5.8 Energy accumulation for all four energy registers (import/export, active/reactive) occurs at the end of each computation cycle, if the energy accumulation has been turned on. See Section 6.3, System Status Register on the Energy Control register. A no-load threshold test is done to make sure the measured energy is not below the no-load threshold; if it is above the no-load threshold, the accumulation occurs with a default energy resolution of 1mWh for all of the energy registers. 5.6.1 The MCP39F521 has two simultaneous sampling A/D converters. For the active power calculation, the instantaneous current and instantaneous voltages are multiplied together to create instantaneous power. This instantaneous power is then converted to active power by averaging or calculating the DC component. Equation 5-4 controls the number of samples used in this accumulation prior to updating the Active Power output register. Please note that although this register is unsigned, the direction of the active power (import or export) can be determined by the Active Power Sign bit (SIGN_PA) located in the System Status register (Register 6-1). NO-LOAD THRESHOLD The no-load threshold is set by modifying the value in the No-Load Threshold register. The unit for this register is power with a default resolution of 0.01W. The default value is 100 or 1.00W. Any power that is below 1W will not be accumulated into any of the energy registers. 5.7 Active Power (P) EQUATION 5-4: ACTIVE POWER 1 P = ------N 2 Apparent Power (S) N k=2 -1 Vk Ik k=0 This 32-bit register is the output register for the final apparent power indication. It is the product of RMS current and RMS voltage as shown in Equation 5-2. EQUATION 5-2: APPARENT POWER (S) S = I RMS V RMS For scaling of the apparent power indication, the calculation engine uses the register Apparent Power Divisor. This is described in the following register operations, per Equation 5-3. EQUATION 5-3: APPARENT POWER (S) CurrentRMS VoltageRMS S = --------------------------------------------------------------------ApparentPowerDivisor 10 GainActivePower:u16 i Range:b32 X v FIGURE 5-4: DS20005442A-page 24 2N-1 0 / 2 ACCU N + X /2RANGE ActivePower:u32 + OffsetActivePower:s32 Active Power Calculation Signal Flow. 2015 Microchip Technology Inc. MCP39F521 5.9 Power Factor (PF) Power factor is calculated by the ratio of P to S or active power divided by apparent power. EQUATION 5-5: POWER FACTOR P PF = --S The Power Factor Reading is stored in a signed 16-bit register (Power Factor). This register is a signed, two's complement register with the MSB representing the polarity of the power factor. Positive means inductive load, negative means capacitive load. Each LSB is then equivalent to a weight of 2-15. A maximum register value of 0x7FFF corresponds to a power factor of 1. The minimum register value of 0x8000 corresponds to a power factor of -1. 5.10 Reactive Power (Q) In the MCP39F521, Reactive Power is calculated using a 90 degree phase shift in the voltage channel. The same accumulation principles apply as with active power where ACCU acts as an accumulator. Any light load or residual power can be removed by using the Offset Reactive Power register. Gain is corrected by the Gain Reactive Power register. The final output is an unsigned 32-bit value located in the Reactive Power register. Please note that although this register is unsigned, the direction of the power can be determined by the Reactive Power Sign bit (SIGN_PR) in the System Status register (Register 6-1). GainReactivePower:u16 i HPF Range:b32 X v FIGURE 5-5: 2N-1 0 / 2 N ACCU1 + - X /2RANGE ReactivePower:u32 OffsetReactivePower:s32 HPF (+90deg.) Reactive Power Calculation Signal Flow. 2015 Microchip Technology Inc. DS20005442A-page 25 MCP39F521 5.11 10-Bit Analog Input The least 10 significant bits of the 16-bit Analog Input register contain the output of the 10-bit ADC. The conversion rate of the analog input occurs once every computation cycle. The Thermistor Voltage can be used for temperature compensation of the calculation engine. See Section 8.7, Temperature Compensation for more information. MCP9700 10-bit ADC AnalogInput:u16 5.13 Zero Crossing Detection (ZCD) The Zero Crossing Detection block generates a logic pulse output on the ZCD pin that is coherent with the zero crossing of the input AC signal present on voltage input pins (V1+, V1-). The ZCD pin can be enabled and disabled by the corresponding bit (ZCD_OUTPUT_DIS) in the System Configuration register (Register 6-2). When enabled, this produces a square wave with a frequency that is twice that of the AC signal present on the voltage input. Figure 5-7 represents the signal on the ZCD pin superimposed with the AC signal present on the voltage input in this mode. <100 s FIGURE 5-6: Using an Analog Out-Temperature Sensor for Automatic Temperature Compensation. 5.12 Minimum and Maximum Recordings The MCP39F521 has the ability to record minimum and maximum outputs and keep them in a total of four registers (two minimum and two maximum) based on the value of address pointers located in the four registers listed below. A minimum and maximum test is done after each calculation interval. If the current measurement value of the value directed to by the pointer is smaller or larger than the value in the Minimum or Maximum register, the record is updated appropriately. FIGURE 5-7: Zero Crossing Detection Operation (Noninverted, Non-Pulsed). A second mode is available that produces a 100 s pulse (ZCD_PULS) at each zero crossing, shown in Figure 5-8. <100 s The registers are listed as follows: * MinMaxPointer1 MinimumRecord1, MaximumRecord1 * MinMaxPointer2 MinimumRecord2, MaximumRecord2 Only the output quantity register addresses can be tracked by the Min/Max pointers. Output quantity registers are defined as those from Voltage RMS to Apparent Power (addresses 0x0006 to 0x001A). All other addresses will be ignored by the calculation engine. Please note that the 64-bit energy registers can not be tracked through the Minimum and Maximum recording registers. FIGURE 5-8: Zero Crossing Detection Operation (Noninverted, Pulsed). Switching modes is done by setting the corresponding bit in the System Configuration register (Register 6-2). In addition, either the toggling of this pin, or the pulse, can be inverted. The ZCD Inversion bit (ZCD_INV) is also in the System Configuration register (Register 6-2). There are two bits in the System Configuration register that can be used to modify the zero crossing. The zero crossing output can be inverted by setting the Inversion bit, or the zero crossing can be a 100 s pulse at each zero crossing, by setting the Pulse Bit. Note that a low-pass filter is included in the signal path that allows the zero crossing detection circuit to filter out the fundamental frequency. An internal compensation circuit is then used to gain back the phase delay introduced by the low-pass filter resulting in a latency of less than 100 s. DS20005442A-page 26 2015 Microchip Technology Inc. MCP39F521 6.0 REGISTER DESCRIPTIONS 6.1 Complete Register Map The following table describes the registers for the MCP39F521 device. TABLE 6-1: MCP39F521 REGISTER MAP Address Register Name Section Read/ Data Number Write Type Description Output Registers 0x0000 Instruction Pointer 6.2 R u16 Address pointer for read or write commands 0x0002 System Status 6.3 R b16 System Status Register 0x0004 System Version 6.4 R u16 System version date code information for MCP39F521, set at Microchip factory; format YMDD 0x0006 Voltage RMS 5.4 R u16 RMS Voltage output 0x0008 Line Frequency 8.6 R u16 Line Frequency output 0x000A Analog Input Voltage 5.11 R u16 Output of the 10-bit SAR ADC 0x000C Power Factor 5.9 R s16 Power Factor output 0x000E Current RMS 5.4 R u32 RMS Current output 0x0012 Active Power (Note 1) 5.8 R u32 Active Power output 0x0016 Reactive Power (Note 1) 5.10 R u32 Reactive Power output 0x001A Apparent Power 5.7 R u32 Apparent Power output 0x001E Import Active Energy Counter 5.6 R u64 Accumulator for Active Energy, Import 0x0026 5.6 R u64 Accumulator for Active Energy, Export 0x002E Import Reactive Energy Counter 5.6 R u64 Accumulator for Reactive Energy, Import 0x0036 5.6 R u64 Accumulator for Reactive Energy, Export 0x003E Minimum Record 1 5.12 R u32 Minimum Value of the Output Quantity Address in Min/Max Pointer 1 Register 0x0042 Minimum Record 2 5.12 R u32 Minimum Value of the Output Quantity Address in Min/Max Pointer 2 Register 0x0046 Reserved -- R u32 Reserved Export Active Energy Counter Export Reactive Energy Counter 0x004A Reserved -- R u32 Reserved 0x004E Maximum Record 1 5.12 R u32 Maximum Value of the Output Quantity Address in Min/Max Pointer 1 Register 0x0052 Maximum Record 2 5.12 R u32 Maximum Value of the Output Quantity Address in Min/Max Pointer 2 Register 0x0056 Reserved -- R u32 Reserved 0x005A Reserved -- R u32 Reserved Note 1: 2: The registers are unsigned, however their sign is kept as a separate bit in the System Status Register (Register 6-1). These registers are reserved for EMI filter compensation when necessary for power supply monitoring. They may require specific adjustment depending on PSU parameters; please contact the local Microchip office for further support. 2015 Microchip Technology Inc. DS20005442A-page 27 MCP39F521 TABLE 6-1: Address MCP39F521 REGISTER MAP (CONTINUED) Register Name Section Read/ Data Number Write Type Description Calibration Registers 0x005E Calibration Register Delimiter 8.8 R/W u16 May be used to initiate loading of the default calibration coefficients at start-up 0x0060 Gain Current RMS 8.3 R/W u16 Gain Calibration Factor for RMS Current 0x0062 Gain Voltage RMS 8.3 R/W u16 Gain Calibration Factor for RMS Voltage 0x0064 Gain Active Power 8.3 R/W u16 Gain Calibration Factor for Active Power 0x0066 Gain Reactive Power 8.3 R/W u16 Gain Calibration Factor for Reactive Power 0x0068 Offset Current RMS 8.5.1 R/W s32 Offset Calibration Factor for RMS Current 0x006C Offset Active Power 8.5.1 R/W s32 Offset Calibration Factor for Active Power 0x0070 Offset Reactive Power 8.5.1 R/W s32 Offset Calibration Factor for Reactive Power 0x0074 DC Offset Current 8.5.2 R/W s16 Offset Calibration Factor for DC Current 0x0076 Phase Compensation 8.5 R/W s16 Phase Compensation 0x0078 Apparent Power Divisor 5.7 R/W u16 Number of Digits for apparent power divisor to match IRMS and VRMS resolution 0x007A System Configuration 6.5 R/W b32 Control for device configuration, including ADC configuration 0x007E Event Configuration 7.0 R/W b16 Settings for the Event pin Design Configuration Registers 0x0082 Range 6.6 R/W b32 Scaling factor for Outputs 0x0086 Calibration Current 8.3.1 R/W u32 Target Current to be used during single-point calibration 0x008A Calibration Voltage 8.3.1 R/W u16 Target Voltage to be used during single-point calibration 0x008C Calibration Power Active 8.3.1 R/W u32 Target Active Power to be used during single-point calibration 0x0090 Calibration Power Reactive 8.3.1 R/W u32 Target Reactive Power to be used during single-point calibration 0x0094 Line Frequency Reference 8.6.1 R/W u16 Reference Value for the nominal line frequency 0x0096 Reserved -- R/W u32 Reserved 0x009A Reserved -- R/W u32 Reserved 0x009E Accumulation Interval Parameter 5.2 R/W u16 N for 2N number of line cycles to be used during a single computation cycle 0x00A0 Voltage Sag Limit 7.2 R/W u16 RMS Voltage threshold at which an event flag is recorded 0x00A2 Voltage Surge Limit 7.2 R/W u16 RMS Voltage threshold at which an event flag is recorded 0x00A4 Over Current Limit 7.2 R/W u32 RMS Current threshold at which an event flag is recorded 0x00A8 Over Power Limit 7.2 R/W u32 Active Power Limit at which an event flag is recorded Note 1: 2: The registers are unsigned, however their sign is kept as a separate bit in the System Status Register (Register 6-1). These registers are reserved for EMI filter compensation when necessary for power supply monitoring. They may require specific adjustment depending on PSU parameters; please contact the local Microchip office for further support. DS20005442A-page 28 2015 Microchip Technology Inc. MCP39F521 TABLE 6-1: Address MCP39F521 REGISTER MAP (CONTINUED) Register Name Section Read/ Data Number Write Type Description EMI Filter Compensation Registers (Note 2) 0x00AC Reserved -- R u16 Reserved 0x00AE Reserved -- R u16 Reserved 0x00B0 Reserved -- R u16 Reserved 0x00B2 Reserved -- R u16 Reserved 0x00B4 Reserved -- R u16 Reserved 0x00B6 Reserved -- R u16 Reserved 0x00B8 Reserved -- R u16 Reserved 0x00BA Reserved -- R u16 Reserved 0x00BC Reserved -- R u16 Reserved 0x00BE Reserved -- R u16 Reserved 0x00C0 Reserved -- R u16 Reserved 0x00C2 Reserved -- R u16 Reserved 0x00C4 Reserved -- R u16 Reserved 0x00C6 Temperature Compensation for Frequency 8.7 R/W u16 Correction factor for compensating the line frequency indication over temperature 0x00C8 Temperature Compensation for Current 8.7 R/W u16 Correction factor for compensating the Current RMS indication over temperature 0x00CA Temperature Compensation for Power 8.7 R/W u16 Correction factor for compensating the active power indication over temperature 0x00CC Ambient Temperature Reference Voltage 8.7 R/W u16 Register for storing the reference temperature during calibration 0x00CE Reserved -- R/W u16 Reserved 0x00D0 Reserved -- R/W u16 Reserved 0x00D2 Reserved -- R/W u16 Reserved 0x00D4 MinMaxPointer1 5.12 R/W u16 Address Pointer for Min/Max 1 Outputs 0x00D6 MinMaxPointer2 5.12 R/W u16 Address Pointer for Min/Max 2 Outputs Temperature Compensation Registers Control Registers for Peripherals 0x00D8 Reserved -- R/W u16 Reserved 0x00DA Reserved -- R/W u16 Reserved 0x00DC Energy Control 5.6 R/W u16 Input register for reset/start of Energy Accumulation -- R/W u16 Reserved 5.6.1 R/W u16 No-Load Threshold for Energy Counting 0x00DE Reserved 0x00E0 Note 1: 2: No-Load Threshold The registers are unsigned, however their sign is kept as a separate bit in the System Status Register (Register 6-1). These registers are reserved for EMI filter compensation when necessary for power supply monitoring. They may require specific adjustment depending on PSU parameters; please contact the local Microchip office for further support. 2015 Microchip Technology Inc. DS20005442A-page 29 MCP39F521 6.2 Address Pointer Register This unsigned 16-bit register contains the address to which all read and write instructions occur. This register is only written through the Set Address Pointer command and is otherwise outside the writable range of register addresses. 6.3 System Status Register The System Status register is a read-only register and can be used to detect the various states of pin levels as defined below. REGISTER 6-1: SYSTEM STATUS REGISTER U-0 U-0 U-0 U-0 U-0 R-x U-0 U-0 -- -- -- -- -- EVENT -- -- bit 15 bit 8 U-0 U-0 R-x R-x R-x R-x R-x R-x -- -- SIGN_PR SIGN_PA OVERPOW OVERCUR VSURGE VSAG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as `0' bit 11 Unimplemented: Read as `0' bit 10 EVENT: State of Event Detection algorithm. This bit is latched and must be cleared. 1 = Event has occurred 0 = Event has not occurred bit 9-8 Unimplemented: Read as `0' bit 7-6 Unimplemented: Read as `0' bit 5 SIGN_PR: Sign of Reactive Power 1 = Reactive Power is positive, inductive and is in quadrants 1,2 0 = Reactive Power is negative, is capacitive and is in quadrants 3,4 bit 4 SIGN_PA: Sign of Active Power (import/export sign of active power) 1 = Active Power is positive (import) and is in quadrants 1,4 0 = Active Power is negative (export) and is in quadrants 2,3 bit 3 OVERPOW: State of Over Power detection algorithm 1 = Over Power threshold has been broken 0 = Over Power threshold has not been broken bit 2 OVERCUR: State of the Over Current detection algorithm 1 = Over Current threshold has been broken 0 = Over Current threshold has not been broken bit 1 VSURGE: State of Voltage Surge Detection algorithm. This bit is latched and must be cleared. 1 = Surge threshold has been broken 0 = Surge threshold has not been broken bit 0 VSAG: State of Voltage Sag Detection algorithm. This bit is latched and must be cleared. 1 = Sag threshold has been broken 0 = Sag threshold has not been broken DS20005442A-page 30 2015 Microchip Technology Inc. MCP39F521 6.5.2 System Version Register The System Version register is hard-coded by Microchip Technology Inc. and contains calculation engine date code information. The System Version register is a date code in the YMDD format, with year and month in hex, day in decimal (e.g. 0xF316 = 2015, Feb. 16th). 6.5 6.5.3 System Configuration The System Configuration register (Register 6-2) contains bits for controlling the following: * * * * * PGA setting ADC Reset State ADC Shutdown State Voltage Reference Trim Single Wire Auto-Transmission These options are described in the following sections. 6.5.1 The two Programmable Gain Amplifiers (PGAs) reside at the front-end of each 24-bit Delta-Sigma ADC. They have two functions: * Translate the Common mode of the input from AGND to an internal level between AGND and AVDD * Amplify the input differential signal The translation of the Common mode does not change the differential signal but enters the Common mode so that the input signal can be properly amplified. The PGA block can be used to amplify very low signals, but the differential input range of the delta-sigma modulator must not be exceeded. The PGA is controlled by the PGA_CHn<2:0> bits in Register 6-2 the System Configuration register. Table 6-2 represents the gain settings for the PGAs. ADC Shutdown mode is defined as a state where the converters and their biases are OFF, consuming only leakage current. When the Shutdown bit (SHUTDOWN <1:0>) is reset to `0', the analog biases will be enabled, as well as the clock and the digital circuitry. Each converter can be placed in Shutdown mode independently. This mode is only available through programming of the SHUTDOWN<1:0> bits in the System Configuration register (Register 6-2). Gain (V/V) Gain (dB) VIN Range (V) 0 0.5 The internal voltage reference comprises a proprietary circuit and algorithm to compensate first-order and second-order temperature coefficients. The compensation allows very low temperature coefficients (typically 10 ppm/C) on the entire range of temperatures from -40C to +125C. This temperature coefficient varies from part to part. The temperature coefficient can be adjusted on each part through the System Configuration register (0x0042) (Register 6-2). The default value of this register is set to 0x42. The typical variation of the temperature coefficient of the internal voltage reference, with respect to VREFCAL register code, is shown in Figure 6-1. 60 50 40 0 0 0 1 0 0 1 2 6 0.25 0 1 0 4 12 0.125 0 1 1 8 18 0.0625 10 1 0 0 16 24 0.03125 0 1 0 1 32 30 0.015625 Note 1: The two undefined settings (110, 111) are G = 1. 2015 Microchip Technology Inc. VREF TEMPERATURE COMPENSATION If desired, the user can calibrate out the temperature drift for ultra-low VREF drift. PGA CONFIGURATION SETTING (Note 1) Gain PGA_CHn<2:0> ADC SHUTDOWN MODE 6.5.4 PROGRAMMABLE GAIN AMPLIFIERS (PGA) TABLE 6-2: 24-BIT ADC RESET MODE (SOFT RESET MODE) 24-bit ADC Reset mode (also called Soft Reset) can only be entered through setting high the RESET<1:0> bits in the System Configuration register (Register 6-2). This mode is defined as the condition where the converters are active but their output is forced to `0'. VREF Drift (ppm) 6.4 30 20 0 64 128 192 VREFCAL Register Trim Code (decimal) FIGURE 6-1: Trimcode Chart. 256 VREF Tempco vs. VREFCAL DS20005442A-page 31 MCP39F521 REGISTER 6-2: SYSTEM CONFIGURATION REGISTER U-0 U-0 -- -- R/W-0 R/W-0 R/W-0 R/W-0 PGA_CH1<2:0> R/W-1 R/W-1 PGA_CH0<2:0> bit 31 bit 24 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 VREFCAL<7:0> bit 23 bit 16 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 TIMEOUT_DIS -- -- ZCD_INV ZCD_PULS ZCD_OUTPUT_ DIS -- -- bit 15 bit 8 R/W-0 R/W-0 TEMPCOMP R/W-0 R/W-0 RESET<1:0> R/W-0 SHUTDOWN<1:0> R/W-0 U-0 U-0 VREFEXT -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-30 Unimplemented: Read as `0' bit 29-27 PGA_CH1 <2:0>: PGA Setting for Channel 1 111 = Reserved (Gain = 1) 110 = Reserved (Gain = 1) 101 = Gain is 32 100 = Gain is 16 011 = Gain is 8 010 = Gain is 4 001 = Gain is 2 000 = Gain is 1 (DEFAULT) bit 26-24 PGA_CH0 <2:0>: PGA Setting for Channel 0 111 = Reserved (Gain = 1) 110 = Reserved (Gain = 1) 101 = Gain is 32 100 = Gain is 16 011 = Gain is 8 (Default) 010 = Gain is 4 001 = Gain is 2 000 = Gain is 1 bit 23-16 VREFCAL<n>: Internal voltage reference temperature coefficient register value (See Section 6.5.4, VREF Temperature Compensation for complete description) bit 15 TIMEOUT_DIS: Time Out Disable 1 = I2C Time Out is Disabled 0 = I2C Time Out is Enabled (DEFAULT) bit 14-13 Unimplemented: Read as `0' bit 12 ZCD_INV: Zero Crossing Detection Output Inverse 1 = ZCD is inverted 0 = ZCD is not inverted (DEFAULT) DS20005442A-page 32 2015 Microchip Technology Inc. MCP39F521 REGISTER 6-2: SYSTEM CONFIGURATION REGISTER (CONTINUED) bit 11 ZCD_PULS: Zero Crossing Detection Pulse mode 1 = ZCD output is 100 s pulses on zero crossings 0 = ZCD Output changes logic state on zero crossings (DEFAULT) bit 10 ZCD_OUTPUT_DIS: Disable the Zero Crossing output pin 1 = ZCD output is disabled 0 = ZCD output is enabled (Default) bit 9-8 Unimplemented: Read as `0' bit 7 TEMPCOMP: temperaure compensation enable bit 1 = Temperature compensation is enabled 0 = Temperature compensation is disabled (DEFAULT) bit 6-5 RESET <1:0>: Reset mode setting for ADCs 11 = Both I1 and V1 are in Reset mode 10 = V1 ADC is in Reset mode 01 = I1 ADC is in Reset mode 00 = Neither ADC is in Reset mode (DEFAULT) bit 4-3 SHUTDOWN <1:0>: Shutdown mode setting for ADCs 11 = Both I1 and V1 are in Shutdown 10 = V1 ADC is in Shutdown 01 = I1 ADC is in Shutdown 00 = Neither ADC is in Shutdown (DEFAULT) bit 2 VREFEXT: Internal Voltage Reference Shutdown Control 1 = Internal Voltage Reference Disabled 0 = Internal Voltage Reference Enabled (DEFAULT) bit 1-0 Unimplemented: Read as `0' REGISTER 6-3: ENERGY ACCUMULATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 -- -- -- -- -- -- -- ENRG_CNTRL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bits 15-1 Unimplemented: Read as `0` bit 0 ENRG_CNTRL: Energy Accumulation Control bit 1 = Energy Accumulation is tuned on and all registers are accumulating 0 = Energy Accumulation is turned off and all energy accumulation registers are reset to 0 (DEFAULT) 2015 Microchip Technology Inc. DS20005442A-page 33 MCP39F521 6.6 Range Register The Range register (Register 6-4) is a 32-bit register that contains the number of right-bit shifts for the following outputs, divided into separate bytes as defined below: * RMS Current * RMS Voltage * Power (Active, Reactive, Apparent) Note that the power range byte operates across both the active and reactive output registers and sets the same scale. The purpose of this register is two-fold: the number of right-bit shifting (division by 2RANGE) must be high enough to prevent overflow in the output register, and low enough to allow for the desired output resolution. It is the user's responsibility to set this register correctly to ensure proper output operation for a given meter design. For further information and example usage, see Section 8.3, Single-Point Gain Calibrations at Unity Power Factor. . REGISTER 6-4: RANGE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 31 bit 24 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 POWER<7:0> bit 23 bit 16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 CURRENT<7:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 VOLTAGE<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as `0' bit 23-16 POWER<7:0>: Sets the number of right-bit shifts for the Active and Reactive Power output registers bit 15-8 CURRENT<7:0>: Sets the number of right-bit shifts for the Current RMS output register bit 7-0 VOLTAGE<7:0>: Sets the number of right-bit shifts for the Voltage RMS output register DS20005442A-page 34 2015 Microchip Technology Inc. MCP39F521 7.0 EVENT OUTPUT PIN/EVENT CONFIGURATION REGISTER 7.1 Event Pin The MCP39F521 device has one Event pin that can be configured in three possible configurations. These configurations are: 1. 2. 3. No event is mapped to the pin Voltage Surge, Voltage Sag, Over Current, or Over Power event is mapped to the pin. More than one event can be mapped to the Event pin. Manual control of the Event pin. These three configurations allow for the control of external interrupts or hardware that is dependent on the measured power, current or voltage. The Event configuration register (Register 7-1) below describes how these events and pins can be configured. 7.2 Voltage Sag and Voltage Surge Detection The event alarms for Voltage Sag and Voltage Surge work differently compared to the Over Current and Over Power events, which are tested against every computation cycle. These two event alarms are designed to provide a much faster interrupt if the condition occurs. Note that neither of these two events have a respective Hold register associated with them, since the detection time is less than one line cycle. The calculation engine keeps track of a trailing mean square of the input voltage, as defined by the following equation: EQUATION 7-1: 2 2 f LINE V SA = -------------------------- f SAMPLE 0 Vn f SAMPLE n = - -------------------------- - 1 2 f LINE Therefore, at each data-ready occurrence, the value of VSA is compared to the programmable threshold set in the Voltage Sag Limit register and Voltage Surge Limit register to determine if a flag should be set. If either of these events are masked to either the Event pin, a logic-high interrupt will be given on these pins. The Sag or Surge events can be used to quickly determine if a power failure has occurred in the system. 2015 Microchip Technology Inc. DS20005442A-page 35 MCP39F521 REGISTER 7-1: EVENT CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 31 bit 24 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- -- OVERPOW_PIN OVERCUR_PIN VSURGE_PIN VSAG_PIN U-0 R/W-0 U-0 U-0 R/W R/W R/W-0 R/W-0 -- EVENT_MANU -- -- OVERCUR_CL OVERPOW_CL VSUR_CL VSAG_CL bit 23 bit 16 bit 15 bit 8 R/W-0 R/W-0 VSUR_LA VSAG_LA R/W-0 R/W-0 OVERPOW_LA OVERCUR_LA R/W-0 R/W-0 VSUR_TST VSAG_TST R/W-0 R/W-0 OVERPOW_TST OVERCUR_TST bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 31-24 x = Bit is unknown Unimplemented: Read as `0' bit 23 Unimplemented: Read as `0' bit 22 Unimplemented: Read as `0' bit 21 Unimplemented: Read as `0' bit 20 Unimplemented: Read as `0' bit 19 OVERPOW_PIN: Pin Operation for the Over Power event 1 = Event mapped to Event pin only 0 = Event not mapped to a pin (Default) bit 18 OVERCUR_PIN: Pin Operation for the Over Current event 1 = Event mapped to Event pin only 0 = Event not mapped to a pin (Default) bit 17 VSURGE_PIN: Pin Operation for the Voltage Surge event 1 = Event mapped to Event pin only 0 = Event not mapped to a pin (Default) bit 16 VSAG_PIN: Pin Operation for the Voltage Sag event 1 = Event mapped to Event pin only 0 = Event not mapped to a pin (Default) bit 15 Unimplemented: Read as `0' bit 14 EVENT_MANU: Manual Control of the Event pin 1 = Pin is logic high 0 = Pin is logic low (Default) bit 13-12 Unimplemented: Read as `0' bit 11 OVERCUR_CL: Reset or clear bit for the Over Current event 1 = Event is cleared 0 = Event is not cleared (Default) bit 10 OVERPOW_CL: Reset or clear bit for the Over Power event 1 = Event is cleared 0 = Event is not cleared (Default) bit 9 VSUR_CL: Reset or clear bit for the Voltage Surge event 1 = Event is cleared 0 = Event is not cleared (Default) DS20005442A-page 36 2015 Microchip Technology Inc. MCP39F521 REGISTER 7-1: EVENT CONFIGURATION REGISTER (CONTINUED) bit 8 VSAG_CL: Reset or clear bit for the Voltage Sag event 1 = Event is cleared 0 = Event is not cleared (Default) bit 7 VSUR_LA: Latching control of the Voltage Surge event 1 = Event is latched and needs to be cleared 0 = Event does not latch bit 6 VSAG_LA: Latching control of the Voltage Sag event 1 = Event is latched and needs to be cleared 0 = Event does not latch bit 5 OVERPOW_LA: Latching control of the Over Power event 1 = Event is latched and needs to be cleared 0 = Event does not latch bit 4 OVERCUR_LA: Latching control of the Over Current event 1 = Event is latched and needs to be cleared 0 = Event does not latch bit 3 VSUR_TST: Test control of the Voltage Surge event 1 = Simulated event is turned on 0 = Simulated Event is turned off bit 2 VSAG_TST: Test control of the Voltage Sag event 1 = Simulated event is turned on 0 = Simulated Event is turned off bit 1 OVERPOW_TST: Test control of the Over Power event 1 = Simulated Event is turned on 0 = Simulated Event is turned off bit 0 OVERCUR_TST: Test control of the Over Current event 1 = Simulated Event is turned on 0 = Simulated Event is turned off Note: Writing a 1 to the Clear bit, clears the event, either real or simulated through test bits, and then returns to a state of 0. 2015 Microchip Technology Inc. DS20005442A-page 37 MCP39F521 8.0 MCP39F521 CALIBRATION 8.3.1 8.1 Overview By applying stable reference voltages and currents that are equivalent to the values that reside in the target Calibration Current, Calibration Voltage and Calibration Active Power registers, the Auto-Calibration Gain command can then be issued to the device. Calibration compensates for ADC gain error, component tolerances and overall noise in the system. The device provides an on-chip calibration algorithm that allows simple system calibration to be performed quickly. The excellent analog performance of the A/D converters on the MCP39F521 allows for a single point calibration and a single calibration command to achieve accurate measurements. Calibration can be done by either using the predefined auto-calibration commands, or by writing directly to the calibration registers. If additional calibration points are required (AC offset, Phase Compensation, DC offset), the corresponding calibration registers are available to the user and will be described separately in this section. 8.2 Calibration Order The proper steps for calibration need to be observed. If the device has an external temperature sensor attached, temperature calibration should be done first by reading the value from the Thermistor Voltage register and copying the value by writing to the Ambient Temperature Reference Voltage register. If the device runs on the internal oscillator, the line frequency must be calibrated next using the Auto-Calibration Frequency command. The single-point gain calibration at unity power factor should be performed next. If non-unity displacement power factor measurements are a concern, then the next step should be phase calibration, followed by reactive power gain calibration. To summarize the order of calibration: 1. 2. 3. 4. 5. 8.3 Temperature Calibration (optional) Line Frequency Calibration (optional) Gain Calibration at PF = 1 Phase Calibration at PF 1 (optional) Reactive Gain Calibration at PF 1(optional) Single-Point Gain Calibrations at Unity Power Factor When using the device in AC mode with the high-pass filters turned on, most offset errors are removed and only a single-point gain calibration is required. Setting the gain registers to properly produce the desired outputs can be done manually by writing to the appropriate register. The alternative method is to use the auto-calibration commands described in this section. DS20005442A-page 38 USING THE AUTO-CALIBRATION GAIN COMMAND After a successful calibration (response = ACK), a Save Registers to Flash command can then be issued to save the calibration constants calculated by the device. The following registers are set when the Auto-Calibration Gain command is issued: * Gain Current RMS * Gain Voltage RMS * Gain Active Power When this command is issued, the MCP39F521 attempts to match the expected values to the measured values for all three output quantities by changing the gain register based on the following formula: EQUATION 8-1: Expected GAIN NEW = GAIN OLD -------------------------Measured The same formula applies for voltage RMS, current RMS and active power. Since the gain registers for all three quantities are 16-bit numbers, the ratio of the expected value to the measured value (which can be modified by changing the Range register) and the previous gain must be such that the equation yields a valid number. Here the limits are set to be from 25,000 to 65,535. A new gain within this range for all three limits will return an ACK for a successful calibration, otherwise the command returns a NAK for a failed calibration attempt. It is the user's responsibility to ensure that the proper range settings, PGA settings and hardware design settings are correct to allow for successful calibration using this command. 8.3.2 EXAMPLE OF RANGE SELECTION FOR VALID CALIBRATION In this example, the user applies a calibration current of 1A to an uncalibrated system. The indicated value in the Current RMS register is 2300 with the system's specific shunt value, PGA gain, etc. The user expects to see a value of 1000 in the Current RMS register when 1A current is applied, meaning 1.000A with 1 mA resolution. Other given values are: * The existing value for Gain Current RMS is 33480 * The existing value for Range is 12 2015 Microchip Technology Inc. MCP39F521 By using Equation 8-2, the calculation for GainNEW yields: EQUATION 8-2: Expected 1000 GAIN NEW = GAIN OLD --------------------------- = 33480 ------------ = 14556 Measured 2300 14556 25 000 When using the Auto-Calibration Gain command, the result would be a failed calibration or a NAK returned form the MCP39F521, because the resulting GainNEW is less than 25,000. The solution is to use the Range register to bring the measured value closer to the expected value, such that a new gain value can be calculated within the limits specified above. The GainNEW is much larger than the 16-bit limit of 65535, so fewer right-bit shifts must be introduced to get the measured value closer to the expected value. The user needs to compute the number of bit shifts that will give a value lower than 65535. To estimate this number: EQUATION 8-5: 145565 ------------------ = 2.2 65535 2.2 rounds to the closest integer value of 2. The range value changes to 12 - 2 = 10; there are 2 less right-bit shifts. The new measured value will be 2300 x 22 = 9200. The Range register specifies the number of right-bit shifts (equivalent to divisions by 2) after the multiplication with the Gain Current RMS register. Refer to Section 5.0, Calculation Engine (CE) Description for information on the Range register. EQUATION 8-6: Incrementing the Range register by 1 unit, an additional right-bit shift or /2 is included in the calculation. Increasing the current range from 12 to 13 yields the new measured Current RMS register value of 2300/2 = 1150. The expected (1000) and measured (1150) are much closer now, so the expected new gain should be within the limits: The resulting new gain is within the limits and the device successfully calibrates Current RMS and returns an ACK. EQUATION 8-3: Expected 1000 GAIN NEW = GAIN OLD --------------------------- = 33480 ------------ = 29113 Measured 1150 25 000 29113 65535 The resulting new gain is within the limits and the device successfully calibrates Current RMS and returns an ACK. It can be observed that the range can be set to 14 and the resulting new gain will still be within limits (GainNEW = 58226). However, since this gain value is close to the limit of the 16-bit Gain register, variations from system to system (component tolerances, etc.) might create a scenario where the calibration is not successful on some units and there would be a yield issue. The best approach is to choose a range value that places the new gain in the middle of the bounds of the gain registers described above. Expected 10000 GAIN NEW = GAIN OLD --------------------------- = 33480 --------------- = 36391 Measured 9200 25 000 36391 65535 8.4 Calibrating the Phase Compensation Register Phase compensation is provided to adjust for any phase delay between the current and voltage path. This procedure requires sinusoidal current and voltage waveforms, with a significant phase shift between them, and significant amplitudes. The recommended displacement power factor for calibration is 0.5. The procedure for calculating the phase compensation register is as follows: 1. Determine what the difference is between the angle corresponding to the measured power factor (PFMEAS) and the angle corresponding to the expected power factor (PFEXP), in degrees. EQUATION 8-7: Value in PowerFactor Register PF MEAS = --------------------------------------------------------------------------32768 180 ANGLEMEAS = acos PFMEAS --------- 180 ANGLE EXP = acos PF EXP --------- In a second example, when applying 1A, the user expects an output of 1.0000A with 0.1 mA resolution. The example is starting with the same initial values: 2. EQUATION 8-4: EQUATION 8-8: Expected 10000 GAIN NEW = GAIN OLD --------------------------- = 33480 --------------- = 145565 Measured 2300 Convert this from degrees to the resolution provided in Equation 8-8: = ANGLE MEAS - ANGLE EXP 40 145565 65535 2015 Microchip Technology Inc. DS20005442A-page 39 MCP39F521 3. Combine this additional phase compensation to whatever value is currently in the phase compensation, and update the register. Equation 8-9 should be computed in terms of an 8-bit two's complement signed value. The 8-bit result is placed in the least significant byte of the 16-bit Phase Compensation register. EQUATION 8-9: PhaseCompensation NEW = PhaseCompensation OLD + Offset/No-Load Calibrations During offset calibrations, no line voltage or current should be applied to the system. The system should be in a No-Load condition. 8.5.1 Calibrating the Line Frequency Register The Line Frequency register contains a 16-bit number with a value equivalent to the input line frequency as it is measured on the voltage channel. When in DC mode, this calculation is turned off and the register will be equal to zero. The measurement of the line frequency is only valid from 45 to 65 Hz. Based on Equation 8-9, the maximum angle in degrees that can be compensated is 3.2 degrees. If a larger phase shift is required, contact your local Microchip sales office. 8.5 8.6 AC OFFSET CALIBRATION There are three registers associated with the AC Offset Calibration: * Offset Current RMS * Offset Active Power * Offset Reactive Power 8.6.1 USING THE AUTO-CALIBRATION FREQUENCY COMMAND By applying a stable reference voltage with a constant line frequency that is equivalent to the value that resides in the Line Frequency Ref, the Auto-Calibration Frequency command can then be issued to the device. After a successful calibration (response = ACK), a Save Registers to Flash command can then be issued to save the calibration constants calculated by the device. The following register is set Auto-Calibration Frequency issued: when the command is * Gain Line Frequency Note that the command is only required when running off the internal oscillator. The formula used to calculate the new gain is shown in Equation 8-1. When computing the AC offset values, the respective Gain and Range registers should be taken into consideration according to the block diagrams in Figures 5-2 and 5-4. After a successful offset calibration, a Save Registers to Flash command can then be issued to save the calibration constants calculated by the device. 8.5.2 DC OFFSET CALIBRATION In DC applications, the high-pass filter on the current and voltage channels is turned off. To remove any residual DC value on the current, the DC Offset Current register adds to the A/D conversion immediately after the ADC and prior to any other function. DS20005442A-page 40 2015 Microchip Technology Inc. MCP39F521 8.7 Temperature Compensation The MCP39F521 measures the indication of the temperature sensor and uses the value to compensate the temperature variation of the shunt resistance and the frequency of the internal RC oscillator. The same formula applies for Line Frequency, Current RMS, Active Power and Reactive Power. The temperature compensation coefficient depends on the 16-bit signed integer value of the corresponding compensation register. 8.8 Retrieving Factory Default Calibration Values After user calibration and a Save to Flash command has been issued, it is possible to retrieve the factory default calibration values. This can be done by writing 0xA5A5 to the Calibration Register Delimiter, issuing a Save to Flash, and then resetting the part. This procedure will retrieve all factory default calibration values and will remain in this state until calibration has been performed again, and a Save to Flash command has been issued. EQUATION 8-10: y = x 1 + c T - T CAL TemperatureCompensation Register c = ----------------------------------------------------------------------------------------------M 2 Where: x = Uncompensated Output (corresponding to Line Frequency, Current RMS, Active Power and Reactive Power) y = Compensated Output c = Temperature Compensation Coefficient (depending on the shunt's Temperature Coefficient of Resistance or on the internal RC oscillator temperature frequency drift). There are three registers: one for Line Frequency compensation, one for Current compensation, and one for power compensation (Active and Reactive) T = Thermistor Voltage (in 10-bit ADC units) TCAL = Ambient Temperature Reference Voltage. It should be set at the beginning of the calibration procedure, by reading the thermistor voltage and writing its value to the ambient temperature reference voltage register. M = 26 (for Line Frequency compensation) = 27 (for Current, Active Power and Reactive Power) When calibrating the temperature, the effect of the compensation coefficients is minimal. The coefficients need to be tuned when the difference between the calibration temperature and the device temperature is significant. It is recommended to use the default values as starting points. 2015 Microchip Technology Inc. DS20005442A-page 41 MCP39F521 9.0 There are three commands that support access to the EEPROM array. EEPROM The data EEPROM is organized as 16-bit wide memory. Each word is directly addressable, and is readable and writable across the entire VDD range. The MCP39F521 has 256 16-bit words of EEPROM that is organized in 32 pages for a total of 512 bytes. TABLE 9-1: * EEPROM Page Read (0x42) * EEPROM Page Write (0x50) * EEPROM Bulk Erase (0x4F) EXAMPLE EEPROM COMMANDS AND DEVICE RESPONSE Command Command ID BYTE 0 BYTE 1-N # Bytes Successful Response 0x42 PAGE 2 ACK, Data, Checksum Page Write EEPROM 0x50 PAGE + 16 BYTES OF DATA 18 ACK Bulk Erase EEPROM 0x4F --------- 1 ACK Page Read EEPROM TABLE 9-2: MCP39F521 EEPROM ORGANIZATION Page 00 02 04 06 08 0A 0C 0E 0 0000 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 1 0010 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 2 0020 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 3 0030 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 4 0040 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 5 0050 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 6 0060 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 7 0070 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 8 0080 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 9 0090 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 10 00A0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 11 00B0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 12 00C0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 13 00D0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 14 00E0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 15 00F0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 16 0100 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 17 0110 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 18 0120 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 19 0130 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 20 0140 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 21 0150 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 22 0160 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 23 0170 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 24 0180 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 25 0190 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 26 01A0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 27 01B0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 28 01C0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 29 01D0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 30 01E0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 31 01F0 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF DS20005442A-page 42 2015 Microchip Technology Inc. MCP39F521 10.0 PACKAGING INFORMATION 10.1 Package Marking Information 28-Lead QFN (5x5x0.9 mm) Example 39F521 -E/MQ e ^^3 1539256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2015 Microchip Technology Inc. DS20005442A-page 43 MCP39F521 28-Lead Plastic Quad Flat, No Lead Package (MQ) - 5x5x0.9 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 E (DATUM B) (DATUM A) 2X 0.10 C 2X TOP VIEW 0.10 C 0.10 C C SEATING PLANE A1 A 28X A3 SIDE VIEW 0.08 C 0.10 C A B D2 0.10 C A B E2 28X K 2 1 NOTE 1 N 28X L e BOTTOM VIEW 28X b 0.10 0.05 C A B C Microchip Technology Drawing C04-140C Sheet 1 of 2 DS20005442A-page 44 2015 Microchip Technology Inc. MCP39F521 28-Lead Plastic Quad Flat, No Lead Package (MQ) - 5x5x0.9 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch Overall Height A Standoff A1 Contact Thickness A3 E Overall Width Exposed Pad Width E2 Overall Length D D2 Exposed Pad Length b Contact Width Contact Length L Contact-to-Exposed Pad K MIN 0.80 0.00 3.15 3.15 0.18 0.35 0.20 MILLIMETERS NOM 28 0.50 BSC 0.90 0.02 0.20 REF 5.00 BSC 3.25 5.00 BSC 3.25 0.25 0.40 - MAX 1.00 0.05 3.35 3.35 0.30 0.45 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-140C Sheet 2 of 2 2015 Microchip Technology Inc. DS20005442A-page 45 MCP39F521 28-Lead Plastic Quad Flat, No Lead Package (MQ) - 5x5 mm Body [QFN] Land Pattern With 0.55 mm Contact Length Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-2140A DS20005442A-page 46 2015 Microchip Technology Inc. MCP39F521 APPENDIX A: REVISION HISTORY Revision A (September 2015) * Original Release of this Document. 2015 Microchip Technology Inc. DS20005442A-page 47 MCP39F521 NOTES: DS20005442A-page 48 2015 Microchip Technology Inc. MCP39F521 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device [X](1) X Tape and Temperature Reel Range Device: /XX Package Examples: a) MCP39F521-E/MQ: Extended temperature, 28LD 5x5 QFN package b) MCP39F521T-E/MQ: Tape and Reel, Extended temperature, 28LD 5x5 QFN package MCP39F521: I2C Power-Monitor with Calculation and Energy Accumulation Tape and Reel Option: Blank = Standard packaging (tube or tray) T = Tape and Reel(1) Note Temperature Range: E = -40C to +125C (Extended) Package: MQ = Plastic Quad Flat, No Lead Package - 5x5x0.9 mm body (QFN), 28-lead 2015 Microchip Technology Inc. 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip sales office for package availability for the Tape and Reel option. DS20005442A-page 49 MCP39F521 NOTES: 2015 Microchip Technology Inc. DS20005442A-page 50 Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-819-2 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2015 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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