71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 FEATURES GENERAL DESCRIPTION The TERIDIAN 71M6521BE is a highly integrated SOC with an MPU core, FLASH and LCD driver. TERIDIAN's patented Single Converter TechnologyTM with a 22-bit delta-sigma ADC, four analog inputs, digital temperature compensation, precision voltage reference, battery voltage monitor, and 32bit computation engine (CE) supports a wide range of residential metering applications with very few low-cost external components. A 32kHz crystal time-base for the entire system further reduces system cost. The IC supports 2-wire single-phase residential metering along with tamperdetection mechanisms. Maximum design flexibility is provided by multiple UARTs, I2C, Wire, up to 14 DIO pins and in-system programmable FLASH memory, which can be updated with data or application code in operation. A complete array of ICE and development tools, programming libraries and reference designs enable rapid development and certification of AMR and Prepay meters that comply with worldwide electricity metering standards. A CT/SHUNT LOAD NEUT POWER SUPPLY LOAD B CONVERTER V3.3A IA V3.3 SYS PWR MODE CONTROL VA IB VB GNDA GNDD TERIDIAN 71M6521BE WAKE-UP REGULATOR VBAT V2.5 VOLTAGE REF VREF VBIAS TEMP SENSOR RAM SERIAL PORTS TX AMR FLASH RX IR POWER FAULT 32 kHz RX/DIO1 TX/DIO2 SENSE DRIVE/MOD COMPARATOR COMPUTE ENGINE MPU COM0..3 SEG0..18 SEG 24..31/ DIO 4..11 SEG 34..37/ DIO 14..17 XOUT I2C or Wire EEPROM TEST PULSE TIMERS ICE ICE_E 11/14/2007 V1.0 3.3V LCD 888888.88 SEG 32,33, 38 V1 OSC/PLL XIN BATTERY DIO, PULSE V3P3D GNDD * < 0.4% Wh accuracy over 2000:1 current range and over temperature * Exceeds IEC62053 / ANSI C12.20 standards * Voltage reference < 40ppm/C * Four sensor inputs--VDD referenced * Low jitter Wh test output (10kHz maximum) * Pulse count for Wh pulse output * Tamper detection: Neutral current with CT or shunt * Line frequency count for time keeping * Digital temperature compensation * Sag detection for phase A and B * Independent 32-bit compute engine * 46-64Hz line frequency range with same calibration * Phase compensation (7) * Battery monitor * Three battery modes w/ wake-up on push-button or timer: Brownout mode (48A) LCD mode (5.7A) Sleep mode (2.9A) * Energy display on main power failure * Wake-up with push-button * 22-bit delta-sigma ADC * 8-bit MPU (80515), 1 clock cycle per instruction w/ integrated ICE for MPU debug * Hardware watchdog timer, power fail monitor * LCD driver (up to 140 pixels) * Up to 14 general purpose I/O pins * 32kHz time base * 8KB FLASH with security * 2KB MPU XRAM * Two UARTs for IR and AMR * Digital I/O pins compatible with 5V inputs * 64-pin LQFP * Lead Free package (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 1 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Table of Contents GENERAL DESCRIPTION ............................................................................................................................................1 FEATURES......................................................................................................................................................1 HARDWARE DESCRIPTION.........................................................................................................................................9 Hardware Overview..........................................................................................................................................9 Analog Front End (AFE)...................................................................................................................................9 Input Multiplexer ................................................................................................................................9 A/D Converter (ADC) .......................................................................................................................10 FIR Filter..........................................................................................................................................10 Voltage References .........................................................................................................................10 Temperature Sensor........................................................................................................................11 Battery Monitor ................................................................................................................................12 Functional Description .....................................................................................................................12 Digital Computation Engine (CE) ...................................................................................................................12 Meter Equations ..............................................................................................................................13 Real-Time Monitor ...........................................................................................................................13 Pulse Generator ..............................................................................................................................13 CE Functional Overview ..................................................................................................................14 80515 MPU Core ...........................................................................................................................................16 Memory Organization ......................................................................................................................16 Special Function Registers (SFRs)..................................................................................................18 Special Function Registers (Generic 80515 SFRs) .........................................................................19 Special Function Registers Specific to the 71M6521BE ..................................................................21 Instruction Set..................................................................................................................................22 UART...............................................................................................................................................22 Timers and Counters .......................................................................................................................25 WD Timer (Software Watchdog Timer)............................................................................................27 Interrupts .........................................................................................................................................29 On-Chip Resources .......................................................................................................................................37 Oscillator..........................................................................................................................................37 PLL and Internal Clocks...................................................................................................................37 Temperature Sensor........................................................................................................................37 Physical Memory .............................................................................................................................37 Optical Interface ..............................................................................................................................38 Digital I/O.........................................................................................................................................39 LCD Drivers .....................................................................................................................................41 Battery Monitor ................................................................................................................................41 EEPROM Interface ..........................................................................................................................41 Hardware Watchdog Timer..............................................................................................................45 Program Security.............................................................................................................................45 Page: 2 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Test Ports ........................................................................................................................................46 FUNCTIONAL DESCRIPTION.....................................................................................................................................47 Theory of Operation .......................................................................................................................................47 System Timing Summary...............................................................................................................................48 Battery Modes................................................................................................................................................49 BROWNOUT Mode .........................................................................................................................50 LCD Mode .......................................................................................................................................51 SLEEP Mode ...................................................................................................................................51 Fault and Reset Behavior ..............................................................................................................................56 Wake Up Behavior .........................................................................................................................................57 Wake on PB.....................................................................................................................................57 Wake on Timer ................................................................................................................................57 Data Flow.......................................................................................................................................................58 CE/MPU Communication ...............................................................................................................................58 Temperature Measurement ...........................................................................................................................59 Temperature Compensation ..........................................................................................................................59 APPLICATION INFORMATION ...................................................................................................................................60 Connection of Sensors (CT, Resistive Shunt)................................................................................................60 Connecting 5V Devices..................................................................................................................................60 Connecting LCDs...........................................................................................................................................61 Connecting I2C EEPROMs ............................................................................................................................63 Connecting Three-Wire EEPROMs................................................................................................................63 UART0 (TX/RX) .............................................................................................................................................64 Optical Interface.............................................................................................................................................64 Connecting V1 and Reset Pins ......................................................................................................................65 Connecting the Emulator Port Pins ................................................................................................................66 Crystal Oscillator............................................................................................................................................67 Flash Programming........................................................................................................................................67 MPU Firmware Library ...................................................................................................................................67 Meter Calibration............................................................................................................................................67 FIRMWARE INTERFACE ............................................................................................................................................68 I/O RAM MAP - In Numerical Order ..............................................................................................................68 SFR MAP (SFRs Specific to TERIDIAN 80515) - In Numerical Order ..........................................................69 I/O RAM DESCRIPTION - Alphabetical Order ..............................................................................................70 CE Interface Description ................................................................................................................................76 CE Program.....................................................................................................................................76 Formats ...........................................................................................................................................76 Constants ........................................................................................................................................76 Environment ....................................................................................................................................76 CE Calculations ...............................................................................................................................77 CE STATUS ....................................................................................................................................77 V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 3 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 CE TRANSFER VARIABLES ..........................................................................................................79 Other CE Parameters ......................................................................................................................80 ELECTRICAL SPECIFICATIONS ................................................................................................................................83 ABSOLUTE MAXIMUM RATINGS ................................................................................................................83 RECOMMENDED EXTERNAL COMPONENTS ...........................................................................................84 RECOMMENDED OPERATING CONDITIONS ............................................................................................84 PERFORMANCE SPECIFICATIONS ............................................................................................................85 INPUT LOGIC LEVELS ...................................................................................................................85 OUTPUT LOGIC LEVELS ...............................................................................................................85 POWER-FAULT COMPARATOR....................................................................................................85 BATTERY MONITOR ......................................................................................................................85 SUPPLY CURRENT ........................................................................................................................86 V3P3D SWITCH ..............................................................................................................................86 2.5V VOLTAGE REGULATOR ........................................................................................................86 LOW POWER VOLTAGE REGULATOR.........................................................................................87 CRYSTAL OSCILLATOR ................................................................................................................87 VREF, VBIAS ..................................................................................................................................87 ADC CONVERTER, V3P3A REFERENCED...................................................................................88 OPTICAL INTERFACE....................................................................................................................88 TEMPERATURE SENSOR .............................................................................................................89 LSB values do not include the 9-bit left shift at CE input. ................................................................89 LCD DRIVERS ................................................................................................................................88 TIMING SPECIFICATIONS ...........................................................................................................................90 RAM AND FLASH MEMORY ..........................................................................................................90 FLASH MEMORY TIMING ..............................................................................................................90 EEPROM INTERFACE....................................................................................................................90 RESET ............................................................................................................................................90 TYPICAL PERFORMANCE DATA ..................................................................................................91 PACKAGE OUTLINE (LQFP 64) ...................................................................................................................92 PINOUT (LQFP-64) .......................................................................................................................................93 PIN DESCRIPTIONS .....................................................................................................................................94 Power/Ground Pins:.........................................................................................................................94 Analog Pins: ....................................................................................................................................94 Digital Pins:......................................................................................................................................95 I/O Equivalent Circuits: ....................................................................................................................96 ORDERING INFORMATION .........................................................................................................................97 Page: 4 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 List of Figures Figure 1: IC Functional Block Diagram...........................................................................................................................8 Figure 2: General Topology of a Chopped Amplifier ....................................................................................................11 Figure 3: AFE Block Diagram.......................................................................................................................................12 Figure 4: Samples from Multiplexer Cycle....................................................................................................................14 Figure 5: Accumulation Interval....................................................................................................................................15 Figure 6: Interrupt Structure .........................................................................................................................................36 Figure 7: Optical Interface ............................................................................................................................................39 Figure 8: Connecting an External Load to DIO Pins.....................................................................................................40 Figure 9: 3-Wire Interface. Write Command, HiZ=0. ....................................................................................................43 Figure 10: 3-Wire Interface. Write Command, HiZ=1 ...................................................................................................43 Figure 11: 3-Wire Interface. Read Command...............................................................................................................44 Figure 12: 3-Wire Interface. Write Command when CNT=0 .........................................................................................44 Figure 13: 3-Wire Interface. Write Command when HiZ=1 and WFR=1.......................................................................44 Figure 14: Functions defined by V1..............................................................................................................................45 Figure 15: Voltage. Current, Momentary and Accumulated Energy .............................................................................47 Figure 16: Timing Relationship between ADC MUX, Compute Engine, and Serial Transfers. .....................................48 Figure 17: RTM Output Format ....................................................................................................................................49 Figure 18: Operation Modes State Diagram.................................................................................................................50 Figure 19: Functional Blocks in BROWNOUT Mode (inactive blocks grayed out)........................................................52 Figure 20: Functional Blocks in LCD Mode (inactive blocks grayed out)......................................................................53 Figure 21: Functional Blocks in SLEEP Mode (inactive blocks grayed out) .................................................................54 Figure 22: Transition from BROWNOUT to MISSION Mode when System Power Returns .........................................55 Figure 23: Power-Up Timing with V3P3SYS and VBAT tied together ..........................................................................55 Figure 24: Power-Up Timing with VBAT only ...............................................................................................................56 Figure 25: Wake Up Timing..........................................................................................................................................57 Figure 26: MPU/CE Data Flow .....................................................................................................................................58 Figure 27: MPU/CE Communication ............................................................................................................................58 Figure 28: Resistive Voltage Divider (Left), Current Transformer (Right) .....................................................................60 Figure 29: Resistive Shunt ...........................................................................................................................................60 Figure 30: Connecting LCDs ........................................................................................................................................61 Figure 31: I2C EEPROM Connection............................................................................................................................63 Figure 32: Three-Wire EEPROM Connection...............................................................................................................63 Figure 33: Connections for the RX Pin .........................................................................................................................64 Figure 34: Connection for Optical Components ...........................................................................................................65 Figure 35: Voltage Divider for V1 .................................................................................................................................65 Figure 36: External Components for the RESET Pin: Push-Button (Left), EMI Circuit (Right) .....................................66 Figure 37: External Components for the Emulator Interface ........................................................................................66 Figure 38: Wh Accuracy, 0.1A to 200A at 240V/50Hz and Room Temperature...........................................................91 Figure 39: Meter Accuracy over Harmonics at 240V, 30A............................................................................................91 Figure 40: Typical Meter Accuracy over Temperature Relative to 25C.......................................................................92 V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 5 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 List of Tables Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles ...........................................................................9 Table 2: CE DRAM Locations for ADC Results............................................................................................................13 Table 3: Memory Map ..........................................................................................................................................16 Table 4: Stretch Memory Cycle Width ..........................................................................................................................17 Table 5: Internal Data Memory Map.............................................................................................................................18 Table 6: Special Function Registers Locations ............................................................................................................18 Table 7: Special Function Registers Reset Values ......................................................................................................19 Table 8: PSW Register Flags .......................................................................................................................................20 Table 9: PSW Bit Functions .........................................................................................................................................20 Table 10: Port Registers ..........................................................................................................................................21 Table 11: Special Function Registers...........................................................................................................................22 Table 12: Baud Rate Generation..................................................................................................................................23 Table 13: UART Modes ..........................................................................................................................................23 Table 14: The S0CON Register ...................................................................................................................................23 Table 15: The S1CON register.....................................................................................................................................23 Table 16: The S0CON Bit Functions ............................................................................................................................24 Table 17: The S1CON Bit Functions ............................................................................................................................24 Table 18: The TCON Register......................................................................................................................................25 Table 19: The TCON Register Bit Functions................................................................................................................25 Table 20: The TMOD Register .....................................................................................................................................26 Table 21: TMOD Register Bit Description ....................................................................................................................26 Table 22: Timers/Counters Mode Description ..............................................................................................................26 Table 23: Timer Modes ..........................................................................................................................................27 Table 24: The PCON Register .....................................................................................................................................27 Table 25: PCON Register Bit Description.....................................................................................................................27 Table 26: The IEN0 Register (see also Table 32) ........................................................................................................28 Table 27: The IEN0 Bit Functions (see also Table 32).................................................................................................28 Table 28: The IEN1 Register (see also Tables 30/31) .................................................................................................28 Table 29: The IEN1 Bit Functions (see also Tables 31/32) ..........................................................................................28 Table 30: The IP0 Register (see also Table 45)...........................................................................................................29 Table 31: The IP0 bit Functions (see also Table 45)....................................................................................................29 Table 32: The WDTREL Register.................................................................................................................................29 Table 33: The WDTREL Bit Functions .........................................................................................................................29 Table 34: The IEN0 Register........................................................................................................................................30 Table 35: The IEN0 Bit Functions ................................................................................................................................30 Table 36: The IEN1 Register........................................................................................................................................30 Table 37: The IEN1 Bit Functions ................................................................................................................................31 Table 38: The IEN2 Register........................................................................................................................................31 Table 39: The IEN2 Bit Functions ................................................................................................................................31 Table 40: The TCON Register......................................................................................................................................31 Table 41: The TCON Bit Functions ..............................................................................................................................31 Table 42: The T2CON Bit Functions ............................................................................................................................32 Table 43: The IRCON Register ....................................................................................................................................32 Table 44: The IRCON Bit Functions.............................................................................................................................32 Table 45: External MPU Interrupts ...............................................................................................................................33 Page: 6 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Table 46: Interrupt Enable and Flag Bits .....................................................................................................................33 Table 47: Priority Level Groups....................................................................................................................................34 Table 48: The IP0 Register 34 Table 49: The IP1 Register: .........................................................................................................................................34 Table 50: Priority Levels ..........................................................................................................................................35 Table 51: Interrupt Polling Sequence ...........................................................................................................................35 Table 52: Interrupt Vectors ..........................................................................................................................................35 Table 53: Data/Direction Registers and Internal Resources for DIO Pin Groups .........................................................39 Table 54: DIO_DIR Control Bit .....................................................................................................................................40 Table 55: Selectable Controls using the DIO_DIR Bits ................................................................................................41 Table 56: EECTRL Status Bits .....................................................................................................................................42 Table 57: EECTRL bits for 3-wire interface .................................................................................................................43 Table 58: TMUX[4:0] Selections...................................................................................................................................46 Table 59: Available Circuit Functions ("--" means "not active).....................................................................................51 Table 60: LCD and DIO Pin Assignment by LCD_NUM ...............................................................................................62 V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 7 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 VREF V3P3A GNDA V3P3SYS ADC CONVERTER IA VA IB VB MUX VBIAS VBIAS V3P3D - V3P3A + FIR ADC_E VREF MUX TEMP MUX CTRL EQU MUX_ALT CHOP_E MUX_DIV VREF VREF_CAL VREF_DIS FIR_LEN VBAT CROSS CK32 VOLT REG X4MHZ XIN MCK PLL 32KHz OSC (32KHz) XOUT CKTEST/ SEG19 DIV ADC CK32 32KHz CKOUT_E CKADC 4.9MHz V2P5 CKFIR 4.9MHz 4.9MHz 2.5V to logic CKOUT_E CK_GEN V3P3D CK_2X LCD_GEN ECK_DIS MPU_DIV MUX_SYNC STRT CKCE CE TEST MODE MUX RTM 32 bit Compute Engine LCD DISPLAY DRIVER DATA 00-7F PROG 000-1FF CE CONTROL MEMORY SHARE 1000-11FF RTM_0..3 RTM_E CE_E LCD_NUM LCD_MODE LCD_CLK LCD_E LCD_BLKMAP LCD_SEG LCD_Y COM0..3 SEG0..18 SEG32,33 SEG19,38 VARPULSE DIO1,2 PB I/O RAM EEPROM INTERFACE SEG24/DIO4 .. SEG31/DIO11 SEG34/DIO14 .. SEG37/DIO17 DIGITAL I/O DIO_EEX DIO_PV/PW DIO_DIR DIO_R LCD_NUM DIO WPULSE XFER BUSY CE_BUSY PLS_INV PLS_INTERVAL PLS_MAXWIDTH CE_LCTN EQU PRE_SAMPS SUM_CYCLES VLC0 LCD_MODE LCD_E WPULSE VARPULSE VLC2 VLC1 CE RAM (0.5KB) <4.9MHz TEST GNDD LCD_ONLY SLEEP CKMPU <4.9MHz SDCK SDIN UART TX OPT_RX/ DIO1 OPT_TX/ DIO2/ WPULSE/ VARPULSE CONFIG (I/O RAM) SDOUT RX MPU (80515) 2000-20FF DATA 0000-FFFF 0000-07FF OPTICAL OPT_RXDIS OPT_RXINV OPT_TXE OPT_TXINV OPT_TXMOD OPT_FDC PROG 0000-1FFF VBIAS POWER FAULT MPU_RSTZ MEMORY SHARE CE_LCTN 00001FFF MPU XRAM (2KB) FLASH 8KB FLSH66ZT EMULATOR PORT WAKE V1 FAULTZ E_RXTX E_TCLK E_RST (Open Drain) COMP_STAT RESET CONFIGURATION PARAMETERS E_RXTX/SEG38 ICE_E TEST MUX TMUXOUT TMUX[4:0] February 2, 2007 E_TCLK/SEG33 E_RST/SEG32 Figure 1: IC Functional Block Diagram Page: 8 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 HARDWARE DESCRIPTION Hardware Overview The TERIDIAN 71M6521BE single-chip energy meter integrates all primary functional blocks required to implement a solidstate electricity meter. Included on chip are an analog front end (AFE), an independent digital computation engine (CE), an 8051-compatible microprocessor (MPU) which executes one instruction per clock cycle (80515), a voltage reference, a temperature sensor, LCD drivers, RAM, Flash memory, and a variety of I/O pins. Various current sensor technologies are supported including Current Transformers (CT) and Resistive Shunts. In a typical application, the 32-bit compute engine (CE) of the 71M6521BE sequentially processes the samples from the voltage inputs on pins IA, VA, IB, VB1 and performs calculations to measure active energy (Wh). This measurement is then accessed by the MPU, processed further and output using the peripheral devices available to the MPU. Measurements can be displayed on 3.3V LCD commonly used in low temperature environments. Flexible mapping of LCD display segments will facilitate integration of existing custom LCD. Design trade-off between the number of LCD segments vs. DIO pins can be implemented in software to accommodate various requirements. The on-chip digital temperature compensation mechanism includes a temperature sensor and associated controls for correction of unwanted temperature effects on measurement. Temperature dependent external components such as crystal oscillator, current sensors, and their corresponding signal conditioning circuits can be characterized and their correction factors can be programmed to produce electricity meters with exceptional accuracy over the industrial temperature range. One of the two internal UARTs is adapted to support an Infrared LED with internal drive and sense configuration, and can also function as a standard UART. The optical output can be modulated at 38kHz. This flexibility makes it possible to implement AMR meters with an IR interface. A block diagram of the IC is shown in Figure 1. A detailed description of various functional blocks follows. Analog Front End (AFE) The AFE of the 71M6521BE is comprised of an input multiplexer, a delta-sigma A/D converter and a voltage reference. Input Multiplexer The input multiplexer supports up to four input signals that are applied to pins IA, VA, IB and VB1 of the device. Additionally, using the alternate multiplexer selection, it has the ability to select temperature and the battery voltage. The multiplexer can be operated in two modes: * * During a normal multiplexer cycle, the signals from the IA, IB, VA, and VB pins are selected. During the alternate (ALT) multiplexer cycle, the temperature signal (TEMP) and the battery monitor are selected, along with the signal sources shown in Table 1. To prevent unnecessary drainage on the battery, the battery monitor is enabled only with the BME bit (0x2020[6]) in the I/O RAM. The alternate multiplexer cycles are usually performed infrequently (e. g. every second or so) by the MPU. In order to prevent disruption of the voltage tracking PLL and voltage allpass networks, VA is not replaced in the ALT multiplexer selections. Missing samples due to an ALT multiplexer sequence are filled in by the CE. EQU 0 Regular MUX Sequence ALT MUX Sequence Mux State Mux State 0 IA 1 VA 2 IB 3 VB 0 TEMP 1 VA 2 IB 3 VBAT Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles 1 : VB is available, but not used in typical 1-phase, 2-wire meters V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 9 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 In a typical application, IA and IB are connected to current transformers that sense the current on each phase of the line voltage. VA is typically connected to a voltage sensor (resistor divider). The multiplexer control circuit handles the setting of the multiplexer. The function of the multiplexer control circuit is governed by the I/O RAM registers MUX_ALT, MUX_DIV and EQU. MUX_DIV controls the number of samples per cycle. It can request 2, 3, or 4 multiplexer states per cycle. Multiplexer states above 4 are reserved and must not be used. The multiplexer always starts at the beginning of its list and proceeds until MUX_DIV states have been converted. The MUX_ALT bit requests an alternative multiplexer frame. The bit may be asserted on any MPU cycle and may be subsequently de-asserted on any cycle including the next one. A rising edge on MUX_ALT will cause the multiplexer control circuit to wait until the next multiplexer cycle and implement a single alternate cycle. The multiplexer control circuit also controls the FIR filter initiation and the chopping of the ADC reference voltage, VREF. The multiplexer control circuits clocked by CK32, the 32768Hz clock from the PLL block, and launches each pass through the CE program. A/D Converter (ADC) A single delta-sigma A/D converter digitizes the voltage and current inputs to the 71M6521BE. The resolution of the ADC is programmable using the FIR_LEN register as shown in the I/O RAM section. ADC resolution can be selected to be 21 bits (FIR_LEN=0), or 22 bits (FIR_LEN=1). Conversion time is two cycles of CK32 with FIR_LEN = 0 and three cycles with FIR_LEN = 1. In order to provide the maximum resolution, the ADC should be operated with FIR_LEN = 1. Accuracy and timing specifications in this data sheet are based on FIR_LEN = 1. Initiation of each ADC conversion is controlled by the multiplexer control circuit as described previously. At the end of each ADC conversion, the FIR filter output data is stored into the CE DRAM location determined by the multiplexer selection. FIR Filter The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multiplexer. The purpose of the FIR filter is to decimate the ADC output to the desired resolution. At the end of each ADC conversion, the output data is stored into the fixed CE DRAM location determined by the multiplexer selection. FIR data is stored LSB justified, but shifted left by nine bits. Voltage References The device includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques. The reference is trimmed to minimize errors caused by component mismatch and drift. The result is a voltage output with a predictable temperature coefficient. The amplifier within the reference is chopper stabilized, i.e. the polarity can be switched by the MPU using the I/O RAM register CHOP_E (0x2002[5:4]). The two bits in the CHOP_E register enable the MPU to operate the chopper circuit in regular or inverted operation, or in "toggling" mode. When the chopper circuit is toggled in between multiplexer cycles, DC offsets on the measured signals will automatically be averaged out. The general topology of a chopped amplifier is given in Figure 2. Page: 10 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 A Vinp B A Vinn A + G - B Voutp B A Voutn B CROSS Figure 2: General Topology of a Chopped Amplifier It is assumed that an offset voltage Voff appears at the positive amplifier input. With all switches, as controlled by CROSS in the "A" position, the output voltage is: Voutp - Voutn = G (Vinp + Voff - Vinn) = G (Vinp - Vinn) + G Voff With all switches set to the "B" position by applying the inverted CROSS signal, the output voltage is: Voutn - Voutp = G (Vinn - Vinp + Voff) = G (Vinn - Vinp) + G Voff, or Voutp - Voutn = G (Vinp - Vinn) - G Voff Thus, when CROSS is toggled, e.g. after each multiplexer cycle, the offset will alternately appear on the output as positive and negative, which results in the offset effectively being eliminated, regardless of its polarity or magnitude. When CROSS is high, the hookup of the amplifier input devices is reversed. This preserves the overall polarity of that amplifier gain, it inverts its input offset. By alternately reversing the connection, the amplifier's offset is averaged to zero. This removes the most significant long-term drift mechanism in the voltage reference. The CHOP_E bits control the behavior of CROSS. The CROSS signal will reverse the amplifier connection in the voltage reference in order to negate the effects of its offset. On the first CK32 rising edge after the last mux state of its sequence, the mux will wait one additional CK32 cycle before beginning a new frame. At the beginning of this cycle, the value of CROSS will be updated according to the CHOP_E bits. The extra CK32 cycle allows time for the chopped VREF to settle. During this cycle, MUXSYNC is held high. The leading edge of muxsync initiates a pass through the CE program sequence. The beginning of the sequence is the serial readout of the 4 RTM words. CHOP_E has 3 states: positive, reverse, and chop. In the `positive' state, CROSS is held low. In the `reverse' state, CROSS is held high. In the `chop' state, CROSS is toggled near the end of each Mux Frame, as described above. It is desirable that CROSS take on alternate values at the beginning of each Mux cycle. For this reason, if `chop' state is selected, CROSS will not toggle at the end of the last Mux cycle in a SUM cycle. The internal bias voltage VBIAS (typically 1.6V) is used by the ADC when measuring the temperature and battery monitor signals. Temperature Sensor The 71M6521BE includes an on-chip temperature sensor implemented as a bandgap reference. It is used to determine the die temperature The MPU may request an alternate multiplexer cycle containing the temperature sensor output by asserting MUX_ALT. The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system (see section titled "Temperature Compensation"). V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 11 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Battery Monitor The battery voltage is measured by the ADC during alternative multiplexer frames if the BME (Battery Measure Enable) bit in the I/O RAM is set. While BME is set, an on-chip 45k load resistor is applied to the battery, and a scaled fraction of the battery voltage is applied to the ADC input. After each alternative MUX frame, the result of the ADC conversion is available at CE DRAM address 07. BME is ignored and assumed zero when system power is not available (V1 < VBIAS). See the Battery Monitor section of the Electrical Specifications for details regarding the ADC LSB size and the conversion accuracy. Functional Description The AFE functions as a data acquisition system, controlled by the MPU. The main signals (IA, VA, IB, VB) are sampled and the ADC counts obtained are stored in CE DRAM where they can be accessed by the CE and, if necessary, by the MPU. Alternate multiplexer cycles are initiated less frequently by the MPU to gather access to the slow temperature and battery signals. VREF IA VA IB VB ADC CONVERTER MUX VBIAS VBIAS VBAT V3P3A FIR + ADC_E VREF TEMP MUX MUX CTRL EQU MUX_ALT CHOP_E MUX_DIV VREF VREF_CAL VREF_DIS FIR_LEN CROSS CK32 4.9MHz FIR_DONE FIR_START Figure 3: AFE Block Diagram Digital Computation Engine (CE) The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately measure energy. The CE calculations and processes include: * Multiplication of each current sample with its associated voltage sample to obtain the energy per sample (when multiplied with the constant sample time). * Frequency-insensitive delay cancellation on all channels (to compensate for the delay between samples caused by the multiplexing scheme). * Pulse generation. * Monitoring of the input signal frequency (for frequency and phase information). * Monitoring of the input signal amplitude (for sag detection). * Scaling of the processed samples based on calibration coefficients. The CE program resides in flash memory. Common access to flash memory by CE and MPU is controlled by a memory share circuit. Each CE instruction word is two bytes long. Allocated flash space for the CE program cannot exceed 1024 words (2KB). The CE program counter begins a pass through the CE code each time multiplexer state 0 begins. The code pass ends when a HALT instruction is executed. For proper operation, the code pass must be completed before the multiplexer cycle ends (see System Timing Summary in the Functional Description Section). Page: 12 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 The CE program must begin on a 1Kbyte boundary of the flash address. The I/O RAM register CE_LCTN[4:0] defines which 1KB boundary contains the CE code. Thus, the first CE instruction is located at 1024*CE_LCTN[4:0]. The CE DRAM can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time slots are reserved for FIR, RTM, and MPU, respectively, to prevent bus contention for CE DRAM data access. Holding registers are used to convert 8-bit wide MPU data to/from 32-bit wide CE DRAM data, and wait states are inserted as needed, depending on the frequency of CKMPU. The CE DRAM is 128 32-bit words. The MPU can read and write the CE DRAM as the primary means of data communication between the two processors. Table 2 shows the CE DRAM addresses allocated to analog inputs from the AFE. Address (HEX) 00 01 02 03 04 05 06 07 Name IA VA IB VB TEMP VBAT Description Phase A current Phase A voltage Phase B current (Phase B voltage - not used) Not used Not used Temperature Battery Voltage Table 2: CE DRAM Locations for ADC Results The CE of the 71M6521BE is aided by support hardware that facilitates implementation of equations, pulse counters, and accumulators. This support hardware is controlled through I/O RAM locations EQU (equation assist), DIO_PV and DIO_PW (pulse count assist), and PRE_SAMPS and SUM_CYCLES (accumulation assist). PRE_SAMPS and SUM_CYCLES support a dual level accumulation scheme where the first accumulator accumulates results from PRE_SAMPS samples and the second accumulator accumulates up to SUM_CYCLES of the first accumulator results. The integration time for each energy output is PRE_SAMPS * SUM_CYCLES/2520.6 (with MUX_DIV = 1). CE hardware issues the XFER_BUSY interrupt when the accumulation is complete. Meter Equations Compute Engine (CE) firmware for residential meter configurations implements the calculations for equation 0 for a singleelement, 2-wire, 1-phase meter with neutral current sense and tamper detection. The energy for element 0 is determined by VA*IA, and the energy for element 1 is determined by VA*IB. Real-Time Monitor The CE contains a Real-Time Monitor (RTM), which can be programmed through the UART to monitor four selectable CE DRAM locations at full sample rate. The four monitored locations are serially output to the TMUXOUT pin via the digital output multiplexer at the beginning of each CE code pass. The RTM can be enabled and disabled with RTM_EN. The RTM output is clocked by CKTEST. Each RTM word is clocked out in 35 cycles and contains a leading flag bit. See the Functional Description section for the RTM output format. RTM is low when not in use. Pulse Generator The chip contains a pulse generator that creates low-jitter Wh pulses at a rate set by the CE. The I/O RAM bit DIO_PW, as described in the Digital I/O section, can be programmed to route WPULSE to the output pin DIO6. Pulses can also be output on OPT_TX (see OPT_TXE[1:0] for details). The value of PLS_INTERVAL depends on the sample rate (nominal 2520Hz) and the number of times the pulse generator is executed in the CE code. Changing these values would require redesign of all CE filters and/or modification of the CE pulse generator code. Since these numbers are fixed for the CE code supplied by TERIDIAN, the value of PLS_INTERVAL is also fixed, to a value of 0x81. V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 13 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 On-chip hardware provides a maximum pulse width feature: PLS_MAXWIDTH[7:0] selects a maximum negative pulse width to be `Nmax' updates according to the formula: Nmax = (2*PLS_MAXWIDTH+1). If PLS_MAXWIDTH = 255, no width checking is performed. Given that PLS_INTERVAL = 81, the maximum pulse width is determined by: Maximum Pulse Width = (2 * PLS_MAXWIDTH +1) * 81*4*203ns = 65.8s + PLS_MAXWIDTH * 131.5s The CE pulse output polarity is programmable to be either positive or negative. Pulse polarity may be inverted with PLS_INV. When this bit is set, the pulses are active high, rather than the more usual active low. CE Functional Overview The ADC processes one sample per channel per multiplexer cycle. Figure 4 shows the timing of the samples taken during one multiplexer cycle. The number of samples processed during one accumulation cycle is controlled by the I/O RAM registers PRE_SAMPS (0x2001[7:6]) and SUM_CYCLES (0x2001[5:0]). The integration time for each energy output is PRE_SAMPS * SUM_CYCLES / 2520.6, where 2520.6 is the sample rate [Hz] For example, PRE_SAMPS = 42 and SUM_CYCLES = 50 will establish 2100 samples per accumulation cycle. PRE_SAMPS = 100 and SUM_CYCLES = 21 will result in the exact same accumulation cycle of 2100 samples or 833ms. After an accumulation cycle is completed, the XFER_BUSY interrupt signals to the MPU that accumulated data are available. 1/32768Hz = 30.518s IB VB IA VA 13/32768Hz = 397s per mux cycle Figure 4: Samples from Multiplexer Cycle The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each multiplexer cycle, status information, such as sag data and the digitized input signal, is available to the MPU. Page: 14 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 833ms 20ms XFER_BUSY Interrupt to MPU Figure 5: Accumulation Interval Figure 5 shows the accumulation interval resulting from PRE_SAMPS = 42 and SUM_CYCLES = 50, consisting of 2100 samples of 397s each, followed by the XFER_BUSY interrupt. The sampling in this example is applied to a 50Hz signal. There is no correlation between the line signal frequency and the choice of PRE_SAMPS or SUM_CYCLES (even though when SUM_CYCLES = 42 one set of SUM_CYCLES happens to sample a period of 16.6ms). Furthermore, sampling does not have to start when the line voltage crosses the zero line, and the length of the accumulation interval need not be an integer multiple of the signal cycles. It is important to note that the length of the accumulation interval, as determined by NACC, the product of SUM_CYCLES and PRE_SAMPS, is not an exact multiple of 1000ms. For example, if SUM_CYCLES = 60, and PRE_SAMPS = 00 (42), the resulting accumulation interval is: = N ACC 60 42 2520 = = 999.75ms = 32768 Hz 2520.62 Hz fS 13 This means that accurate time measurements should be not be based on the accumulation interval without correction. V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 15 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 80515 MPU Core The 71M6521BE includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a 5MHz clock results in a processing throughput of 5 MIPS. The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. Normally a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte instructions are performed in a single cycle. This leads to an 8x performance (in average) improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency. Actual processor clocking speed can be adjusted to the total processing demand of the application (metering calculations, AMR management, memory management, LCD driver management and I/O management) using the I/O RAM register MPU_DIV[2:0]. Typical measurement and metering functions based on the results provided by the internal 32-bit compute engine (CE) are available for the MPU as part of TERIDIAN's standard library. A standard ANSI "C" 80515-application programming interface library is available to help reduce design cycle. Memory Organization The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces. Memory organization in the 80515 is similar to that of the industry standard 8051. There are three memory areas: Program memory (Flash), external data memory (XRAM), physically consisting of XRAM, CE DRAM, and I/O RAM, and internal data memory (Internal RAM). Table 3 shows the memory map. Address (hex) 0000-1FFF on 1K boundary 0000-07FF 1000-11FF 2000-20FF Memory Technology Wait States Memory Size (at 5MHz) (bytes) 0 8K CE program 0 2K MPU data XRAM, CE data Configuration RAM I/O RAM 0 6 2K 512 0 256 Memory Type Typical Usage Flash Memory Non-volatile MPU Program and nonvolatile data Flash Memory Non-volatile Static RAM Static RAM Volatile Volatile Static RAM Volatile Table 3: Memory Map Internal and External Data Memory: Both internal and external data memory are physically located on the 71M6521BE IC. "External" data memory is only external to the 80515 MPU core. Program Memory: The 80515 can theoretically address up to 64KB of program memory space from 0x0000 to 0xFFFF. Program memory is read when the MPU fetches instructions or performs a MOVC operation. After reset, the MPU starts program execution from location 0x0000. The lower part of the program memory includes reset and interrupt vectors. The interrupt vectors are spaced at 8-byte intervals, starting from 0x0003. External Data Memory: While the 80515 is capable of addressing up to 64KB of external data memory in the space from 0x0000 to 0xFFFF, only the memory ranges shown in Error! Reference source not found. contain physical memory. The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX A,@DPTR instruction (SFR USR2 provides the upper 8 bytes for the MOVX A,@Ri instruction). Clock Stretching: MOVX instructions can access fast or slow external RAM and external peripherals. The three low order bits of the CKCON register define the stretch memory cycles. Setting all the CKCON stretch bits to one allows access to very slow external RAM or external peripherals. Page: 16 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Table 4 shows how the signals of the External Memory Interface change when stretch values are set from 0 to 7. The widths of the signals are counted in MPU clock cycles. The post-reset state of the CKCON register, which is in bold in the table, performs the MOVX instructions with a stretch value equal to 1. CKCON register Stretch Value Read signals width Write signal width memaddr memrd memaddr memwr 0 1 1 2 1 1 1 2 2 3 1 0 2 3 3 4 2 1 1 3 4 4 5 3 1 0 0 4 5 5 6 4 1 0 1 5 6 6 7 5 1 1 0 6 7 7 8 6 1 1 1 7 8 8 9 7 CKCON.2 CKCON.1 CKCON.0 0 0 0 0 0 0 1 0 Table 4: Stretch Memory Cycle Width There are two types of instructions, differing in whether they provide an eight-bit or sixteen-bit indirect address to the external data RAM. In the first type (MOVX A,@Ri), the contents of R0 or R1, in the current register bank, provide the eight lower-ordered bits of address. The eight high-ordered bits of address are specified with the USR2 SFR. This method allows the user paged access (256 pages of 256 bytes each) to all ranges of the external data RAM. In the second type of MOVX instruction (MOVX A,@DPTR), the data pointer generates a sixteen-bit address. This form is faster and more efficient when accessing very large data arrays (up to 64 Kbytes), since no additional instructions are needed to set up the eight high ordered bits of address. It is possible to mix the two MOVX types. This provides the user with four separate data pointers, two with direct access and two with paged access to the entire 64KB of external memory range. Dual Data Pointer: The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a 16-bit register that is used to address external memory or peripherals. In the 80515 core, the standard data pointer is called DPTR, the second data pointer is called DPTR1. The data pointer select bit chooses the active pointer. The data pointer select bit is located at the LSB of the DPS register (DPS.0). DPTR is selected when DPS.0 = 0 and DPTR1 is selected when DPS.0 = 1. The user switches between pointers by toggling the LSB of the DPS register. All DPTR-related instructions use the currently selected data pointer for any activity. The second data pointer may not be supported by certain compilers. Internal Data Memory: The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data memory address is always one byte wide and can be accessed by either direct or indirect addressing. The Special Function Registers occupy the upper 128 bytes. This SFR area is available only by direct addressing. Indirect addressing accesses the upper 128 bytes of Internal RAM. V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 17 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Internal Data Memory: The lower 128 bytes contain working registers and bit-addressable memory. The lower 32 bytes form four banks of eight registers (R0-R7). Two bits on the program memory status word (PSW) select which bank is in use. The next 16 bytes form a block of bit-addressable memory space at bit addressees 0x00-0x7F. All of the bytes in the lower 128 bytes are accessible through direct or indirect addressing. Table 5 shows the internal data memory map. Address Direct addressing Indirect addressing 0xFF Special Function Registers (SFRs) RAM 0x80 0x7F Byte-addressable area 0x30 0x2F Bit-addressable area 0x20 0x1F Register banks R0...R7 0x00 Table 5: Internal Data Memory Map Special Function Registers (SFRs) A map of the Special Function Registers is shown in Table 6. Hex\Bin Bit-addressable X000 Byte-addressable X001 X010 X011 X100 X101 Bin/Hex X110 X111 F8 F0 E8 E0 D8 INTBITS B WDI A WDCON FF F7 EF E7 DF D0 PSW D7 C8 T2CON CF C0 B8 B0 A8 A0 98 90 88 80 IRCON IEN1 C7 BF B7 AF A7 9F 97 8F 87 IP1 S0RELH IEN0 IP0 FLSHCTL S0RELL P2 S0CON DIR2 S0BUF P1 TCON DIR1 TMOD SP P0 DIR0 IEN2 DPS TL0 DPL S1RELH USR2 PGADR S1CON S1BUF S1RELL EEDATA EECTRL TL1 DPH ERASE TH0 DPL1 TH1 DPH1 CKCON WDTREL PCON Table 6: Special Function Registers Locations Only a few addresses are occupied, the others are not implemented. SFRs specific to the 6521BE are shown in bold print. Any read access to unimplemented addresses will return undefined data, while any write access will have no effect. The registers at 0x80, 0x88, 0x90, etc., are bit-addressable, all others are byte-addressable. Page: 18 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Special Function Registers (Generic 80515 SFRs) Table 7 shows the location of the SFRs and the value they assume at reset or power-up. Name P0 SP DPL DPH DPL1 DPH1 WDTREL PCON TCON TMOD TL0 TL1 TH0 TH1 CKCON P1 DPS S0CON S0BUF IEN2 S1CON S1BUF S1RELL P2 IEN0 IP0 S0RELL IEN1 IP1 S0RELH S1RELH USR2 IRCON T2CON PSW WDCON A B Location Reset Value 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x90 0x92 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0xA0 0xA8 0xA9 0xAA 0xB8 0xB9 0xBA 0xBB 0xBF 0xC0 0xC8 0xD0 0xD8 0xE0 0xF0 0xFF 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xD9 0x00 0x00 0x03 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Description Port 0 Stack Pointer Data Pointer Low 0 Data Pointer High 0 Data Pointer Low 1 Data Pointer High 1 Watchdog Timer Reload register UART Speed Control Timer/Counter Control Timer Mode Control Timer 0, low byte Timer 1, high byte Timer 0, low byte Timer 1, high byte Clock Control (Stretch=1) Port 1 Data Pointer select Register Serial Port 0, Control Register Serial Port 0, Data Buffer Interrupt Enable Register 2 Serial Port 1, Control Register Serial Port 1, Data Buffer Serial Port 1, Reload Register, low byte Port 2 Interrupt Enable Register 0 Interrupt Priority Register 0 Serial Port 0, Reload Register, low byte Interrupt Enable Register 1 Interrupt Priority Register 1 Serial Port 0, Reload Register, high byte Serial Port 1, Reload Register, high byte User 2 Port, high address byte for MOVX@Ri Interrupt Request Control Register Polarity for INT2 and INT3 Program Status Word Baud Rate Control Register (only WDCON.7 bit used) Accumulator B Register Table 7: Special Function Registers Reset Values V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 19 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Accumulator (ACC, A): ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The mnemonics for accumulator-specific instructions refer to accumulator as "A", not ACC. B Register: The B register is used during multiply and divide instructions. It can also be used as a scratch-pad register to hold temporary data. Program Status Word (PSW): MSB LSB CV AC F0 RS1 RS OV - P Table 8: PSW Register Flags Bit Symbol Function PSW.7 CV Carry flag PSW.6 AC Auxiliary Carry flag for BCD operations PSW.5 F0 General purpose Flag 0 available for user. F0 is not to be confused with the F0 flag in the CE STATUS register. PSW.4 PSW.3 RS1 Register bank select control bits. The contents of RS1 and RS0 select the working register bank: RS1/RS0 Bank selected 00 Bank 0 (0x00 - 0x07) 01 Bank 1 (0x08 - 0x0F) 10 Bank 2 (0x10 - 0x17) 11 Bank 3 (0x18 - 0x1F) RS0 Location Overflow flag PSW.2 OV PSW.1 - User defined flag PSW.0 P Parity flag, affected by hardware to indicate odd / even number of "one" bits in the Accumulator, i.e. even parity. Table 9: PSW Bit Functions Stack Pointer (SP): The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is incremented before PUSH and CALL instructions, causing the stack to begin at location 0x08. Data Pointer: The data pointer (DPTR) is 2 bytes wide. The lower part is DPL, and the highest is DPH. It can be loaded as two registers (e.g. MOV DPL,#data8). It is generally used to access external code or data space (e.g. MOVC A,@A+DPTR or MOVX A,@DPTR respectively). Program Counter: The program counter (PC) is 2 bytes wide initialized to 0x0000 after reset. This register is incremented when fetching operation code or when operating on data from program memory. Page: 20 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Port Registers: The I/O ports are controlled by Special Function Registers P0, P1, and P2. The contents of the SFR can be observed on corresponding pins on the chip. Writing a `1' to any of the ports (see Table 10) causes the corresponding pin to be at high level (V3P3), and writing a `0' causes the corresponding pin to be held at low level (GND). The data direction registers DIR0, DIR1, and DIR2 define individual pins as input or output pins (see section Digital I/O for details). SFR Address R/W Description P0 DIR0 0x80 0xA2 R/W R/W P1 DIR1 P2 DIR2 0x90 0x91 0xA0 0xA1 R/W R/W R/W R/W Register for port 0 read and write operations (pins DIO4...DIO7) Data direction register for port 0. Setting a bit to 1 means that the corresponding pin is an output. Register for port 1 read and write operations (pins DIO8...DIO11, DIO14...DIO15) Data direction register for port 1. Register for port 2 read and write operations (pins DIO16...DIO17) Data direction register for port 2. Register Table 10: Port Registers All DIO ports on the chip are bi-directional. Each of them consists of a Latch (SFR `P0' to `P2'), an output driver, and an input buffer, therefore the MPU can output or read data through any of these ports. Even if a DIO pin is configured as an output, the state of the pin can still be read by the MPU, for example when counting pulses issued via DIO pins that are under CE control. The technique of reading the status of or generating interrupts based on DIO pins configured as outputs, can be used to implement pulse counting. Special Function Registers Specific to the 71M6521BE Table 11 shows the location and description of the 71M6521BE-specific SFRs. Register ERASE Alternative Name FLSH_ERASE SFR Address R/W 0x94 W Description This register is used to initiate either the Flash Mass Erase cycle or the Flash Page Erase cycle. Specific patterns are expected for FLSH_ERASE in order to initiate the appropriate Erase cycle (default = 0x00). 0x55 - Initiate Flash Page Erase cycle. Must be preceded by a write to FLSH_PGADR @ SFR 0xB7. 0xAA - Initiate Flash Mass Erase cycle. Must be preceded by a write to FLSH_MEEN @ SFR 0xB2 and the debug port must be enabled. Any other pattern written to FLSH_ERASE will have no effect. PGADDR EEDATA EECTRL V1.0 FLSH_PGADR 0xB7 0x9E 0x9F R/W R/W R/W Flash Page Erase Address register containing the flash memory page address (page 0 thru 127) that will be erased during the Page Erase cycle (default = 0x00). Must be re-written for each new Page Erase cycle. I2C EEPROM interface data register 2 I C EEPROM interface control register. If the MPU wishes to write a byte of data to EEPROM, it places the data in EEDATA and then writes the `Transmit' code to EECTRL. The write to EECTRL initiates the transmit sequence. See the EEPROM Interface section for a description of the command and status bits available for EECTRL. (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 21 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 0xB2 FLSHCRL R/W W R/W R 0xE8 WDI R/W R/W W INTBITS INT0...INT6 0xF8 R Bit 0 (FLSH_PWE): Program Write Enable: 0 - MOVX commands refer to XRAM Space, normal operation (default). 1 - MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR. This bit is automatically reset after each byte written to flash. Writes to this bit are inhibited when interrupts are enabled. Bit 1 (FLSH_MEEN): Mass Erase Enable: 0 - Mass Erase disabled (default). 1 - Mass Erase enabled. Must be re-written for each new Mass Erase cycle. Bit 6 (SECURE): Enables security provisions that prevent external reading of flash memory and CE program RAM. This bit is reset on chip reset and may only be set. Attempts to write zero are ignored. Bit 7 (PREBOOT): Indicates that the preboot sequence is active. Only byte operations on the whole WDI register should be used when writing. The byte must have all bits set except the bits that are to be cleared. The multi-purpose register WDI contains the following bits: Bit 0 (IE_XFER): XFER Interrupt Flag: This flag monitors the XFER_BUSY interrupt. It is set by hardware and must be cleared by the interrupt handler Bit 1: Reserved Bit 7 (WD_RST): WD Timer Reset: Read: Reads the PLL_FALL interrupt flag Write 0: Clears the PLL_FALL interrupt flag Write 1: Resets the watch dog timer Interrupt inputs. The MPU may read these bits to see the input to external interrupts INT0, INT1, up to INT6. These bits do not have any memory and are primarily intended for debug use Table 11: Special Function Registers Instruction Set All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set and of the associated op-codes is contained in the 71M6521 Software User's Guide (SUG). UART The 71M6521BE includes a UART (UART0) that can be programmed to communicate with a variety of AMR modules. A second UART (UART1) is connected to the optical port, as described in the optical port description. The UART is a dedicated 2-wire serial interface, which can communicate with an external host processor at up to 38,400 bits/s ((with MPU clock = 1.2288MHz). The operation of each pin is as follows: RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are input LSB first. TX: This pin is used to output the serial data. The bytes are output LSB first. Page: 22 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 The 71M6521BE has several UART-related registers for the control and buffering of serial data. All UART transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud rates from 300 to 38400 bps. Table 12 shows how the baud rates are calculated. Table 13 shows the selectable UART operation modes. Using Timer 1 Using Internal Baud Rate Generator UART0 2SMOD * fCKMPU/ (384 * (256-TH1)) 2 SMOD * fCKMPU/(64 * (210-S0REL)) UART1 N/A fCKMPU/(32 * (210-S1REL)) Note: S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload registers. SMOD is the SMOD bit in the SFR PCON. TH1 is the high byte of timer 1. Table 12: Baud Rate Generation UART 0 UART 1 Mode 0 N/A Start bit, 8 data bits, parity, stop bit, variable baud rate (internal baud rate generator) Mode 1 Start bit, 8 data bits, stop bit, variable baud rate (internal baud rate generator or timer 1) Start bit, 8 data bits, stop bit, variable baud rate (internal baud rate generator) Mode 2 Start bit, 8 data bits, parity, stop bit, fixed baud rate 1/32 or 1/64 of fCKMPU N/A Mode 3 Start bit, 8 data bits, parity, stop bit, variable baud rate (internal baud rate generator or timer 1) N/A Table 13: UART Modes Parity of serial data is available through the P flag of the accumulator. Seven-bit serial modes with parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of 8-bit output data. Seven-bit serial modes without parity can be simulated by setting bit 7 to a constant 1. 8-bit serial modes with parity can be simulated by setting and reading the 9th bit, using the control bits TB80 (S0CON.3) and TB81 (S1CON.3) in the S0CON and S1CON SFRs for transmit and RB81 (S1CON.2) for receive operations. SM20 (S0CON.5) and SM21 (S1CON.5) can be used as handshake signals for inter-processor communication in multi-processor systems. Serial Interface 0 Control Register (S0CON). The function of the UART0 depends on the setting of the Serial Port Control Register S0CON. MSB SM0 LSB SM1 SM20 REN0 TB80 RB80 TI0 RI0 Table 14: The S0CON Register Serial Interface 1 Control Register (S1CON). The function of the serial port depends on the setting of the Serial Port Control Register S1CON. MSB SM LSB - SM21 REN1 TB81 RB81 TI1 RI1 Table 15: The S1CON register V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 23 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Bit Symbol S0CON.7 SM0 S0CON.6 Function These two bits set the UART0 mode: Mode Description SM0 SM1 0 N/A 0 0 1 8-bit UART 0 1 2 9-bit UART 1 0 3 9-bit UART 1 1 SM1 S0CON.5 SM20 Enables the inter-processor communication feature. S0CON.4 REN0 If set, enables serial reception. Cleared by software to disable reception. S0CON.3 TB80 The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the MPU, depending on the function it performs (parity check, multiprocessor communication etc.) S0CON.2 RB80 In Modes 2 and 3 it is the 9th data bit received. In Mode 1, if SM20 is 0, RB80 is the stop bit. In Mode 0 this bit is not used. Must be cleared by software S0CON.1 TI0 Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by software. S0CON.0 RI0 Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software Table 16: The S0CON Bit Functions Bit Symbol S1CON.7 SM Function Sets the baud rate for UART1 SM Mode Description Baud Rate 0 A 9-bit UART variable 1 B 8-bit UART variable S1CON.5 SM21 Enables the inter-processor communication feature. S1CON.4 REN1 If set, enables serial reception. Cleared by software to disable reception. S1CON.3 TB81 The 9th transmitted data bit in Mode A. Set or cleared by the MPU, depending on the function it performs (parity check, multiprocessor communication etc.) S1CON.2 RB81 In Modes A and B, it is the 9th data bit received. In Mode B, if SM21 is 0, RB81 is the stop bit. Must be cleared by software S1CON.1 TI1 Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by software. S1CON.0 RI1 Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software Table 17: The S1CON Bit Functions Page: 24 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Timers and Counters The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured for counter or timer operations. In timer mode, the register is incremented every machine cycle meaning that it counts up after every 12 periods of the MPU clock signal. In counter mode, the register is incremented when the falling edge is observed at the corresponding input signal T0 or T1 (T0 and T1 are the timer gating inputs derived from certain DIO pins, see the DIO Ports chapter). Since it takes two machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator frequency. There are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle. The timers/counters are controlled by the TCON Register Timer/Counter Control Register (TCON) MSB LSB TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Table 18: The TCON Register Bit Symbol Function TCON.7 TF1 The Timer 1 overflow flag is set by hardware when Timer 1 overflows. This flag can be cleared by software and is automatically cleared when an interrupt is processed. TCON.6 TR1 Timer 1 Run control bit. If cleared, Timer 1 stops. TCON.5 TF0 Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can be cleared by software and is automatically cleared when an interrupt is processed. TCON.4 TR0 Timer 0 Run control bit. If cleared, Timer 0 stops. TCON.3 IE1 Interrupt 1 edge flag is set by hardware when the falling edge on external pin int1 is observed. Cleared when an interrupt is processed. TCON.2 IT1 Interrupt 1 type control bit. Selects either the falling edge or low level on input pin to cause an interrupt. TCON.1 IE0 Interrupt 0 edge flag is set by hardware when the falling edge on external pin int0 is observed. Cleared when an interrupt is processed. TCON.0 IT0 Interrupt 0 type control bit. Selects either the falling edge or low level on input pin to cause interrupt. Table 19: The TCON Register Bit Functions V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 25 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function Registers (TMOD and TCON) are used to select the appropriate mode. Timer/Counter Mode Control register (TMOD): MSB LSB GATE C/T M1 Timer 1 M0 GATE C/T M1 Timer 0 M0 Table 20: The TMOD Register Bits TR1 (TCON.6) and TR0 (TCON.4) in the TCON register (see Table 18 and Table 19) start their associated timers when set. Bit Symbol Function TMOD.7 TMOD.3 Gate If set, enables external gate control (pin int0 or int1 for Counter 0 or 1, respectively). When int0 or int1 is high, and TRX bit is set (see TCON register), a counter is incremented every falling edge on T0 or T1 input pin TMOD.6 TMOD.2 C/T Selects Timer or Counter operation. When set to 1, a Counter operation is performed. When cleared to 0, the corresponding register will function as a Timer. TMOD.5 TMOD.1 M1 Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in TMOD description. TMOD.4 TMOD.0 M0 Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in TMOD description. Table 21: TMOD Register Bit Description M1 M0 Mode Function 0 0 Mode 0 13-bit Counter/Timer with 5 lower bits in the TL0 or TL1 register and the remaining 8 bits in the TH0 or TH1 register (for Timer 0 and Timer 1, respectively). The 3 high order bits of TL0 and TL1 are held at zero. 0 1 Mode 1 16-bit Counter/Timer. 1 0 Mode 2 8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or TH1, while TL0 or TL1 is incremented every machine cycle. When TL(x) overflows, a value from TH(x) is copied to TL(x). 1 1 Mode 3 If Timer 1 M1 and M0 bits are set to '1', Timer 1 stops. If Timer 0 M1 and M0 bits are set to '1', Timer 0 acts as two independent 8-bit Timer/Counters. Table 22: Timers/Counters Mode Description Note: Page: 26 of 97 In Mode 3, TL0 is affected by TR0 and gate control bits, and sets the TF0 flag on overflow, while TH0 is affected by the TR1 bit, and the TF1 flag is set on overflow. (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Table 23 specifies the combinations of operation modes allowed for timer 0 and timer 1: Timer 1 Mode 0 Mode 1 Mode 2 Timer 0 - mode 0 YES YES YES Timer 0 - mode 1 YES YES YES Timer 0 - mode 2 Not allowed Not allowed YES Table 23: Timer Modes Timer/Counter Mode Control register (PCON): MSB LSB SMOD -- -- -- -- -- -- -- Table 24: The PCON Register The SMOD bit in the PCON register doubles the baud rate when set. Bit Symbol PCON.7 SMOD Function Table 25: PCON Register Bit Description WD Timer (Software Watchdog Timer) The software watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles. After a reset, the watchdog timer is disabled and all registers are set to zero. The watchdog consists of a 16-bit counter (WDT), a reload register (WDTREL), prescalers (by 2 and by 16), and control logic. Once the watchdog is started, it cannot be stopped unless the internal reset signal becomes active. Note: It is recommended to use the hardware watchdog timer instead of the software watchdog timer. WD Timer Start Procedure: The WDT is started by setting the SWDT flag. When the WDT register enters the state 0x7CFF, an asynchronous WDTS signal will become active. The signal WDTS sets bit 6 in the IP0 register and requests a reset state. WDTS is cleared either by the reset signal or by changing the state of the WDT timer. Refreshing the WD Timer: The watchdog timer must be refreshed regularly to prevent the reset request signal from becoming active. This requirement imposes an obligation on the programmer to issue two instructions. The first instruction sets WDT and the second instruction sets SWDT. The maximum delay allowed between setting WDT and SWDT is 12 clock cycles. If this period has expired and SWDT has not been set, the WDT is automatically reset, otherwise the watchdog timer is reloaded with the content of the WDTREL register and the WDT is automatically reset. Since the WDT requires exact timing, firmware needs to be designed with special care in order to avoid unwanted WDT resets. TERIDIAN strongly discourages the use of the software WDT. V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 27 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Special Function Registers for the WD Timer Interrupt Enable 0 Register (IEN0): MSB LSB EAL WDT ET2 ES0 ET1 EX1 ET0 EX0 Table 26: The IEN0 Register (see also Table 32) Bit Symbol IEN0.6 WDT Function Watchdog timer refresh flag. Set to initiate a refresh of the watchdog timer. Must be set directly before SWDT is set to prevent an unintentional refresh of the watchdog timer. WDT is reset by hardware 12 clock cycles after it has been set. Table 27: The IEN0 Bit Functions (see also Table 32) Note: The remaining bits in the IEN0 register are not used for watchdog control Interrupt Enable 1 Register (IEN1): MSB LSB EXEN2 SWDT EX6 EX5 EX4 EX3 EX2 Table 28: The IEN1 Register (see also Tables 30/31) Bit Symbol IEN1.6 SWDT Function Watchdog timer start/refresh flag. Set to activate/refresh the watchdog timer. When directly set after setting WDT, a watchdog timer refresh is performed. Bit SWDT is reset by the hardware 12 clock cycles after it has been set. Table 29: The IEN1 Bit Functions (see also Tables 31/32) Note: The remaining bits in the IEN1 register are not used for watchdog control Page: 28 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Interrupt Priority 0 Register (IP0): MSB LSB -- WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0 Table 30: The IP0 Register (see also Table 45) Bit Symbol IP0.6 WDTS Function Watchdog timer status flag. Set when the watchdog timer was started. Can be read by software. Table 31: The IP0 bit Functions (see also Table 45) Note: The remaining bits in the IP0 register are not used for watchdog control Watchdog Timer Reload Register (WDTREL): MSB LSB 7 6 5 4 3 2 1 0 Table 32: The WDTREL Register Bit Symbol Function WDTREL.7 7 Prescaler select bit. When set, the watchdog is clocked through an additional divide-by-16 prescaler WDTREL.6 to WDTREL.0 6-0 Seven bit reload value for the high-byte of the watchdog timer. This value is loaded to the WDT when a refresh is triggered by a consecutive setting of bits WDT and SWDT. Table 33: The WDTREL Bit Functions The WDTREL register can be loaded and read at any time. Interrupts The 80515 provides 11 interrupt sources with four priority levels. Each source has its own request flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0, IEN1, and IEN2. External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the 71M6521BE, for example the CE, DIO, EEPROM interface. Interrupt Overview When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 52. Once interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a return from instruction, "RETI". When an RETI is performed, the processor will return to the instruction that would have been next when the interrupt occurred. V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 29 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 52. Once interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a return from instruction, "RETI". When a RETI instruction is performed, the processor will return to the instruction that would have been next when the interrupt occurred. When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, then samples are polled by the hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the interrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector address, if the following conditions are met: * No interrupt of equal or higher priority is already in progress. * An instruction is currently being executed and is not completed. * The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1. Special Function Registers for Interrupts: Interrupt Enable 0 register (IE0) MSB LSB EAL WDT ES0 ET1 EX1 ET0 EX0 Table 34: The IEN0 Register Bit Symbol Function IEN0.7 EAL EAL=0 - disable all interrupts IEN0.6 WDT Not used for interrupt control IEN0.5 - IEN0.4 ES0 ES0=0 - disable serial channel 0 interrupt IEN0.3 ET1 ET1=0 - disable timer 1 overflow interrupt IEN0.2 EX1 EX1=0 - disable external interrupt 1 IEN0.1 ET0 ET0=0 - disable timer 0 overflow interrupt IEN0.0 EX0 EX0=0 - disable external interrupt 0 Table 35: The IEN0 Bit Functions Interrupt Enable 1 Register (IEN1) MSB LSB SWDT EX6 EX5 EX4 EX3 EX2 Table 36: The IEN1 Register Page: 30 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Bit Symbol IEN1.7 - Function IEN1.6 SWDT IEN1.5 EX6 EX6=0 - disable external interrupt 6 IEN1.4 EX5 EX5=0 - disable external interrupt 5 IEN1.3 EX4 EX4=0 - disable external interrupt 4 IEN1.2 EX3 EX3=0 - disable external interrupt 3 IEN1.1 EX2 EX2=0 - disable external interrupt 2 IEN1.0 - Not used for interrupt control Table 37: The IEN1 Bit Functions Interrupt Enable 2 register (IE2) MSB LSB - - - - - - - ES1 Table 38: The IEN2 Register Bit Symbol IEN2.0 ES1 Function ES1=0 - disable serial channel 1 interrupt Table 39: The IEN2 Bit Functions Timer/Counter Control register (TCON) MSB LSB TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Table 40: The TCON Register Bit Symbol TCON.7 TF1 Function Timer 1 overflow flag TCON.6 TR1 Not used for interrupt control TCON.5 TF0 Timer 0 overflow flag TCON.4 TR0 Not used for interrupt control TCON.3 IE1 External interrupt 1 flag TCON.2 IT1 External interrupt 1 type control bit TCON.1 IE0 External interrupt 0 flag TCON.0 IT0 External interrupt 0 type control bit Table 41: The TCON Bit Functions V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 31 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Timer2/Counter2 Control register (T2CON): Bit Symbol Function T2CON.7 -- Not used T2CON.6 I3FR Polarity control for INT3: 0 - falling edge, 1 - rising edge T2CON.5 I2FR Polarity control for INT3: 0 - falling edge, 1 - rising edge TCON.4 ... T2CON0 -- Not used Table 42: The T2CON Bit Functions Interrupt Request register (IRCON) MSB LSB EX6 IEX5 IEX4 IEX3 IEX2 Table 43: The IRCON Register Bit Symbol Function IRCON.7 - IRCON.6 - IRCON.5 IEX6 External interrupt 6 edge flag IRCON.4 IEX5 External interrupt 5 edge flag IRCON.3 IEX4 External interrupt 4 edge flag IRCON.2 IEX3 External interrupt 3 edge flag IRCON.1 IEX2 External interrupt 2 edge flag IRCON.0 Table 44: The IRCON Bit Functions Note: Only TF0 and TF1 (timer 0 and timer 1 overflow flag) will be automatically cleared by hardware when the service routine is called (Signals T0ACK and T1ACK - port ISR - active high when the service routine is called). Page: 32 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 External Interrupts The 71M6521BE MPU allows seven external interrupts. These are connected as shown in Table 45. The direction of interrupts 2 and 3 is programmable in the MPU. Interrupts 2 and 3 should be programmed for falling sensitivity. The generic 8051 MPU literature states that interrupt 4 through 6 are defined as rising edge sensitive. Thus, the hardware signals attached to interrupts 5 and 6 are inverted to achieve the edge polarity shown in Table 45. External Interrupt 0 1 2 3 4 5 6 Connection Digital I/O High Priority Digital I/O Low Priority FWCOL0, FWCOL1 CE_BUSY PLL_OK (rising), PLL_OK (falling) EEPROM busy XFER_BUSY Polarity Flag Reset see DIO_Rx see DIO_Rx falling falling rising falling falling automatic automatic automatic automatic automatic automatic manual Table 45: External MPU Interrupts FWCOLx interrupts occur when the CE collides with a flash write attempt. See the flash write description for more detail. SFR (special function register) enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit, which is set by the interrupt hardware, and reset by the MPU interrupt handler. Note that XFER_BUSY, FWCOL0, FWCOL1, PLLRISE, PLLFALL, have their own enable and flag bits in addition to the interrupt 6, 4, and 2 enable and flag bits. IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler. The other flags, IE_XFER through IE_PB, are cleared by writing a zero to them. Since these bits are in a bit-addressable SFR byte, common practice would be to clear them with a bit operation. This is to be avoided. The hardware implements bit operations as a byte wide readmodify-write hardware macro. If an interrupt occurs after the read, but before the write, its flag will be cleared unintentionally. The proper way to clear the flag bits is to write a byte mask consisting of all ones except for a zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore ones written to them. Interrupt Enable Interrupt Flag Name Location Name Location EX0 EX1 EX2 EX3 EX4 EX5 EX6 EX_XFER SFR A8[[0] SFR A8[2] SFR B8[1] SFR B8[2] SFR B8[3] SFR B8[4] SFR B8[5] 2002[0] EX_FWCOL 2007[4] EX_PLL 2007[5] IE0 IE1 IEX2 IEX3 IEX4 IEX5 IEX6 IE_XFER IE_FWCOL0 IE_FWCOL1 IE_PLLRISE IE_PLLFALL IE_WAKE IE_PB SFR 88[1] SFR 88[3] SFR C0[1] SFR C0[2] SFR C0[3] SFR C0[4] SFR C0[5] SFR E8[0] SFR E8[3] SFR E8[2] SFRE8[6] SFRE8[7] SFRE8[5] SFRE8[4] Interrupt Description External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 XFER_BUSY interrupt (int 6) FWCOL0 interrupt (int 2) FWCOL1 interrupt (int 2) PLL_OK rise interrupt (int 4) PLL_OK fall interrupt (int 4) AUTOWAKE flag PB flag Table 46: Interrupt Enable and Flag Bits V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 33 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 The AUTOWAKE and PB flag bits are shown in Table 46 because they behave similarly to interrupt flags, even though they are not actually related to an interrupt. These bits are set by hardware when the MPU wakes from a push button or wake timeout. The bits are reset by writing a zero. Note that the PB flag is set whenever the PB is pushed, even if the part is already awake. Each interrupt has its own flag bit, which is set by the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). XFER_BUSY has its own enable and flag bit in addition to the interrupt 6 enable and flag bit (see Table 46), and these interrupts must be cleared by the MPU software. The external interrupts are connected as shown in Table 46. The polarity of interrupts 2 and 3 is programmable in the MPU via the I3FR and I2FR bits in T2CON. Interrupts 2 and 3 should be programmed for falling sensitivity. The generic 8051 MPU literature states that interrupts 4 through 6 are defined as rising edge sensitive. Thus, the hardware signals attached to interrupts 5 and 6 are inverted to achieve the edge polarity shown in Table 46. SFR (special function register) enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). Interrupt Priority Level Structure All interrupt sources are combined in groups, as shown in Table 47. Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in the special function register IP0 and one in IP1. If requests of the same priority level are received simultaneously, an internal polling sequence as per Table 51 determines which request is serviced first. An overview of the interrupt structure is given in Figure 6. Group 0 External interrupt 0 Serial channel 1 interrupt 1 Timer 0 interrupt - External interrupt 2 2 External interrupt 1 - External interrupt 3 3 Timer 1 interrupt - External interrupt 4 4 Serial channel 0 interrupt - External interrupt 5 5 - - External interrupt 6 Table 47: Priority Level Groups IEN enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). XFER_BUSY has its own enable and flag bit in addition to the interrupt 6 enable and flag bit (see Table 46) and this interrupt must be cleared by the MPU software. Interrupt Priority 0 Register (IP0) MSB LSB -- WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0 Table 48: The IP0 Register Note: WDTS is not used for interrupt controls Interrupt Priority 1 Register (IP1) MSB LSB - - IP1.5 IP1.4 IP1.3 IP1.2 IP1.1 IP1.0 Table 49: The IP1 Register: Page: 34 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 IP1.x IP0.x Priority Level 0 0 Level0 (lowest) 0 1 Level1 1 0 Level2 1 1 Level3 (highest) Table 50: Priority Levels External interrupt 0 Serial channel 1 interrupt Timer 0 interrupt Polling sequence External interrupt 2 External interrupt 1 External interrupt 3 Timer 1 interrupt External interrupt 4 Serial channel 0 interrupt External interrupt 5 External interrupt 6 Table 51: Interrupt Polling Sequence Interrupt Sources and Vectors Table 52 shows the interrupts with their associated flags and vector addresses. Interrupt Request Flag Description Interrupt Vector Address IE0 External interrupt 0 0x0003 TF0 Timer 0 interrupt 0x000B IE1 External interrupt 1 0x0013 TF1 Timer 1 interrupt 0x001B RI0/TI0 Serial channel 0 interrupt 0x0023 RI1/TI1 Serial channel 1 interrupt 0x0083 IEX2 External interrupt 2 0x004B IEX3 External interrupt 3 0x0053 IEX4 External interrupt 4 0x005B IEX5 External interrupt 5 0x0063 IEX6 External interrupt 6 0x006B Table 52: Interrupt Vectors V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 35 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Individual I nt erru pt Flags DIO General I nt er rupt Flags Lo gi c an d Polarity Selection I nt er rupt Control Regi s t er I nt err upt Enable IEN0.7 IEN0.0 Priority A s s i g nm en t IE0 IEN2.0 RI1 UART1 (optical) IP1.0/ IP0.0 Polling Se quence Internal/ External Source >=1 TI1 IEN0.1 Timer 0 TF0 IEN1.1 Flash Write Collision IE_FWCOL0 IE_FWCOL1 INT2 I2FR IP1.1/ IP0.1 I n t e rrup t Vector IRCON.1 IEN0.2 DIO IE1 IEN1.2 CE_BUSY INT3 Timer 1 TF1 I3FR IP1.2/ IP0.2 IRCON.2 IEN0.3 IEN1.3 PLL OK IE_PLLRISE IE_PLLFALL INT4 IRCON.3 IEN0.4 RI0 UART0 IP1.3/ IP0.3 >=1 TI0 IEN1.4 EEPROM/ I2C INT5 IP1.4/ IP0.4 IRCON.4 IEN1.5 XF ER_ BUSY IRCON.5 IE_XFER IP1.5/ IP0.5 INT6 RTC_1S IE_RTC Figure 6: Interrupt Structure Page: 36 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 On-Chip Resources Oscillator The 71M6521BE oscillator drives a standard 32.768kHz watch crystal. These crystals are accurate and do not require a highcurrent oscillator circuit. The 71M6521BE oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. PLL and Internal Clocks Timing for the device is derived from the 32.768kHz oscillator output. On-chip timing functions include the MPU master clock and the delta-sigma sample clock. In addition, the MPU has two general counter/timers (see MPU section). The ADC master clock, CKADC, is generated by an on-chip PLL. It multiplies the oscillator output frequency (CK32) by 150. The CE clock frequency is always CK32 * 150, or 4.9152MHz, where CK32 is the 32kHz clock. The MPU clock frequency is determined by MPU_DIV and can be 4.9152MHz *2-MPU_DIV Hz where MPU_DIV varies from 0 to 7 (MPU_DIV is 0 on powerup). This makes the MPU clock scalable from 4.9152MHz down to 38.4kHz. The circuit also generates a 2x MPU clock for use by the emulator. This clock is not generated when ECK_DIS is asserted by the MPU. The setting of MPU_DIV is maintained when the device transitions to BROWNOUT mode, but the time base in BROWNOUT mode is 28,672Hz. Temperature Sensor The device includes an on-chip temperature sensor for determining the temperature of the bandgap reference. The MPU may request an alternate multiplexer frame containing the temperature sensor output by asserting MUX_ALT. The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system (see section titled "Temperature Compensation"). Physical Memory Flash Memory: The 71M6521 includes 8KB of on-chip flash memory. The flash memory primarily contains MPU and CE program code. It also contains images of the CE DRAM, MPU RAM, and I/O RAM. On power-up, before enabling the CE, the MPU copies these images to their respective locations. Allocated flash space for the CE program cannot exceed 1024 words (2KB). The CE program must begin on a 1KB boundary of the flash address. The CE_LCTN[4:0] word defines which 1KB boundary contains the CE code. Thus, the first CE instruction is located at 1024*CE_LCTN[4:0]. The CE_LCTN[4:0] register must be set before the CE is enabled. The flash memory is segmented into 512 byte individually erasable pages. The CE engine cannot access its program memory when flash write occurs. Thus, the flash write procedure is to begin a sequence of flash writes when CE_BUSY falls (CE_BUSY interrupt) and to make sure there is sufficient time to complete the sequence before CE_BUSY rises again. The actual time for the flash write operation will depend on the exact number of cycles required by the CE program. Typically (CE program is 512 instructions, mux frame is 13 CK32 cycles), there will be 200s of flash write time, enough for 4 bytes of flash write. If the CE code is shorter, there will be even more time. Two interrupts warn of collisions between the 8051 firmware and the CE timing. If a flash write is attempted while the CE is busy, the flash write will not execute and the FW_COL0 interrupt will be issued. If a flash write is still in progress when the CE would otherwise begin a code pass, the code pass is skipped, the write is completed, and the FW_COL1 interrupt is issued. The bit FLASH66Z (see I/O RAM table) defines the speed for accessing flash memory. To minimize supply current draw, this bit should be set to 1. Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence. These special pattern/sequence requirements prevent inadvertent erasure of the flash memory. V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 37 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 The mass erase sequence is: 1. Write 1 to the FLSH_MEEN bit (SFR address 0xB2[1]. 2. Write pattern 0xAA to FLSH_ERASE (SFR address 0x94) The mass erase cycle can only be initiated when the ICE port is enabled. The page erase sequence is: 1. Write the page address to FLSH_PGADR (SFR address 0xB7[7:1] 2. Write pattern 0x55 to FLSH_ERASE (SFR address 0x94) The MPU may write to the flash memory. This is one of the non-volatile storage options available to the user in addition to external EEPROM. FLSH_PWE (flash program write enable) differentiates 80515 data store instructions (MOVX@DPTR,A) between Flash and XRAM writes. Updating individual bytes in flash memory: The original state of a flash byte is 0xFF (all ones). Once, a value other than 0xFF is written to a flash memory cell, overwriting with a different value usually requires that the cell is erased first. Since cells cannot be erased individually, the page has to be copied to RAM, followed by a page erase. After this, the page can be updated in RAM and then written back to the flash memory. MPU RAM: The 71M6521BE includes 2K-bytes of static RAM memory on-chip (XRAM) plus 256-bytes of internal RAM in the MPU core. The 2K-bytes of static RAM are used for data storage during normal MPU operations. CE DRAM: The CE DRAM is the working data memory of the CE (128 32-bit words). The MPU can read and write the CE DRAM as the primary means of data communication between the two processors. Optical Interface The device includes an interface to implement an IR/optical port. The pin OPT_Tx is designed to directly drive an external LED for transmitting data on an optical link. The pin OPT_RX is designed to sense the input from an external photo detector used as the receiver for the optical link. These two pins are connected to a dedicated UART port (UART1). The OPT_TX and OPT_RX pins can be inverted with configuration bits OPT_TXINV and OPT_RXINV, respectively. Additionally, the OPT_TX output may be modulated at 38kHz. Modulation is available when system power is present (i.e. not in BROWNOUT mode). The OPT_TXMOD bit enables modulation. Duty cycle is controlled by OPT_FDC[1:0], which can select 50%, 25%, 12.5%, and 6.25% duty cycle. 6.25% duty cycle means OPT_TX is low for 6.25% of the period. Figure 7 illustrates the OPT_TX generator. When not needed for the optical UART, the OPT_TX pin can alternatively be configured as DIO2 or WPULSE. The configuration bits are OPT_TXE[1:0]. Likewise, OPT_RX can alternately be configured as DIO_1. Its control is OPT_RXDIS. Page: 38 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 V3P3 Internal from OPT_TX UART WPULSE 2 DIO2 B 1 MOD A OPT_TXINV EN OPT_TXMOD OPT_FDC DUTY OPT_TX 0 OPT_TXE[1:0] 2 OPT_TXMOD=1, OPT_FDC=2 (25%) OPT_TXMOD=0 A A B B 1/38kHz Figure 7: Optical Interface Digital I/O The device includes up to 14 pins of general purpose digital I/O. These pins are compatible with 5V inputs (no current-limiting resistors are needed). Some are dual function that can alternatively be used as LCD drivers (DIO4-11, 14-17) and some share functions with the optical port (DIO1, DIO2). On reset or power-up, all DIO pins are inputs until they are configured for the desired direction under MPU control. The pins are configured by the DIO registers and by the five bits of the LCD_NUM register (located in I/O RAM). Once declared as DIO, each pin can be configured independently as an input or output with the DIO_DIRn bits. A 3-bit configuration word, DIO_Rx, can be used for certain pins, when configured as DIO, to individually assign an internal resource such as an interrupt or a timer control. Table 53 lists the direction registers and configurability associated with each group of DIO pins. Table 54 shows the configuration for a DIO pin through its associated bit in its DIO_DIR register. Tables showing the relationship between LCD_NUM and the available segment/DIO pins can be found in the Applications section and in the I/O RAM Description under LCD_NUM[4:0]. DIO Pin number 3 2 4 5 6 3 -37 38 39 2 -4 5 6 DIO0=P0 (SFR 0x80) 1 2 -4 5 6 DIO_DIR0 (SFR 0xA2) 7 40 7 8 41 0 9 42 1 7 0 1 Y Y Y Y Y Y 16 22 0 17 12 1 18 19 20 21 22 ----------DIO2=P2 (SFR 0xA0) 1 -----DIO_DIR2 (SFR 0xA1) 23 --- N -- PB 62 0 Data Register Direction Register Internal Resources Configurable DIO Pin number Data Register Direction Register Internal Resources Configurable 0 0 N 1 57 1 Y -- -- -- Y -- Y -- -- 10 11 12 13 14 43 44 --20 2 3 --6 DIO1=P1 (SFR 0x90) 2 3 --6 DIO_DIR1 (SFR 0x91) Y Y -- -- -- 15 21 7 7 -- -- Table 53: Data/Direction Registers and Internal Resources for DIO Pin Groups V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 39 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 DIO_DIR [n] DIO Pin n Function 0 1 Input Output Table 54: DIO_DIR Control Bit Additionally, if DIO6 is declared an output, it can be configured as dedicated pulse output (WPULSE = DIO6) using the DIO_PW register. In this case, DIO6 is under CE control. DIO4 and DIO5 can be configured to implement the EEPROM Interface. The PB pin is a dedicated digital input. If the optical UART is not used, OPT_TX and OPT_RX can be configured as dedicated DIO pins (DIO1, DIO2, see Optical Interface section). A 3-bit configuration word, I/O RAM register, DIO_Rx (0x2009[2:0] through 0x200E[6:4]) can be used for certain pins, when configured as DIO, to individually assign an internal resource such as an interrupt or a timer control (see Table 55 for DIO pins available for this option). This way, DIO pins can be tracked even if they are configured as outputs. Tracking DIO pins configured as outputs is useful for pulse counting without external hardware. When driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD (as shown in Figure 8, right), not source it from V3P3D (as shown in Figure 8, left). This is due to the resistance of the internal switch that connects V3P3D to either V3P3SYS or VBAT. When configured as inputs, the dual-function (DIO/SEG) pins should not be pulled above V3P3SYS in MISSION and above VBAT in LCD and BROWNOUT modes. Doing so will distort the LCD waveforms of the other pins. This limitation applies to any pin that can be configured as a LCD driver. 71M6521B 71M6521B V3P3SYS VBAT V3P3D 3.3V DIO1 V3P3SYS VBAT V3P3D 3.3V LED DIO1 R R LED DGND DGND Not recommended Recommended Figure 8: Connecting an External Load to DIO Pins The PB pin is a dedicated digital input. In addition, if the optical UART is not used, OPT_TX and OPT_RX can be configured as dedicated DIO pins DIO1 and DIO2. Thus, in addition to the 12 general-purpose DIO pins (DIO4...DIO11, DIO14...DIO17), there are three additional pins that can be used for digital input and output. Page: 40 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 The control resources selectable for the DIO pins are listed in Table 55. If more than one input is connected to the same resource, the resources are combined using a logical OR. DIO_R Value Resource Selected for DIO Pin 0 NONE 1 Reserved 2 T0 (counter0 clock) 3 T1 (counter1 clock) 4 High priority I/O interrupt (INT0 rising) 5 Low priority I/O interrupt (INT1 rising) 6 High priority I/O interrupt (INT0 falling) 7 Low priority I/O interrupt (INT1 falling) Table 55: Selectable Controls using the DIO_DIR Bits LCD Drivers The device contains 20 dedicated LCD segment drivers in addition to the 15 multi-use pins described above. Thus, the device is capable of driving between 80 to 140 pixels of LCD display with 25% duty cycle (or 60 to 105 pixels with 33% duty cycle). At eight pixels per digit, this corresponds to 10 to 17 digits. The LCD drivers are grouped into 4 commons and 35 segment drivers. The LCD interface is flexible and can drive either digit segments or enunciator symbols. Segment drivers SEG18 and SEG19 can be configured to blink at either 0.5Hz or 1Hz. The blink rate is controlled by LCD_Y. There can be up to four pixels/segments connected to each of these drivers. LCD_BLKMAP18[3:0] and LCD_BLKMAP19[3:0] identify which pixels, if any, are to blink. LCD interface memory is powered by the non-volatile supply. The bits of the LCD memory are preserved in LCD and SLEEP modes, even if their pin is not configured as SEG. In this case, they can be useful as generalpurpose non-volatile storage. Battery Monitor The battery voltage is measured by the ADC during alternative MUX frames if the BME (Battery Measure Enable) bit is set. While BME is set, an on-chip 45k load resistor is applied to the battery and a scaled fraction of the battery voltage is applied to the ADC input. After each alternative MUX frame, the result of the ADC conversion is available at CE DRAM address 0x07. BME is ignored and assumed zero when system power is not available. See the Battery Monitor section of the Electrical Specification section for details regarding the ADC LSB size and the conversion accuracy. EEPROM Interface The 71M6521BE provides hardware support for either type of EEPROM interface, a two-pin interface and a three-pin interface. The interfaces use the EECTRL and EEDATA registers for communication. Two-Pin EEPROM Interface The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is multiplexed onto DIO4 (SCK) and DIO5 (SDA) controlled by the DIO_EEX bit (see I/O RAM Table). The MPU communicates with the interface through two SFR registers: EEDATA and EECTRL. If the MPU wishes to write a byte of data to EEPROM, it places the data in EEDATA and then writes the `Transmit' command (CMD = 0011) to EECTRL. The write to EECTRL initiates the transmit operation. The transmit operation is finished when the BUSY bit falls. INT5 is also asserted when BUSY falls. The MPU can then check the RX_ACK bit to see if the EEPROM acknowledged the transmission. V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 41 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 A byte is read by writing the `Receive' command (CMD = 0001) to EECTRL and waiting for the BUSY bit to fall. Upon completion, the received data is in EEDATA. The serial transmit and receive clock is 78kHz during each transmission, and the clock is held in a high state until the next transmission. The bits in EECTRL are shown in Table 56. The EEPROM interface can also be operated by controlling the DIO4 and DIO5 pins directly. However, controlling DIO4 and DIO5 directly is discouraged, because it may tie up the MPU to the point where it may become too busy to process interrupts. Status Bit Name Read/ Write Reset State Polarity Description 7 ERROR R 0 Positive 1 when an illegal command is received. 6 BUSY R 0 Positive 1 when serial data bus is busy. 5 RX_ACK R 1 Negative 0 indicates that the EEPROM sent an ACK bit. 4 TX_ACK R 1 Negative 0 indicates when an ACK bit has been sent to the EEPROM 3-0 CMD[3:0] W 0000 Positive, see CMD Table CMD Operation 0000 No-op. Applying the no-op command will stop the I2C clock (SCK, DIO4). Failure to issue the no-op command will keep the SCK signal toggling. 0010 Receive a byte from EEPROM and send ACK. 0011 Transmit a byte to EEPROM. 0101 Issue a `STOP' sequence. 0110 Receive the last byte from EEPROM and do not send ACK. 1001 Issue a `START' sequence. Others No Operation, set the ERROR bit. Table 56: EECTRL Status Bits Three-Wire EEPROM Interface A 500kHz three-wire interface, using SDATA, SCK, and a DIO pin for CS is available. The interface is selected with DIO_EEX=3. The same 2-wire EECTRL register is used, except the bits are reconfigured, as shown in Table 57. When EECTRL is written, up to 8 bits from EEDATA are either written to the EEPROM or read from the EEPROM, depending on the values of the EECTRL bits.The timing diagrams in Figure 9 through Figure 13 describe the 3-wire EEPROM interface behavior. All commands begin when the EECTRL register is written. Transactions start by first raising the DIO pin that is connected to CS. Multiple 8-bit or less commands such as those shown in Figure 9 through Figure 13 are then sent via EECTRL and EEDATA. When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM will be driving SDATA, but will transition to HiZ (high impedance) when CS falls. The firmware should then immediately issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to a low-Z state. Page: 42 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Control Bit Name Read/Write 7 WFR W 6 BUSY R 5 HiZ W 4 RD W 3-0 CNT[3:0] W Description Wait for Ready. If this bit is set, the trailing edge of BUSY will be delayed until a rising edge is seen on the data line. This bit can be used during the last byte of a Write command to cause the INT5 interrupt to occur when the EEPROM has finished its internal write sequence. This bit is ignored if HiZ=0. Asserted while serial data bus is busy. When the BUSY bit falls, an INT5 interrupt occurs. Indicates that the SD signal is to be floated to high impedance immediately after the last SCK rising edge. Indicates that EEDATA is to be filled with data from EEPROM. Specifies the number of clocks to be issued. Allowed values are 0 through 8. If RD=1, CNT bits of data will be read MSB first, and right justified into the low order bits of EEDATA. If RD=0, CNT bits will be sent MSB first to EEPROM, shifted out of EEDATA's MSB. If CNT is zero, SDATA will simply obey the HiZ bit. Table 57: EECTRL bits for 3-wire interface EECTRL Byte Written INT5 CNT Cycles (6 shown) Write -- No HiZ SCLK (output) SDATA (output) D7 D6 SDATA output Z D5 D4 D3 D2 (LoZ) BUSY (bit) Figure 9: 3-Wire Interface. Write Command, HiZ=0. EECTRL Byte Written INT5 CNT Cycles (6 shown) Write -- With HiZ SCLK (output) SDATA (output) SDATA output Z D7 D6 D5 D4 D3 D2 (LoZ) (HiZ) BUSY (bit) Figure 10: 3-Wire Interface. Write Command, HiZ=1 V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 43 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 EECTRL Byte Written INT5 CNT Cycles (8 shown) READ SCLK (output) SDATA (input) D7 D6 SDATA output Z D5 D4 D3 D2 D1 D0 (HiZ) BUSY (bit) Figure 11: 3-Wire Interface. Read Command. EECTRL Byte Written EECTRL Byte Written INT5 not issued CNT Cycles (0 shown) Write -- No HiZ INT5 not issued CNT Cycles (0 shown) Write -- HiZ SCLK (output) SCLK (output) SDATA (output) SDATA (output) D7 SDATA output Z SDATA output Z (LoZ) BUSY (bit) (HiZ) BUSY (bit) Figure 12: 3-Wire Interface. Write Command when CNT=0 EECTRL Byte Written INT5 CNT Cycles (6 shown) Write -- With HiZ and WFR SCLK (output) SDATA (out/in) SDATA output Z D7 D6 D5 (From 6520) (LoZ) D4 D3 D2 BUSY (From EEPROM) READY (HiZ) BUSY (bit) Figure 13: 3-Wire Interface. Write Command when HiZ=1 and WFR=1. Page: 44 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Hardware re Watchdog Timer V1 V3P3 V3P3 - 10mV WDT disabled V3P3 400mV Normal operation, WDT enabled VBIAS Battery modes In addition to the basic watchdog timer included in the 80515 MPU, an independent, robust, fixed-duration, watchdog timer (WDT) is included in the device. It uses the crystal oscillator as its time base and must be refreshed by the MPU firmware at least every 1.5 seconds. When not refreshed on time the WDT overflows, and the part is reset as if the RESET pin were pulled high, except that the I/O RAM bits will be in the same state as after a wake-up from SLEEP or LCD modes (see the I/O RAM description for a list of I/O RAM bit states after RESET and wake-up). 4100 oscillator cycles (or 125ms) after the WDT overflow, the MPU will be launched from program address 0x0000. A status bit, WD_OVF, is set when WDT overflow occurs. This bit is powered by the nonvolatile supply and can be read by the MPU when WAKE rises to determine if the part is initializing after a WD overflow event or after a power-up. After it is read, MPU firmware must clear WD_OVF. The WD_OVF bit is cleared by the RESET pin There is no internal digital state that deactivates the WDT. For debug purposes, however, the WDT can be disabled by tying the V1 pin to V3P3 (see Figure 35). Of course, this also deactivates V1 power fault detection. Since there is no firmware way to disable the crystal oscillator or the WDT, it is guaranteed that whatever state the part might find itself in, upon watchdog overflow, the part will be reset to a known state. Asserting ICE_E will also deactivate the WDT. This is the only method that will work in BROWNOUT mode. 0V In normal operation, the WDT is reset by periodically writing a one to the WDT_RST bit. The watchdog timer is also reset when the internal signal WAKE=0 (see section on Wake Up Behavior). Figure 14: Functions defined by V1. Program Security When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE operations are blocked. This guarantees the security of the user's MPU and CE program code. Security is enabled by MPU code that is executed in a 32 cycle preboot interval before the primary boot sequence begins. Once security is enabled, the only way to disable it is to perform a global erase of the flash, followed by a chip reset. The first 32 cycles of the MPU boot code are called the preboot phase because during this phase the ICE is inhibited. A readonly status bit, PREBOOT, identifies these cycles to the MPU. Upon completion of preboot, the ICE can be enabled and is permitted to take control of the MPU. SECURE, the security enable bit, is reset whenever the chip is reset. Hardware associated with the bit permits only ones to be written to it. Thus, preboot code may set SECURE to enable the security feature but may not reset it. Once SECURE is set, the preboot code is protected and no external read of program code is possible Specifically, when SECURE is set: * The ICE is limited to bulk flash erase only. * Page zero of flash memory, the preferred location for the user's preboot code, may not be page-erased by either MPU or ICE. Page zero may only be erased with global flash erase. Writes to page zero, whether by MPU or ICE are inhibited. * The SECURE bit is to be used with caution! Inadvertently setting this bit will inhibit access to the part via the ICE interface, if no mechanism for actively resetting the part between reset and erase operations is provided (see ICE Interface description). V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 45 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Test Ports TMUXOUT Pin: One out of 16 digital or 8 analog signals can be selected to be output on the TMUXOUT pin. The function of the multiplexer is controlled with the I/O RAM register TMUX (0x20AA[4:0]), as shown in Table 58. TMUX[4:0] Mode Function 0 1 2 3-5 6 7 8-0x0F 0x10 - 0x13 0x14 0x15 0x16 - 0x17 0x18 0x19 0x1A 0x1B 0x1C 0X1E 0X1F Analog Analog Analog Analog Analog Analog --Digital Digital DGND Reserved DGND Reserved VBIAS Not used Reserved Not used RTM (Real time output from CE) WDTR_EN (Comparator 1 Output AND V1LT3) Not used RXD (from Optical interface, w/ optional inversion) MUX_SYNC CK_10M CK_MPU Reserved CE_BUSY XFER_BUSY Digital Digital Digital Digital -Digital Digital Table 58: TMUX[4:0] Selections Page: 46 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 FUNCTIONAL DESCRIPTION Theory of Operation The energy delivered by a power source into a load can be expressed as: t E = V (t ) I (t )dt 0 Assuming phase angles are constant, the following formulae apply: P = Real Energy [Wh] = V * A * cos * t Q = Reactive Energy [VARh] = V * A * sin * t S = Apparent Energy [VAh] = P2 + Q2 For a practical meter, not only voltage and current amplitudes, but also phase angles and harmonic content may change constantly. Thus, simple RMS measurements are inherently inaccurate. A modern solid-state electricity meter IC such as the TERIDIAN 71M6521BE functions by emulating the integral operation above, i.e. it processes current and voltage samples through an ADC at a constant frequency. As long as the ADC resolution is high enough and the sample frequency is beyond the harmonic range of interest, the current and voltage samples, multiplied with the time period of sampling will yield an accurate quantity for the momentary energy. Summing up the momentary energy quantities over time will result in accumulated energy. 500 400 300 200 100 0 0 5 10 15 20 -100 -200 Current [A] -300 Voltage [V] Energy per Interval [Ws] -400 Accumulated Energy [Ws] -500 Figure 15: Voltage. Current, Momentary and Accumulated Energy Figure 15 shows the shapes of V(t), I(t), the momentary power and the accumulated energy, resulting from 50 samples of the voltage and current signals over a period of 20ms. The application of 240VAC and 100A results in an accumulation of 480Ws (= 0.133Wh) over the 20ms period, as indicated by the Accumulated Energy curve. The described sampling method works reliably, even in the presence of dynamic phase shift and harmonic distortion. V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 47 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 System Timing Summary Figure 16 summarizes the timing relationships between the input MUX states, the CE_BUSY signal, and the two serial output streams. In this example, MUX_DIV=4 and FIR_LEN=1 (384). The duration of each MUX frame is 1 + MUX_DIV * 2 if FIR_LEN=288, and 1 + MUX_DIV * 3 if FIR_LEN=384. An ADC conversion will always consume an integer number of CK32 clocks. Followed by the conversions is a single CK32 cycle where the bandgap voltage is allowed to recover from the change in CROSS. Each CE program pass begins when ADC0 (channel IA) conversion begins. Depending on the length of the CE program, it may continue running until the end of the ADC3 (VB) conversion. CE opcodes are constructed to ensure that all CE code passes consume exactly the same number of cycles. The result of each ADC conversion is inserted into the CE DRAM when the conversion is complete. The CE is written to tolerate sudden changes in ADC data. The exact CK count when each ADC value is loaded into DRAM is shown in Figure 16. Figure 16 also shows that the serial RTM data stream begins transmitting at the beginning of state `S.' RTM, consisting of 140 CK cycles, will always finish before the next code pass starts. ADC MUX Frame ADC TIMING MUX_DIV Conversions, MUX_DIV=1 (4 conversions) is shown Settle CK32 150 MUX_SYNC MUX STATE S 0 1 2 3 S ADC EXECUTION ADC0 CE TIMING 0 ADC1 450 900 ADC2 ADC3 1350 1800 CE_EXECUTION CK COUNT = CE_CYCLES + floor((CE_CYCLES + 2) / 5) MAX CK COUNT CE_BUSY XFER_BUSY INITIATED BY A CE OPCODE AT END OF SUM INTERVAL RTM TIMING 140 RTM NOTES: 1. ALL DIMENSIONS ARE 5MHZ CK COUNTS. 2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz. 3. XFER_BUSY OCCURS ONCE EVERY (PRESAMPS * SUM_CYCLES) CODE PASSES. Figure 16: Timing Relationship between ADC MUX, Compute Engine, and Serial Transfers. Page: 48 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 CK32 MUX_SYNC CKTEST 30 31 0 FLAG 1 30 31 0 FLAG 1 30 31 SIG N FLAG 1 LSB 0 SIG N 31 LSB 30 SIG N RTM DATA0 (32 bits) RTM DATA1 (32 bits) RTM DATA2 (32 bits) RTM DATA3 (32 bits) 1 LSB FLAG LSB 0 SIG N TMUXOUT/RTM Figure 17: RTM Output Format Battery Modes Shortly after system power (V3P3SYS) is applied, the part will be in MISSION mode. MISSION mode means that the part is operating with system power and that the internal PLL is stable. This mode is the normal operation mode where the part is capable of measuring energy. When system power is not available (i.e. when V1<VBIAS), the 71M6521DE/FE can be in one of three battery modes, i.e. BROWNOUT, LCD, or SLEEP mode. As soon as V1 falls below VBIAS or when the part wakes up under battery power (with sufficient voltage margin), the part will automatically enter BROWNOUT mode (see Wake Up Behavior section). From BROWNOUT mode, the MPU may enter either LCD mode or SLEEP mode by setting either the LCD_ONLY or SLEEP I/O RAM bits (only one bit can be set at the same time in BROWNOUT mode, since setting one bit will already force the part into SLEEP or LCD mode, disabling the MPU). Figure 18 shows a state diagram of the various operation modes, with the possible transitions between modes. For information on the timing of mode transitions refer to Figure 22 through Figure 24. When V1 falls below VBIAS or the part wakes up under battery power, the part will automatically enter BROWNOUT mode (see Wake Up Behavior section). From BROWNOUT mode, the part may choose to enter either LCD mode or SLEEP mode, as controlled by the MPU via the I/O RAM bits LCD_ONLY and SLEEP. Meters that do not require functionality in the battery modes still need to contain code that brings the chip from BROWNOUT mode to SLEEP mode. Otherwise, the chip remains in BROWNOUT mode, once the system power is missing, and consumes more current than intended. Similarly, meters equipped with batteries need to contain code that transitions the chip to SLEEP mode as soon as the battery is attached in production. Otherwise, remaining in BROWNOUT mode would add unnecessary drain to the battery. The transition from MISSION mode to BROWNOUT mode is signaled by the IE_PLLFALL interrupt flag (in SFR 0xE8[7]). The transition in the other direction is signaled by the IE_PLLRISE interrupt flag (SFR 0xE8[6]), when the PLL becomes stable. Transitions from both LCD and SLEEP mode are initiated by wake-up timer timeout conditions or pushbutton events. When the PB pin is pulled high (pushbutton is pressed), the IE_PB interrupt flag (SFR 0xE8[4]) is set, and when the wake-up timer times out, the IE_WAKE interrupt flag (SFR 0xE8[5]) is set. In the absence of system power, if the voltage margin for the LDO regulator providing 2.5V to the internal circuitry becomes too low to be safe, the part automatically enters sleep mode (BAT_OK false). The battery voltage must stay above 3V to ensure that BAT_OK remains true. Under this condition, the 71M6521BE stays in SLEEP mode, even if the voltage margin for the LDO improves (BAT_OK true). Table 59 shows the circuit functions available in each operating mode. V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 49 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 BROWNOUT Mode In BROWNOUT mode, most non-metering digital functions, as shown in Table 59, are active, including ICE, UART, EEPROM, and LCD. In BROWNOUT mode, a low bias current regulator will provide 2.5 Volts to V2P5 and the nonvolatile V2P5 net. The regulator has an output called BAT_OK to indicate that it has sufficient overhead. When BAT_OK = 0, the part will enter SLEEP mode. The V3P3D output pin is active in BROWNOUT mode, and low-current external components, such as EEPROMs can be supplied with the current from this pin while the chip is in BROWNOUT mode. From BROWNOUT mode, the processor can voluntarily enter LCD or SLEEP modes. When system power is restored, the part will automatically transition from any of the battery modes to mission mode, once the PLL has settled. The MPU will run at crystal clock rate in BROWNOUT mode. The value of MPU_DIV will be remembered (not changed) as the part enters and exits BROWNOUT. While PLL_OK = 0, the I/O RAM bits ADC_E and CE_E are held in zero state disabling both ADC and CE. When PLL_OK falls, the CE program counter is cleared immediately and all FIR processing halts. Figure 19 shows the functional blocks active in BROWNOUT mode. MISSION RESET V3P3SYS falls IE_PLLRISE -> 1 V3P3SYS rises V1 > VBIAS V1 <= VBIAS IE_PLLFALL -> 1 V3P3SYS rises LCD_ONLY BROWNOUT V3P3SYS rises RESET & VBAT_OK IE_PB -> 1 IE_WAKE -> 1 PB SLEEP or VBAT_OK timer LCD timer PB VBAT_OK VBAT_OK RESET & VBAT_OK SLEEP Figure 18: Operation Modes State Diagram Page: 50 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 LCD Mode In LCD mode, the data contained in the LCD_SEG registers is displayed, i.e. up to four LCD segments connected to each of the pins SEG18 and SEG19 can be made to blink without the involvement of the MPU, which is disabled in LCD mode. The V3P3D output pin is inactive in LCD mode. This mode can be exited only by system power up, a timeout of the wake-up timer, or a push button. Figure 20 shows the functional blocks active in LCD mode. SLEEP Mode In SLEEP mode, the battery current is minimized and only the Oscillator is active. The V3P3D output pin is inactive in LCD mode. This mode can be exited only by system power-up, a timeout of the wake-up timer, or a push button event. Figure 21 shows the functional blocks active in SLEEP mode. System Power Circuit Function CE CE Data RAM FIR Analog circuits: PLL, ADC, VREF, BME, etc. MPU clock rate MPU_DIV ICE DIO Pins Watchdog Timer LCD EEPROM Interface (2-wire) EEPROM Interface (3-wire) UART Optical TX modulation Flash Read Flash Page Erase Flash Write RAM Read and Write Wakeup Timer Crystal oscillator DRAM data preservation V3P3D voltage output Battery Power (nonvolatile Supply) MISSION BROWNOUT LCD SLEEP Yes Yes Yes -Yes -- ---- ---- Yes -- -- -- 4.92MHz (from PLL) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 28.672kHz (7/8 of 32768Hz) Yes Yes Yes Yes Yes Yes (8kb/s) Yes (16kb/s) Yes -Yes Yes -Yes Yes Yes Yes -- -- ----Yes --------Yes Yes -- -------------Yes Yes -- Yes Yes -- -- Table 59: Available Circuit Functions ("--" means "not active) V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 51 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 VREF IA VA IB VB V3P3A GNDA V3P3SYS ADC CONVERTER MUX V3P3D VBIAS VBIAS V3P3D - V3P3A VBAT + FIR ADC_E VREF TEMP MUX MUX CTRL EQU MUX_ALT CHOP_E MUX_DIV VREF_CAL VREF_DIS CROSS VBAT VOLT REG MCK PLL 32KHz OSC (32KHz) DIV ADC CK32 32KHz XOUT CKTEST/ SEG19 FIR_LEN CK32 X4MHZ XIN VBAT VREF CKOUT_E 4.9MHz V2P5 CKFIR 4.9MHz 4.9MHz 2.5V to logic CKOUT_E CK_GEN V3P3D CK_2X LCD_GEN ECK_DIS MPU_DIV MUX_SYNC STRT CKCE CE TEST MODE MUX RTM 32 bit Compute Engine CE CONTROL LCD DISPLAY DRIVER DATA 00-7F PROG 000-7FF MEMORY SHARE 1000-11FF RTM_0..3 RTM_E CE_E COM0..3 SEG0..18 SEG32,33 SEG19,38 VARPULSE EEPROM INTERFACE SEG24/DIO4 .. SEG31/DIO11 SEG34/DIO14 .. SEG37/DIO17 DIO1,2 PB I/O RAM CE_BUSY LCD_NUM LCD_MODE LCD_CLK LCD_E LCD_BLKMAP LCD_SEG LCD_Y DIGITAL I/O DIO_EEX DIO_PV/PW DIO_DIR DIO_R LCD_NUM DIO WPULSE XFER BUSY PLS_INV PLS_INTERVAL PLS_MAXWIDTH CE_LCTN EQU PRE_SAMPS SUM_CYCLES VLC0 LCD_MODE LCD_E WPULSE VARPULSE VLC2 VLC1 CE RAM (0.5KB) <4.9MHz TEST GNDD LCD_ONLY SLEEP CKADC CKMPU <4.9MHz SDCK RX UART TX OPT_RX/ DIO1 OPT_TX/ DIO2/ WPULSE/ VARPULSE MPU (80515) OPTICAL MOD OPT_TXMOD OPT_FDC CONFIG (I/O RAM) SDOUT SDIN OPT_RXDIS OPT_RXINV OPT_TXE OPT_TXINV CONFIGURATION PARAMETERS 2000-20FF DATA 0000-FFFF 0000-07FF PROG 0000-1FFF MEMORY SHARE CE_LCTN MPU XRAM (2KB) 00001FFF FLASH (8KB) FLSH66ZT VBIAS MPU_RSTZ POWER FAULT V1 EMULATOR PORT WAKE FAULTZ E_RXTX E_TCLK E_RST (Open Drain) COMP_STAT RESET E_RXTX/SEG38 ICE_E TEST MUX TMUXOUT TMUX[4:0] February 2, 2007 E_TCLK/SEG33 E_RST/SEG32 Figure 19: Functional Blocks in BROWNOUT Mode (inactive blocks grayed out) Page: 52 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 VREF IA VA IB VB V3P3A GNDA V3P3SYS ADC CONVERTER MUX V3P3D VBIAS VBIAS V3P3D - V3P3A VBAT + FIR ADC_E VREF TEMP MUX MUX CTRL EQU MUX_ALT CHOP_E MUX_DIV VREF_CAL VREF_DIS CROSS VBAT VOLT REG MCK PLL 32KHz OSC (32KHz) DIV ADC CK32 32KHz XOUT CKTEST/ SEG19 FIR_LEN CK32 X4MHZ XIN VBAT VREF CKOUT_E 4.9MHz V2P5 CKFIR 4.9MHz 4.9MHz 2.5V to logic CKOUT_E CK_GEN V3P3D CK_2X LCD_GEN ECK_DIS MPU_DIV MUX_SYNC STRT CKCE CE TEST MODE MUX RTM 32 bit Compute Engine CE CONTROL LCD DISPLAY DRIVER DATA 00-7F PROG 000-1FF MEMORY SHARE 1000-11FF RTM_0..3 RTM_E CE_E SEG0..18 SEG32,33 SEG19,38 VARPULSE EEPROM INTERFACE SEG24/DIO4 .. SEG31/DIO11 SEG34/DIO14 .. SEG37/DIO17 DIO1,2 PB I/O RAM CE_BUSY COM0..3 LCD_NUM LCD_MODE LCD_CLK LCD_E LCD_BLKMAP LCD_SEG LCD_Y DIGITAL I/O DIO_EEX DIO_PV/PW DIO_DIR DIO_R LCD_NUM DIO WPULSE XFER BUSY PLS_INV PLS_INTERVAL PLS_MAXWIDTH CE_LCTN EQU PRE_SAMPS SUM_CYCLES VLC0 LCD_MODE LCD_E WPULSE VARPULSE VLC2 VLC1 CE RAM (0.5KB) <4.9MHz TEST GNDD LCD_ONLY SLEEP CKADC CKMPU <4.9MHz SDCK RX UART TX OPT_RX/ DIO1 OPT_TX/ DIO2/ WPULSE/ VARPULSE MPU (80515) OPTICAL MOD OPT_TXMOD OPT_FDC CONFIG (I/O RAM) SDOUT SDIN OPT_RXDIS OPT_RXINV OPT_TXE OPT_TXINV CONFIGURATION PARAMETERS 2000-20FF DATA 0000-FFFF 0000-07FF PROG 0000-1FFF MEMORY SHARE 00001FFF MPU XRAM (2KB) FLASH (8KB) FLSH66ZT VBIAS MPU_RSTZ POWER FAULT V1 EMULATOR PORT WAKE FAULTZ E_RXTX E_TCLK E_RST (Open Drain) COMP_STAT RESET E_RXTX/SEG38 ICE_E TEST MUX TMUXOUT TMUX[4:0] February 2, 2007 E_TCLK/SEG33 E_RST/SEG32 Figure 20: Functional Blocks in LCD Mode (inactive blocks grayed out) V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 53 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 VREF IA VA IB VB V3P3A GNDA V3P3SYS ADC CONVERTER MUX V3P3D VBIAS VBIAS V3P3D - V3P3A VBAT + FIR ADC_E VREF TEMP MUX MUX CTRL EQU MUX_ALT CHOP_E MUX_DIV VREF_CAL VREF_DIS CROSS VBAT VOLT REG MCK PLL 32KHz OSC (32KHz) DIV ADC CK32 32KHz XOUT CKTEST/ SEG19 FIR_LEN CK32 X4MHZ XIN VBAT VREF CKOUT_E 4.9MHz V2P5 CKFIR 4.9MHz 4.9MHz 2.5V to logic CKOUT_E CK_GEN V3P3D CK_2X LCD_GEN ECK_DIS MPU_DIV MUX_SYNC STRT CKCE CE TEST MODE MUX RTM 32 bit Compute Engine CE CONTROL LCD DISPLAY DRIVER DATA 00-7F PROG 000-1FF MEMORY SHARE 1000-11FF RTM_0..3 RTM_E CE_E COM0..3 SEG0..18 SEG32,33 SEG19,38 VARPULSE EEPROM INTERFACE SEG24/DIO4 .. SEG31/DIO11 SEG34/DIO14 .. SEG37/DIO17 DIO1,2 PB I/O RAM CE_BUSY LCD_NUM LCD_MODE LCD_CLK LCD_E LCD_BLKMAP LCD_SEG LCD_Y DIGITAL I/O DIO_EEX DIO_PV/PW DIO_DIR DIO_R LCD_NUM DIO WPULSE XFER BUSY PLS_INV PLS_INTERVAL PLS_MAXWIDTH CE_LCTN EQU PRE_SAMPS SUM_CYCLES VLC0 LCD_MODE LCD_E WPULSE VARPULSE VLC2 VLC1 CE RAM (0.5KB) <4.9MHz TEST GNDD LCD_ONLY SLEEP CKADC CKMPU <4.9MHz SDCK RX UART TX OPT_RX/ DIO1 OPT_TX/ DIO2/ WPULSE/ VARPULSE MPU (80515) OPTICAL MOD OPT_TXMOD OPT_FDC CONFIG (I/O RAM) SDOUT SDIN OPT_RXDIS OPT_RXINV OPT_TXE OPT_TXINV CONFIGURATION PARAMETERS 2000-20FF DATA 0000-FFFF 0000-07FF PROG 0000-1FFF MEMORY SHARE 00001FFF MPU XRAM (2KB) FLASH (8KB) FLSH66ZT VBIAS MPU_RSTZ POWER FAULT V1 EMULATOR PORT WAKE FAULTZ E_RXTX E_TCLK E_RST (Open Drain) COMP_STAT RESET E_RXTX/SEG38 ICE_E TEST MUX TMUXOUT TMUX[4:0] February 2, 2007 E_TCLK/SEG33 E_RST/SEG32 Figure 21: Functional Blocks in SLEEP Mode (inactive blocks grayed out) Page: 54 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 System Power (V3P3SYS) V1_OK Battery Current MPU Mode 300nA BROWNOUT PLL_OK MISSION 13..14 CK cycles WAKE MPU Clock Source Transition PLL (4.2MHz/MUX_DIV) Xtal 2048...4096 CK32 cycles time Figure 22: Transition from BROWNOUT to MISSION Mode when System Power Returns V3P3SYS and VBAT V1_OK Battery Current MPU Mode MPU Clock Source WAKE PLL_OK Internal RESETZ 300nA BROWNOUT MISSION Xtal PLL (4.2MHz) 14.5 CK32 cycles 4096 CK32 cycles 1024 CK32 cycles time Figure 23: Power-Up Timing with V3P3SYS and VBAT tied together V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 55 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 VBAT Battery Current BROWNOUT MPU Mode MPU Clock Source WAKE Xtal 14.5 CK32 cycles PLL_OK Internal RESETZ 1024 CK32 cycles VBAT_OK time Figure 24: Power-Up Timing with VBAT only Fault and Reset Behavior Reset Mode: When the RESET pin is pulled high all digital activity stops. The oscillator module continues to run. Additionally, all I/O RAM bits are set to their default states. As long as V1, the input voltage at the power fault block, is greater than VBIAS, the internal 2.5V regulator will continue to provide power to the digital section. Once initiated, the reset mode will persist until the reset timer times out, signified by WAKE rising. This will occur in 4100 cycles of the real time clock after RESET goes low, at which time the MPU will begin executing its preboot and boot sequences from address 00. See the security section for more description of preboot and boot. If system power is not present, the reset timer duration will be 2 cycles of the crystal clock, at which time the MPU will begin executing in BROWNOUT mode, starting at address 00. Power Fault Circuit: The 71M6521BE includes a comparator to monitor system power fault conditions. When the output of the comparator falls (V1<VBIAS), the I/P RAM bits PLL_OK is zeroed and the part switches to BROWNOUT mode if a battery is present. Once, system power returns, the MPU remains in reset and does not start Mission Mode until 4100 oscillator clocks later, when PLL_OK rises. If a battery is not present, indicated by BAT_OK=0, WAKE will fall and the part will enter SLEEP mode. There are several conditions the part could be in as system power returns. If the part is in BROWNOUT mode, it will automatically switch to mission mode when PLL_OK rises. It will receive an interrupt indicating this. No configuration bits will be reset or reconfigured during this transition. If the part is in LCD or SLEEP mode when system power returns, it will also switch to mission mode when PLL_OK rises. In this case, all configuration bits will be in the reset state due to WAKE having been zero. The MPU RAM must be re-initialized. The hardware watchdog timer will become active when the part enters MISSION mode. Page: 56 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 If there is no battery when system power returns, the part will switch to mission mode when PLL_OK rises. All configuration bits will be in reset state, and MPU RAM data will be unknown and must be initialized by the MPU. Wake Up Behavior As described above, the part will always wake up in mission mode when system power is restored. Additionally, the part will wake up in BROWNOUT mode when PB rises (push button pressed) or when a timeout of the wake-up timer occurs. Wake on PB If the part is in SLEEP or LCD mode, it can be awakened by a rising edge on the PB pin. This pin is normally pulled to GND and can be pulled high by a push button depression. Before the PB signal rises, the MPU is in reset due to WAKE being low. When PB rises, WAKE rises and within three crystal cycles, the MPU begins to execute. The MPU can determine whether the PB signal woke it up by checking the IE_PB flag. For debouncing, the PB pin is monitored by a state machine operating from a 32Hz clock. This circuit will reject between 31ms and 62ms of noise. Detection hardware will ignore all transitions after the initial rising edge. This will continue until the MPU clears the IE_PB bit. System Power (V3P3SYS) PB or wakeup timer 15 CK32 cycles WAKE MPU Mode LCD BROWNOUT PLL_OK time Figure 25: Wake Up Timing Wake on Timer If the part is in SLEEP or LCD mode, it can be awakened by the wake-up timer. Until this timer times out, the MPU is in reset due to WAKE being low. When the wake-up timer times out, the WAKE signal rises and within three crystal cycles, the MPU begins to execute. The MPU can determine whether the timer woke it by checking the AUTOWAKE interrupt flag (IE_WAKE). The wake-up timer begins timing when the part enters LCD or SLEEP mode. Its duration is controlled by WAKE_PRD[2:0] and WAKE_RES. WAKE_RES selects a timer LSB of either 1 minute (WAKE_RES=1) or 2.5 seconds (WAKE_RES=0). WAKE_PRD[2:0] selects a duration of from 1 to 7 LSBs. The timer is armed by WAKE_ARM=1. It must be armed at least three crystal clock cycles before SLEEP or LCD_ONLY is initiated. Setting WAKE_ARM presets the timer with the values in WAKE_RES and WAKE_PRD and readies the timer to start when the processor writes to SLEEP or LCD_ONLY. The timer is reset and disarmed whenever the processor is awake. Thus, if it is desired to wake the MPU periodically (every 5 seconds, for example) the timer must be rearmed every time the MPU is awakened. V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 57 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Data Flow The data flow between CE and MPU is shown in Figure 26. In a typical application, the 32-bit compute engine (CE) sequentially processes the samples from the voltage inputs on pins IA, VA, IB, and VB, performing calculations to measure active power (Wh). These measurements are then accessed by the MPU, processed further and output using the peripheral devices available to the MPU. Pulse IRQ Samples CE MPU Data PreProcessor PostProcessor Processed Metering Data I/O RAM (Configuration RAM) Figure 26: MPU/CE Data Flow CE/MPU Communication Figure 27 shows the functional relationship between CE and MPU. The CE is controlled by the MPU via shared registers in the I/O RAM and by registers in the CE DRAM. The CE outputs two interrupt signals to the MPU: CE_BUSY and XFER_BUSY, which are connected to the MPU interrupt service inputs as external interrupts. CE_BUSY indicates that the CE is actively processing data. This signal will occur once every multiplexer cycle. XFER_BUSY indicates that the CE is updating data to the output region of the CE DRAM. This will occur whenever the CE has finished generating a sum by completing an accumulation interval determined by SUM_CYCLES * PRE_SAMPS samples. Interrupts to the MPU occur on the falling edges of the XFER_BUSY and CE_BUSY signals. WPULSE (DIO6) DISPLAY (memory-mapped LCD segments) WSUM SERIAL (UART0/1) SAG CONTROL ADC SAMPLES MPU DATA EEPROM (I2C) CE_BUSY CE Mux Ctrl. XFER_BUSY DIO INTERRUPTS I/O RAM (CONFIGURATION RAM) Figure 27: MPU/CE Communication Page: 58 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Temperature Measurement Measurement of absolute temperature uses the on-chip temperature sensor while applying the following formula: T= ( N (T ) - N n ) + Tn Sn In the above formula T is the temperature in C, N(T) is the ADC count at temperature T, Nn is the ADC count at 25C, Sn is the sensitivity in LSB/C as stated in the Electrical Specifications, and Tn is +25C. Example: At 25C a temperature sensor value of 518,203,584 (Nn) is read by the ADC. At an unknown temperature T the value 449.648.000 is read at (N(T)). The absolute temperature is then determined by dividing both Nn and N(T) by 512 to account for the 9-bit shift of the ADC value and then inserting the results into the above formula, using -2220 for LSB/C: T= 449.648.000 - 518,203,584 + 25C = 85.3C 512 (-2220) It is recommended to base temperature measurements on TEMP_RAW_X which is the sum of two consecutive temperature readings thus being higher by a factor of two than the raw sensor readings. Temperature Compensation Temperature Coefficients: The internal voltage reference is calibrated during device manufacture. The temperature coefficients TC1 and TC2 are given as constants that represent typical component behavior (in V/C and V/C2, respectively). Since TC1 and TC2 are given in V/C and V/C2, respectively, the value of the VREF voltage (1.195V) has to be taken into account when transitioning to PPM/C and PPM/C2. This means that PPMC = 26.84*TC1/1.195, and PPMC2 = 1374*TC2/1.195). Temperature Compensation: The CE provides the bandgap temperature to the MPU, which then may digitally compensate the power outputs for the temperature dependence of VREF, using the CE register GAIN_ADJ. Since the band gap amplifier is chopper-stabilized via the CHOP_EN bits, the most significant long-term drift mechanism in the voltage reference is removed. The MPU, not the CE, is entirely in charge of providing temperature compensation. The MPU applies the following formula to determine GAIN_ADJ (address 0x12). In this formula TEMP_X is the deviation from nominal or calibration temperature expressed in multiples of 0.1C: GAIN _ ADJ = 16385 + TEMP _ X PPMC TEMP _ X 2 PPMC 2 + 214 2 23 In a production electricity meter, the 71M6521BE is not the only component contributing to temperature dependency. A whole range of components (e.g. current transformers, resistor dividers, power sources, filter capacitors) will contribute temperature effects. Since the output of the on-chip temperature sensor is accessible to the MPU, temperature-compensation mechanisms with great flexibility are possible. MPU access to GAIN_ADJ permits a system-wide temperature correction over the entire meter rather than local to the chip. V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 59 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 APPLICATION INFORMATION Connection of Sensors (CT, Resistive Shunt) Figure 28 and Figure 29 show how resistive dividers, current transformers, and restive shunts are connected to the voltage and current inputs of the 71M6521BE. Rin Iout Iin VA Vin Vout = R * Iout = R * Iin/N core VA = Vin * Rout/(Rout + Rin) IA R Rout Iin Vout V3P3 1/N Filter Iout Figure 28: Resistive Voltage Divider (Left), Current Transformer (Right) Vout = R * Iin Iin IA R Vout V3P3 Iin Figure 29: Resistive Shunt Connecting 5V Devices All digital input pins of the 71M6521BE are compatible with external 5V devices. I/O pins configured as inputs do not require current-limiting resistors when they are connected to external 5V devices. See the cautionary note on the restrictions for combined SEG/DIO pins configured as digital inputs in the Digital I/O Section. Page: 60 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Connecting LCDs The 71M6521BE has a LCD controller on-chip capable of controlling static or multiplexed LCDs. Figure 30 shows the basic connection for a LCD. 6521 LCD segments commons Figure 30: Connecting LCDs Nineteen pins are dedicated LCD segment pins (SEG0 to SEG18). If more pins are needed to drive segments, the dualfunction pins CKTEST/SEG19, E_RXTX/SEG38, E_TCLK/SEG33, and E_RST/SEG32 can be used. Even more segment pins are available in the form of combined DIO and segment pins (SEG24/DIO4 to SEG31/DIO11, SEG34/DIO14 to SEG37/DIO17). The split between DIO and LCD use of the combined pins is controlled with the DIO register LCD_NUM. LCD_NUM can be assigned any number between 0 and 18. The first dual-purpose pin to be allocated as LCD is SEG37/DIO17. Thus if LCD_NUM=5, SEG37 will be configured as LCD. The remaining SEG36 to SEG24 will be configured as DIO16 to DIO4. DIO1 and DIO2 are always available, if not used for the optical port. Pins CKTEST/SEG19, E_RXTX/SEG38, E_TCLK/SEG33, and E_RST/SEG32 are not affected by LCD_NUM. V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 61 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 LCD_NUM SEG in Addition to SEG0-SEG19 Total Number of LCD Segment Pins Including SEG0-SEG19 DIO Pins in Addition to DIO1-DIO2 Total Number of DIO Pins Including DIO1, DIO2 0 - 19 4-11, 14-17 14 1 - 19 4-11, 14-17 14 2 - 19 4-11, 14-17 14 3 - 19 4-11, 14-17 14 4 - 19 4-11, 14-17 14 5 37 20 4-11, 14-16 13 6 36-37 21 4-11, 14-15 12 7 35-37 22 4-11, 14 11 8 34-37 23 4-11 10 9 34-37 23 4-11 10 10 34-37 23 4-11 10 11 31, 34-37 24 4-10 9 12 30-31, 34-37 25 4-9 8 13 29-31, 34-37 26 4-8 7 14 28-31, 34-37 27 4-7 6 15 27-31, 34-37 28 4-6 5 16 26-31, 34-37 29 4-5 4 17 25-31, 34-37 30 4 3 18 24-31, 34-37 31 None 2 LCD segment numbers are given without CKTEST/SEG19, E_RXTX/SEG38, E_TCLK/SEG33, and E_RST/SEG32. Table 60: LCD and DIO Pin Assignment by LCD_NUM Page: 62 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Connecting I2C EEPROMs I2C EEPROMs or other I2C compatible devices should be connected to the DIO pins DIO4 and DIO5, as shown in Figure 31. Pull-up resistors of roughly 10k to V3P3D (to ensure operation in BROWNOUT mode) should be used for both SCL and SDA signals. The DIO_EEX register in I/O RAM must be set to 01 in order to convert the DIO pins DIO4 and DIO5 to I2C pins SCL and SDA. V3P3D 6521B 10k EEPROM DIO4 SCL DIO5 SDA 2 Figure 31: I C EEPROM Connection Connecting Three-Wire EEPROMs Wire EEPROMs and other compatible devices should be connected to the DIO pins DIO4 and DIO5, as shown in Figure 32. DIO5 connects to both the DI and DO pins of the three-wire device. The CS pin must be connected to a vacant DIO pin of the 71M6521BE. A pull-up resistor of roughly 10k to V3P3D (to ensure operation in BROWNOUT mode) should be used for the DI/DO signals, and the CS pin should be pulled down with a resistor to prevent that the three-wire device is selected on powerup, before the 71M6521BE can establish a stable signal for CS. The DIO_EEX register in I/O RAM must be set to 10 in order to convert the DIO pins DIO4 and DIO5 to uWire pins. The pull-up resistor for DIO5 may not be necessary. V3P3D 6521B 10k 10k EEPROM SCLK DI DO CS DIO4 DIO5 DIOn 10k Figure 32: Three-Wire EEPROM Connection V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 63 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 UART0 (TX/RX) The RX pin should be pulled down by a 10k resistor and additionally protected by a 100pF ceramic capacitor, as shown in Figure 33. 71M6521BE RX 100pF 10k TX RX TX Figure 33: Connections for the RX Pin Optical Interface The pins OPT_TX and OPT_RX can be used for a regular serial interface, e.g. by connecting a RS-232 transceiver, or they can be used to directly operate optical components, e.g. an infrared diode and phototransistor implementing a FLAG interface. Figure 34 shows the basic connections. The OPT_TX pin becomes active when the I/O RAM register OPT_TXDIS is set to 0. The polarity of the OPT_TX and OPT_RX pins can be inverted with configuration bits OPT_TXINV and OPT_RXINV, respectively. The OPT_TX output may be modulated at 38kHz when system power is present. Modulation is not available in BROWNOUT mode. The OPT_TXMOD bit enables modulation. The duty cycle is controlled by OPT_FDC[1:0], which can select 50%, 25%, 12.5%, and 6.25% duty cycle. A 6.25% duty cycle means OPT_TX is low for 6.25% of the period. The receive pin (OPT_RX) may need an analog filter when receiving modulated optical signals. With modulation, an optical emitter can be operated at higher current than nominal, enabling it to increase the distance along the optical path. If operation in BROWNOUT mode is desired, the external components should be connected to V3P3D. Page: 64 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 V3P3SYS R1 71M6521BE OPT_RX 100pF 10k Phototransistor V3P3SYS R2 OPT_TX LED Figure 34: Connection for Optical Components Connecting V1 and Reset Pins A voltage divider should be used to establish that V1 is in a safe range when the meter is in mission mode (V1 must be lower than 2.9V in all cases in order to keep the hardware watchdog timer enabled). For proper debugging or loading code into the 71M6521BE mounted on a PCB, it is necessary to have a provision like the header shown above R1 in Figure 35. A shorting jumper on this header pulls V1 up to V3P3 disabling the hardware watchdog timer. The parallel impedance of R1 and R2 should be approximately 20 to 30k in order to provide hysteresis for the power fault monitor. V3P3 R3 R1 5k R2 C1 V1 100pF GND Figure 35: Voltage Divider for V1 Even though a functional meter will not necessarily need a reset switch, it is useful to have a reset pushbutton for prototyping, as shown in Figure 36, left side. The RESET signal may be sourced from V3P3SYS (functional in MISSION mode only), V3P3D (MISSION and BROWNOUT modes), VBAT (all modes, if battery is present), or from a combination of these sources, depending on the application. When the 71M6521BE is used in an EMI environment, the RESET pin should be protected by the external components shown in Figure 36, right side. R1 should be in the range of 100 and mounted as closely as possible to the IC. Since the 71M6521BE generates its own power-on reset, a reset button or circuitry, as shown in Figure 36, left side, is only required for test units and prototypes. V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 65 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 VBAT/ V3P3D 71M6521 71M6521 V3P3D R2 1k Reset Switch RESET RESET 10k R1 1nF 100 R1 DGND DGND Figure 36: External Components for the RESET Pin: Push-Button (Left), EMI Circuit (Right) Connecting the Emulator Port Pins Capacitors to ground must be used for protection from EMI. Production boards should have the ICE_E pin connected to ground. If the ICE pins are used to drive LCD segments, the pull-up resistors should be omitted, as shown in Figure 37, and 22pF capacitors to GNDD should be used for protection from EMI. It is important to bring out the ICE_E pin to the programming interface in order to create a way for reprogramming parts that have the flash SECURE bit (SFR 0xB2[6]) set. Providing access to ICE_E ensures that the part can be reset between erase and program cycles, which will enable programming devices to reprogram the part. The reset required is implemented with a watchdog timer reset (i.e. the hardware WDT must be enabled). LCD Segments (optional) V3P3D 71M6521B ICE_E 62 E_RST 62 E_RXTX E_TCLK 62 22pF 22pF Figure 37: External Components for the Emulator Interface Page: 66 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Crystal Oscillator The oscillator of the 71M6521BE drives a standard 32.768kHz watch crystal. The oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to VBAT. Board layouts with minimum capacitance from XIN to XOUT will require less battery current. Good layouts will have XIN and XOUT shielded from each other. Since the oscillator is self-biasing, an external resistor must not be connected across the crystal. With a typical 32kHz crystal, the 71M6521BE needs 600 to 650 milliseconds to stabilize the oscillator clock after power-up. This time is added to the 125ms (4096 CK32 cycles) for the PLL_OK signal to become true which is required for the part to enter MISSION mode. Flash Programming Operational or test code can be programmed into the flash memory using either an in-circuit emulator or the Flash Programmer Module (TFP-1) available from TERIDIAN. The flash programming procedure uses the E_RST, E_RXTX, and E_TCLK pins. MPU Firmware Library All application-specific MPU functions mentioned above under "Application Information" are available from TERIDIAN as a standard ANSI C library and as ANSI "C" source code. The code is available as part of the Demonstration Kit for the 71M6521BE IC. The Demonstration Kits come with the 71M6521BE IC preprogrammed with demo firmware mounted on a functional sample meter PCB (Demo Board). The Demo Boards allow for quick and efficient evaluation of the IC without having to write firmware or having to supply an in-circuit emulator (ICE). Meter Calibration Once the TERIDIAN 71M6521BE energy meter device has been installed in a meter system, it has to be calibrated for tolerances of the current sensors, voltage dividers and signal conditioning components. The device can be calibrated using the gain and phase adjustment factors accessible to the CE. The gain adjustment is used to compensate for tolerances of components used for signal conditioning, especially the resistive components. Phase adjustment is provided to compensate for phase shifts introduced by the current sensors. Due to the flexibility of the MPU firmware, any calibration method, such as calibration based on energy, or current and voltage can be implemented. It is also possible to implement segment-wise calibration (depending on current range). The 71M6521BE supports common industry standard calibration techniques, such as single-point (energy-only), multi-point (energy, Vrms, Irms), and auto-calibration. V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 67 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 FIRMWARE INTERFACE I/O RAM MAP - In Numerical Order `Not Used' bits are grayed out, contain no memory and are read by the MPU as zero. RESERVED bits may be in use and should not be changed. This table lists only the SFR registers that are not generic 8051 SFR registers. Name Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Configuration: EQU[2:0] CE_E CE0 2000 Reserved PRE_SAMPS[1:0] SUM_CYCLES[5:0] CE1 2001 MUX_DIV[1:0] CHOP_E[1:0] RTM_E WD_OVF Reserved* EX_XFR CE2 2002 PLL_OK COMP0 2003 Not Used Not Used Reserved Reserved Reserved COMP_STAT[0] CKOUT_E[1:0] VREF_DIS MPU_DIV[2:0] CONFIG0 2004 VREF_CAL PLS_INV ECK_DIS FIR_LEN ADC_E MUX_ALT FLSH66Z CONFIG1 2005 Reserved Reserved Reserved VERSION[7:0] VERSION 2006 OPT_TXE[1:0] EX_PLL EX_FWCOL OPT_FDC[1:0] CONFIG2 2007 Reserved CE_LCTN[4:0] CE3 20A8 Not Used Not Used Not Used SLEEP LCD_ONLY Not Used WAKE_RES WAKE_PRD[2:0] WAKE 20A9 WAKE_ARM TMUX[4:0] TMUX 20AA Not Used Not Used Not Used Digital I/O: DIO_EEX[1:0] OPT_RXDIS OPT_RXINV DIO_PW DIO_PV OPT_TXMOD OPT_TXINV DIO0 2008 DIO_R1[2:0] DI_RPB[2:0] DIO1 2009 Not Used Not Used DIO_R2[2:0] DIO2 200A Not Used Reserved Not Used DIO_R5[2:0] DIO_R4[2:0] DIO3 200B Not Used Not Used DIO_R7[2:0] DIO_R6[2:0] DIO4 200C Not Used Not Used DIO_R9[2:0] DIO_R8[2:0] DIO5 200D Not Used Not Used DIO_R11[2:0] DIO_R10[2:0] DIO6 200E Not Used Not Used WE 201F Reserved LCD Display Interface: BME LCD_NUM[4:0] LCDX 2020 Not Used Reserved LCD_Y LCD_E LCD_MODE[2:0] LCD_CLK[1:0] LCDY 2021 Not Used LCDZ 2022 Not Used Not Used Not Used Reserved LCD_SEG0[3:0] LCD0 2030 Not Used ... ... ... Not Used LCD_SEG19[3:0] LCD19 2043 Not Used LCD_SEG24[3:0] LCD24 2048 Not Used ... ... ... Not Used LCD_SEG38[3:0] LCD38 2056 Not Used LCD_BLKMAP19[3:0] LCD_BLKMAP18[3:0] LCD_BLNK 205A * Must be set to 0 (CE2 bit 1) Page: 68 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 RTM Probes: RTM0 2060 RTM1 2061 RTM2 2062 RTM3 2063 Pulse Generator: PLS_W 2080 PLS_I 2081 RTM0[7:0] RTM1[7:0] RTM2[7:0] RTM3[7:0] PLS_MAXWIDTH[7:0] PLS_INTERVAL[7:0] SFR MAP (SFRs Specific to TERIDIAN 80515) - In Numerical Order `Not Used' bits are blacked out and contain no memory and are read by the MPU as zero. RESERVED bits are in use and should not be changed. This table lists only the SFR registers that are not generic 8051 SFR registers Name SFR Bit 7 Bit 6 Bit 5 Bit 4 Digital I/O: DIO_0[7:4] (Port 0) DIO7 80 DIO_DIR0[7:4] DIO8 A2 DIO_1[7:6] DIO9 90 Reserved DIO_DIR1[7:6] DIO10 91 Reserved DIO11 A0 Not Used Not Used Reserved DIO12 A1 Not Used Not Used Reserved Interrupts and WD Timer: INT6 INT5 INT4 INTBITS F8 IFLAGS E8 IE_PLLFALL IE_PLLRISE WD_RST Flash: ERASE 94 FLSHCTL B2 PREBOOT PGADR B7 Serial EEPROM: EEDATA 9E EECTRL 9F V1.0 SECURE IE_WAKE IE_PB Bit 3 Reserved Reserved INT3 Bit 2 Bit 1 DIO_0[2:1] PB DIO_DIR0[2:1] Reserved DIO_1[3:0] (Port 1) DIO_DIR1[3:0] DIO_2[1:0] (Port 2) Reserved DIO_DIR2[1:0] Reserved INT2 INT1 IE_FWCOL1 IE_FWCOL0 Reserved FLSH_ERASE[7:0] Not Used Not Used Not Used FLSH_PGADR[6:0] Bit 0 Not Used INT0 IE_XFER FLSH_MEEN FLSH_PWE Not Used EEDATA[7:0] EECTRL[7:0] (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 69 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 I/O RAM DESCRIPTION - Alphabetical Order Bits with a W (write) direction are written by the MPU into configuration RAM. Typically, they are initially stored in flash memory and copied to the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The remaining bits are mapped to 2xxx. Bits with R (read) direction can be read by the MPU. Columns labeled Rst and Wk describe the bit values upon reset and wake, respectively. No entry in one of these columns means the bit is either read-only or is powered by the nonvolatile supply and is not initialized. Write only bits will return zero when they are read. Name Location Rst Wk Dir Description ADC_E 2005[3] 0 0 R/W Enables ADC and VREF. When disabled, removes bias current BME 2020[6] 0 - R/W Battery Measure Enable. When set, a load current is immediately applied to the battery and it is connected to the ADC to be measured on Alternative Mux Cycles. See MUX_ALT bit. CE_E 2000[4] 0 0 R/W CE enable. CE_LCTN[4:0] 20A8[4:0] 1F 1F R/W CHOP_E[1:0] 2002[5:4] 0 0 R/W CE program location. The starting address for the CE program is 1024*CE_LCTN. CE_LCTN must be defined before the CE is started. Chop enable for the reference bandgap circuit. The value of CHOP will change on the rising edge of MUXSYNC according to the value in CHOP_E: 00-toggle1 01-positive 10-reversed 11-toggle 1 except at the mux sync edge at the end of SUMCYCLE. CKOUT_E[1:0] 2004[5,4] 00 00 R/W CKTEST Enable. The default is 00 00-SEG19, 01-CK_FIR (5MHz Mission, 32kHz Brownout) 10-Not allowed (reserved for production test) 11-Same as 10. COMP_STAT[0] 2003[0] -- -- R The status of the power fail comparator for V1. DI_RPB[2:0] DIO_R1[2:0] DIO_R2[2:0] DIO_R4[2:0] DIO_R5[2:0] DIO_R6[2:0] DIO_R7[2:0] DIO_R8[2:0] DIO_R9[2:0] DIO_R10[2:0] DIO_R11[2:0] 2009[2:0] 2009[6:4] 200A[2:0] 200B[2:0] 200B[6:4] 200C[2:0] 200C[6:4] 200D[2:0] 200D[6:4] 200E[2:0] 200E[6:4] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W DIO_DIR0[7:4,2:1] SFRA2 [7:4,2:0] 0 0 R/W Page: 70 of 97 Connects dedicated I/O pins DIO2 and DIO4 through DIO11 as well as input pins PB and OPT_RX/DIO1 to internal resources. If more than one input is connected to the same resource, the `MULTIPLE' column below specifies how they are combined. DIO_Rx 000 001 010 011 100 101 110 111 Resource NONE Reserved T0 (Timer0 clock or gate) T1 (Timer1 clock or gate) High priority IO interrupt (int0 rising) Low priority IO interrupt (int1 rising) High priority IO interrupt (int0 falling) Low priority IO interrupt (int1 falling) MULTIPLE -OR OR OR OR OR OR OR Programs the direction of pins DIO7-DIO4 and DIO2-DIO1. 1 indicates output. Ignored if the pin is not configured as I/O. See DIO_PV and DIO_PW for special option for DIO6 and DIO7 outputs. See DIO_EEX for special option for DIO4 and DIO5. (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 DIO_DIR1[7:6, 3:0] SFR91 [7:6,3:0] 0 0 R/W Programs the direction of pins DIO15-DIO14, DIO11-DIO8. 1 indicates output. Ignored if the pin is not configured as I/O. DIO_DIR2 [5:3,2:1] DIO_0[7:4,2:0] SFRA1 [5:3,2:1] SFR80 [7:4,2:0] 0 0 R/W 0 0 R/W DIO_1[7:6,3:0] SFR90 [7:6,3:0] 0 0 R/W DIO_2[5:3,1:0] SFRA0 [5:3,1:0] 0 0 R/W DIO_EEX[1:0] 2008[7:6] 0 0 R/W DIO_PW 2008[3] 0 0 R/W EEDATA[7:0] EECTRL[7:0] ECK_DIS SFR9E SFR9F 2005[5] 0 0 0 0 0 0 R/W R/W R/W EQU[2:0] EX_XFR Reserved EX_FWCOL EX_PLL 2000[7:5] 2002[0] 2001[1] 2007[4] 2007[5] 0 0 0 0 0 0 0 0 0 0 R/W R/W FIR_LEN 2005[4] 0 0 R/W Programs the direction of pins DIO17-DIO16. 1 indicates output. Ignored if the pin is not configured as I/O. The value on the pins DIO7-DIO4 and DIO2-DIO1. Pins configured as LCD will read zero. When written, changes data on pins configured as outputs. Pins configured as LCD or input will ignore write operations. The pushbutton input PB is read on DIO_0[0]. The value on the pins DIO15-DIO14 and DIO11-DIO8. Pins configured as LCD will read zero. When written, changes data on pins configured as outputs. Pins configured as LCD or input will ignore write operations. The value on the pins DIO17-DIO16. Pins configured as LCD will read zero. When written, changes data on pins configured as outputs. Pins configured as LCD or input will ignore write operations. When set, converts DIO4 and DIO5 to interface with external EEPROM. DIO4 becomes SDCK and DIO5 becomes bi-directional SDATA. LCD_NUM must be less than or equal to 18. DIO_EEX[1:0] Function 00 Disable EEPROM interface 01 2-Wire EEPROM interface 10 3-Wire EEPROM interface 11 --not used-Causes WPULSE to be output on DIO6, if DIO6 is configured as output. LCD_NUM must be less than 16. Serial EEPROM interface data Serial EEPROM interface control Emulator clock disable. When one, the emulator clock is disabled. This bit is to be used with caution! Inadvertently setting this bit will inhibit access to the part with the ICE interface and thus preclude flash erase and programming operations. If ECK_DIS is set to zero, it should be done at least 1000ms after power-up to give emulators and programming devices enough time to complete an erase operation. Specifies the power equation to be used by the CE. Interrupt enable bits. These bits enable the XFER_BUSY, the Firmware Collision, and PLL interrupts. Note that if one of these interrupts is to be enabled, its corresponding 8051 EX enable must also be set. See the Interrupts section for details. Note that bit 2001[1] must always be 0. The length of the ADC decimation FIR filter. 1-384 cycles, 0-288 cycles When FIR_LEN=1, the ADC has 2.370370x higher gain. V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 71 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 FLSH_ERASE[7:0] SFR94[7:0] 0 0 W FLSH_MEEN SFRB2[1] 0 0 W FLSH_PGADR[6:0] SFRB7[7:1] 0 0 W FLSH_PWE SFRB2[0] 0 0 R/W FOVRIDE 20FD[4] 0 0 R/W IE_FWCOL0 IE_FWCOL1 IE_PB SFRE8[2] SFRE8[3] SFRE8[4] 0 0 0 0 0 -- R/W R/W R/W IE_PLLRISE SFRE8[6] 0 0 R/W IE_PLLFALL SFRE8[7] 0 0 R/W IE_XFER SFRE8[0] 0 0 R/W IE_WAKE SFRE8[5] 0 -- R/W Page: 72 of 97 Flash Erase Initiate FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or the Flash Page Erase cycle. Specific patterns are expected for FLSH_ERASE in order to initiate the appropriate Erase cycle. (default = 0x00). 0x55 - Initiate Flash Page Erase cycle. Must be proceeded by a write to FLSH_PGADR @ SFR 0xB7. 0xAA - Initiate Flash Mass Erase cycle. Must be proceeded by a write to FLSH_MEEN @ SFR 0xB2 and the debug (CC) port must be enabled. Any other pattern written to FLSH_ERASE will have no effect. Mass Erase Enable 0 - Mass Erase disabled (default). 1 - Mass Erase enabled. Must be re-written for each new Mass Erase cycle. Flash Page Erase Address FLSH_PGADR[6:0] - Flash Page Address (page 0 thru 127) that will be erased during the Page Erase cycle. (default = 0x00). Must be re-written for each new Page Erase cycle. Program Write Enable 0 - MOVX commands refer to XRAM Space, normal operation (default). 1 - MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR. This bit is automatically reset after each byte written to flash. Writes to this bit are inhibited when interrupts are enabled. Permits the values written by MPU to temporarily override the values in the fuse register (reserved for production test). Interrupt flags for Firmware Collision Interrupt. See Flash Memory Section for details. PB flag. Indicates that a rising edge occurred on PB. Firmware must write a zero to this bit to clear it. The bit is also cleared when MPU requests SLEEP or LCD mode. On bootup, the MPU can read this bit to determine if the part was woken with the PB DIO0[0]. Indicates that the MPU was woken or interrupted (int 4) by System power becoming available, or more precisely, by PLL_OK rising. Firmware must write a zero to this bit to clear it Indicates that the MPU has entered BROWNOUT mode because System power has become unavailable (int 4), or more precisely, because PLL_OK fell. Note: this bit will not be set if the part wakes into BROWNOUT mode because of PB or the WAKE timer. Firmware must write a zero to this bit to clear it. Interrupt flag. This flag monitors the XFER_BUSY interrupt. The flags is set by hardware and must be cleared by the interrupt handler. Note that IE6, the interrupt 6 flag bit in the 8051 must also be cleared when this interrupt occurs. Indicates that the MPU was woken by the autowake timer. This bit is typically read by the MPU on bootup. Firmware must write a zero to this bit to clear it (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 INTBITS SFRF8[6:0] -- -- R/W LCD_BLKMAP19[3:0] LCD_BLKMAP18[3:0] 205A[7:4] 205A[3:0] 0 -- R/W LCD_CLK[1:0] 2021[1:0] 0 -- R/W Interrupt inputs. The MPU may read these bits to see the input to external interrupts INT0, INT1, up to INT6. These bits do not have any memory and are primarily intended for debug use. Identifies which segments connected to SEG18 and SEG19 should blink. 1 means `blink.' Most significant bit corresponds to COM3. Least significant, to COM0. Sets the LCD clock frequency (for COM/SEG pins, not frame rate). Note: fw = 32768Hz 00: fw/29, 01: fw/28, 10: fw/27, 11: fw/26 LCD_E 2021[5] 0 -- R/W LCD_MODE[2:0] 2021[4:2] 0 -- R/W LCD_NUM[4:0] 2020[4:0] 0 -- R/W LCD_ONLY 20A9[5] 0 0 W LCD_SEG0[3:0] ... LCD_SEG19[3:0] LCD_SEG24[3:0] ... LCD_SEG38[3:0] 2030[3:0] ... 2043[3:0] 2048[3:0] ... 2056[3:0] 0 ... 0 0 ... 0 -... --... -- R/W LCD_Y 2021[6] 0 0 R/W MPU_DIV[2:0] 2004[2:0] 0 0 R/W MUX_ALT 2005[2] 0 0 R/W MUX_DIV[1:0] 2002[7:6] 0 0 R/W R/W Enables the LCD display. When disabled, VLC2, VLC1, and VLC0 are ground as are the COM and SEG outputs. The LCD bias mode. 000: 4 states, 1/3 bias 001: 3 states, 1/3 bias 010: 2 states, 1/2 bias 011: 3 states, 1/2 bias 100: static display Number of dual-purpose LCD/DIO pins to be configured as LCD. This will be a number between 0 and 18. The first dual-purpose pin to be allocated as LCD is SEG37/DIO17 if LCD_NUM=5. If LCD_NUM=6, SEG36 and SEG 37 will be configured as LCD. The remaining SEG35 to SEG24 will be configured as DIO16 to DIO4. DIO1 and DIO2 are always available, if not used for the optical port. See tables in Application Section. Takes the device to LCD mode. Ignored if system power is present. The part will awaken when autowake timer times out, when push button is pushed, or when system power returns. LCD Segment Data. Each word contains information for from 1 to 4 time divisions of each segment. In each word, bit 0 corresponds to COM0, on up to bit 3 for COM3. These bits are preserved in LCD and SLEEP modes, even if their pin is not configured as SEG. In this case, they can be useful as general-purpose non-volatile storage. LCD Blink Frequency (ignored if blink is disabled or if segment is off). 0: 1Hz (500ms ON, 500ms OFF) 1: 0.5Hz (1s ON, 1s OFF) The MPU clock divider (from 4.9152MHz). These bits may be programmed by the MPU without risk of losing control. 000-4.9152MHz, 001-4.9152MHz /21, ..., 111-4.9152MHz /27 MPU_DIV remains unchanged when the part enters BROWNOUT mode. The MPU asserts this bit when it wishes the MUX to perform ADC conversions on an alternate set of inputs. The number of states in the input multiplexer. 00- illegal 01- 4 states V1.0 10-3 states (c) 2005-2008 TERIDIAN Semiconductor Corporation 11-2 states Page: 73 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 2007[1:0] 0 0 R/W OPT_RXDIS 2008[5] 0 0 R/W OPT_RXINV 2008[4] 0 0 R/W OPT_TXE[1,0] 2007[7,6] 00 00 R/W OPT_TXINV OPT_TXMOD 2008[0] 2008[1] 0 0 0 0 R/W R/W PLL_OK 2003[6] 0 0 R PLS_MAXWIDTH [ 7: 0 ] 2080[7:0] FF FF R/W PLS_INTERVAL [7:0] 2081[7:0] 0 0 R/W 2004[6] 0 0 R/W PREBOOT SFRB2[7] -- -- R PRE_SAMPS[1:0] 2001[7:6] 0 0 R/W 2002[3] 0 0 R/W 2060 2061 2062 2063 SFRB2[6] 0 0 0 0 0 0 0 0 0 -- R/W R/W 20A9[6] 0 0 W 2001[5:0] 0 0 R/W OPT_FDC[1:0] PLS_INV RTM_E RTM0[7:0] RTM1[7:0] RTM2[7:0] RTM3[7:0] SECURE SLEEP SUM_CYCLES[5:0] Page: 74 of 97 Selects OPT_TX modulation duty cycle OPT_FDC Function 00 50% Low 01 25% Low 10 12.5% Low 11 6.25% Low OPT_RX can be configured as an analog input to the optical UART comparator or as a digital input/output, DIO1. 0--OPT_RX, 1--DIO1. Inverts result from OPT_RX comparator when 1. Affects only the UART input. Has no effect when OPT_RX is used as a DIO input. Configures the OPT_TX output pin. 00--OPT_TX, 01--DIO2, 10--WPULSE, 11--RESERVED Invert OPT_TX when 1. This inversion occurs before modulation. Enables modulation of OPT_TX. When OPT_TXMOD is set, OPT_TX is modulated when it would otherwise have been zero. The modulation is applied after any inversion caused by OPT_TXINV. Indicates that system power is present and the clock generation PLL is settled. Determines the maximum width of the pulse (low going pulse). Maximum pulse width is (2*PLS_MAXWIDTH + 1)*TI. Where TI is PLS_INTERVAL. If PLS_INTERVAL=0, TI is the sample time (397s). If 255, disable MAXWIDTH. If the FIFO is used, PLS_INTERVAL must be set to 81. If PLS_INTERVAL = 0, the FIFO is not used and pulses are output as soon as the CE issues them. Inverts the polarity of WPULSE. Normally, these pulses are active low. When inverted, they become active high. Indicates that preboot sequence is active. The duration of the pre-summer, in samples. 00-42, 01-50, 10-84, 11-100. Real Time Monitor enable. When `0', the RTM output is low. This bit enables the two wire version of RTM Four RTM probes. Before each CE code pass, the values of these registers are serially output on the RTM pin. The RTM registers are ignored when RTM_E=0. Enables security provisions that prevent external reading of flash memory and CE program RAM. This bit is reset on chip reset and may only be set. Attempts to write zero are ignored. Takes the 6521BE to sleep mode. Ignored if system power is present. The 6521BE will wake when the autowake timer times out, when push button is pushed, or when system power returns. The number of pre-summer outputs summed in the final summer. (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 TMUX[4:0] 20AA[4:0] 2 -- R/W 2006 -- -- R VREF_CAL 2004[7] 0 0 R/W VREF_DIS WAKE_ARM 2004[3] 20A9[7] 0 0 1 -- R/W W WAKE_PRD 20A9[2:0] 001 -- R/W WAKE_RES WD_RST 20A9[3] SFRE8[7] 0 0 -0 R/W W 2002[2] 0 0 R/W VERSION[7:0] WD_OVF V1.0 Selects one of 32 signals for TMUXOUT. [4:0] Selected Signal [4:0] 0x00 DGND (analog) 0x01 0x02 Reserved 0x03 0x04 Reserved 0x05 0x06 VBIAS (analog) 0x07 0x08 Reserved 0x09 0x0A Reserved 0x0B -0x13 0x14 RTM (Real time 0x15 output from CE) 0x16 - Not used 0x18 0x17 Selected Signal Reserved Reserved Reserved Not used Reserved Reserved WDTR_E, comparator 1 Output AND V1LT3) RXD, from optical interface, after optional inversion CK_10M Reserved CE_BUSY 0x19 MUX_SYNC 0x1A 0x1B CK_MPU 0x1C 0x1D Reserved 0x1E 0x1F XFER_BUSY The version index. This word may be read by firmware to determine the silicon version. VERSION[7:0] Silicon Version 0000 0110 A06 Brings VREF to VREF pad. This feature is disabled when VREF_DIS=1. Disables the internal voltage reference. Arm the autowake timer. Writing a 1 to this bit arms the autowake timer and presets it with the values presently in WAKE_PRD and WAKE_RES. The autowake timer is reset and disarmed whenever the processor is in MISSION mode or BROWNOUT mode. The timer must be armed at least three crystal clock cycles before the SLEEP or LCD-ONLY mode is commanded. Sleep time. Time=WAKE_PRD[2:0]*WAKE_RES. Default=001. Maximum value is 7. Resolution of WAKE timer: 1 - 1 minute, 0 - 2.5 seconds. WD timer bit: Possible operations to this bit are: Read: Gets the status of the flag IE_PLLFALL Write 0: Clears the flag Write 1:.Resets the WDT The WD overflow status bit. This bit is set when the WD timer overflows. It is powered by the nonvolatile supply and at bootup will indicate if the part is recovering from a WD overflow or a power fault. This bit should be cleared by the MPU on bootup. It is also automatically cleared when RESET is high. (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 75 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 CE Interface Description CE Program The CE program is supplied by TERIDIAN as a data image that can be merged with the MPU operational code for meter applications. Typically, the CE program covers most applications and does not need to be modified. The description in this section applies to CE code revision CE6521BE_A04. Formats All CE words are 4 bytes. Unless specified otherwise, they are in 32-bit two's complement (-1 = 0xFFFFFFFF). `Calibration' parameters are defined in flash memory (or external EEPROM) and must be copied to CE data memory by the MPU before enabling the CE. `Internal' variables are used in internal CE calculations. `Input' variables allow the MPU to control the behavior of the CE code. `Output' variables are outputs of the CE calculations. Constants Constants used in the CE Data Memory tables are: FS = 32768Hz/13 = 2520.62Hz. F0 is the fundamental frequency. IMAX is the external rms current corresponding to 250mV pk at the inputs IA and IB. VMAX is the external rms voltage corresponding to 250mV pk at the VA and VB inputs. NACC, the accumulation count for energy measurements is PRE_SAMPS*SUM_CYCLES. Accumulation count time for energy measurements is PRE_SAMPS*SUM_CYCLES/FS. The system constants IMAX and VMAX are used to convert internal quantities (as used by the CE) to external, i.e. metering quantities. Their values are determined by the off-chip scaling of the voltage and current sensors used in an actual meter. The LSB values used in this document relate digital quantities at the CE interface to external meter input quantities. For example, if a SAG threshold of 80V peak is desired at the meter input, the digital value that should be programmed into SAG_THR would be 80V/SAG_THRLSB, where SAG_THRLSB is the LSB value in the description of SAG_THR. The parameters EQU, CE_E, PRE_SAMPS, and SUM_CYCLES essential to the function of the CE are stored in I/O RAM (see I/O RAM section). Environment Before starting the CE using the CE_E bit, the MPU has to establish the proper environment for the CE by implementing the following steps: Load the CE data into CE DRAM. Establish the equation to be applied in EQU. Establish the accumulation period and number of samples in PRE_SAMPS and SUM_CYCLES. Establish the number of cycles per ADC mux frame. Set PLS_INTERVAL[7:0] to 81. Set FIR_LEN to 1 and MUX_DIV to 1. There must be thirteen 32768Hz cycles per ADC mux frame (see System Timing Diagram, Figure 16). This means that the product of the number of cycles per frame and the number of conversions per frame must be 12 (allowing for one settling cycle). The required configuration is FIR_LEN = 1 (three cycles per conversion) and MUX_DIV = 1 (4 conversions per mux frame). During operation, the MPU is in charge of controlling the multiplexer cycles, for example by inserting an alternate multiplexer sequence at regular intervals using MUX_ALT. This enables temperature measurement. The polarity of chopping circuitry must be altered for each sample. It must also alternate for each alternate multiplexer reading. This is accomplished by maintaining CHOP_E = 00. Page: 76 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 CE Calculations The CE performs the precision computations necessary to accurately measure energy. These computations include offset cancellation, products, product smoothing, product summation, frequency detection, and sag detection. All data computed by the CE is dependent on the selected meter equation as given by EQU (in I/O RAM). However, for the 6521BE CE code, EQU is always 0. Watt Formula EQU 0 Element Input Mapping (WSUM) VA IA (1 element, 2W 1) with tamper detection W0SUM W1SUM I0SQSUM I1SQSUM VA*IA VA*IB IA IB CESTATUS Since the CE_BUSY interrupt occurs at 2520.6Hz, it is desirable to minimize the computation required in the interrupt handler of the MPU. The MPU can read the CE status word at every CE_BUSY interrupt. CE Address 0x11E8 Name CESTATUS Description See description of CE status word below The CE Status Word is used for generating early warnings to the MPU. It contains sag warnings for VA as well as the F0 bit, a clock derived from the fundamental input frequency. CESTATUS provides information about the status of voltage and input AC signal frequency, which are useful for generating early power fail warnings, e.g. to initiate necessary data storage. CESTATUS represents the status flags for the preceding CE code pass (CE busy interrupt). Sag alarms are not remembered from one code pass to the next. The CE Status word is refreshed at every CE_BUSY interrupt. The significance of the bits in CESTATUS is shown in the table below: CESTATUS [bit] Name 31-29 Not Used Description These unused bits will always be zero. F0 is a square wave at the exact fundamental input frequency. Mains Signal V1.0 28 F0 27 CREEP Normally zero. Becomes one when creep logic has been applied to either WA or WB. 26 SAG_B 25 SAG_A Normally zero. These bits come one when the voltage in the respective channel remains below SAG_THR for SAG_CNT samples. Will not return to zero until the voltage rises above SAG_THR. 24-0 Not Used F0 These unused bits will always be zero. (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 77 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 The CE is initialized by the MPU using CECONFIG (CESTATE). This register contains in packed form the control bits for SAG_CNT, FREQSEL, NEUTRAL_TAMPER, IB_SHUNT, IA_SHUNT, PULSE_SLOW, and PULSE_FAST. CE Address 0x1040 Name Default Description CECONFIG 0x5000 See description of CECONFIG below The significance of the bits in CECONFIG is shown in the table below: IA_SHUNT and/or IB_SHUNT can configure their respective current inputs to accept shunt resistor sensors. In this case the CE provides an additional gain of 8 to the selected current input. WRATE may need to be adjusted based on the values of IA_SHUNT and IB_SHUNT. Whenever IA_SHUNT or IB_SHUNT are set to 1, In_8 (in the equation for Kh) is assigned a value of 8. The CE pulse generator is controlled only by the CE (internal) variables. Note: The 6521BE Demo Code creep function halts both internal and external pulse generation. CECONFIG [bit] Name Default [15:8] SAG_CNT 80 (0x50) [7] -- 0 Reserved [6] FREQSEL 0 Selected phase for frequency monitor (0 = A, 1 = B). [5] NEUTRAL TAMPER 0 Alert CE that neutral line tampering has been detected. [4] MAGNETIC TAMPER 0 Alert CE that magnetic tampering has been detected. [3] IB_SHUNT 0 When 1, the current gain of channel B is increased by 8. The gain factor controlled by In_SHUNT is referred to as In_8 throughout this document. [2] IA_SHUNT 0 When 1, the current gain of channel A is increased by 8. [1] PULSE_FAST 0 Description Number of consecutive voltage samples below SAG_THR before a sag alarm is declared. The maximum value is 255. SAG_THR is at address 0x14. When PULSE_SLOW = 1, the pulse generator input is reduced by a factor of 64. When PULSE_FAST = 1, the pulse generator input is increased 16x. These two parameters control the pulse gain factor X (see table below). Allowed values are either 1 or 0. Default is 0 (X = 6). X PULSE_SLOW PULSE_FAST 0 0 0 1 1.5 * 2 = 0.09375 1 0 1.5 1 1 2 1.5 * 2 = 6 6 [0] Page: 78 of 97 PULSE_SLOW 0 1.5 * 2 = 96 -4 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 CE TRANSFER VARIABLES When the MPU receives the XFER_BUSY interrupt, it knows that fresh data is available in the transfer variables. Fundamental Energy Measurement Variables The table below describes each transfer variable for fundamental energy measurement. All variables are signed 32 bit integers. Accumulated variables such as WSUM are internally scaled so they have at least 2x margin before overflow when the integration time is 1 second. Additionally, the hardware will not permit output values to `fold back' upon overflow. CE Address Name 0x11D8 W0SUM_X The sum of Watt samples from each wattmeter element (In_8 is the gain configured by IA_SHUNT or IB_SHUNT). 0x11C8 W1SUM_X LSB = 6.6952*10-13 VMAX IMAX / In_8 Wh. Description WxSUM_X is the Wh value accumulated for element `X' in the last accumulation interval and can be computed based on the specified LSB value. For example with VMAX = 600V and IMAX = 208A, LSB (for WxSUM_X) is 0.08356 Wh. Instantaneous Energy Measurement Variables The Frequency measurement is computed using the Frequency locked loop for the selected phase. IxSQSUM_X and VxSQSUM are the squared current and voltage samples acquired during the last accumulation interval. INSQSUM_X can be used for computing the neutral current. CE Address Name 0x11E4 FREQ_X 0x11F0 MAINEDGE_X 0x11DC I0SQSUM_X The sum of squared current samples from each element. 0x11CC I1SQSUM_X LSB = 6.6952*10-13 IMAX2 / In_82 A2h 0x11E0 V0SQSUM_X The sum of squared voltage samples from each element. 0x11D0 V1SQSUM_X LSB= 6.6952*10-13 VMAX2 V2h 0x11F4 WSUM_ACCUM 0x11D4 I0SQRT_X 0x11C4 I1SQRT_X V1.0 Description Fundamental frequency. LSB FS 0.587 10 -6 Hz 32 2 The number of zero crossings of the selected voltage in the previous accumulation interval. Zero crossings are either direction and are debounced. Rollover accumulator for WPULSE. RMS current determined by calculating the square root of I0SQSUM_X and I1SQSUM_X (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 79 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Other CE Parameters Temperature Parameters MAINEDGE_X is useful for implementing a real-time clock based on the input AC signal. MAINEDGE_X is the number of halfcycles accounted for in the last accumulated interval for the AC signal. TEMP_RAW may be used by the MPU to monitor chip temperature. Temperature compensation is implemented by the CE, based on the value written to TEMP_NOM. CE Address Name Default 0x11EC TEMP_RAW_X N/A Filtered, unscaled reading from the temperature sensor. 0x105C TEMP_NOM N/A Reference temperature for temperature compensation. 0x1054 DEGSCALE 19065 Multiplier for temperature calculation. 0x1048 GAIN_ADJ 16384 Scales all voltage and current inputs, based on the temperature compensation mechanism. 16384 provides unity gain. 0x1080 PPMC1 N/A Linear parameter for temperature compensation. 0x1084 PPMC2 N/A Quadratic parameter for temperature compensation. Description GAIN_ADJ is a scaling factor for measurements based on the temperature. GAIN_ADJ is controlled by the MPU for temperature compensation. Sag, Creep and Tamper Control CE Address Name Default 0x1070 CREEP0_THR 8311 0x1074 CREEP1_THR 8311 Description Wh threshold for channels A and B. LSB = 6.6952 10 -13 IMAX VMAX N ACC FS The default value is equivalent to 2.5W 0x1050 SAG_THR 443000 The threshold for sag warnings. The default value is equivalent to 80V RMS if VMAX = 600V. The LSB value is 1.80587*10-4V (RMS). 0x1078 VNOMINAL 1.27*108 Nominal voltage to be applied to the larger of the two currents when neutral tampering is detected. The default value is equivalent to 230V RMS. Nominal power consumption to be applied when magnetic tampering is detected. 0x107C WNOMINAL 7646227 LSB = 6.6952 10 -13 IMAX VMAX N ACC FS The default value is equivalent to 0.65Wh per accumulation interval, or 2300Wh/h (230V, 10A). Page: 80 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Pulse Generation CE Address Name 0x1044 Default 389 WRATE Description Kh = VMAX*IMAX*47.1132 / (In_8*WRATE*NACC*X) Wh/pulse. The default value results in a Kh of 1.0Wh/pulse when 2520 samples are taken in each accumulation interval (and VMAX=600, IMAX = 208, In_8 = 1, X = 6). The maximum value for WRATE is 215 - 1. WRATE controls the number of pulses that are generated per measured Wh quantities. The lower WRATE is the slower the pulse rate for measured energy quantity. The metering constant Kh is derived from WRATE as the amount of energy measured for each pulse. That is, if Kh = 1Wh/pulse, a power applied to the meter of 120V and 30A results in one pulse per second. If the load is 240V at 150A, ten pulses per second will be generated. X is controlled by the PULSE_FAST and PULSE_SLOW bits in the CECONFIG register. The maximum pulse rate is 7.5kHz. The maximum time jitter is 67s and is independent of the number of pulses measured. Thus, if the pulse generator is monitored for 1 second, the peak jitter is 67ppm. After 10 seconds, the peak jitter is 6.7ppm. The average jitter is always zero. If it is attempted to drive either pulse generator faster than its maximum rate, it will simply output at its maximum rate without exhibiting any rollover characteristics. The actual pulse rate, using WSUM as an example, is: RATE = WRATE WSUM FS X Hz , 2 46 where FS = sampling frequency (2520.6Hz), X = Pulse speed factor CE Calibration Parameters The table below lists the parameters that are typically entered to effect calibration of meter accuracy. CE Address Name Default 0x1020 CAL_IA 16384 0x1024 CAL_VA 16384 0x1028 CAL_IB 16384 0x102C CAL_VB 16384 0x1030 0x1034 V1.0 PHADJ_A PHADJ_B 0 0 Description These constants control the gain of their respective channels. The nominal value for each parameter is 214 = 16384. The gain of each channel is directly proportional to its CAL parameter. Thus, if the gain of a channel is 1% slow, CAL should be scaled by 1/(1 - 0.01). These two constants control the CT phase compensation. No compensation occurs when PHADJ_X = 0. As PHADJ_X is increased, more compensation 15 (lag) is introduced. Range: 2 - 1. If it is desired to delay the current by the angle : PHADJ _ X = 2 20 0.02229 TAN at 60Hz 0.1487 - 0.0131 TAN PHADJ _ X = 2 20 0.0155 TAN at 50Hz 0.1241 - 0.009695 TAN (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 81 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Other CE Parameters The table below shows CE parameters used for suppression of noise due to scaling and truncation effects. CE Address Name Default 0x104C QUANTA 0 This parameter is added to the Watt calculation for element 0 to compensate for input noise and truncation. LSB = (VMAX*IMAX / In_8) *7.4162*10-10 W 0x1060 QUANTB 0 This parameter is added to the Watt calculation for element 1 to compensate for input noise and truncation. LSB = (VMAX*IMAX / In_8) *7.4162*10-10 W 0x1058 QUANT_IA 0 Description This parameter is added to compensate for input noise and truncation in the squaring calculations for I2. QUANT_IA affects only I0SQSUM and I1SQSUM. LSB = (IMAX2/In_82)*7.4162*10-10 A2 0x106C QUANT_IB 0 This parameter is added to compensate for input noise and truncation in the squaring calculations for I2. QUANT_IB affects only I0SQSUM and I1SQSUM. LSB = (IMAX2/In_82)*7.4162*10-10 A2 Page: 82 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Supplies and Ground Pins: V3P3SYS, V3P3A VBAT GNDD Analog Output Pins: -0.5V to 4.6V -0.5V to 4.6V -0.5V to +0.5V -10mA to 10mA, -0.5V to 4.6V -10mA to +10mA, -0.5V to V3P3A+0.5V -10mA to +10mA, -0.5V to 3.0V V3P3D VREF V2P5 Analog Input Pins: -10mA to +10mA -0.5V to V3P3A+0.5V -10mA to +10mA -0.5V to 3.0V IA, VA, IB, VB, V1 XIN, XOUT All Other Pins: -1mA to +1mA, -0.5 to V3P3D+0.5 -10mA to +10mA, -0.5 to 6V -15mA to +15mA, -0.5V to V3P3D+0.5V -0.5V to V3P3D+0.5V Configured as SEG or COM drivers Configured as Digital Inputs Configured as Digital Outputs All other pins Operating junction temperature (peak, 100ms) Operating junction temperature (continuous) Storage temperature Solder temperature - 10 second duration ESD stress on all pins 140 C 125 C -45 C to +165 C 250 C 4kV Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GNDA. V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 83 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 RECOMMENDED EXTERNAL COMPONENTS NAME C1 C2 CSYS C2P5 FROM V3P3A V3P3D V3P3SYS V2P5 TO AGND DGND DGND DGND FUNCTION VALUE UNIT Bypass capacitor for 3.3V supply 0.120% F Bypass capacitor for 3.3V output 0.120% F Bypass capacitor for V3P3SYS 1.030% F Bypass capacitor for V2P5 0.120% F 32.768kHz crystal - electrically similar to ECS XTAL .327-12.5-17X or Vishay XT26T, load capaci32.768 kHz XIN XOUT tance 12.5pF Load capacitor for crystal (depends on crystal pF CXS XIN AGND 2710% specs and board parasitics). Load capacitor for crystal (depends on pF CXL XOUT AGND 2710% crystal specs and board parasitics). Depending on trace capacitance, higher or lower values for CXS and CXL must be used. Capacitance from XIN to GNDD and XOUT to GNDD (combining pin, trace and crystal capacitance) should be 30pF to 42pF. RECOMMENDED OPERATING CONDITIONS PARAMETER 3.3V Supply Voltage (V3P3SYS, V3P3A) V3P3A and V3P3SYS must be at the same voltage CONDITION Normal Operation Battery Backup No Battery Battery Backup BRN and LCD modes SLEEP mode VBAT Operating Temperature Maximum input voltage on DIO/SEG pins configured as DIO input. * MIN 3.0 0 TYP 3.3 UNIT V V Externally Connect to V3P3SYS 3.0 2.0 -40 MISSION mode BROWNOUT mode LCD mode *Exceeding this limit will distort the LCD waveforms on other pins. Page: 84 of 97 MAX 3.6 3.6 (c) 2005-2008 TERIDIAN Semiconductor Corporation 3.8 3.8 +85 V3P3SYS+0.3 VBAT+0.3 VBAT+0.3 V V C V V V V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 PERFORMANCE SPECIFICATIONS INPUT LOGIC LEVELS PARAMETER CONDITION MIN TYP MAX Digital high-level input voltage, VIH 2 Digital low-level input voltage, VIL 0.8 Exceptions to above input standard: VIN=0V, ICE_E=1 Input pull-up current, IIL 100 10 E_RXTX, 100 10 E_RST, CKTEST 1 0 -1 Other digital inputs VIN=V3P3D Input pull down current, IIH 100 10 ICE_E 1 0 -1 PB 1 0 -1 Other digital inputs In battery powered modes, digital inputs should be below 0.3V or above 2.5V to minimize battery current. UNIT V V A A A A A A OUTPUT LOGIC LEVELS PARAMETER CONDITION ILOAD = 1mA Digital high-level output voltage VOH ILOAD = 15mA ILOAD = 1mA ILOAD = 15mA ISOURCE=1mA ISINK=20mA Digital low-level output voltage VOL OPT_TX VOH (V3P3D-OPT_TX) OPT_TX VOL MIN V3P3D -0.4 V3P3D0.6 0 TYP MIN TYP MAX UNIT V V 0.4 0.8 0.4 0.7 V V V V MAX UNIT -20 +15 mV 0.8 1.2 A 10 s -10 mV MAX 63 -4.9 -2.0 +100 UNIT k V V mV POWER-FAULT COMPARATOR PARAMETER Offset Voltage V1-VBIAS Hysteresis Current V1 Response Time V1 WDT Disable Threshold (V1-V3P3A) CONDITION Vin = VBIAS - 100mV +100mV overdrive 2 5 -400 BATTERY MONITOR BME=1 PARAMETER Load Resistor LSB Value - does not include the 9- bit left shift at CE input. Offset Error V1.0 CONDITION FIR_LEN=0 FIR_LEN=1 MIN 27 -6.0 -2.6 -200 (c) 2005-2008 TERIDIAN Semiconductor Corporation TYP 45 -5.4 -2.3 -72 Page: 85 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 SUPPLY CURRENT PARAMETER V3P3A + V3P3SYS current VBAT current CONDITION Normal Operation, V3P3A=V3P3SYS=3.3V MPU_DIV = 3 (614kHz), CKOUT_E = 0, CE_EN = 1, RTM_E = 0, ECK_DIS = 1, ADC_E = 1, ICE_E = 0 MIN MAX UNIT 6.1 7.7 mA +300 nA -300 mA/ MHz V3P3A + V3P3SYS current vs. MPU clock frequency Same conditions as above 0.5 V3P3A + V3P3SYS current, Write Flash Normal Operation as above, except write Flash at maximum rate, CE_E=0, ADC_E=0 9.1 10 mA 48 65 120 150 A A LCD Mode, 25C LCD mode, over temperature 5.7 8.5 15 A A SLEEP Mode, 25C Sleep mode, over temperature 2.9 5.0 10 A A VBAT=3.6V BROWNOUT mode, <25C BROWNOUT mode, >25C VBAT current TYP Current into V3P3A and V3P3SYS pins is not zero if voltage is applied at these pins in brownout, LCD or sleep modes. V3P3D SWITCH PARAMETER On resistance - V3P3SYS to V3P3D On resistance - VBAT to V3P3D CONDITION | IV3P3D | 1mA | IV3P3D | 1mA MIN TYP MAX 10 40 UNIT CONDITION Reduce V3P3 until V2P5 drops 200mV RESET=0, iload=0 MIN TYP MAX UNIT 440 mV +3 mV/V 2.5V VOLTAGE REGULATOR Unless otherwise specified, load = 5mA PARAMETER Voltage overhead V3P3-V2P5 PSSR V2P5/V3P3 Page: 86 of 97 -3 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 LOW POWER VOLTAGE REGULATOR Unless otherwise specified, V3P3SYS=V3P3A=0, PB=GND (BROWNOUT) PARAMETER V2P5 V2P5 load regulation VBAT voltage requirement PSRR V2P5/VBAT CONDITION ILOAD=0 ILOAD=0mA to 1mA ILOAD=1mA, Reduce VBAT until REG_LP_OK=0 ILOAD=0 MIN 2.0 CONDITION Crystal connected MIN TYP 2.5 MAX 2.7 30 UNIT V mV 3.0 V 50 mV/V MAX 1 3 UNIT W pF 5 5 pF pF MAX 1.197 50 UNIT V mV 2.5 k -50 CRYSTAL OSCILLATOR PARAMETER Maximum Output Power to Crystal XIN to XOUT Capacitance Capacitance to DGND XIN XOUT TYP VREF, VBIAS Unless otherwise specified, VREF_DIS=0 PARAMETER VREF output voltage, VNOM(25) VREF chop step VREF output impedance VNOM definitionA CONDITION Ta = 22C MIN 1.193 VREF_CAL =1, ILOAD = 10A, -10A VNOM (T ) = VREF(22) + (T - 22)TC1 + (T - 22) 2 TC 2 VREF temperature coefficients TC1 TC2 VREF aging VREF(T) deviation from VNOM(T) VREF (T ) - VNOM (T ) 10 6 VNOM 62 TYP 1.195 -40 Ta = 25C (-1%) Ta = -40C to 85C (-4%) A This relationship describes the nominal behavior of VREF at different temperatures. VBIAS voltage V1.0 V/C V/C2 ppm/year +7.0 -0.341 25 Ta = -40C to +85C (c) 2005-2008 TERIDIAN Semiconductor Corporation 1.6 1.6 V +40 ppm/C (+1%) (+4%) V V Page: 87 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 LCD DRIVERS Applies to all COM and SEG pins. PARAMETER VLC2 Max Voltage VLC1 Voltage, 1/3 bias 1/2 bias VLC0 Voltage, 1/3 bias 1/2 bias CONDITION With respect to VLCD MIN -0.1 TYP MAX 0+.1 UNIT V With respect to 2*VLC2/3 With respect to VLC2/2 -4 -3 0 +2 % % With respect to VLC2/3 With respect to VLC2/2 -3 -3 +2 +2 % % MAX UNIT mV peak VLCD is V3P3SYS in MISSION mode and VBAT in BROWNOUT and LCD modes. ADC CONVERTER, V3P3A REFERENCED FIR_LEN=0, VREF_DIS=0, LSB values do not include the 9-bit left shift at CE input. PARAMETER Recommended Input Range (Vin-V3P3A) Voltage to Current Crosstalk: CONDITION MIN TYP -250 250 -10 10 V/V 40 -75 -90 90 dB dB k Vin = 200mV peak, 65Hz, on VA 10 6 *Vcrosstalk cos(Vin - Vcrosstalk ) Vcrosstalk = largest Vin measurement on IA or IB THD (First 10 harmonics) 250mV-pk 20mV-pk Input Impedance Temperature coefficient of Input Impedance LSB size Digital Full Scale ADC Gain Error vs %Power Supply Variation 10 6 Nout PK 357nV / VIN 100 V 3P3 A / 3.3 Vin=65Hz, 64kpts FFT, BlackmanHarris window Vin=65Hz Vin=65Hz 1.7 357 151 +884736 2097152 FIR_LEN=0 FIR_LEN=1 FIR_LEN=0 FIR_LEN=1 Vin=200mV pk, 65Hz V3P3A=3.0V, 3.6V -10 Input Offset (Vin-V3P3A) /C nV/LSB LSB 50 ppm/% 10 mV MAX 0.4 0.7 UNIT V V OPTICAL INTERFACE PARAMETER OPT_TX VOH (V3P3D-OPT_TX) OPT_TX VOL Page: 88 of 97 CONDITION ISOURCE=1mA ISINK=20mA MIN (c) 2005-2008 TERIDIAN Semiconductor Corporation TYP V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 TEMPERATURE SENSOR LSB values do not include the 9-bit left shift at CE input. PARAMETER Nominal Sensitivity (Sn)4 FIR_LEN=1 Nominal Sensitivity (Sn)4 FIR_LEN=0 Nominal (Nn) 4, FIR_LEN=1 Nominal (Nn) 4, FIR_LEN=0 Temperature Error MIN Tn=25C Nominal relationship: N(T)= Sn*(T-Tn)+Nn TYP -2180 -923 1.0 MAX UNIT LSB/C LSB/C 6 10 LSB 6 10 LSB +10 C 0.4 ( N (T ) - N n ) + Tn ERR = T - Sn CONDITION T = -40C to +85C, Tn = 25C -10 Nn is measured at Tn during meter calibration and is stored in MPU or CE for use in temperature calculations. V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 89 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 TIMING SPECIFICATIONS RAM AND FLASH MEMORY PARAMETER CE DRAM wait states Flash Read Pulse Width Flash write cycles Flash data retention Flash data retention Flash byte writes between page or mass erase operations CONDITION CKMPU = 4.9MHz CKMPU = 1.25MHz CKMPU = 614kHz MIN 5 2 1 V3P3A=V3P3SYS=0 BROWNOUT MODE 30 -40C to +85C 25C 85C TYP MAX UNIT Cycles Cycles Cycles 100 ns 20,000 100 10 Cycles Years Years 2 Cycles FLASH MEMORY TIMING PARAMETER Write Time per Byte Page Erase (512 bytes) Mass Erase CONDITION MIN TYP MAX 42 20 200 UNIT s ms ms MIN TYP MAX UNIT EEPROM INTERFACE PARAMETER 2 Write Clock frequency (I C) Write Clock frequency (3-wire) CONDITION CKMPU=4.9MHz, Using interrupts CKMPU=4.9MHz, "bitbanging" DIO4/5 CKMPU=4.9MHz 78 kHz 150 kHz 500 kHz RESET PARAMETER Reset pulse width Reset pulse fall time CONDITION MIN 5 TYP MAX 1 UNIT s s FOOTNOTES 1 This spec is guaranteed, has been verified in production samples, but is not measured in production. This spec is guaranteed, has been verified in production samples, but is measured in production only at DC. 3 This spec is measured in production at the limits of the specified operating temperature. 4 This spec defines a nominal relationship rather than a measured parameter. Correct circuit operation is verified with other specs that use this nominal relationship as a reference. 2 Page: 90 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 TYPICAL PERFORMANCE DATA 0.5 0.4 0.3 Error [%] 0.2 0.1 0 -0.1 -0.2 Phase_0 -0.3 Phase_60 -0.4 Phase_300 -0.5 0.1 1 10 100 1000 Current [A] Figure 38: Wh Accuracy, 0.1A to 200A at 240V/50Hz and Room Temperature 2 1 0 Error [%] -1 -2 -3 50Hz Harmonic Data 60Hz Harmonic Data -4 -5 -6 -7 -8 1 3 5 7 9 11 13 15 17 19 21 23 25 Harmonic Measured at current distortion amplitude of 40% and voltage distortion amplitude of 10%. Figure 39: Meter Accuracy over Harmonics at 240V, 30A V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 91 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Relative Accuracy over Temperature Accuracy [PPM/C] 40 30 20 10 0 -10 -20 -30 -60 -40 -20 0 20 40 60 80 100 Temperature [C] Figure 40: Typical Meter Accuracy over Temperature Relative to 25C PACKAGE OUTLINE (LQFP 64) 11.7 12.3 11.7 + 12.3 PIN No. 1 Indicator 9.8 10.2 0.60 Typ. 0.50 Typ. 0.00 0.20 0.14 0.28 1.40 1.60 Controlling dimensions are in mm Page: 92 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 V1.0 SEG3 6 V3P3D 7 CKTEST/SEG19 8 V3P3SYS 9 IB VB VA V3P3A GNDA 52 51 50 49 54 53 VREF IA 55 OPT_RX/DIO1 V1 56 5 X4MHZ 4 TX 57 TMUXOUT 58 3 TEST OPT_TX/DIO2 XIN 2 59 XOUT 61 1 60 63 GNDD E_RXTX/SEG38 62 E_TCLK/SEG33 E_RST/SEG32 PB 64 PINOUT (LQFP-64) 48 V2P5 46 VBAT 45 TERIDIAN 71M6521BE-IGT RESET 47 RX 44 SEG31/DIO11 43 SEG30/DIO10 42 SEG29/DIO9 41 SEG28/DIO8 40 SEG27/DIO7 39 SEG26/DIO6 30 31 SEG13 SEG14 32 29 SEG15 28 SEG11 SEG12 27 26 SEG16 SEG9 SEG10 SEG17 33 25 34 16 SEG8 15 COM3 24 COM2 23 SEG18 SEG7 35 SEG6 14 22 ICE_E COM1 SEG36/DIO16 36 21 13 SEG35/DIO15 SEG24/DIO4 COM0 20 37 19 12 SEG2 SEG25/DIO5 SEG37/DIO17 SEG34/DIO14 38 18 11 17 SEG5 SEG1 10 SEG0 SEG4 (c) 2005-2008 TERIDIAN Semiconductor Corporation \ Page: 93 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 PIN DESCRIPTIONS Power/Ground Pins: Name Type Circuit Description GNDA P -- Analog ground: This pin should be connected directly to the ground plane. GNDD P -- Digital ground: This pin should be connected directly to the ground plane. V3P3A P -- Analog power supply: A 3.3V power supply should be connected to this pin, must be the same voltage as V3P3SYS. V3P3SYS P -- System 3.3V supply. This pin should be connected to a 3.3V power supply. V3P3D O 13 Auxiliary voltage output of the chip, controlled by the internal 3.3V selection switch. In mission mode, this pin is internally connected to V3P3SYS. In BROWNOUT mode, it is internally connected to VBAT. This pin is floating in LCD and sleep mode. VBAT P 12 Battery backup power supply. A battery or super-capacitor is to be connected between VBAT and GNDD. If no battery is used, connect VBAT to V3P3SYS. V2P5 O 10 Output of the internal 2.5V regulator. A 0.1F capacitor to GNDA should be connected to this pin. Analog Pins: Name Type Circuit IA, IB I 6 Line Current Sense Inputs: These pins are voltage inputs to the internal A/D converter. Typically, they are connected to the outputs of current sensors. Unused pins must be connected to V3P3A. VA, VB I 6 Line Voltage Sense Inputs: These pins are voltage inputs to the internal A/D converter. Typically, they are connected to the outputs of resistor dividers. Unused pins must be connected to V3P3A or tied to the voltage sense input that is in use. V1 I 7 VREF O 9 I 8 XIN XOUT Description Comparator Input: This pin is a voltage input to the internal comparator. The voltage applied to the pin is compared to an internal BIAS voltage (1.6V). If the input voltage is above the reference, the comparator output will be high (1). If the comparator output is low, a voltage fault will occur. A 0.1F capacitor to GNDA should be connected to this pin. Voltage Reference for the ADC. This pin is normally disabled by setting the VREF_CAL bit in the I/O RAM and can be left unconnected. If enabled, a 0.1F capacitor to GNDA should be connected. Crystal Inputs: A 32kHz crystal should be connected across these pins. Typically, a 27pF capacitor is also connected from each pin to GNDA. It is important to minimize the capacitance between these pins. See the crystal manufacturer datasheet for details. Pin types: P = Power, O = Output, I = Input, I/O = Input/Output The circuit number denotes the equivalent circuit, as specified under "I/O Equivalent Circuits". Page: 94 of 97 (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 Digital Pins: Name Type Circuit Description COM3, COM2, COM1, COM0 O 5 LCD Common Outputs: These 4 pins provide the select signals for the LCD display. SEG0...SEG18 O 5 Dedicated LCD Segment Output. SEG24/DIO4... SEG31/DIO11 I/O 3, 4, 5 Multi-use pins, configurable as either LCD SEG driver or DIO. (DIO4 = SCK, DIO5 = SDA when configured as EEPROM interface, WPULSE = DIO6 when configured as pulse outputs). If unused, these pins must be configured as outputs. SEG34/DIO14... SEG37/DIO17 I/O 3, 4, 5 Multi-use pins, configurable as either LCD SEG driver or DIO. If unused, these pins must be configured as outputs. E_RXTX/SEG38 I/O 1, 4, 5 E_RST/SEG32 I/O 1, 4, 5 E_TCLK/SEG33 O 4, 5 Multi-use pins, configurable as either emulator port pins (when ICE_E pulled high) or LCD SEG drivers (when ICE_E tied to GND). ICE_E I 2 ICE enable. When zero, E_RST, E_TCLK, and E_RXTX become SEG32, SEG33, and SEG38 respectively. For production units, this pin should be pulled to GND to disable the emulator port. This pin should be brought out to the programming interface in order to create a way for reprogramming parts that have the SECURE bit set. CKTEST/SEG19 O 4, 5 Multi-use pin, configurable as either Clock PLL output or LCD segment driver. Can be enabled and disabled by CKOUT_EN. TMUXOUT O 4 OPT_RX/DIO1 OPT_TX/DIO2 I/O 3, 4, 7 Digital output test multiplexer. Controlled by TMUX[4:0]. Multi-use pin, configurable as either Optical Receive Input or general DIO. When configured as OPT_RX, this pin receives a signal from an external photo-detector used in an IR serial interface. If unused, this pin must be configured as an output or terminated to V3P3D or GNDD. Multi-use pin, configurable as either Optical LED Transmit Output, WPULSE, RPULSE, or general DIO. When configured as OPT_TX, this pin is capable of directly driving an LED for transmitting data in an IR serial interface. If unused, this pin must be configured as an output or terminated to V3P3D or GNDD. This input pin resets the chip into a known state. For normal operation, this pin is connected to GNDD. To reset the chip, this pin should be pulled high. No external reset circuitry is necessary. UART input. If unused, this pin must be terminated to V3P3D or GNDD. I/O 3, 4 RESET I 3 RX I 3 TX O 4 UART output. TEST I 7 Enables Production Test. Must be grounded in normal operation. PB I 3 Push button input. A rising edge sets the IE_PB flag and causes the part to wake up if it is in SLEEP or LCD mode. PB does not have an internal pull-up or pull-down. If unused, this pin must be terminated to GNDD. X4MHZ I 3 This pin must be connected to GNDD. Pin types: P = Power, O = Output, I = Input, I/O = Input/Output The circuit number denotes the equivalent circuit, as specified on the following page. V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation Page: 95 of 97 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 I/O Equivalent Circuits: V3P3D V3P3D V3P3A 110K Digital Input Pin CMOS Input LCD SEG Output Pin LCD Driver from internal reference VREF Pin GNDD GNDA GNDD Digital Input Equivalent Circuit Type 1: Standard Digital Input or pin configured as DIO Input with Internal Pull-Up V3P3D VREF Equivalent Circuit Type 9: VREF LCD Output Equivalent Circuit Type 5: LCD SEG or pin configured as LCD SEG V3P3A V3P3D Digital Input Pin CMOS Input 110K GNDD GNDD Analog Input Pin from internal reference To MUX V2P5 Pin GNDA Digital Input Type 2: Pin configured as DIO Input with Internal Pull-Down GNDD Analog Input Equivalent Circuit Type 6: ADC Input V2P5 Equivalent Circuit Type 10: V2P5 V3P3D V3P3A Digital Input Pin CMOS Input Comparator Input Pin To Comparator Power Down Circuits VBAT Pin GNDD GNDA Digital Input Type 3: Standard Digital Input or pin configured as DIO Input GNDD Comparator Input Equivalent Circuit Type 7: Comparator Input VBAT Equivalent Circuit Type 12: VBAT Power V3P3D V3P3D Digital Output Pin CMOS Output from V3P3SYS Oscillator Pin GNDD Digital Output Equivalent Circuit Type 4: Standard Digital Output or pin configured as DIO Output Page: 96 of 97 V3P3D Pin To Oscillator GNDD GNDD Oscillator Equivalent Circuit Type 8: Oscillator I/O 10 from VBAT 40 V3P3D Equivalent Circuit Type 13: V3P3D (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 71M6521BE Energy Meter IC DATA SHEET JANUARY 2008 ORDERING INFORMATION PART 71M6521BE 71M6521BE PART DESCRIPTION (PACKAGE, ACCURACY) FLASH MEMORY SIZE 64-pin LQFP, Lead Free, 0.5% 8KB Bulk 8KB Tape & Reel 64-pin LQFP, Lead Free, 0.5% Packaging ORDERING NUMBER PACKAGE MARKING 71M6521BE-IGT/F 71M6521BE-IGT 71M6521BEIGTR/F 71M6521BE-IGT Data Sheet: This Data Sheet is proprietary to TERIDIAN Semiconductor Corporation (TSC) and sets forth design goals for the described product. This data sheet is subject to change. TSC assumes no obligation regarding future manufacture, unless agreed to in writing. If and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. TERIDIAN Semiconductor Corporation (TSC) reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. TSC assumes no liability for applications assistance. TERIDIAN Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com (c) 2005-2008 TERIDIAN Semiconductor Corporation V1.0 (c) 2005-2008 TERIDIAN Semiconductor Corporation 1/28/2008 Page: 97 of 97 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Maxim Integrated: 71M6521BE-DB