CMOS DUAL-PORT RAMS IDT7133SA/LA 32K (2K x 16-BIT) IDT7143SA/LA Integrated Device Technology, Inc. FEATURES: DESCRIPTION: High-speed access Military: 35/45/55/70/90ns (max.) Commercial: 25/35/45/55/70/90ns (max.} Low-power operation 1IDT7133/43SA Active: 500 mW (typ.) Standby: SmW (typ.) 1DT7133/43LA Active: 500mW (typ.) Standby: 1mW (typ.) Versatile control for write: separate write control for lower and upper byte of each port MASTER IDT7133 easily expands data bus width to 32 bits or more using SLAVE IDT7143 On-chip port arbitration logic (IDT7133 only) BUSY output flag on IDT7133; BUSY input on IDT7143 Fully asynchronous operation from either port Battery backup operation2V data retention TTL-compatible; single 5V (+10%) power supply Available in 68-pin ceramic PGA, Flatpack, and PLCC Military product compliant to MIL-STD-883, Class B Industrial temperature range (40C to +85C) is avail- able, tested to military electrical specifications oe 6 The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static RAMs. The IDT7133 is designed to be used as a stand-alone 16-bit Dual-Port RAM or as a MASTER Dual-Port RAM together with the IDT7143 SLAVE Dual-Port in 32-bit-or- more word width systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit-or-wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. Bath devices provide two independent ports with separate control, address, and |/O pins that permitindependent, asyn- chronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technal- ogy, these devices typically operate on only SOOmW of power. Low-power (LA) versions offer battery backup data retention capability, with each port typically consuming 200UW for a 2V battery. The IDT7133/7143 devices have identical pinouts. Each is packed in a 68-pin ceramic PGA, 68-pin flatpack, and 68-pin PLCC. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. FUNCTIONAL BLOCK DIAGRAM RAWiue CEL RAW LLB OEL Atol AaL VOat-V/O15L VOoL-VO7L Busy) ATL Aoi AioL Ao CEL OEL RAWLUB NOTES: 1. 1077133 (MASTER): BUSY is open drain output and requires pull-up resistor. IDT7143 (SLAVE): BUSY is input. 2. LB = LOWER BYTE 3. UB = UPPER BYTE RW The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1999 Integrated Device Technology, Inc. 6.5 COLUMN R/Wrvs CEA R/Wris GER A1oR Asr V/Osr-/015A V/Oor-//O7R BusvA COLUMN vo vO MEMORY Arr ARRAY Row | SELECT| 3 Aor Aion Aon CER GEA R/WRUB FUWRLB ARBITRATION LOGIC (1DT7133 ONLY) 2748 dew 01 NOVEMBER 1993 OSC-1033/3 1IDT7133SA/LA, IDT7143SA/LA CMOS DUAL-PORT RAMS 32K (2K x 16-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS" 23) Da | 588S8SS8 BEE C2 a ee 2aagRr mon SSS 555555 > loadaa 4 CSG SSS oa YN 98 7 6 5 4 3 21! 68 G7 66 65 64 63 62 61 (Oar [1 10 4 el] As VOro [1 141 sol] Ast VOrw 1 12 saf] A4L VOra fl 13 s7E] Ast VOraL PI 14 se[] Aa VOr T) 15 ssC] Aw VOrs. [1 16 540] Aoi Veo!) [] 17 IDT7 139/43 53{] BUSYL GND 11] 18 & s2[] CEL WOor [1] 19 F8-1 sil] CER Voir [1 20 so[] BUSY R VOe [1 21 PLCC/FLATPACK 40[] Aon VOsr [] 22 TOP VIEW asf] AiR Oar [] 23 47[] Aor VOsr [1] 24 46[] Asn VOer [] 25 45] Aan VO7 [] 26 44[] Asa 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Nifoaletatstatlatatatalalatatstinialtalall, 2748 drw 62 RRSESETES SSESESES So99 000 9sEl < 51 50 48 46 4 a 40 38 Er | 1t Aa. ASL Aa | Aw |BUSYi| CEn | Aor | Am | Aap ; 53 52 49 a7 oy a3 41 390 7 36 a 10 Aa | An | Aw | Aa | Aw | CEL | BUSYR| Aim | Aan | Asa | Aor 7) cay 32 3 09 Ato. Aw Asa AMR 57 56 30 cD) 08 RWus| OEL Aton | Agr 59 58 28 2 07 Veo" | RAW Lue RWre| OER 1DT7133/43, 61 a G@Ug-1 26 re 06 Vou | Vou GND @) | RAV RUS 6 82 24 r-) 05 VOs Oa PGA VOR | VO1sR & et TOP VIEW 2 2 04 vO | VOa VO12n | VO13R 8? 66 2 2 03 von vow VO19R | VOR 68 a 5 7 a W 13, 15 18 19 02 WOa | VOw | VO | VOrae | VO1sL |GND@ | VO | VOsR | VOsA | VOaR | /Oon 2 4 6 8 10 12 4 16 W 01 / VO ror | Ora | VO | Veo) | VOor | VOoR | Can | VOoR | Om Pin 1 Designator 4 B Cc DB F G H J K L 2746 drw 03 NOTES: 1. Both Vcc pins must be connected to the supply to assure teliable operation. 2. Both GND pins must be connected to the supply to assure reliable operation. 3. UB = Upper Byte, LB = Lower Byte 6.5IDT7133SA/LA, IDT7143SA/LA CMOS DUAL-PORT RAMS 32K (2K x 16-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS") CAPACITANCE (Ta = +25C, f = 1.0MHz) Symbol Rating Commercial} Military | Unit Symbol Parameter Conditions | Max. | Unit VteRM)| Terminal Voltage |-0.5 to +7.0 | 0.510 +7.0] V CIN Input Capacitance VIN = OV 11 |. pF with Respect CoutT Input/Output Vo = OV 1 pF to GND Capacitance TA Operating 0 to +70 5 10 +125 F C NOTE: 2748 thlo2 Temperature 1. This parameter is determined by device characterization but is not TBIAS Temperature 55 to +125 | 65 to +135 | C production tested, Under Bias TSTG Storage 55 to +125 | -65 to +150 | C RECOMMENDED OPERATING t Temperature TEMPERATURE AND SUPPLY VOLTAGE pri) Power 2.0 2.0 Ww Ambient Dissipation Grade Temperature GND Vec lout DC Output 50 50 mA Military ~55C to +125C ov 5.0V+10% Current - ; Commercial OC to +70C ov 5.0V + 10% NOTE: 2746 tbl 01 2746 (bl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress tating only and functional operation of the device at these or any other RECOMMENDED DC OPERATING conditions above those indicated in the operational sections of ths CONDITIONS specification is not implied. Exposure to absolute maximum rating condi- Fs ; tions for extended periods may affect reliability. Symbol Parameter Min. | Typ. | Max. | Unit 2. VTERM must not exceed Vcc + 0.5V. Voc Supply Voltage 45 5.0 5.5 Vv 3. VTERM = 5.5V. GND Supply Voltage 0 0 0 v VIH Input High Voltage 2.2 _ 6.0 v VIL Input Low Voltage |-05] | o8 | v NOTE: 2746 tol 04 1. Vit (min.) = -3.0V for pulse width less than 20ns. 2. VTERM must not exceed Vec + 0.5V. 6.5 3IDT7133SA/LA, IDT7143SA/LA CMOS DUAL-PORT RAMS 32K (2K x 16-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Either port, Vcc = 5.0V + 10%} IDT7133SA IDT7133LA IDT7143SA IDT7143LA Symbol Parameter Test Conditions Min. Max. Min. Max. | Unit [ILit Input Leakage Current Voc = 5.5V, VIN = OV to Voc _ 10 _ 5 pA ILo| Output Leakage Current CE = Vin, VouT = OV to Vec _ 10 _ 5 pA VOL Output Low Voltage (|/O0-1/015} lo. = 4mA 0.4 _ 0.4 Vv VoL Open Drain Output Low Voltage lot = 16mA _ 0.5 _ 05 v (BUSY) VOH Output High Voltage OH = -4mA 2.4 _ 24 _ Vv 2746 tol 05 DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE) (vcc = 5.0V + 10%) 7133x25(1)] 7133x35 7133x45 | 7133x55 | 7133x70/90 Test 7143x25(1)) 7143x385 7143x45 | 7143x55 | 7143x70/90 Symbol Parameter Condition Version = | typ.2| max. [Typ.| Max. [Typ.2)] Max. [Typ.@] max. [| Typ.2] Max. | Unit icc Dynamic Operating | CEs Vit MIL. JS} ] | | 325 | | 320] |315 | ]310|ma Current Outputs Open L} }t | | 295 | | 290] | 285 | | 280 (Both Ports Active) f = fuax'4) COML.|S]| | 300 | | 295 | | 290] | 285 | | 280 L] | 270] | 265 | | 260] | 255 | | 250 Isat Standby Current CE. and CEa2 WH IMIL. |S} | ] 25 | 85 | 25 | 80 | 25 | 80 | 25 | 75 [mA (Both Ports TTL f = fmaxl4) L] ] | 25] 75 | 25 | 7a | 25 | 70 | 25 | 65 Level Inputs) COM'L.|S| 25 | 80 | 25 | 75 | 25 | 75 | 25 | 70 | 25 | 70 L] 25} 70 | 25 | 65 | 25 | 65 | 25 | 60 | 25 | 60 IsB2 Standby Current CEL or CER> Vin MIL. Ss} ] | |] 220] }210] | 210] |200|mA (One Port TTL f = tmax'4) L} | | | 200 | | 190] | 190] |180 Level Inputs) Active Port COML.|S| | 200 | | 190 | |] 190] | 180 | | 7180 Outputs Open L} | 180} |} 170] | 170] | 160] | 160 IsB3 Full Standby Current | Both Ports CE.& |MIL. Ss} ] - 1 30 1 30 1 30 1 30 |mA (Both Ports CER > Vcc -02V L] |02] 10 [02] 10] 02] 10 [02 | 10 CMOS Level Inputs) | Vin>Vcc-0.2Vor|/COM'L.|S] 1 15 1 15 1 15 1 15 1 15 Vin < 0.2V, f = of) L}o2| 4 Jo2] 4 |o2!] 4 |o2] 4 Jo2] 4 IsB4 Full Standby Current | One Port CEL or MIL. Ss} ] | | 210 |] | 200} | 200] |190|mA (One Port All CER 2 Vcc - 0.2V CMOS Level Inputs) Vin > Vcc - 0.2V or L} | | ]190 | | 180] | 180 | | 170 VIN < 0.2V COM'L.JS} | 190 | ] 180 | | 180] | 170 | | 170 Active Port Outputs| Open, f = fuax'4) L} ]170] | 160 | | 160] | 150 |] | 150 NOTES: 1. 2 3. 4. Att = fax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRc, and using AC Test Conditions m . Veo = SV, TA = +25C. x" in part number indicates power rating (SA or LA). of input levels of GND to 3V. 0C to +70C temperature range only. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. At Vcc<2.0V input leakages are undefined. 2746 tbl 06 6.5IDT7133SA/LA, IDT7143SA/LA CMOS DUAL-PORT RAMS 32K (2K x 16-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES" (LA Version Only) Vic = 0.2V, VHe = Vcc - 0.2V IDT7133LA/DT7143LA Symbol Parameter Test Condition Min. Max. Unit VoR Vcc for Data Retention Voc = 2V 2.0 Vv IccorR Data Retention Current CE Vuc MIL. 4000 yA VIN VHC or VLC COM'L. _ 1500 tcor) Chip Deselect to Data Retention Time 0 - ns ta) Operation Recovery Time tac) ns NOTES: 2746 tol 07 1. Voce = 2V, TA = +25C 2. tac = Read Cycle Time 3. This parameter is guaranteed but not tested. LOW Vcc DATA RETENTION WAVEFORM DATA RETENTION MODE Vcc 4.5V \ Von22V / 4.5V tcoOR > tR == Vor 2746 drw 06 AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load See Figures 1,2 &3 2746 tbl 08 5V 5V 5V 12500 12500 270Q DATAouT DATAouT BUSY 775Q > 30pF* 775Q 5pF* 30pF* 2746 drw 06 Figure 1. Output Load Figure 2, Output Load Figure 3. BUSYOutput Load Including scope and jig {for tuz, tHz, twz, tow) (iIDT7133 only) *Including scope and jig 6.5 5IDT7133SA/LA, IDT7143SA/LA CMOS DUAL-PORT RAMS 32K (2K x 16-BiT) MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE IDT7133x25'] 1DT7133x35 | IDT7133x45 | 1DT7133x55 |IDT7133x70/90 IDT7143x259] 1DT7143x35 | 1DT7143x45 | IDT7143x55|IDT7143x70/90 Symbol Parameter { Min. | Max. | Min. |] Max. | Min. | Max. } Min. | Max.[ Min. | Max. [Unit READ CYCLE IRC Read Cycle Time 25 _ 35 45 ~ 55 | 70/90]; ns tAA Address Access Time _ 25 35 _ 45 55 | 70/90] ns tACE Chip Enable Access Time _ 25 _ 35 _ 45 55 | 70/80] ns {ADE Output Enabie Access Time _ 15 _ 20 _ 25 _ 30 | 40/40] ns tOH Output Hold from Address Change 0 _ 0 _ 0 0 _ o/o _ ns {Lz Output Low-Z Time! ) 0 0 0 5 | 55) | ns tHZ Output High-Z Timet": >} | 15 | | 20 | | 20 | | 20 | | 25/25] ns tPU Chip Enable to Power Up Time) 0 0 0 0 | vo} | ns teD Chip Disable to Power Down Time | | 50 | | 50 | 50 / 50 | 50/50] ns NOTES: 2746 tbl 09 1. Transition is measured +500mV fram low or high impedance voltage with load (Figures 1, 2, and 3). 2. 0C to +70C temperature range only. 3. This parameter is guaranteed but not tested. 4. "x" in part number indicates power rating (SA or LA). TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE")? 4 | tRC r| ADDRESS 3 <~ tAA _| tOH | tOH DATAQuT PREVIOUS DATA VALID DATA VALID oy 2746 drw 07 TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE" ) $$ $$ ACE ce A 4A0E THZ oC LS 4 THZ > DAT AUT VALID DATA tz P teu | }< tPD Ice CURRENT 50% oS Iss AC 50% 2746 drw 08 NOTES: 1. RiWis high for Read Cycles. 2. Device ts continuously enabled, CE = Vit. 3. Addresses valid prior to or coincident with CE transition LOW. 4, OF = Vi. 6.5 6IDT7133SA/LA, IDT7143SA/LA CMOS DUAL-PORT RAMS 32K (2K x 16-BIT) AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE MILITARY AND COMMERCIAL TEMPERATURE RANGES IDT7133x25 IDT7133x35 | IDT7133x45 | 1DT7133x55 1DT7143x25@ | 10T7143x35 | IDT7143x45 | 1DT7143x55 Symbol Parameter Min. | Max. | Min. | Max. | Min. ] Max. [ Min. | Max Unit WRITE CYCLE two Write Cycle Time'* 25 35 45 ~ 55 | 70900] ns tew Chip Enable to End-of-Write 20 _ 25 _ 30 ~ 40 | 50/0} ns taw Address Valid to End-of-Write 20 _ 25 -_ 30 _ 40 | 50/50] ns tas Address Set-up Time 0 _ 0 _ 0 _ 0 _- 0/0 _ ns twP Write Pulse Width 20 | {| 2 | [| 30 | | 40 | | so50] Tons twR Write Recovery Time 0 _ 0 _ 0 0 _ 0/0 _ ns tow Data Valid to End-of-Write 15 - 20 _- 20 _- 25 | 3030] ns tHZ Output High-Z Time": *) | 15 | | 20 | |] 20] | 20 | [2525] ns tDH Data Hold Time o;f{of]s5]-]5 ]] 55 7 [ns twz Write Enable to Output in High-Z"") | 15 | | 20 | | 20] | 20 | [e255] ns tow Output Active from End-of-Write*5) | 9 0 _ 5 _ 5 | 95 | | ns NOTES: 2746 thi 10 1. Transition is measured +500mV from low or high impedance voltage with load (Figures 1, 2, and 3). 2. C to +70C temperature range only. 3. This parameter is guaranteed but not tested. 4. For MASTER/SLAVE combination, twc = tBAA + tWR + twP. 5. The specification for tH must be met by the device supplying write data to the RAM under all operation conditions. Although tDH and tow values will vary over voltage and temperature, the actual tOH will always be smaller than the actual tow. "x" in part number indicates power rating (SA or LA). . Specified for OE at high (refer to Timing Waveform of Write Cycle, Note 7). 7. AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE) IDT7133x25) 1DT7133x35 | 1DT7133x45 | IDT7133x55 IDT7133x70/90 IDT7143x25(| 1D77143x35 | 1DT7143x45 | 1DT7143x55 IDT7143x70/90 Symbol Parameter [_Min. | Max. | Min.| Max. [ Min.] Max.] Min. ] Max.| Min. | Max. [Unit BUSY TIMING (For MASTER IDT7133) tBAA BUSY Access Time from Address _ 25 _ 35 _ 45 _ 50 | 55/55 | ns tBDA BUSY Disabie Time from Address _ 20 _ 30 = 40 ~ 40 | 45/45 J ns teac BUSY Access Time from Chip Enable _ 20 _ 25 _ 30 _ 35 135/35 | ns tepc BUSY Disable Time from Chip Enable _ 20 _ 20 _ 25 _ 30 |30/30 | ns twoD Write Pulse to Data Delay") _ 50 _ 60 _ 80 _ 80 |90/90 | ns toop Write Data Valid to Read Data Delay) 35 45 - 55 - 55 | 70/70 | ns tBDD BUSY Disable to Vaiid Data) [Notes] |Notesj |Notes| [Notes] |Notes | ns taps Arbitration Priority Set Up Time? 5 5 5 5 | 55 | Ins BUSY INPUT TIMING (For SLAVE !DT7143) twa Write to BUSY? oo} ]off{offofftTt{oo!l Ins twH Write Hold After BUSY) 20 | | 2 | [| 30 | | 30 | |sao30/ | ns twop Write Pulse to Data Delay) | 50; ]| 60 | | 80 | | 80 | Joao] ns tooo Write Data Valid to Read DataDelay | | 35 | | 45 | | 55 | [55 | lvor701 ns NOTES 2746 tot 11 1, 0C to +70C temperature range only. 2. Port-to-port delay through RAM calls from writing port to reading port, refer to TIMING WAVEFORM OF READ WITH BUSY (For Master 1DT7133) 3. tBDD is calculated parameter and is greater of 0, twoo - twe (actual) or toop - tow (actual). 4 To ensure that the earlier of the two ports wins. 5. To ensure that the write cycle is inhibited during contention. 6. To ensure that a write cycle is completed after contention. 7. Portto-port delay through RAM cells from writing port to reading port, refer to TIMING WAVEFORMOF READ WITH PORT-TO-PORT DELAY (For Slave IDT7143)" 8. "x" in part number indicates power rating (SA or LA). 6.5IDT7133SA/LA, 1DT7143SA/LA CMOS DUAL-PORT RAMS 32K (2K x 16-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE CYCLE NO. 1 (R/W CONTROLLED TIMING)"2: 3 7 two ADDRESS OE CE RW? DATAouT DATAIN WRITE CYCLE NO. 2 (CE CONTROLLED TIMING)? 3.5) twc 2746 dew 09 ADDRESS xK ~ttt tAW - CE * i~e tAS t tew Rw \ tWR a 2746 drw 10 tow tOH DATAN NOTES: 1. RAW or CE must be high during all address transitions. 2. A write occurs during the overlap (tew or twp) of a low CE and a low R/W. 3. twr is measured from the earlier of CE or R/W going high to the end-of-write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CE low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high impedance state. 6. Transition is measured +500mV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested. 7. \f Eis low during a R/W controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to turn off and data to be placed on the bus for the required tow. If OE is high during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tw. 8. R/W for either upper or lower byte. 6.5IDT7133SA/LA, IDT7143SA/LA CMOS DUAL-PORT RAMS 32K (2K x 16-BIT} MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ WITH BUSY: 2) (For MASTER IDT7133) twc ADDRR MATCH RWR DATAINR ADDRL BUSYL DATAOUTL NOTES: 2746 dew 11 1. To ensure that the earlier of the two ports wins. 2. Write cycle parameters should be adhered to in order to ensure proper writing. 3. Device is continuously enabled for both ports. 4. OE at LO for the reading port. TIMING WAVEFORM OF READ WITH PORT-TO-PORT DELAY" 25) (For SLAVE IDT7143) twc ADDRa MATCH RWaR DATANA ADDR. DAT/ouTL NOTES: 1. Assume BUSY input at HI for the writing port, and OE at LO for the reading port. 2. Write cycle parameters should be adhered ta in order to ensure proper writing. 3. Device is continuously enabled for both ports. 2746 drw 12 TIMING WAVEFORM OF WRITE WITH BUSY) twe _- 4] RW twe TWH NOTES: BUSY 1. tws only applies to slave, IDT7143. 2746 drw 13 6.5 9IDT7133SA/LA, IDT7143SA/LA CMOS DUAL-PORT RAMS 32K (2K x 16-BiT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF CONTENTION CYCLE NO. 1, CE ARBITRATION (For MASTER 1DT7133) CEL VALID FIRST: ADDRLANDA x ADDRESSES MATCH x CEL We TAPS CER a a tBAC peat tBDC BUSYA 2746 drw 14 CER VALID FIRST: ADDAANoR x ADDRESSES MATCH >< CER He tAPS CEL ~ js IBAC t {BDC BUSYL 2746 drw 15 TIMING WAVEFORM OF CONTENTION CYCLE NO. 2, ADDRESS VALID ARBITRATION 6 | (For MASTER IDT7133) LEFT ADDRESS VALID FIRST: tRc OR twe ADDR. ADDRESSES MATCH ADDRESSES BO NOT MATCH x TAPS ADDFR x< tBAA i_ tBDA BUSYR 2746 drw 16 RIGHT ADDRESS VALID FIRST: trac OR two ADDFR ADDRESSES MATCH ADDRESSES DO NOT MATCH x TAPS ADDR. >< tBAA 1BDA BUSYL a /) 2746 drw 17 NOTE: 1. CEL = CER = ViLIDT7133SA/LA, IDT7143SA/LA CMOS DUAL-PORT RAMS 32K (2K x 16-BiT) FUNCTIONAL DESCRIPTION: The 1|DT7133/43 provides two ports with separate control, address, and |/O pins that permit independent access for reads or writes to any location in memory. The devices have an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE high). When a port is enabled, access to the entire memory array is pemitted. Each port has its own Output Enable control (OE). In the read mode, the port's OE turns on the output drivers when set LOW. Non-contention READ/ WRITE conditions are illustrated in Table 1. ARBITRATION LOGIC, FUNCTIONAL DESCRIPTION: The arbitration logic will resolve an address match or a chip enable match down to 5ns minimum and determine which port has access. In all cases, an active BUSY flag will be set for the delayed port. The BUSY flags are provided for the situation when both ports simultaneously access the same memory location. When this situation occurs, on-chip arbitration logic will determine which port has access and sets the delayed port's BUSY flag. BUSY is set at speeds that permit the processor to hold the operation andits respective address and data. Itis important to note that a write operation is invalid for the port that has BUSY set LOW. The delayed port will have access when BUSY goes inactive. Contention occurs when both left and right ports are active and both addresses match. When this occurs, the on-chip arbitration logic determines access. Two modes of arbitration are provided: (1) if the addresses match and are valid before CE, on-chip control logic arbitrates between CEL and CER for MILITARY AND COMMERCIAL TEMPERATURE RANGES access; or (2) if the CEs are low before an address match, on- chip control logic arbitrates between the left and right addresses for access (refer to Table Il). In either mode of arbitration, the delayed port's BUSY flag is set and will reset when the port granted access completes its operation. DATA BUS WIDTH EXPANSION, MASTER/SLAVE DESCRIPTION: Expanding the data bus width to 32 bits or more in a Dual- Port RAM system implies that several chips will be active at the same time. If each chip includes a hardware arbitrator, and the addresses for each chip arrive at the same time, it is possible that one will activate its BUSYt while another activates its BUSYR signal. Both sides are now busy and the CPUs will await indefinately for their port to become free. To avoid the Busy Lock-Out problem, IDT has developed a MASTER/SLAVE approach where only one hardware arbitrator, in the MASTER, is used. The SLAVE has BUSY inputs which allow an interface to the MASTER with no external components and with a speed advantage over other systems. When expanding Dual-Port RAMs in width, the writing of the SLAVE RAMs mustbe delayed until after the BUSY input has settled. Otherwise, the SLAVE chip may begin a write cycle during a contention situation. Conversely, the write pulse must extend a hold time past BUSY to ensure that a write cycle takes place after the contention is resolved. This timing is inherent in all Dual-Port memory systems where more than one chip is active at the same time. The write pulse to the SLAVE should be delayed by the maximum arbitration time of the MASTER. If, then, a conten- tion occurs, the write to the SLAVE will be inhibited due to BUSY from the MASTER. TABLE | - NON-CONTENTION READ/WRITE CONTROL LEFT OR RIGHT PORT!) Rs | RWus] CE OE | VOo7 | Voss Function xX Xx H xX Zz Zz Port Disabled and in Power Down Mode, Isbz, IsB4 a= xX X H X Zz 4 CER = CEL = H, Power Down Mode, Isat or IsB3 L L L X | DATAIN | DATAIN Data on Lower Byte and Upper Byte Written into Memory) L H L L | DATAIn |DATAouT| Data on Lower Byte Written into Memory), Data in Memory Output on Upper Byte!) H L L L |DATAouT] DATAIN Data in Memory Output on Lower Byte), Data on Upper Byte Written into Memory! L H L H_ | DATAIN Zz Data on Lower Byte Written into Memory?) H L L H DATAIN | Data on Upper Byte Written into Memory H H L L bar DATAouT| Data in Memory Output on Lower Byte and Upper Byte H H L H Zz High Impedance Outputs NOTES: 2746 thl 12 1. Aoi - Ato # Aor - Aton 2. If BUSY = LOW, data is not written. 3. If BUSY = LOW, data may not be valid, see twoo and toop timing. 4. H= HIGH, L = LOW, X = Don't Care, Z = High Impedance, LB = Lower Byte, UB = Upper Bytle 11IDT7133SA/LA, IDT7143SA/LA CMOS DUAL-PORT RAMS 32K (2K x 16-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TABLE Il ARBITRATION! LEFT PORT RIGHT PORT FLAGS CEL Aot - A1oL CER Aor - Aor BUSYL BUSYr Function H x X Xx H H No Contention X xX H X H H No Contention L # AOR - A10R L # AoL - A10L H H No Contention ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH L LV5R L LV5R H L L-Port Wins L RV5L L RV5L L H R-Port Wins L Same L Same H L Arbitration Resolved L Same L Same L H Arbitration Resolved CE ARBITRATION WITH ADDRESS MATCH BEFORE CE LL5R = Aon - Aion LL5R = Ao - A10L H L L-Port Wins RLSL = Aor - A10R RLSL = AoL - AtoL L H R-Port Wins LW5R = Aor - A10R LW5R = AoL - A1aL H L Arbitration Resolved LW5R = Aor - Aior LW5R = Aoi - A1oL L H Arbitration Resolved NOTES: __ _ 2746 tol 13 1. H=HIGH, L = LOW, X = Dont Care LLSR = Left CE = LOW 2 5ns before Right CE LV5R = Left Address Valid = 5ns before right address RLSL = Right CE = LOW 2 Sns before Left CE RV5L = Right Address Valid 2 5ns before left address LWS5R = Left and Right CE = LOW within 5ns of each other Same = Left and Right Address match within 5ns of each other 32-BIT MASTER/SLAVE DUAL-PORT MEMORY SYSTEMS LEFT RIGHT RW R/W IDT7133 RW RW BUSY Busy MASTER Busy BUSY AA 45V +5V +4 ~|R/W pt7143. 0 RW __ 1 __ | l5usy SLAVE BUSY 2746 drw 18 NOTES: 1. No arbitration in |IDT7143 (SLAVE). BUSY-IN inhibits write in IDT7143 (SLAVE). 6.5 12IDT7133SA/LA, IDT71435A/LA CMOS DUAL-PORT RAMS 32K (2K x 16-BIT) ORDERING INFORMATION IDT XXXX XX XX x x Device Power Speed Package Process/ Type Temperature Range MILITARY AND COMMERCIAL TEMPERATURE RANGES Blank Commercial (0 C to +70 C) Military (-55 C to +125 C) Compliant to MIL-STD-883, Ciass B 68-pin PLCC (J68-1) 68-pin PGA (GU68-1)} 68-pin Flatplack (F68-1)} Commercial Only Speed in Nanoseconds Low Power Standard Power 32K (2K x 16-Bit) MASTER Dual-Port RAM 32K (2K x 16-Bit) SLAVE Dual-Port RAM 2746 drw 19 6.5