1
S2076QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
S2076
®
QUAD FIBRE CHANNEL TRANSCEIVER
DEVICE
SPECIFICATION
FEATURES
• Functionally compliant with ANSI X3T11 Fibre
Channel physical and transmission protocol
standards.
• 1062 MHz (Fibre Channel) operating rate
- 1/2 Rate Operation
• Quad Transmitter incorporating phase-locked
loop (PLL) clock synthesis from low speed
reference
• Quad Receiver PLL provides clock and data
recovery
• Internally series terminated TTL outputs
• Low-jitter serial PECL interface
• Local Loopback
• Interfaces with coax, twinax, or fiber optics
• Single +3.3V supply, 2.3 W Power dissipation
• Compact 23mm x 23mm 208 TBGA package
APPLICATIONS
High-speed data communications
• Switched networks
• Data broadcast environments
• Fibre Channel Switches
GENERAL DESCRIPTION
The S2076 quad transmitter and receiver chip is de-
signed to provide four channels of high-speed serial
data transmission over fiber optic or copper interfaces
conforming to the requirements of the ANSI X3T11
Fibre Channel specification. The chip runs at 1062.5
Mbps serial data rate with an associated 10-bit paral-
lel data word. The chip provides four separate trans-
ceivers which can be operated individually at slightly
different frequencies.
Each bi-directional channel provides parallel to serial
and serial to parallel conversion, clock generation
and recovery, and framing. The on-chip transmit PLL
synthesizes the high-speed clock from a low-speed
reference. The on-chip quad receive PLL is used for
clock recovery and data re-timing on the four inde-
pendent data inputs. The transmitter and receiver
each support differential PECL-compatible I/O for
copper or fiber optic component interfaces and pro-
vide excellent signal integrity. Local loopback mode
allows for system diagnostics. The chip requires a
3.3V power supply and dissipates approximately 2.3
watts.
Figure 1 shows the use of the S2064 and S2076 in a
Fibre Channel application. Figure 2 summarizes the
input/output signals of the device. Figures 3 and 4
show the transmit and receive block diagrams, re-
spectively.
Figure 1. Typical Quad Fibre Channel Application
MAC
(ASIC)
S2064
QUAD
FIBRE
CHANNEL
INTERFACE
MAC
(ASIC)
MAC
(ASIC)
MAC
(ASIC)
TO SERIAL BACKPLANE
S2076
FC INTERFACE SERIAL BP DRIVER
2
S2076 QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
Figure 2. S2076 Input/Output Diagram
REFCLK
TMODE
RATE
RESET
TCLKO
TXAP/N
TXBP/N
TXCP/N
TXDP/N
RXAP/N
RXBP/N
RXCP/N
RXDP/N
DINA[0:9]
10
DINB[0:9]
10
DINC[0:9]
10
DIND[0:9]
10
TBCA
TBCB
TBCC
TBCD
10
RBC1/0A
10
RBC1/0B
10
RBC1/0C
10
RBC1/0D
DOUTA[0:9]
DOUTB[0:9]
DOUTC[0:9]
DOUTD[0:9]
TESTMODE
CLKSEL
COM_DETA
COM_DETB
COM_DETC
COM_DETD
LPEN
CMODE
S2076
3
S2076QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
Figure 3. Transmitter Block Diagram
TMODE
10
DINA[0:9] 10
Shift
Reg
10
DINB[0:9] 10
Shift
Reg
TBCB
10
DINC[0:9] 10
Shift
Reg
TBCC
10
DIND[0:9] 10
Shift
Reg
TBCD
DIN PLL
10x/20x
REFCLK
CLKSEL
RATE REFCLK
TCLKO
FIFO
(input)
FIFO
(input)
FIFO
(input)
FIFO
(input)
TBCA
0 1
0 1
0 1
0 1
TXAP
TXAN
TXABP
TXBP
TXBN
TXBBP
TXCP
TXCN
TXCBP
TXDP
TXDN
TXDBP
4
S2076 QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
Figure 4. Receiver Block Diagram
DOUT CRU
Serial-
Parallel
DOUT CRU
Serial-
Parallel
DOUTA[0:9] RXAP
RXAN
RXBP
RXBN
DOUTB[0:9]
Q
FIFO
(output)
DOUT CRU
Serial-
Parallel
DOUTD[0:9] RXDP
RXDN
LPEN
DOUT CRU
Serial-
Parallel
DOUTC[0:9] RXCP
RXCN
TXDBP
TXCBP
TXBBP
TXABP
REFCLK
10
10
10
10
10
RBC1/0A 2
RBC1/0B 2
RBC1/0C 2
RBC1/0D
CMODE
FIFO
(output)
FIFO
(output)
FIFO
(output)
10
10
10
COM_DETA
COM_DETB
COM_DETC
COM_DETD
2
TMODE
RATE
5
S2076QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
TRANSMITTER DESCRIPTION
The transmitter section of the S2076 contains a
single PLL which is used to generate the serial rate
transmit clock for all transmitters. Transmitter
functionalities are shown schematically in Figure 3.
Four channels are provided with a variety of options
regarding input clocking and loopback. The transmit-
ters operate at 1.062 GHz, 10 or 20 times the refer-
ence clock frequency.
Data Input
The S2076 has been designed to simplify the paral-
lel interface data transfer and provides flexibility in
the clocking of parallel data. Prior implementations
of this function have either forced the user to syn-
chronize transmit data to the reference clock or to
provide the output clock as a reference to the PLL,
resulting in increased jitter at the serial interface.
The S2076 incorporates a unique FIFO structure
which enables the user to provide a “clean” refer-
ence source for the PLL and to accept a separate
external clock which is used exclusively to reliably
clock data into the device.
The S2076 also provides a system clock output,
TCLKO, which is derived from the internal VCO. The
frequency of this output is constant at the parallel
word rate, 1/10 the serial data rate, regardless of
whether the reference is provided at 1/10 or 1/20 the
serial data rate. This clock can be used by upstream
circuitry as a system clock. See Table 2.
Data to be input to the S2076 should be coded to
insure transition density and DC balance. Data is
input to each channel of the S2076 as a 10 bit wide
word. An input FIFO and a clock input, TBCx, are
provided for each channel of the S2076. The device
can operate in two different modes. The S2076 can
be configured to use either the TBCx (TBC MODE)
input or the REFCLK input (REFCLK MODE). Table
1 provides a summary of the input modes for the
S2076.
Operation in the TBC MODE makes it easier for us-
ers to meet the relatively narrow setup and hold time
window required by the parallel 10-bit interface. The
TBC signal is used to clock the data into an internal
holding register and the S2076 synchronizes its in-
ternal data flow to insure stable operation. REFCLK,
not TBCx, is used as the reference for the DIN PLL.
This insures minimum jitter on the high speed serial
data stream.
The TBC must be frequency locked to REFCLK, but
may have an arbitrary but fixed phase relationship.
Adjustment of internal timing of the S2076 is per-
formed during reset. Once synchronized, the S2076
can tolerate up to ±3ns of phase drift between TBC
and REFCLK.
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ETARLESKLC KLCFER ycneuqerF tuptuOlaireS etaR 0KLCT qerF
00 01/RDSspbM5.260101/RDS
01 02/RDSspbM5.260101/RDS
10 01/RDSspbM52.13501/RDS
11 02/RDSspbM52.13501/RDS
Table 1. Input Modes
Table 2. Operating Rates
REFCLK
S2076
106.25 MHz or 53.125 MHz
TBCx
DINx[0:9]
REF
OSCILLATOR
MAC
ASIC
TCLKO
PLL
Figure 5. DIN Clocking with TBC
Note that internal synchronization of FIFOs is performed upon
de-assertion of RESET.
Note: SDR = Serial Data Rate.
6
S2076 QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
Figure 5 demonstrates the flexibility afforded by the
S2076. A low jitter reference is provided directly to
the S2076 at either 1/10 or 1/20 the serial data rate.
This insures minimum jitter in the synthesized clock
used for serial data transmission. A system clock
output at the parallel word rate, TCLKO, is derived
from the PLL and provided to the upstream circuit as
a system clock. This clock can be buffered as re-
quired without concern about added delay. There is
no phase requirement placed upon TCLKO and the
TBCx clock, which is provided back to the S2076,
other than they remain within ±3ns of the phase rela-
tionship established at reset.
The S2076 also supports the traditional REFCLK
clocking found in Fibre Channel applications and is
illustrated in Figure 6.
Half Rate Operation
The S2076 supports full and 1/2 rate operation for all
modes of operation. When RATE is LOW, the S2076
serial data rate equals the VCO frequency. When
RATE is HIGH, the VCO is divided by 2 before being
provided to the chip. Thus the S2076 can support
Fibre Channel and serial backplane functions at both
full and 1/2 the VCO rate.
Parallel-to-Serial Conversion
The 10-bit parallel data handled by the S2076 device
should be from a DC-balanced encoding scheme,
such as the 8B/10B transmission code, in which in-
formation to be transmitted is encoded, 8 bits at a
time, into a 10-bit transmission character and must
be compliant with ANSI X3.230 FC-PH (Fibre Chan-
nel Physical and Signaling Interface).
The 8B/10B transmission code includes serial en-
coding and decoding rules, special characters, and
error control. Information is encoded, 8 bits at a time,
into a 10 bit transmission character. The characters
defined by this code ensure that short run lengths
and enough transitions are present in the serial bit
stream to make clock recovery possible at the re-
ceiver. The encoding also greatly increases the like-
lihood of detecting any single or multiple errors that
might occur during the transmission and reception of
data1.
Table 3 identifies the mapping of the 8B/10B charac-
ters to the data inputs of the S2076. The S2076 will
serialize the parallel data for each channel and will
transmit bit “a” or DIN[0] first.
Frequency Synthesizer (PLL)
The S2076 synthesizes a serial transmit clock from
the reference signal provided. The S2076 will obtain
phase and frequency lock within 2500 bit times after
the start of receiving reference clock inputs. Reliable
locking of the transmit PLL is assured, but a lock-
detect output is NOT provided.
etyBataD
ro]9:0[NID ]9:0[TUOD 0123456789
.rper.hplaB01/B8 abcdeifghj
REFCLK
S2076
TBCx
DINx[0:9]
REF
OSCILLATOR
MAC
ASIC
TCLKO
PLL
106.25 MHz
Figure 6. FC DIN Clocking with REFCLK
Table 3. Data to 8B/10B Alphabetic Representation
1. A.X. Widner and P.A. Franaszek, "A Byte-Oriented DC Bal-
anced (0,4) 8B/10B Transmission Code," IBM Research Report
RC9391, May 1982.
7
S2076QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
Test Functions
The S2076 can be configured for factory test to aid
in functional testing of the device. When in the test
mode, the internal transmit and receive voltage-con-
trolled oscillator (VCO) is bypassed and the refer-
ence clock substituted. This allows full functional
testing of the digital portion of the chip or bypassing
the internal synthesized clock with an external clock
source. (See the section Other Operating Modes.)
Reference Clock Input
The reference clock input must be supplied with a
low-jitter clock source. All reference clocks in a sys-
tem must be within 200 ppm of each other to insure
that the clock recovery units can lock to the serial
data.
The frequency of the reference clock must be either
1/10 the serial data rate, CLKSEL = 0, or 1/20 the
serial data rate, CLKSEL = 1. Note that in both
cases, the frequency of the parallel word rate output,
TCLKO, is constant at 1/10 the serial data rate.
Serial Data Outputs
The S2076 provides LVPECL level serial outputs.
Each high speed output should be provided with a
resistor to VSS (Gnd) near the device. A value of
4.5K Ω provides optimal performance with minimum
impact on power dissipation. The resistance may be
as low as 450 Ω, but will dissipate additional power
with no substantive performance improvement.
Transmit FIFO Initialization
The transmit FIFO must be initialized after stable
delivery of data and TBC to the parallel interface,
and before entering the normal operational state of
the circuit. FIFO initialization is performed upon the
de-assertion of the RESET signal. The DIN FIFO is
automatically reset upon power up immediately after
the DIN PLL obtains stable frequency lock. If the
circuit has not reached steady state timing at this
point, then the user must initialize by asserting the
RESET signal. The TCLKO output will operate nor-
mally even when RESET is asserted and is available
for use as an upstream clock source.
8
S2076 QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
RECEIVER DESCRIPTION
Each receiver channel is designed to implement the
ANSI X3T11 Fibre Channel specification. A block
diagram showing the basic function is provided in
Figure 4.
Whenever a signal is present, the receiver attempts
to recover the serial clock from the received data
stream. After acquiring bit synchronization, the
S2076 searches the serial bit stream for the occur-
rence of a K28.5 character on which to perform word
synchronization. Once synchronization on both bit
and word boundaries is achieved, the receiver pro-
vides the word-aligned data on its parallel outputs.
Data Input
A differential input receiver is provided for each
channel of the S2076. Each channel has a loopback
mode in which the serial data from the transmitter
replaces external serial data. The loopback function
for all four channels is controlled by the loopback
enable signal, LPEN.
The high speed serial inputs to the S2076 are inter-
nally biased to VDD-1.3V. This facilities AC-coupling
of the differential inputs and termination with a
single differential termination.
Clock Recovery Function
Clock recovery is provided for each channel of the
S2076. The receiver PLL has been optimized for the
needs of Fibre Channel systems. A simple state ma-
chine in the clock recovery macro decides whether
to acquire lock from the serial data input or from the
reference clock. The decision is based upon the fre-
quency and run length of the serial data inputs.
The run-length requirements insure that the S2076
will respond appropriately and quickly to a loss of
signal. The run-length checker looks for a minimum
of 120 consecutive ones or zeros. The checking is
done in parallel, thus 12 parallel words are exam-
ined.
An off-frequency detection circuit in the S2076 moni-
tors the receiver VCO frequency to insure that the
input signal is at a valid data rate. The data stream
must be within 200 ppm of the appropriate rate for
reliable locking of the CRU to the data stream.
If both the off-frequency test and the run-length test
are satisfied, the CRU will attempt to lock to the
incoming data. Note that if the run length test is sat-
isfied due to noise on the inputs, and no signal is
present, the receiver VCO will maintain frequency
accuracy to within 100 ppm of the target rate as
determined by the REFCLK.
In any transfer of PLL control from the serial data to
the reference clock, the RBC1/0x outputs remain
phase continuous and glitch free, assuring the integ-
rity of downstream clocking.
If at any time, the frequency or run length checks are
violated, the state machine forces the VCO to lock to
the reference clock. This is required to guarantee
that the VCO maintains the correct frequency in the
absence of data.
Reference Clock Input
The reference clock must be provided from a low
jitter clock source. The frequency of the received
data stream (divided by 10 or 20) must be within 200
ppm of the reference clock to insure reliable locking
of the receiver PLL. A single reference clock is pro-
vided to both the transmitter and the receiver of the
S2076.
Serial-to-Parallel Conversion
Once bit synchronization has been attained by the
S2076 CRU, the S2076 must synchronize to the 10
bit word boundary. Word synchronization in the
S2076 is accomplished by detecting and aligning to
the 8B/10B K28.5 codeword. The S2076 will detect
and byte-align to either polarity of the K28.5. Each
channel of the S2076 will detect and align to a K28.5
anywhere in the data stream. The presence of a
K28.5 is indicated for each channel by the assertion
of the COM_DETx (Comma Detect) signal.
Data Output
Data is output on the DOUTx[0:9] outputs. The
COM_DETx signal is used to indicate the reception
of a valid K28.5 character and is driven concurrent
with the K28.5 character on the DOUTx[0:9] outputs.
The S2076 TTL outputs are optimized to drive 65Ω
line impedences. Internal source matching provides
good performance on unterminated lines of reason-
able length.
9
S2076QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
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edoMkcolCflaH0zHM521.35
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Table 4. Output Clock Modes
Parallel Output Clock Rate
Two output clock modes are supported. When
CMODE is HIGH, a complementary TTL clock at the
data rate is provided on the RBC1/0x outputs. Data
should be clocked on the rising edge of RBC1x.
When CMODE is LOW, the S2076 outputs a
complementary TTL clock at 1/2 the data rate in
compliance with the Fibre Channel 10 Bit Interface
Specification. Data should be latched on the rising
edge of RBC1x and the rising edge of RBC0x.
If consecutive K28.5 characters are received, the
S2076 RBC1/0x clock operates without glitches or
loss of cycles.
OTHER OPERATING MODES
Loopback Mode
When loopback mode is enabled, the serial data
from the transmitter is provided to the serial input of
the receiver. Loopback mode can be simultaneously
enabled for all four channels using the loopback-en-
able input, LPEN.
The loopback mode provides the ability to perform
system diagnostics and off-line testing of the inter-
face to guarantee the integrity of the serial channel
before enabling the transmission medium. Loopback
is enabled when LPEN = 1.
Note that the high speed outputs are disabled during
loopback operation.
Test Modes
The RESET pin is used to initialize the Transmit
FIFOs and must be asserted (LOW) prior to entering
the normal operational state (see section Transmit
FIFO Initialization). Note that Reset does not disable
the TCLKO output unless the TBCB input is HIGH.
Operating Frequency Rate
The S2076 is designed to operate at the Fibre Chan-
nel rate of 1.062 GHz.
output
disabled
CRU
CSU
Figure 7. S2076 Diagnostic Loopback Operation
10
S2076 QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
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9BNID 8BNID 7BNID 6BNID 5BNID 4BNID 3BNID 2BNID 1BNID 0BNID
LTTI 61R 61T 51R 41P 51T 41R 71U 61U 31P 41T
nidekcolcsisubsihtnoatadlellaraP.BlennahCrofataDtimsnarT ).1elbaTeeS(.KLCFERroBCBTfoegdegnisirehtno
BCBTLTTI 31Rdesusilangissiht,hgiHsiEDOMTnehW.BkcolCetyBtimsnarT ,woLsiEDOMTnehW.6702Sehtotni]9:0[BNIDnoataDkcolcot .derongisiBCBT
9CNID 8CNID 7CNID 6CNID 5CNID 4CNID 3CNID 2CNID 1CNID 0CNID
LTTI 71N 71P 51M 61N 41M 71R 61P 51N 71T 41N
nidekcolcsisubsihtnoatadlellaraP.ClennahCrofataDtimsnarT ).1elbaTeeS(.KLCFERroCCBTfoegdegnisirehtno
CCBTLTTI 51Pdesusilangissiht,hgiHsiEDOMTnehW.CkcolCetyBtimsnarT ,woLsiEDOMTnehW.6702Sehtotni]9:0[CNIDnoataDkcolcot .derongisiCCBT
Table 5. Transmitter Input Signals Assignment and Description
Note: All TTL inputs except REFCLK have internal pull-up networks.
11
S2076QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
Table 5. Transmitter Input Signals Assignment and Description (Continued)
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9DNID 8DNID 7DNID 6DNID 5DNID 4DNID 3DNID 2DNID 1DNID 0DNID
LTTI61J 71K 71L 61K 51K 41K 71M 61L 61M 51L
nidekcolcsisubsihtnoatadlellaraP.DlennahCrofataDtimsnarT ).1elbaTeeS(.KLCFERroDCBTfoegdegnisirehtno
DCBTLTTI41Ldesusilangissiht,hgiHsiEDOMTnehW.DkcolCetyBtimsnarT ,woLsiEDOMTnehW.6702Sehtotni]9:0[DNIDnoataDkcolcot .derongisiDCBT
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PAXT NAXT .ffiD LCEPVL O71A 71B .AlennahCrofstuptuolairesdeepshgiH
PBXT NBXT .ffiD LCEPVL O71C 71D .BlennahCrofstuptuolairesdeepshgiH
PCXT NCXT .ffiD LCEPVL O61F 71E .ClennahCrofstuptuolairesdeepshgiH
PDXT NDXT .ffiD LCEPVL O71F 71G .DlennahCrofstuptuolairesdeepshgiH
OKLCTLTTO41JrofdedivorpsikcolcsihT.etaratadlellarapehttakcolCtuptuOLTT .yrtiucricmaerts-puybesu
Table 6. Transmitter Output Signals Assignment and Description
Note: All TTL inputs except REFCLK have internal pull-up networks.
12
S2076 QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
Table 7. Receiver Output Signals Assignment and Description
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9ATUOD 8ATUOD 7ATUOD 6ATUOD 5ATUOD 4ATUOD 3ATUOD 2ATUOD 1ATUOD 0ATUOD
LTTO1G3G1J3J2J1H2H3H1F2G
dilavsisubsihtnoatadlellaraP.stuptuOataDrevieceRAlennahC ehtnodilavdnaedomkcolcllufniA1CBRfoegdegnisirehtno .edomkcolcflahniA0CBRdnaA1CBRhtobfoegdegnisir
ATED_MOCLTTO2FatahtsetacidnituptuosihtnohgiHA.tceteDammoCAlennahC atadlellarapehtnotneserpsidnadetcetedneebsah5.82Kdilav .]9:0[ATUODstuptuo
A1CBR A0CBR LTTO2K1K dna]9:0[ATUOD,atadeviecerlellaraP.skcolCetyBevieceR llufninehwA1CBRfoegdegnisirehtnodilaveraATED_MOC dnaA1CBRhtobfoegdegnisirehtnodilavdnaedomkcolc .edomkcolcflahniA0CBR
9BTUOD 8BTUOD 7BTUOD 6BTUOD 5BTUOD 4BTUOD 3BTUOD 2BTUOD 1BTUOD 0BTUOD
LTTO3K2P1R1P3M2N2M1N2L1M
dilavsisubsihtnoatadlellaraP.stuptuOataDrevieceRBlennahC ehtnodilavdnaedomkcolcllufniB1CBRfoegdegnisirehtno .edomkcolcflahniB0CBRdnaB1CBRhtobfoegdegnisir
BTED_MOCLTTO1LatahtsetacidnituptuosihtnohgiHA.tceteDammoCBlennahC atadlellarapehtnotneserpsidnadetcetedneebsah5.82Kdilav .]9:0[BTUODstuptuo
B1CBR B0CBR LTTO1U1T dna]9:0[BTUOD,atadeviecerlellaraP.skcolCetyBevieceR llufninehwB1CBRfoegdegnisirehtnodilaveraBTED_MOC dnaB1CBRhtobfoegdegnisirehtnodilavdnaedomkcolc .edomkcolcflahniB0CBR
9CTUOD 8CTUOD 7CTUOD 6CTUOD 5CTUOD 4CTUOD 3CTUOD 2CTUOD 1CTUOD 0CTUOD
LTTO2T3P7R6R5T3U4T5R2U3T
sisubsihtnoatadlellaraP.stuptuOataDrevieceRClennahC nodilavdnaedomkcolcllufniC1CBRfoegdegnisirehtnodilav .edomkcolcflahniC0CBRdnaC1CBRhtobfoegdegnisireht
13
S2076QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
Table 7. Receiver Output Signals Assignment and Description (Continued)
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CTED_MOCLTTO2RatahtsetacidnituptuosihtnohgiHA.tceteDammoCClennahC atadlellarapehtnotneserpsidnadetcetedneebsah5.82Kdilav .]9:0[CTUODstuptuo
C1CBR C0CBR LTTO5U4U dna]9:0[CTUOD,atadeviecerlellaraP.skcolCetyBevieceR llufninehwC1CBRfoegdegnisirehtnodilaveraCTED_MOC dnaC1CBRhtobfoegdegnisirehtnodilavdnaedomkcolc .edomkcolcflahniC0CBR
9DTUOD 8DTUOD 7DTUOD 6DTUOD 5DTUOD 4DTUOD 3DTUOD 2DTUOD 1DTUOD 0DTUOD
LTTO6T7T 11U 01R 9U9R9T8U7U8T
sisubsihtnoatadlellaraP.stuptuOataDrevieceRDlennahC nodilavdnaedomkcolcllufniD1CBRfoegdegnisirehtnodilav .edomkcolcflahniD0CBRdnaD1CBRhtobfoegdegnisireht
DTED_MOCLTTO6UatahtsetacidnituptuosihtnohgiHA.tceteDammoCDlennahC atadlellarapehtnotneserpsidnadetcetedneebsah5.82Kdilav .]9:0[DTUODstuptuo
D1CBR D0CBR LTTO01T 01U dna]9:0[DTUOD,atadeviecerlellaraP.skcolCetyBevieceR llufninehwD1CBRfoegdegnisirehtnodilaveraDTED_MOC dnaD1CBRhtobfoegdegnisirehtnodilavdnaedomkcolc .edomkcolcflahniD0CBR
14
S2076 QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
Table 8. Receiver Input Signals Assignment and Description
emaNniPleveLO/I#niPnoitpircseD
PAXR NAXR .ffiD LCEPVL I4D3B ehtsiPAXR.AlennahcrofstupnielbitapmocLCEPVLlaitnereffiD -DDVotdesaibyllanretnI.evitagenehtsiNAXR,tupnievitisop .snoitacilppadelpuocCArofV3.1
PBXR NBXR .ffiD LCEPVL I6C5B ehtsiPBXR.BlennahcrofstupnielbitapmocLCEPVLlaitnereffiD -DDVotdesaibyllanretnI.evitagenehtsiNBXR,tupnievitisop .snoitacilppadelpuocCArofV3.1
PCXR NCXR .ffiD LCEPVL I8A9A ehtsiPCXR.ClennahcrofstupnielbitapmocLCEPVLlaitnereffiD -DDVotdesaibyllanretnI.evitagenehtsiNCXR,tupnievitisop .snoitacilppadelpuocCArofV3.1
PDXR NDXR .ffiD LCEPVL I11C 21B ehtsiPDXR.DlennahcrofstupnielbitapmocLCEPVLlaitnereffiD -DDVotdesaibyllanretnI.evitagenehtsiNDXR,tupnievitisop .snoitacilppadelpuocCArofV3.1
Table 9. Receiver Control Signals Assignment and Description
emaNniPleveLO/I#niPnoitpircseD
NEPLLTTI 41Dehtsilennahchcaerofecruostupni,woLnehW.elbanEkcabpooL hcaeroftuptuolaireseht,hgiHnehW.tuptuolairesdeepshgih .tupnistiotkcabdepoolsilennahc
EDOMCLTTI2Cskcolctuptuolellarapeht,woLnehW.lortnoCedoMkcolC lellarapeht,hgiHnehW.etaratadeht2/1slauqeetar)x0/1CBR( .etaratadehtotlauqesietar)x0/1CBR(skcolctuptuo
Note: All TTL inputs except REFCLK have internal pull-up networks.
15
S2076QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
Note: All TTL inputs except REFCLK have internal pull-up networks.
emaNniPleveLO/I#niPnoitpircseD
EDOMTSETLTTI4E.noitarepolamronrofwoLpeeK.lortnoCedoMtseT
EDOMTLTTI 31BdesusiKLCFER,woLsiEDOMTnehW.lortnoCedoMtimsnarT siEDOMTnehW.6702Sehtotni]9:0[xNIDnoatadkcolcot .6702SehtotniatadkcolcotdesusixCBT,hgiH
LESKLCLTTI 21CehtrofLLPehtserugifnoclangissihT.tupnItceleSKLCFER KLCFEReht,0=LESKLCnehW.ycneuqerfKLCFERetairporppa nehW.etardrowlellarapehtlauqedluohsycneuqerf lellarapeht2/1ebdluohsycneuqerfKLCFEReht,1=LESKLC .etaratad
KLCFERLTTI 71HycneuqerfdnaOCVtimsnartehtrofdesusikcolCecnerefeR .atadlairesreviecerehtmorfderevocerkcolcehtrofkcehc
TESERLTTI 51CdecrofsiLLPreviecerehT.tesernidlehsi6702Seht,woLnehW egdegnisirehtnodezilaitinierasOFIFehT.KLCFERehtotkcolot .yllamronsetarepo6702Seht,hgiHnehW.TESERfo
ETARLTTI 21Dlauqeetartuptuolairesehthtiwsetarepo6702Seht,woLnehW ehthtiwsetarepo6702Seht,hgiHnehW.ycneuqerfOCVehtot .snoitcnufllarof2ybdedividyllanretniOCV
Table 10. S2076 Mode Control Signal Assignment and Description
16
S2076 QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
emaNniP.ytQ#niPnoitpircseD
ADDV5 ,61A,31A,6A,1A 8C .esionwol)DDV(rewoPgolanA
ASSV5 ,4C,51B,8B,7B 11D .)SSV(dnuorGgolanA
DDV5 ,6B,4B,51A,21A 9D .)DDV(yrtiucricdeepshgihrofrewoP
SSV BUSSSV 01,11A,7A,4A,2A ,41B,01B,41A 8D,6D,31C
.)SSV(yrtiucricdeepshgihrofdnuorG
RWPLCEP2 61G,51E.)DDV(rewoPLCEP
DNGLCEP2 61H,61C.)SSV(dnuorGLCEP
RWPGID6 ,71J,3E,2B,1B 9P,4L .)DDV(rewoPyrtiucriceroC
DNGGID8 ,4F,2D,3C,1C 3R,01P,4N,51J .)SSV(dnuorGyrtiucriceroC
RWPLTT8 ,4K,4H,4G,1E 8P,7P,5P,3N .)DDV(O/ILTTrofrewoP
DNGLTT01,4J,3F,2E,1D ,6P,4P,4M,3L 8R,4R
.)SSV(O/ILTTrofdnuorG
RWP9 ,61B,11B,9B,3A ,7D,3D,9C,5C 01D
rewoP
DNG51,7C,01A,5A ,51D,5D,01C ,61E,41E,61D ,41G,51F,41F 51H,41H,51G
dnuorG
1PAC 2PAC 231D 41C .roticapacretlifpoollanretxerofsniP
Table 11. Power and Ground Signals Assignment and Description
17
S2076QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
Figure 8. S2076 Pinout (Bottom View)
A B C D E F G H J K L M N P R T U
1ADDVRWPGIDDNGGIDDNGLTTRWPLTT1ATUOD9ATUOD4ATUOD7ATUODA0CBR _MOC BTED 0BTUOD2BTUOD6BTUOD7BTUODB0CBRB1CBR
2BUSSSVRWPGIDEDOMCDNGGIDDNGLTT _MOC ATED 0ATUOD3ATUOD5ATUODA1CBR1BTUOD3BTUOD4BTUOD8BTUOD _MOC CTED 9CTUOD1CTUOD
3RWPNAXRDNGGIDRWPRWPGIDDNGLTT8ATUOD2ATUOD6ATUOD9BTUODDNGLTT5BTUODRWPLTT8CTUODDNGGID0CTUOD4CTUOD
4SSVDDVASSVPAXR TSET EDOM DNGGIDRWPLTTRWPLTTDNGLTTRWPLTTRWPGIDDNGLTTDNGGIDDNGLTTDNGLTT3CTUODC0CBR
5DNGNBXRRWPDNG RWPLTT2CTUOD5CTUODC1CBR
6ADDVDDVPBXRSSV DNGLTT6CTUOD9DTUOD _MOC DTED
7BUSSSVASSVDNGRWP RWPLTT7CTUOD8DTUOD1DTUOD
8PCXRASSVADDVBUSSSV RWPLTTDNGLTT0DTUOD2DTUOD
9NCXRRWPRWPDDV RWPGID4DTUOD3DTUOD5DTUOD
01 DNGSSVDNGRWP DNGGID6DTUODD1CBRD0CBR
11 SSVRWPPDXRASSV 2ANID1ANID0ANID7DTUOD
21 DDVNDXRLESKLCETAR 7ANID6ANID4ANIDACBT
31 ADDVEDOMTBUSSSV1PAC 1BNIDBCBT5ANID3ANID
41 BUSSSVSSV2PACNEPLDNGDNGDNGDNGOKLCT4DNIDDCBT5CNID0CNID6BNID4BNID0BNID8ANID
51 DDVASSVTESERDNG LCEP RWP DNGDNGDNGDNGGID5DNID0DNID7CNID2CNIDCCBT7BNID5BNID9ANID
61 ADDVRWPDNGLCEPDNGDNGPCXT LCEP RWP DNGLCEP9DNID6DNID2DNID1DNID6CNID3CNID9BNID8BNID2BNID
71 PAXTNAXTPBXTNBXTNCXTPDXTNDXTKLCFERRWPGID8DNID7DNID3DNID9CNID8CNID4CNID1CNID3BNID
18
S2076 QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
Figure 9. S2076 Pinout (Top View)
U T R P N M L K J H G F E D C B A
B1CBRB0CBR7BTUOD6BTUOD2BTUOD0BTUOD _MOC BTED A0CBR7ATUOD4ATUOD9ATUOD1ATUODRWPLTTDNGLTTDNGGIDRWPGIDADDV 1
1CTUOD9CTUOD _MOC CTED 8BTUOD4BTUOD3BTUOD1BTUODA1CBR5ATUOD3ATUOD0ATUOD _MOC ATED DNGLTTDNGGIDEDOMCRWPGIDBUSSSV 2
4CTUOD0CTUODDNGGID8CTUODRWPLTT5BTUODDNGLTT9BTUOD6ATUOD2ATUOD8ATUODDNGLTTRWPGIDRWPDNGGIDNAXRRWP 3
C0CBR3CTUODDNGLTTDNGLTTDNGGIDDNGLTTRWPGIDRWPLTTDNGLTTRWPLTTRWPLTTDNGGID TSET EDOM PAXRASSVDDVSSV 4
C1CBR5CTUOD2CTUODRWPLTT DNGRWPNBXRDNG 5
_MOC DTED 9DTUOD6CTUODDNGLTT SSVPBXRDDVADDV 6
1DTUOD8DTUOD7CTUODRWPLTT RWPDNGASSVBUSSSV 7
2DTUOD0DTUODDNGLTTRWPLTT BUSSSVADDVASSVPCXR 8
5DTUOD3DTUOD4DTUODRWPGID DDVRWPRWPNCXR 9
D0CBRD1CBR6DTUODDNGGID RWPDNGSSVDNG 01
7DTUOD0ANID1ANID2ANID ASSVPDXRRWPSSV 11
ACBT4ANID6ANID7ANID ETARLESKLCNDXRDDV 21
3ANID5ANIDBCBT1BNID 1PACBUSSSVEDOMTADDV 31
8ANID0BNID4BNID6BNID0CNID5CNIDDCBT4DNIDOKLCTDNGDNGDNGDNGNEPL2PACSSVBUSSSV 41
9ANID5BNID7BNIDCCBT2CNID7CNID0DNID5DNIDDNGGIDDNGDNGDNG LCEP RWP DNGTESERASSVDDV 51
2BNID8BNID9BNID3CNID6CNID1DNID2DNID6DNID9DNIDDNGLCEP LCEP RWP PCXTDNGDNGDNGLCEPRWPADDV 61
3BNID1CNID4CNID8CNID9CNID3DNID7DNID8DNIDRWPGIDKLCFERNDXTPDXTNCXTNBXTPBXTNAXTPAXT 71
19
S2076QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
Figure 10. 208 TBGA Package
eciveD Θ)riAllitS(aj Θcj
6702SW/C˚7.71W/C˚5.3
Thermal Management
20
S2076 QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
Figure 11. Transmitter Timing (REFCLK Mode, TMODE = 0)
Table 12. S2076 Transmitter Timing (REFCLK Mode, TMODE = 0)
Figure 12. Transmitter Timing (TBC Mode, TMODE = 1)
Table 13. S2076 Transmitter Timing (TBC Mode, TMODE = 0)
REFCLK
DINx[0:9]
T
1
T
2
SERIAL DATA OUT
TBCx
DINx[0:9]
T
1
T
2
SERIAL DATA OUT
sretemaraPnoitpircseDniMxaMstinUsnoitidnoC
T
1
KLCFER.t.r.wputeSataD5.0-sn.1etoNeeS
T
2
KLCFER.t.r.wdloHataD3.1-sn
sretemaraPnoitpircseDniMxaMstinUsnoitidnoC
T
1
CBT.t.r.wputeSataD0.1-sn.1etoNeeS
T
2
CBT.t.r.wdloHataD5.0-sn
1. All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or
output data levels (.8V or 2.0V).
1. All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or
output data levels (.8V or 2.0V).
21
S2076QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
sretemaraPnoitpircseDniMxaMstinUsnoitidnoC
T
3
KLCFER.t.r.wOKLCT25.7sn
elcyCytuDOKLCT%04%06%
Note: Measurements are made at 1.4V level of clocks.
Table 15. S2076 Transmitter (TCLKO Timing)
REFCLK
T3
TCLKO
Figure 13. TCLKO Timing
sretemaraPnoitpircseDniMxaMstinUsnoitidnoC
T
RDS
T,
FDS
llaFdnaesiRataDlaireS-003spelpmasnodetset,%08-%02 k5.4.sisab Ω.dnuorgot
T
J
rettijlatottuptuOataDlaireS )p-p( -32.0IU
noderusaem,kaep-ot-kaeP htiwderusaeM.sisabelpmas 2ro5.82K±
7
tanrettap1-
.zHG260.1
T
JD
tuptuOataDlaireS )p-p(rettijcitsinimreted -80.0IUanodetset,kaep-ot-kaeP htiwderusaeM.sisabelpmas .zHG260.1tanrettap5.82K±
Table 14. S2076 Transmitter Timing
22
S2076 QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
Figure 14. Receiver Timing (Full Clock Mode, CMODE = 1)
Table 16. S2076 Receiver Timing (Full Clock Mode, CMODE = 1)
Figure 15. Receiver Timing (Half Clock Mode, CMODE = 0)
Table 17. S2076 Receiver Timing (Half Clock Mode, CMODE = 0)
RBC0x
DOUTx[0:9],
COM_DETx
SERIAL DATA IN
T
4
T
5
RBC1x
1. All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or
output data levels (.8V or 2.0V).
RBC0x
DOUTx[0:9],
COM_DETx
SERIAL DATA IN
RBC1x
T
6
T
7
T
8
T
6
T
7
sretemaraPnoitpircseDniMxaMstinUsnoitidnoC
T
4
x1CBR.t.r.wputeSataD5.3-sn.1etoNeeS
T
5
x1CBR.t.r.wdloHataD0.2-sn
elcyCytuDx0/1CBR0406%
sretemaraPnoitpircseDniMxaMstinUsnoitidnoC
T
6
x0/1CBR.t.r.wputeSataD5.3-sn.1etoNeeS
T
7
x0/1CBR.t.r.wdloHataD0.2-sn
T
8
otesirx1CBRmorfemiT esirx0CBR 3.94.01sn
elcyCytuDx0/1CBR0406%
1. All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or
output data levels (.8V or 2.0V).
23
S2076QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
sretemaraPnoitpircseDniMxaMstinUsnoitidnoC
T
RCR
T,
FCR
emiTllaFdnaesiR0CBR,1CBR-4.2sneeS.V0.2+otV8.+derusaeM .71erugiF
T
RD
T,
FD
emiTllaFdnaesiRtuptuOataD0.3sneeS.V0.2+otV8.+derusaeM .61erugiF
T
KCOL
)ycneuqerF( emiTkcoLnoitisiuqcAycneuqerF )spbG260.1()kcoLfossoL( -571sµ.purewopretfA
T
JDF
rettiJtnednepeDycneuqerF ecnareloT 01.0-IU.11T3XISNAnideificepssA
T
JD
ecnareloTrettiJtupnIcitsinimreteD83.0-IU.11T3XISNAnideificepssA
T
JR
ecnareloTrettiJtupnImodnaR22.0-IU.11T3XISNAnideificepssA
T
J
ecnareloTrettiJtupnIlatoT7.0-IU.11T3XISNAnideificepssA
Table 18. S2076 Receiver Timing
24
S2076 QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
Table 19. Absolute Maximum Ratings
Table 20. Recommended Operating Conditions
Table 21. Reference Clock Requirements
retemaraPniMpyTxaMstinU
saiBrednUerutarepmeTtneibmA007C˚
saiBrednUerutarepmeTnoitcnuJ031C˚
ottcepserhtiwniprewopynanoegatloV SSV/DNG 31.33.374.3V
niPtupnILTTynanoegatloV074.3V
niPtupnILCEPynanoegatloV DDV V2- DDVV
sretemaraPnoitpircseDniMxaMstinUsnoitidnoC
TFecnareloTycneuqerF001-001+mpp
DT
2-1
yrtemmyS0406% .tp%05taelcyCytuD
T
RCR
T,
FCR
emiTllaFdnaesiRKLCFER2sn.%08-%02
—rettiJ08sp.eyeatad%77,kaeP-ot-kaeP
retemaraPniMpyTxaMstinU
saiBrednUerutarepmeTesaC55-521C˚
saiBrednUerutarepmeTnoitcnuJ55-051C˚
erutarepmeTegarotS56-051C˚
DNGottcepseRhtiwDDVnoegatloV5.0-0.7+V
niPtupnILTTynanoegatloV5.0-74.3V
niPtupnILCEPynanoegatloV0DDVV
tnerruCkniStuptuOLTT8Am
tnerruCecruoStuptuOLTT8Am
tnerruCecruoStuptuOLCEPdeepShgiH05Am
O/ILTT,egatloVegrahcsiDcitatS0002V
O/ILCEP,egatloVegrahcsiDcitatS0051V
25
S2076QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
Table 22. DC Characteristics
sretemaraPnoitpircseDniMpyTxaMstinUsnoitidnoC
V
HO
)LTT(egatloVhgiHtuptuO4.28.2DDVV Inim=DDV
HO
Am4-=
V
LO
)LTT(egatloVwoLtuptuODNG520.5.0V Inim=DDV
LO
Am4=
V
HI
)LTT(egatloVhgiHtupnI0.2V
V
LI
)LTT(egatloVwoLtupnIDNG8.0V
I
HI
)LTT(tnerruChgiHtupnI04AµV
NI
xaM=DDV,V4.2=
I
LI
)LTT(tnerruCwoLtupnI006AµV
NI
xaM=DDV,V8.0=
DDItnerruCylppuS096019Am.nrettap0101
P
D
noitapissiDrewoP72.251.3W .nrettap0101
V
FFID
gniwsegatlovtupnilaitnereffid.niM stupniLCEPlaitnereffidrof 0010022Vm.91erugiFeeS
∆V
TUO
egatloVtuptuOlaireSlaitnereffiD gniwS 002100910022Vmk5.4htiwdelpuocCA Ω.81erugiFeeS.nwodllup
C
NI
ecnaticapaCtupnI3fp
26
S2076 QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
OUTPUT LOAD
The S2076 serial outputs require a resistive load to
set the output current. The recommended resistor
value is 4.5 kΩ to ground. This value can be varied
to adjust drive current, signal voltage swing, and
power usage on the board.
ACQUISITION TIME
With the input eye diagram shown in Figure 21, the
S2076 will recover data with a ≤ IE-9 BER within the
time specified by TLOCK in Table 18 after an instan-
taneous phase shift of the incoming data.
T
r
T
f
80%
20%
50%
80%
20%
50%
T
r
T
f
+2.0V
+0.8V
+2.0V
+0.8V
4.5 kΩ
4.5 kΩ
0.01 µf
0.01 µf
100 Ω
0.01 µf
0.01 µf
Vcc - 1.3 V
Bit Time
Amplitude
24%
1.3
Normalized Amplitude
Normalized Time
1.0
0.0
0.2
0.3
0.5
0.7
0.8
0.1
0.6
0.4
0.3
0.7
0.9
1.0
0.0
Figure 19. High Speed Differential Inputs
Figure 16. Serial Input/Output Rise and Fall Time Figure 20. Receiver Input Eye Diagram Jitter Mask
Figure 17. TTL Input/Output Rise and Fall Time
Figure 18. Serial Output Load Figure 21. Acquisition Time Eye Diagram
27
S2076QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
Figure 22. Loop Filter Capacitor Connections
CAP1
270Ω
22 nf
CAP2
270Ω
S2076
28
S2076 QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright ®, 2000 Applied Micro Circuits Corporation
D171/R259
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey
any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
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Phone: (858) 450-9333 • (800) 755-2622 • Fax: (858) 450-9885
http://www.amcc.com
C
E
R
T
I
F
I
E
D
I
S
O
9
0
0
1
Ordering Information
XIFERPECIVEDEGAKCAP ERUTAREPMET EDARG
detargetnI–S stiucriC 6702AGBT802–BTlaicremmoC–C
XXXXX X
Prefix Device Package Temperature Grade
X
