LTC3863
1
Rev. B
For more information www.analog.com
TYPICAL APPLICATION
FEATURES DESCRIPTION
60V Low IQ Inverting
DC/DC Controller
The LT C
®
3863 is a robust, inverting DC/DC PMOS control-
ler optimized for automotive and industrial applications. It
drives a P-channel power MOSFET to generate a negative
output and requires just a single inductor to complete the
circuit. Output voltages from –0.4V to –150V are typically
achievable with higher voltages possible, only limited by
external components.
The LTC3863 offers excellent light load efficiency, draw-
ing only 70μA quiescent current in a user programmable
Burst Mode operation. Its peak current mode, constant
frequency PWM architecture provides for good control of
switching frequency and output current limit. The switch-
ing frequency can be programmed from 50kHz to 850kHz
with an external resistor and can be synchronized to an
external clock from 75kHz to 750kHz.
The LTC3863 offers programmable soft-start or output
tracking. Safety features include overvoltage, overcurrent
and short-circuit protection including frequency foldback.
The LTC3863 is available in thermally enhanced 12-lead
MSOP and 3mm × 4mm DFN packages.
4.5V to 16V Input, –5V/1.7A Output, 350kHz Inverting Converter
APPLICATIONS
n Wide Operating VIN Range: 3.5V to 60V
n Wide Negative VOUT Range: –0.4V to Beyond –150V
n Low Operating IQ = 70µA
n Strong High Voltage MOSFET Gate Driver
n Constant Frequency Current Mode Architecture
n Verified FMEA for Adjacent Pin Open/Short
n Selectable High Efficiency Burst Mode
®
Operation or
Pulse-Skipping Mode at Light Loads
n Programmable Fixed Frequency: 50kHz to 850kHz
n Phase-Lockable Frequency: 75kHz to 750kHz
n Accurate Current Limit
n Programmable Soft-Start or Voltage Tracking
n Internal Soft-Start Guarantees Smooth Start-Up
n Low Shutdown IQ = 7µA
n Available in Small 12-Lead Thermally Enhanced
MSOP and DFN Packages
n Industrial and Automotive Power Supplies
n Telecom Power Supplies
n Distributed Power Systems
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. patents, including 5731694.
Efficiency
350kHz
16mΩ
10µH
Si7129
B540C
CAP
0.47µF 10µF
25V
×2
PGND
LTC3863
3863 TA01a
SS
ITH
FREQ
SGND
RUN VIN
PLLIN/MODE
SENSE
GATE
VFBN
VFB
14.7k
61.9k
511k
33µF
×2
VOUT
–5V
1.7A
80.6k
68pF
VIN
4.5V TO 16V
27nF
150µF
16V
×2
+
100µF
20V
+
LOAD CURRENT (A)
0.002
40
EFFICIENCY (%)
POWER LOSS (W)
60
90
80
0.02 0.2 2
3863 TA01b
20
30
50
70
10
0
4
6
9
8
2
3
5
7
1
0
EFFICIENCY
POWER LOSS
VIN = 12V
VOUT = –5V
PULSE-SKIPPING MODE
Burst Mode OPERATION
Document Feedback
LTC3863
2
Rev. B
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PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage (VIN) ......................... –0.3V to 65V
VIN-VSENSE Voltage ...................................... –0.3V to 6V
VIN-VCAP Voltage ........................................ –0.3V to 10V
RUN Voltage............................................... –0.3V to 65V
VFBN, PLLIN/MODE Voltages ....................... –0.3V to 6V
SS, ITH, FREQ, VFB Voltages ........................ –0.3V to 5V
(Note 1)
12
11
10
9
8
7
13
PGND
1
2
3
4
5
6
GATE
VIN
SENSE
CAP
RUN
VFBN
PLLIN/MODE
FREQ
SGND
SS
VFB
ITH
TOP VIEW
DE PACKAGE
12-LEAD (4mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 43°C/W, θJC = 5.5°C/W
EXPOSED PAD (PIN 13) IS PGND, MUST BE SOLDERED TO PCB
1
2
3
4
5
6
PLLIN/MODE
FREQ
SGND
SS
VFB
ITH
12
11
10
9
8
7
GATE
VIN
SENSE
CAP
RUN
VFBN
TOP VIEW
13
PGND
MSE PACKAGE
12-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 40°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 13) IS PGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3863EMSE#PBF LTC3863EMSE#TRPBF 3863 12-Lead Plastic MSOP –40°C to 125°C
LTC3863IMSE#PBF LTC3863IMSE#TRPBF 3863 12-Lead Plastic MSOP –40°C to 125°C
LTC3863HMSE#PBF LTC3863HMSE#TRPBF 3863 12-Lead Plastic MSOP –40°C to 150°C
LTC3863MPMSE#PBF LTC3863MPMSE#TRPBF 3863 12-Lead Plastic MSOP –55°C to 150°C
LTC3863EDE#PBF LTC3863EDE#TRPBF 3863 12-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LTC3863IDE#PBF LTC3863IDE#TRPBF 3863 12-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C
LTC3863HDE#PBF LTC3863HDE#TRPBF 3863 12-Lead (4mm × 3mm) Plastic DFN –40°C to 150°C
LTC3863MPDE#PBF LTC3863MPDE#TRPBF 3863 12-Lead (4mm × 3mm) Plastic DFN –55°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Operating Junction Temperature Range (Notes 2, 3, 4)
LTC3863E,I ....................................... –40°C to 125°C
LTC3863H .......................................... –40°C to 150°C
LTC3863MP ....................................... –55°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MSOP Package ................................................. 300°C
LTC3863
3
Rev. B
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ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Supply
VIN Input Voltage Operating Range 3.5 60 V
VUVLO Undervoltage Lockout (VIN-VCAP) Ramping Up Threshold
(VIN-VCAP) Ramping Down Threshold
Hysteresis
l
l
3.25
3.00
3.50
3.25
0.25
3.8
3.50
V
V
V
IQInput DC Supply Current
Pulse-Skipping Mode PLLIN/MODE = 0V, FREQ = 0V,
VFB = 0.83V (No Load)
0.77 1.2 mA
Burst Mode Operation PLLIN/MODE = Open, FREQ = 0V,
VFB = 0.83V (No Load)
50 70 µA
Shutdown Supply Current RUN = 0V 7 12 µA
Output Sensing
VREG Regulated Feedback Voltage VREG = (VFB – VFBN) VITH = 1.2V (Note 5) l0.791 0.800 0.809 V
∆VREG
∆VIN
Feedback Voltage Line Regulation VIN = 3.8V to 60V (Note 5) –0.005 0.005 %/V
∆VREG
∆VITH
Feedback Voltage Load Regulation VITH = 0.6V to 1.8V (Note 5) –0.1 –0.015 0.1 %
gm(EA) Error Amplifier Transconductance VITH = 1.2V, ∆IITH = ±5µA (Note 5) 1.8 mS
IFBN Feedback Negative Input Bias Current –50 –10 50 nA
Current Sensing
VILIM Current Limit Threshold (VIN-VSENSE) VFB = 0.77V l85 95 103 mV
ISENSE SENSE Pin Input Current VSENSE = VIN 0.1 2 µA
Start-Up and Shutdown
VRUN RUN Pin Enable Threshold VRUN Rising l1.22 1.26 1.32 V
VRUNHYS RUN Pin Hysteresis 150 mV
ISS Soft-Start Pin Charging Current VSS = 0V 10 µA
Switching Frequency and Clock Synchronization
f Programmable Switching Frequency RFREQ = 24.9kΩ
RFREQ = 64.9kΩ
RFREQ = 105kΩ
375
105
440
810
505
kHz
kHz
kHz
fLO Low Switching Frequency FREQ = 0V 320 350 380 kHz
fHI High Switching Frequency FREQ = Open 485 535 585 kHz
fSYNC Synchronization Frequency l75 750 kHz
VCLK(IH) Clock Input High Level into PLLIN/MODE l2 V
VCLK(LO) Clock Input Low Level into PLLIN/MODE l0.5 V
fFOLD Foldback Frequency as Percentage of
Programmable Frequency
VFB = 0V, FREQ = 0V 18 %
tON(MIN) Minimum On-Time 220 ns
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 4) VIN = 12V, unless otherwise noted.
LTC3863
4
Rev. B
For more information www.analog.com
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Gate Driver
VCAP Gate Bias LDO Output Voltage (VIN-VCAP) IGATE = 0mA l7.6 8.0 8.5 V
VCAPDROP Gate Bias LDO Dropout Voltage VIN = 5V, IGATE = 15mA 0.2 0.5 V
∆VCAP(LINE) Gate Bias LDO Line Regulation 9V ≤ VIN ≤ 60V, IGATE = 0mA 0.002 0.03 %/V
∆VCAP(LOAD)Gate Bias LDO Load Regulation Load = 0mA to 20mA –3.5 %
RUP Gate Pull-Up Resistance Gate High 2 Ω
RDN Gate Pull-Down Resistance Gate Low 0.9 Ω
Overvoltage
VFBOV VFB Overvoltage Lockout Threshold GATE Going High without Delay,
VFB(OV)-VFB(NOM) in Percent
10 %
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 4) VIN = 12V, unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 3: The junction temperature (TJ in °C) is calculated from the ambient
temperature (TA in °C) and power dissipation (PD in Watts) as follows:
TJ = TA + (PD • θJA)
where θJA (in °C/W) is the package thermal impedance provided in the Pin
Configuration section for the corresponding package.
Note 4:
The LTC3863 is tested under pulsed load conditions such that TJ
≈ TA. The LTC3863E is guaranteed to meet performance specifications
from 0°C to 85°C operating junction temperature range. The LTC3863E
specifications over the –40°C to 125°C operating junction temperature
range are assured by design, characterization and correlation with
statistical process controls. The LTC3863I is guaranteed to meet
performance specifications over the –40°C to 125°C operating junction
temperature range, the LTC3863H is guaranteed over the –40°C to 150°C
operating junction temperature range, and the LTC3863MP is guaranteed
and tested over the full –55°C to 150°C operating junction temperature
range. High junction temperatures degrade operating lifetimes; operating
lifetime is derated for junction temperatures greater than 125°C. The
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors.
Note 5: The LTC3863 is tested in a feedback loop that adjust VREG
or (VFB – VFBN) to achieve a specified error amplifier output voltage
(on ITH pin).
LTC3863
5
Rev. B
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Transient Response:
Pulse-Skipping Mode Operation
Transient Response: Rising Edge
Pulse-Skipping Mode Operation
Transient Response: Falling Edge
Pulse-Skipping Mode Operation
Normal Soft-Start Soft-Start into a Prebiased Output Output Tracking
Pulse-Skipping Mode Operation
Waveforms
Burst Mode Operation
Waveforms
Transient Response:
Burst Mode Operation
TA = 25°C, unless otherwise noted.
VIN = 12V
VOUT = –5V
ILOAD = 100mA
FIGURE 7 CIRCUIT
VSW
10V/DIV
VOUT
50mV/DIV
IL
500mA/DIV
2µs/DIV 3863 G01 VIN = 12V
VOUT = –5V
ILOAD = 100mA
FIGURE 7 CIRCUIT
VSW
10V/DIV
VOUT
50mV/DIV
IL
500mA/DIV
20µs/DIV 3863 G02 VIN = 12V
VOUT = –5V
TRANSIENT = 100mA TO 1.6A
FIGURE 7 CIRCUIT
VOUT
200mV/DIV
ILOAD
1A/DIV
IL
1A/DIV
100µs/DIV 3863 G03
VIN = 12V
VOUT = –5V
TRANSIENT = 100mA TO 1.6A
FIGURE 7 CIRCUIT
VOUT
200mV/DIV
ILOAD
1A/DIV
IL
1A/DIV
100µs/DIV 3863 G04 VIN = 12V
VOUT = –5V
TRANSIENT = 100mA TO 1.6A
FIGURE 7 CIRCUIT
VOUT
200mV/DIV
ILOAD
1A/DIV
IL
1A/DIV
10µs/DIV 3863 G05 VIN = 12V
VOUT = –5V
TRANSIENT = 1.6A TO 100mA
FIGURE 7 CIRCUIT
VOUT
200mV/DIV
ILOAD
1A/DIV
IL
1A/DIV
10µs/DIV 3863 G06
VIN = 12V
VOUT1 = 5V
VOUT2 = –5V
ILOAD1 = ILOAD2 = 100mA
FIGURE 11 CIRCUIT
VOUT1
2V/DIV
VOUT2
2V/DIV
VIN
5V/DIV
TRACK/SS
200mV/DIV
1ms/DIV 3863 G07 VIN = 12V
VOUT1 = 5V, VOUT2 = –5V
PRE-BIAS1 = 2V, PRE-BIAS2 = –2V
ILOAD = 50mA
FIGURE 11 CIRCUIT
VOUT1
2V/DIV
VOUT2
2V/DIV
RUN
5V/DIV
TRACK/SS
200mV/DIV
1ms/DIV 3863 G08 VIN = 12V
VOUT1 = 5V
VOUT2 = –5V
ILOAD1 = ILOAD2 = 100mA
FIGURE 11 CIRCUIT
VOUT1
2V/DIV
VOUT2
2V/DIV
TRACK/SS
200mV/DIV
20ms/DIV 3863 G09
LTC3863
6
Rev. B
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Burst Mode Input Current Over
Input Voltage (No Load)
Pulse-Skipping Mode Input
Current Over Input Voltage
(No Load)
Shutdown Current Over Input
Voltage
Output Regulation Over Input
Voltage
Output Regulation Over Load
Current
Output Regulation Over
Temperature
Overcurrent Protection Short-Circuit Protection VIN Line Transient Behavior
TA = 25°C, unless otherwise noted.
VIN = 12V
VOUT = –5V
ILOAD2 = 1A TO 3.2A
FIGURE 7 CIRCUIT
IL
1A/DIV
VOUT
500mV/DIV
ILOAD
1A/DIV
20ms/DIV 3863 G10 VIN = 12V
VOUT = –5V
ILOAD2 = 1A TO SHORT-CIRCUIT
FIGURE 7 CIRCUIT
IL
1A/DIV
VOUT
5V/DIV
SHORT-
CIRCUIT
TRIGGER
500µs/DIV
FOLDBACK
3863 G11
SOFT-START
RECOVERY
COUT DISCHARGE
VIN = 12V, SURGE TO 48V
VOUT = –5V
ILOAD = 500mA
FIGURE 7 CIRCUIT
GATE
20V/DIV
VOUT
50mV/DIV
VIN
20V/DIV
10ms/DIV 3863 G12
12V
48V
VIN (V)
0
110
IVIN (µA)
115
120
125
130
140
10 20 30 40
3863 G13
50 60
135
VIN = 12V
VOUT = –5V
ILOAD = 0A
FIGURE 7 CIRCUIT
VIN (V)
0
IVIN (µA)
900
3863 G14
800
700 20 40
10 30 50
1000
1100
850
750
950
1050
60
VIN = 12V
VOUT = –5V
ILOAD = 0A
FIGURE 7 CIRCUIT
VIN (V)
0
0
IVIN (µA)
5
10
15
20
30
10 20 30 40
3863 G15
50 60
25
VIN = 12V
FIGURE 7 CIRCUIT
VIN (V)
0
–1.0
NORMALIZED ∆VOUT (%)
–0.5
0
0.5
1.0
10 20 30 40
3863 G16
50 60
VOUT = –5V
ILOAD = 100mA
NOMALIZED AT VIN = 12V
FIGURE 7 CIRCUIT
PULSE-SKIPPING MODE
Burst Mode OPERATION
ILOAD (A)
–0.5
–1.0
NORMALIZED ∆VOUT (%)
–0.5
0
0.5
1.0
0 0.5 1.0 1.5
3863 G17
2.0 2.5
VIN = 12V, VOUT = –5V
ILOAD NORMALIZED AT ILOAD = 1A
FIGURE 7 CIRCUIT
PULSE-SKIPPING MODE
Burst Mode OPERATION
TEMPERATURE (°C)
–75
NORMALIZED ∆VOUT (%)
0.2
0.6
1.0
125
3963 G18
–0.2
–0.6
0
0.4
0.8
–0.4
–0.8
–1.0 –25 25 75 175
VIN = 12V, VOUT = –5V
ILOAD = 200mA
VOUT NOMALIZED TO TA = 25°C
FIGURE 7 CIRCUIT
PULSE-SKIPPING MODE
Burst Mode OPERATION
LTC3863
7
Rev. B
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
GATE Bias LDO (VIN - VCAP) Load
Regulation
GATE Bias LDO (VIN - VCAP)
Dropout Behavior
Current Sense Voltage Over ITH
Voltage
Current Sense Voltage Over
Temperature
SS Pin Pull-Up Current Over
Temperature
RUN Pin Pull-Up Current Over
Temperature
Free Running Frequency Over
Input Voltage
Free Running Frequency Over
Temperature
Frequency Foldback % Over
Feedback Voltage
TA = 25°C, unless otherwise noted.
VIN (V)
0
300
f (kHz)
450
600
550
500
400
350
10 20 30 40 50
3863 G19
60
FREQ = 0V
FREQ = OPEN
VFB (mV)
0
0
FREQUENCY FOLDBACK (%)
60
120
100
80
40
20
200 400 600
3863 G21
800
IGATE (mA)
0
–3.5
(VIN - VCAP) REGULATION (%)
–2.0
0.5
–1.0
–0.5
0.0
–1.5
–2.5
–3.0
510 15
3863 G22
20
IGATE (mA)
0
–0.5
(VIN - VCAP) DROPOUT (V)
0.1 VIN = 5V
–0.1
0.0
–0.2
–0.3
–0.4
510 15
3863 G23
20
TEMPERATURE (°C)
–75
90
CURRENT LIMIT SENSE VOLTAGE (mV)
100
98
94
92
96
–25 25 75 125
3863 G25
175
TEMPERATURE (°C)
–75
0.25
RUN PULL-UP CURRENT (µA)
0.65
0.55
0.35
0.45
–25 25 75 125
3863 G27
175
VRUN = 0V
TEMPERATURE (°C)
–75
300
f (kHz)
450
600
550
500
400
350
–25 25 75 125
3864 G20
175
FREQ = 0V
FREQ = OPEN
TEMPERATURE (°C)
–75
6
SS PULL-UP CURRENT (µA)
14
12
8
10
–25 25 75 125
3863 G26
175
VSS = 0V
ITH VOLTAGE (V)
0
–10
CURRENT SENSE VOLTAGE (mV)
100
80
90
40
30
20
10
0
70
60
50
0.4 0.8 1.2 1.6
3863 G24
2
Burst Mode OPERATION
PULSE-SKIPPING
LTC3863
8
Rev. B
For more information www.analog.com
PIN FUNCTIONS
PLLIN/MODE (Pin 1): External Reference Clock Input
and Burst Mode Enable/Disable. When an external clock
is applied to this pin, the internal phase-locked loop will
synchronize the turn-on edge of the gate drive signal with
the rising edge of the external clock. When no external
clock is applied, this input determines the operation during
light loading. Floating this pin selects low IQ (50µA) Burst
Mode operation. Pulling to ground selects pulse-skipping
mode operation.
FREQ (Pin 2): Switching Frequency Setpoint Input. The
switching frequency is programmed by an external set-
point resistor RFREQ connected between the FREQ pin and
signal ground. An internal 20µA current source creates
a voltage across the external setpoint resistor to set the
internal oscillator frequency. Alternatively, this pin can
be driven directly by a DC voltage to set the oscillator
frequency. Grounding selects a fixed operating frequency
of 350kHz. Floating selects a fixed operating frequency
of 535kHz.
SGND (Pin 3): Ground Reference for Small-Signal Analog
Component (Signal Ground). Signal ground should be
used as the common ground for all small-signal analog
inputs and compensation components. Connect the signal
ground to the power ground (ground reference for power
components) only at one point using a single PCB trace.
SS (Pin 4): Soft-Start and External Tracking Input. The
LTC3863 regulates the feedback voltage to the smaller of
0.8V or the voltage on the SS pin. An internal 10μA pull-up
current source is connected to this pin. A capacitor to
ground at this pin sets the ramp time to the final regulated
output voltage. Alternatively, another voltage supply con-
nected through a resistor divider to this pin allows the
output to track the other supply during start-up.
VFB (Pin 5): Output Feedback Sense. A resistor divider
from the regulated output point to this pin sets the output
voltage. The LTC3863 will nominally regulate VFB to the
internal reference value of 0.8V. If VFB is less than 0.4V,
the switching frequency will linearly decrease and fold
back to about one-fifth of the internal oscillator frequency
to reduce the minimum duty cycle.
ITH (Pin 6): Current Control Threshold and Controller
Compensation Point. This pin is the output of the error
amplifier and the switching regulator’s compensation
point. The voltage ranges from 0V to 2.9V, with 0.8V
corresponding to zero sense voltage (zero current). RITH
should never be less than 10K to avoid large signal com-
pensation issues. For further detail please see the section
Large Signal Effects on ITH.
VFBN (Pin 7): Feedback Input for an Inverting PWM Control-
ler. Connect VFBN to the center of a resistor divider between
the output and VFB. The resistor divider is comprised of
RFB1, placed from the VOUT pin to VFBN pin and RFB2, placed
from the VFBN pin to VFB. It is recommended to set RFB2
to be greater than 8K, please see the Output Voltage Pro-
gramming section for further detail. The VFBN threshold is
0V. To defeat the inverting amplifier and use the LTC3863
as an LTC3864 (noninverting buck), tie VFBN > 2V.
RUN (Pin 8): Digital Run Control Input. A RUN voltage
above the 1.26V threshold enables normal operation, while
a voltage below the threshold shuts down the controller.
An internal 0.4µA current source pulls the RUN pin up to
about 3.3V. The RUN pin can be connected to an external
power supply up to 60V.
CAP (Pin 9): Gate Driver (–) Supply. A low ESR ceramic
bypass capacitor of at least 0.1µF or 10X the effective
CMILLER of the P-channel power MOSFET, is required
from VIN to this pin to serve as a bypass capacitor for the
internal regulator. To ensure stable low noise operation, the
bypass capacitor should be placed adjacent to the VIN and
CAP pins and connected using the same PCB metal layer.
SENSE (Pin 10): Current Sense Input. A sense resistor,
RSENSE, from the VIN pin to the SENSE pin sets the maxi-
mum current limit. The peak inductor current limit is equal
to 95mV/RSENSE. For accuracy, it is important that the VIN
pin and the SENSE pin route directly to the current sense
resistor and make a Kelvin (4-wire) connection.
VIN (Pin 11): Chip Power Supply. A minimum bypass
capacitor of 0.1µF is required from the VIN pin to power
ground. For best performance use a low ESR ceramic
capacitor placed near the VIN pin.
LTC3863
9
Rev. B
For more information www.analog.com
–+
EA
(Gm = 1.8mS)
0.8V
EN
10µA
LOGIC
CONTROL
LDO
IN
OUT
PLL
SYSTEM
Q
S R
MODE/CLOCK
DETECT
VCO
OV 0.88V
SLOPE
COMPENSATION
3.25V
GATE
CAP
SS
VFBN
VIN – 8V
SENSE
VIN
1.26V
–
+
+
PLLIN/MODE
PGND
CCAP
MP
D1
0.5µA
UVLO
RFREQ
SGND
FREQ
RUN RUN
0.4µA
20µA
3863 FD
+
–
–
+
–
DRV
CLOCK
+
–
+
–
O.425V
Burst Mode
OPERATION
+
–
ITH
RITH
CITH1
L
CSS
CFB2
CIN
V
IN
RSENSE
COUT
V
OUT
VFB
RFB1
RFB2
ICMP
+
PIN FUNCTIONS
FUNCTIONAL DIAGRAM
GATE (Pin 12): Gate Drive Output for External P-Channel
MOSFET. The gate driver bias supply voltage (VIN-VCAP)
is regulated to 8V when VIN is greater than 8V. The gate
driver is disabled when (VIN-VCAP) is less than 3.5V (typi-
cal), 3.8V maximum in start-up and 3.25V (typical) 3.5V
maximum in normal operation.
PGND (Exposed Pad Pin 13): Ground Reference for Power
Components (Power Ground). The PGND exposed pad must
be soldered to the circuit board for electrical contact and
for rated thermal performance of the package. Connect
signal ground to power ground only at one point using a
single PCB trace.
LTC3863
10
Rev. B
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OPERATION
LTC3863 Main Control Loop
The LTC3863 is a nonsynchronous inverting PMOS
controller, where an inverting amplifier is used to
sense the negative output voltage below ground. The
LTC3863 uses a peak current mode control architecture
to regulate the output. A feedback resistor, RFB1, is
placed between VOUT and VFBN and a second resistor,
RFB2, is placed between VFBN and and VFB. The LTC3863
has a trimmed internal reference, VREF, that is equal to
(VFB – VFBN). The output voltage is equal to –(RFB1/RFB2)
• VREF where VREF is equal to 800mV in normal regulation.
The LTC3863 can also be configured as a noninverting
step-down buck regulator when the VFBN node is pulled
greater than 2V but held less than 5V, which disables the
internal inverting amplifier. A feedback resistor, RFB1,
is placed between VOUT and VFB and a second resistor,
RFB2, is placed between VFB and SGND. In the noninvert-
ing buck mode the VFB input is compared to the internal
reference, VREF, by a transconductance error amplifier
(EA). The internal reference can be either a fixed 0.8V
reference, VREF, or the voltage input on the SS pin. In
normal operation VFB regulates to the internal 0.8V refer-
ence voltage. The output voltage in normal regulation is
equal to (RFB1 + RFB2)/RFB2 • 800mV.
In soft-start or tracking mode when the SS pin voltage
is less than the internal 0.8V reference voltage, VFB will
regulate to the SS pin voltage. The error amplifier output
connects to the ITH (current [I] threshold [TH]) pin. The
voltage level on the ITH pin is then summed with a slope
compensation ramp to create the peak inductor current
set point.
The peak inductor current is measured through a sense
resistor, RSENSE, placed across the VIN and SENSE pins.
The resultant differential voltage from VIN to SENSE is
proportional to the inductor current and is compared to
the peak inductor current setpoint. During normal opera-
tion the P-channel power MOSFET is turned on when the
clock leading edge sets the SR latch through the S input.
The P-channel MOSFET is turned off through the SR latch
R input when the differential voltage from VIN to SENSE
is greater than the peak inductor current setpoint and the
current comparator, ICMP, trips high.
Power CAP and VIN Undervoltage Lockout (UVLO)
Power for the P-channel MOSFET gate driver is derived
from the CAP pin. The CAP pin is regulated to 8V below
VIN in order to provide efficient P-channel operation. The
power for the VCAP supply comes from an internal LDO,
which regulates the VIN-CAP differential voltage. A mini-
mum capacitance of 0.1µF (low ESR ceramic) is required
between VIN and CAP to assure stability.
For VIN ≤ 8V, the LDO will be in dropout and the CAP volt-
age will be at ground, i.e., the VIN-CAP differential voltage
will equal VIN. If VIN-CAP is less than 3.25V (typical), the
LTC3863 enters a UVLO state where the GATE is prevented
from switching and most internal circuitry is shut down.
In order to exit UVLO, the VIN-CAP voltage would have to
exceed 3.5V (typical).
Shutdown and Soft-Start
When the RUN pin is below 0.7V, the controller and most
internal circuits are disabled. In this micropower shutdown
state, the LTC3863 draws only 7µA. Releasing the RUN
pin allows a small internal pull-up current to pull the RUN
pin above 1.26V and enable the controller. The RUN pin
can be pulled up to an external supply of up to 60V or it
can be driven directly by logic levels.
LTC3863
11
Rev. B
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OPERATION
The start-up of the output voltage VOUT is controlled by
the voltage on the SS pin. When the voltage on the SS
pin is less than the 0.8V internal reference, the VFB pin is
regulated to the voltage on the SS pin. This allows the SS
pin to be used to program a soft-start by connecting an
external capacitor from the SS pin to signal ground. An
internal 10µA pull-up current charges this capacitor, creat-
ing a voltage ramp on the SS pin. As the SS voltage rises
from 0V to 0.8V, the output voltage VOUT rises smoothly
from zero to its final value.
Alternatively, the SS pin can be used to cause the start-up of
VOUT to track that of another supply. Typically, this requires
connecting the SS pin to an external resistor divider from
the other supply to ground (see Applications Information).
Under shutdown or UVLO, the SS pin is pulled to ground
and prevented from ramping up.
If the slew rate of the SS pin is greater than 1.2V/ms, the
output will track an internal soft-start ramp instead of the
SS pin. The internal soft-start will guarantee a smooth
start-up of the output under all conditions, including in the
case of a short-circuit recovery where the output voltage
will recover from near ground.
Light Load Current Operation (Burst Mode Operation
or Pulse-Skipping Mode)
The LTC3863 can be enabled to enter high efficiency Burst
Mode operation or pulse-skipping mode at light loads. To
select pulse-skipping operation, tie the PLLIN/MODE pin
to signal ground. To select Burst Mode operation, float
the PLLIN/MODE pin.
In Burst Mode operation, if the VFB is higher than the refer-
ence voltage, the error amplifier will decrease the voltage
on the ITH pin. When the ITH voltage drops below 0.425V,
the internal sleep signal goes high, enabling sleep mode.
The ITH pin is then disconnected from the output of the
error amplifier and held at 0.55V.
In sleep mode, much of the internal circuitry is turned
off, reducing the quiescent current to 70µA while the
load current is supplied by the output capacitor. As the
output voltage and hence the feedback voltage decreases,
the error amplifier’s output will rise. When the output
voltage drops enough, the ITH pin is reconnected to the
output of the error amplifier, the sleep signal goes low,
and the controller resumes normal operation by turning
on the external P-channel MOSFET on the next cycle of
the internal oscillator. In Burst Mode operation, the peak
inductor current has to reach at least 25% of current limit
for the current comparator, ICMP, to trip and turn the
P-channel MOSFET back off, even though the ITH voltage
may indicate a lower current setpoint value.
When the PLLIN/MODE pin is connected for pulse-skipping
mode, the LTC3863 will skip pulses during light loads. In
this mode, ICMP may remain tripped for several cycles and
force the external MOSFET to stay off, thereby skipping
pulses. This mode offers the benefits of smaller output
ripple, lower audible noise, and reduced RF interference,
at the expense of lower efficiency when compared to Burst
Mode operation.
Frequency Selection and Clock Synchronization
The switching frequency of the LTC3863 can be selected
using the FREQ pin. If the PLLIN/MODE pin is not being
driven by an external clock source, the FREQ pin can be
tied to signal ground, floated, or programmed through an
external resistor. Tying FREQ pin to signal ground selects
350kHz, while floating selects 535kHz. Placing a resistor
between FREQ pin and signal ground allows the frequency
to be programmed between 50kHz and 850kHz.
The phase-locked loop (PLL) on the LTC3863 will syn-
chronize the internal oscillator to an external clock source
when connected to the PLLIN/MODE pin. The PLL forces
the turn-on edge of the external P-channel MOSFET to be
aligned with the rising edge of the synchronizing signal.
LTC3863
12
Rev. B
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OPERATION
The oscillator’s default frequency is based on the operating
frequency set by the FREQ pin. If the oscillator’s default
frequency is near the external clock frequency, only slight
adjustments are needed for the PLL to synchronize the
external P-channel MOSFET’s turn-on edge to the rising
edge of the external clock. This allows the PLL to lock
rapidly without deviating far from the desired frequency.
The PLL is guaranteed from 75kHz to 750kHz. The clock
input levels should be greater than 2V for HI and less
than 0.5V for LO.
Fault Protection
When the VFB voltage is above +10% of the regulated
voltage of 0.8V, this is considered as an overvoltage con-
dition and the external P-MOSFET is immediately turned
off and prevented from ever turning on until VFB returns
below +7.5%.
In the event of an output short circuit or overcurrent con-
dition that causes the output voltage to drop significantly
while in current limit, the LTC3863 operating frequency
will fold back. Anytime the output feedback VFB voltage is
less than 50% of the 0.8V internal reference (i.e., 0.4V),
frequency foldback is active. The frequency will continue
to drop as VFB drops until reaching a minimum foldback
frequency of about 18% of the setpoint frequency. Fre-
quency foldback is designed, in combination with peak
current limit, to limit current in start-up and short-circuit
conditions. Setting the foldback frequency as a percentage
of operating frequency assures that start-up characteristics
scale appropriately with operating frequency.
LTC3863
13
Rev. B
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The LTC3863 is a nonsynchronous inverting, current mode,
constant frequency PWM controller. It drives an external
P-channel power MOSFET which connects to a Schottky
power diode acting as the commutating catch diode. The
input range extends from 3.5V to 60V. The output range
has no theoretical minimum or maximum, but the duty
factor and external components practically limit the out-
put to one-tenth and ten times the input voltage. Higher
output ratios can be obtained with transformers and more
efficient external components.
The LTC3863 offers a highly efficient Burst Mode operation
with 70µA quiescent current, which delivers outstanding
efficiency in light load operation. The LTC3863 is a low
pin count, robust and easy-to-use inverting power supply
solution in applications which require high efficiency and
operate with widely varying input and output voltages.
The typical application on the front page is a basic LTC3863
application circuit. The LTC3863 can sense the inductor
current through a high side series sense resistor, RSENSE,
placed between VIN and the source of the external P-channel
MOSFET. Once the required output voltage and operating
frequency have been determined, external component
selection is driven by load requirements, and begins with
the selection of inductor and RSENSE. Next, the power
MOSFET and catch diode are selected. Finally, input and
output capacitors are selected.
Output Voltage Programming
The output voltage is programmed by connecting a
feedback resistor divider from the output to the VFB pin
as shown in Figure 1. The output voltage in steady-state
operation is set by the feedback resistors according to
the equation:
VOUT =–0.8V • RFB1
R
APPLICATIONS INFORMATION
Great care should be taken to route the VFB and VFBN
lines away from noise sources, such as the inductor or
SW node or the GATE signal that drives the external P-
channel MOSFET.
The integrator capacitor, CFB2, should be sized to ensure
the negative sense amplifier gain rolls off and limits high
frequency gain peaking in the DC/DC control loop. The
integrator capacitor pole can be safely set to be two times
the switching frequency without affecting the DC/DC phase
margin according to the following equation. It is highly
recommended that CFB2 be used in most applications.
CFB2 =1
2 • π• 2 • RFB2 • FREQSW
The feedback resistor RFB2 placed from the VFBN pin to
the VFB pin is driven from VFB by an internal amplifier with
limited VFB output current capability. For Operation at VIN
down to 3.5V, it is recommended to limit the VFB output
current to 100µA, and RFB2 should be no smaller than
8K. For VIN always greater than 6V, it is recommended to
limit the current to 250µA, and RFB2 should be no smaller
than 3.2K. For minimum VIN between 3.5V and 6V, add
75µA for each volt VIN-min is above 3.5V to the maximum
current until reaching a maximum of 250µA at 6VIN, and
minimum RFB2 would be 0.8V/lo-max.
LTC3863
VFB
VFBN
VOUT
RFB2 CFB2
RFB1
3863 F01
Figure 1. Setting the Output Voltage
LTC3863
14
Rev. B
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APPLICATIONS INFORMATION
Switching Frequency and Clock Synchronization
The choice of operating frequency is a trade-off between
efficiency and component size. Lowering the operating fre-
quency improves efficiency by reducing MOSFET switching
losses but requires larger inductance and/or capacitance
to maintain low output ripple voltage. Conversely, raising
the operating frequency degrades efficiency but reduces
component size.
The LTC3863 can free-run at a user programmed switch-
ing frequency, or it can synchronize with an external
clock to run at the clock frequency. When the LTC3863 is
synchronized, the GATE pin will synchronize in phase with
the rising edge of the applied clock in order to turn the
external P-channel MOSFET on. The switching frequency
of the LTC3863 is programmed with the FREQ pin, and the
external clock is applied at the PLLIN/MODE pin. Table 1
highlights the different states in which the FREQ pin can
be used in conjunction with the PLLIN/MODE pin.
Table 1
FREQ PIN PLLIN/MODE PIN FREQUENCY
OV DC Voltage 350kHz
Floating DC Voltage 535kHz
Resistor to GND DC Voltage 50kHz to 850kHz
Either of the Above External Clock Phase Locked to
External Clock
The free-running switching frequency can be programmed
from 50kHz to 850kHz by connecting a resistor from FREQ
pin to signal ground. The resulting switching frequency
as a function of resistance on the FREQ pin is shown in
Figure 2.
Set the free-running frequency to the desired synchroni-
zation frequency using the FREQ pin so that the internal
oscillator is prebiased approximately to the synchronization
frequency. While it is not required that the free-running
frequency be near the external clock frequency, doing so
will minimize synchronization time.
Inductor Selection
Operating frequency, inductor selection, capacitor selection
and efficiency are interrelated. Higher operating frequen-
cies allow the use of smaller inductors, smaller capacitors,
but result in lower efficiency because of higher MOSFET
gate charge and transition losses. In addition to this basic
trade-off, the selection of inductor value is also influenced
by other factors.
Small inductor values result in large inductor ripple cur-
rents, large output voltage ripples and low efficiency due
to higher core and conduction loss. Large inductor ripple
currents result in high inductor peak currents, which re-
quire physically large inductors with large magnetic cross
sections and higher saturation current ratings.
The value of the inductor can also impact the stability of
the feedback loop. In continuous mode, the buck-boost
converter transfer function has a right-half plane zero at
a frequency that is inversely proportional to the value of
the inductor. As a result, large inductor values can move
this zero to a frequency that is low enough to degrade the
phase margin of the feedback loop. Large inductor values
also tend to degrade stability due to low noise margin
caused from low ripple current. Additionally, large value
inductors can lead to slow transient response due to slow
inductor current ramping time.
Figure 2. Switching Frequency vs Resistor on FREQ pin
FREQ PIN RESISTOR (kΩ)
15
FREQUENCY (kHz)
600
800
1000
35 45 5525
3863 F02
400
200
500
700
900
300
100
065 75 85 95 105 115 125
LTC3863
15
Rev. B
For more information www.analog.com
APPLICATIONS INFORMATION
For an inverting buck-boost converter operating in con-
tinuous conduction mode (CCM), given the desired input,
output voltages and switching frequency, the peak-to-peak
inductor ripple current is determined by the inductor value:
∆IL(CCM) =VIN •D
L • f =VIN • | VOUT |+VD
( )
L • f • VIN +| VOUT |+VD
( )
where VD is the diode forward conduction voltage. In cases
where VOUT >> VD, VD can be ignored. D is the duty factor
and is given as:
D=
| V
OUT
|
+
V
D
V
IN
+| V
OUT
|+V
D
0<D<1
( )
The duty factor increases with increasing VOUT and de-
creasing VIN. For a given VOUT, the maximum duty factor
occurs at minimum VIN.
A typical starting point for selecting an inductor is to choose
the inductance such that the maximum peak-to-peak in-
ductor ripple current, ∆IL(MAX), is set to 40% ~ 50% of the
inductor average current, IL(AVG), at maximum load current.
Since ∆IL(MAX) occurs at maximum VIN in continuous mode,
the inductance is calculated at maximum VIN:
L=VIN(MAX)2• | VOUT |+VD
( )
0.4 •IOUT(MAX) • f • VIN(MAX)+| VOUT |+VD
( )
2
The inductance can be further adjusted to achieve specific
design optimization of efficiency, output ripple, component
size and loop response.
Once the inductance value has been determined, the type
of inductor must be selected. Core loss is independent of
core size for a given inductor value, but it is very depen-
dent on the inductance selected. As inductance increases,
core losses decrease. Unfortunately, increased inductance
requires more turns of wire and therefore, copper losses
will increase.
High efficiency converters generally cannot tolerate the
core loss of low cost powdered iron cores, forcing the use
of more expensive ferrite materials. Ferrite designs have
very low core loss and are preferred at high switching
frequencies, so design goals can concentrate on cop-
per loss and preventing saturation. Ferrite core material
saturates hard, which means that inductance collapses
abruptly when the peak design current is exceeded. This
will result in an abrupt increase in inductor ripple current
and output voltage ripple. Do not allow the core to saturate!
A variety of inductors are available from manufacturers
such as Sumida, Panasonic, Coiltronics, Coilcraft, Toko,
Vishay, Pulse and Würth.
Current Sensing and Current Limit Programming
The LTC3863 senses the inductor current through a cur-
rent sense resistor, RSENSE, placed across the VIN and
SENSE pins. The voltage across the resistor, VSENSE, is
proportional to inductor current and in normal operation is
compared to the peak inductor current setpoint. An inductor
current limit condition is detected when VSENSE exceeds
95mV. When the current limit threshold is exceeded, the
P-channel MOSFET is immediately turned off by pulling
the GATE voltage to VIN regardless of the controller input.
The peak inductor current limit is equal to:
IL(PEAK) ≅95mV
R
SENSE
⎛
⎝
⎜
⎞
⎠
⎟
This inductor current limit would translate to an output
current limit based on the inductor ripple and duty factor:
IOUT(LIMIT) =95mV
RSENSE
–∆IL
2
⎛
⎝
⎜
⎞
⎠
⎟• 1– D
( )
LTC3863
16
Rev. B
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APPLICATIONS INFORMATION
The SENSE pin is a high impedance input with a maximum
leakage of ±2µA. Since the LTC3863 is a peak current
mode controller, noise on the SENSE pin can create pulse
width jitter. Careful attention must be paid to the layout of
RSENSE. To ensure the integrity of the current sense signal,
VSENSE, the traces from VIN and SENSE pins should be
short and run together as a differential pair and Kelvin
(4-wire) connected across RSENSE (Figure 3).
The LTC3863 has internal filtering of the current sense
voltage which should be adequate in most applications.
However, adding a provision for an external filter offers
added flexibility and noise immunity, should it be neces-
sary. The filter can be created by placing a resistor from the
RSENSE resistor to the SENSE pin and a capacitor across
the VIN and SENSE pins.
Power MOSFET Selection
The LTC3863 drives a P-channel power MOSFET that
serves as the main switch for the nonsynchronous
inverting converter. Important P-channel power MOSFET
parameters include drain-to-source breakdown voltage
BVDSS, threshold voltage VGS(TH), on-resistance RDS(ON),
gate-to-drain reverse transfer capacitance CRSS, maximum
drain current ID(MAX), and the MOSFET’s thermal resistance
θJC(MOSFET) and θJA(MOSFET).
The drain-to-source breakdown voltage must meet the
following condition:
BVDSS > VIN(MAX) + |VOUT| + VD
The gate driver bias voltage VIN-VCAP is set by an internal
LDO regulator. In normal operation, the CAP pin will be
regulated to 8V below VIN. A minimum 0.1µF capacitor
is required across the VIN and CAP pins to ensure LDO
stability. If required, additional capacitance can be added
to accommodate higher gate currents without voltage
droop. In shutdown and Burst Mode operation, the CAP
LDO is turned off. In the event of CAP leakage to ground,
the CAP voltage is limited to 9V by a weak internal clamp
from VIN to CAP. As a result, a minimum 10V VGS rated
MOSFET is required.
The power dissipated by the P-channel MOSFET when the
LTC3863 is in continuous conduction mode is given by:
PPMOS ≈D • IOUT
1– D
⎛
⎝
⎜⎞
⎠
⎟
2
•ρT•RDS(ON)
+f •CMILLER • VIN +| VOUT |+VD
( )
2
2•IOUT
1– D
•RDN
VIN – VCAP – VMILLER
( )
+RUP
VMILLER
⎡
⎣
⎢
⎤
⎦
⎥
where D is duty factor, RDS(ON) is on-resistance of
P-channel MOSFET, ρT is temperature coefficient of on-
resistance, RDN is the pull-down driver resistance specified
at 0.9Ω typical and RUP is the pull-up driver resistance
specified at 2Ω typical. VMILLER is the Miller effective VGS
voltage and is taken graphically from the power MOSFET
data sheet.
Figure 3. Inductor Current Sensing
VIN
RSENSE
LTC3863
VIN
SENSE
RF
MP
OPTIONAL
FILTERING
3863 F03
CF
LTC3863
17
Rev. B
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Figure 4. (4a) Typical P-Channel MOSFET Gate Charge
Characteristics and (4b) Test Set-Up to Generate Gate
Charge Curve
S
D
G
VSD(TEST)
RLOAD
IGATE
3863 F04
MILLER EFFECT
QIN
(4a) (4b)
a b
CMILLER = (QB – QA)/VSD(TEST)
VSG
–
+
APPLICATIONS INFORMATION
The power MOSFET input capacitance, CMILLER, is the most
important selection criteria for determining the transition
loss term in the P-channel MOSFET but is not directly speci-
fied on MOSFET data sheets. CMILLER is a combination of
several components, but it can be derived from the typical
gate charge curve included on most data sheets (Figure4).
The curve is generated by forcing a constant current out
of the gate of a common-source connected P-channel
MOSFET that is loaded with a resistor, and then plotting
the gate voltage versus time. The initial slope is the effect
of the gate-to-source and gate-to-drain capacitances. The
flat portion of the curve is the result of the Miller multipli-
cation effect of the drain-to-gate capacitance as the drain
voltage rises across the resistor load. The Miller charge
(the increase in coulombs on the horizontal axis from a to
b while the curve is flat) is specified for a given VSD test
voltage, but can be adjusted for different VSD voltages by
multiplying by the ratio of the adjusted VSD to the curve
specified VSD value. A way to estimate the CMILLER term
is to take the change in gate charge from points a and b
(or the parameter QGD on a manufacturer’s data sheet)
and dividing it by the specified VSD test voltage, VSD(TEST).
CMILLER ≅QGD
VSD(TEST)
The term with CMILLER accounts for transition loss, which
is highest at high input voltages. For VIN < 20V, the high
current efficiency generally improves with larger MOSFETs,
while for VIN > 20V, the transition losses rapidly increase
to the point that the use of a higher RDS(ON) device with
lower CMILLER actually provides higher efficiency.
Schottky Diode Selection
When the P-channel MOSFET is turned off, a power
Schottky diode is required to function as a commutating
diode to carry the inductor current. The average forward
diode current is independent of duty factor and is de-
scribed as:
IF(AVG) = IOUT
The worst-case condition for diode conduction is a short-
circuit condition where the Schottky must handle the
maximum current as its duty factor approaches 100% (and
the P-channel MOSFET’s duty factor approaches 0%). The
diode therefore must be chosen carefully to meet worst-
case voltage and current requirements. A good practice
is to choose a diode that has a forward current rating two
times higher than IOUT(MAX).
Once the average forward diode current is calculated, the
power dissipation can be determined. Refer to the Schottky
diode data sheet for the power dissipation, PDIODE, as a
function of average forward current, IF(AVG). PDIODE can
LTC3863
18
Rev. B
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APPLICATIONS INFORMATION
also be iteratively determined by the two equations below,
where VF(IOUT,TJ) is a function of both IF(AVG) and junction
temperature TJ. Note that the thermal resistance, θJA(DIODE),
given in the data sheet is typical and can be highly layout
dependent. It is therefore important to make sure that the
Schottky diode has adequate heat sinking.
TJ ≅ PDIODE • θJA(DIODE)
PDIODE ≅ IF(AVG) • VD(IOUT,TJ)
The Schottky diode forward voltage is a function of both
IF(AVG) and TJ, so several iterations may be required to
satisfy both equations. The Schottky forward voltage,
VD, should be taken from the Schottky diode data sheet
curve showing instantaneous forward voltage. The forward
voltage will change as a function of both TJ and IF(AVG).
The nominal forward voltage will also tend to increase as
the reverse breakdown voltage increases. It is therefore
advantageous to select a Schottky diode appropriate to the
input voltage requirements. The diode reverse breakdown
voltage must meet the following condition:
VR > VIN(MAX) + |VOUT|
CIN and COUT Selection
The input and output capacitance, CIN/COUT, are required
to filter the square wave current through the P-channel
MOSFET and diode respectively. Use a low ESR capacitor
sized to handle the maximum RMS current:
ICIN(RMS) =ICOUT(RMS) =IOUT •| VOUT |+VD
V
IN
The formula shows that the RMS current is greater than
the maximum IOUT when VOUT is greater than VIN. Choose
capacitors with higher RMS rating with sufficient margin.
Note that ripple current ratings from capacitor manufac-
turers are often based on only 2000 hours of life, which
makes it advisable to derate the capacitor.
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple and load step transients.
The ∆VOUT is approximately bounded by:
∆VOUT ≤IL(PEAK) •ESR +
I
OUT
•D
f •C
OUT
where IL(PEAK) is the peak inductor current and it’s given as:
IL(PEAK) =IOUT VIN +| VOUT |+VD
( )
VIN
+VIN • | VOUT |+VD
( )
2 •L • f • VIN +| V
OUT
|+VD
( )
Since IL(PEAK) and D reach their maximum values at mini-
mum VIN, the output voltage ripple is highest at minimum
VIN and maximum IOUT. Typically, once the ESR require-
ment is satisfied, the capacitance is adequate for filtering
and has the necessary RMS current rating.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, specialty polymer, aluminum electrolytic
and ceramic capacitors are all available in surface mount
packages. Specialty polymer capacitors offer very low
ESR but have lower specific capacitance than other types.
Tantalum capacitors have the highest specific capacitance,
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications provided that
consideration is given to ripple current ratings and long-
term reliability. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient and
audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing. When used as input
capacitors, care must be taken to ensure that ringing from
inrush currents and switching does not pose an overvolt-
age hazard to the power switch and controller. To dampen
input voltage transients, add a small 5μF to 40μF aluminum
electrolytic capacitor with an ESR in the range of 0.5Ω to
2Ω. High performance through-hole capacitors may also
be used, but an additional ceramic capacitor in parallel
is recommended to reduce the effect of lead inductance.
LTC3863
19
Rev. B
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Figure 5a. Tw o Different Modes of Output Tracking
Figure 5b. Setup for Ratiometric and Coincident Tracking
TIME
Coincident Tracking
EXTERNAL
SUPPLY
EXTERNAL
SUPPLY
–VOUT
(VOUT < 0V)
–VOUT
(VOUT < 0V)
VOLTAGE
TIME 3863 F05a
Ratiometric Tracking
VOLTAGE
R1 = RFB1 – RFB2
|VOUT| > 0.8V
EXT. V
R2 = RFB2
Coincident Tracking Setup
TO SS
RFB1
VOUT
TO VFBN
TO FB TO FB
RFB2
R1
EXT. V
R2
R1+ R2 ≥
R2
TO SS
RFB1
VOUT
TO VFBN
RFB2
3863 F05b
Ratiometric Tracking Setup
0.8V
EXT. V
APPLICATIONS INFORMATION
Discontinuous and Continuous Operation
The LTC3863 operates in discontinuous conduction (DCM)
until the load current is high enough for the inductor
current to be positive at the end of the switching cycle.
The output load current at the continuous/discontinuous
boundary, IOUT(CDB), is given by the following equation:
IOUT(CDB) =VIN(MAX)2• | VOUT |+VD
( )
2 •L • f • VIN(MAX)+| VOUT |+VD
( )
2
The continuous/discontinuous boundary is inversely
proportional to the inductor value. Therefore, if required,
IOUT(CDB) can be reduced by increasing the inductor value.
External Soft-Start and Output Tracking
Start-up characteristics are controlled by the voltage on
the SS pin. When the voltage on the SS pin is less than
the internal 0.8V reference, the LTC3863 regulates the
VFB pin voltage to the voltage on the SS pin. When the SS
pin is greater than the internal 0.8V reference, the VFB pin
voltage regulates to the 0.8V internal reference. The SS
pin can be used to program an external soft-start function
or to allow VOUT to track another supply during start-up.
Soft-start is enabled by connecting a capacitor from
the SS pin to ground. An internal 10µA current source
charges the capacitor, providing a linear ramping voltage
at the SS pin that causes VOUT to rise smoothly from 0V
to its final regulated value. The total soft-start time will
be approximately:
tSS =CSS •
0.8V
10µA
When the LTC3863 is configured to track another supply,
a voltage divider can be used from the tracking supply to
the SS pin to scale the ramp rate appropriately. Tw o com-
mon implementations of tracking as shown in Figure5a
are coincident and ratiometric. For coincident tracking,
LTC3863
20
Rev. B
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APPLICATIONS INFORMATION
choose the divider ratio for the external supply as shown
in Figure 5b. Ratiometric tracking could be achieved by
using a different ratio than the feedback (Figure 5b).
Note that the soft-start capacitor charging current is always
flowing, producing a small offset error. To minimize this
error, select the tracking resistive divider values to be small
enough to make this offset error negligible.
Short-Circuit Faults: Current Limit and Foldback
The inductor current limit is inherently set in a current mode
controller by the maximum sense voltage and RSENSE. In
the LTC3863, the maximum sense voltage is 95mV, mea-
sured across the inductor sense resistor, RSENSE, placed
across the VIN and SENSE pins. The output current limit
is approximately:
I
LIMIT(MIN) =95mV
RSENSE
–∆IL
2
⎛
⎝
⎜
⎞
⎠
⎟•VIN(MIN)
VIN(MIN) +| VOUT |+VD
( )
The current limit must be chosen to ensure that ILIMIT(MIN)
> IOUT(MAX) under all operating conditions. The inductor
current limit should be greater than the inductor current
required to produce maximum output power at worst-case
efficiency. For the LTC3863, both minimum and maximum
VIN cases should be checked to determine the worst-case
efficiency.
Short-circuit fault protection is assured by the combination
of current limit and frequency foldback. When the output
feedback voltage, VFB, drops below 0.4V, the operating
frequency, f, will fold back to a minimum value of 0.18•f
when VFB reaches 0V. Both current limit and frequency
foldback are active in all modes of operation. In a short-
circuit fault condition, the output current is first limited
by current limit and then further reduced by folding back
the operating frequency as the short becomes more se-
vere. The worst-case fault condition occurs when VOUT
is shorted to ground.
Short-Circuit Recovery and Internal Soft-Start
An internal soft-start feature guarantees a maximum posi-
tive output voltage slew rate in all operational cases. In a
short-circuit recovery condition for example, the output
recovery rate is limited by the internal soft-start so that
output voltage overshoot and excessive inductor current
buildup is prevented.
The internal soft-start voltage and the external SS pin
operate independently. The output will track the lower of
the two voltages. The slew rate of the internal soft-start
voltage is roughly 1.2V/ms, which translates to a total
soft-start time of 650µs. If the slew rate of the SS pin is
greater than 1.2V/ms the output will track the internal soft-
start ramp. To assure robust fault recovery, the internal
soft-start feature is active in all operational cases. If a
short-circuit condition occurs which causes the output to
drop significantly, the internal soft-start will assure a soft
recovery when the fault condition is removed.
The internal soft-start assures a clean soft ramp-up from
any fault condition that causes the output to droop, guar-
anteeing a maximum ramp rate in soft-start, short-circuit
fault release. Figure 6 illustrates how internal soft-start
controls the output ramp-up rate under varying scenarios.
Figure 6. Internal Soft-Start (6a) Allows Soft-Start without an
External Soft-Start Capacitor and Allows Soft Recovery from (6b)
a Short-Circuit
TIME~650µs
(6a)
––VOUT
VIN
VOLTAGE
3863 F06
INTERNAL SOFT-START INDUCED START-UP
(NO EXTERNAL SOFT-START CAPACITOR)
TIME
SHORT-CIRCUIT
(6b)
–VOUT
VOLTAGE
INTERNAL SOFT-START
INDUCED RECOVERY
LTC3863
21
Rev. B
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APPLICATIONS INFORMATION
VIN Undervoltage Lockout (UVLO)
The LTC3863 is designed to accommodate applications
requiring widely varying power input voltages from
3.5V to 60V. To accommodate the cases where VIN
drops significantly once in regulation, the LTC3863 is
guaranteed to operate down to a VIN of 3.5V over the
full temperature range.
The implications of both the UVLO rising and UVLO falling
specifications must be carefully considered for low VIN
operation. The UVLO threshold with VIN rising is typi-
cally 3.5V (with a maximum of 3.8V) and UVLO falling is
typically 3.25V (with a maximum of 3.5V). The operating
input voltage range of the LTC3863 is guaranteed to be
3.5V to 60V over temperature, but the initial VIN ramp
must exceed 3.8V to guarantee start-up.
Minimum On-Time Considerations
The minimum on-time, tON(MIN), is the smallest time
duration that the LTC3863 is capable of turning on the
power MOSFET, and is typically 220ns. It is determined
by internal timing delays and the gate charge required to
turn on the MOSFET. Low duty cycle applications may
approach this minimum on-time limit, so care should be
taken to ensure that:
tON(MIN) <| VOUT |+VD
( )
f • VIN(MAX)+| VOUT |+VD
( )
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will skip cycles.
However, the output voltage will continue to regulate.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
the dominant contributors and therefore where efficiency
improvements can be made. Percent efficiency can be
expressed as:
% Efficiency = 100% - (L1+L2+L3+…)
where L1, L2, L3, etc., are the individual losses as a per-
centage of input power.
Although all dissipative elements in the circuit produce
losses, four main sources account for most of the losses
in LTC3863 application circuits.
1. Conduction Loss: Conduction losses result from the
P-channel MOSFET RDS(ON), inductor resistance DCR,
the current sense resistor RSENSE, and input and output
capacitor ESR. The current through DCR is continuous.
The currents through both the P-channel MOSFET and
Schottky diode are discontinuous. The following equa-
tion may be used to determine the total conduction loss
(PCOND) in continuous conduction mode:
PCOND ≈IOUT2
1– D
( )
2+∆IL2
12
⎛
⎝
⎜
⎞
⎠
⎟
•RDCR +D • RDS(ON) +RSENSE +RESR(CIN)
( )
+1– D
( )
•RESR(COUT)
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
2. Transition Loss: Transition loss of the P-channel
MOSFET becomes significant only when operating
at high input voltages (typically 20V or greater.) The
P-channel transition losses (PPMOSTRL) can be deter-
mined from the following equation:
PPMOSTRL =f •CMILLER • VIN +| VOUT |+VD
( )
2
2
•IOUT
1– D •RDN
VIN – VCAP
( )
– VMILLER
+RUP
VMILLER
⎡
⎣
⎢
⎤
⎦
⎥
LTC3863
22
Rev. B
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APPLICATIONS INFORMATION
3. Gate Charging Loss: Charging and discharging the gate
of the MOSFET will result in an effective gate charg-
ing current. Each time the P-channel MOSFET gate is
switched from low to high and low again, a packet of
charge, dQ, moves from the capacitor across VIN – VCAP
and is then replenished from ground by the internal VCAP
regulator. The resulting dQ/dt current is a current out
of VIN flowing to ground. The total power loss in the
controller including gate charging loss is determined
by the following equation:
PCNTRL = VIN • (IQ + f • QG(PMOSFET))
4. Schottky Loss: The Schottky loss is independent of
duty factors. The critical component is the Schottky
forward voltage as a function of junction temperature
and current. The Schottky power loss is given by the
equation:
PDIODE = IOUT • VD(IOUT,TJ)
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If
changes cause the input current to decrease, then the
efficiency has increased. If there is no change in input
current, there is no change in efficiency.
OPTI-LOOP
®
Compensation
OPTI-LOOP compensation, through the availability of the
ITH pin, allows the transient response to be optimized for a
wide range of loads and output capacitors. The ITH pin not
only allows optimization of the control loop behavior but
also provides a test point for the regulator ’s DC-coupled
and AC-filtered closed-loop response. The DC step, rise
time and settling at this test point truly reflects the closed-
loop response. Assuming a predominantly second order
system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at this pin.
The ITH series RITH-CITH1 filter sets the dominant pole-zero
loop compensation. Additionally, a small capacitor placed
from the ITH pin to signal ground, CITH2, may be required to
attenuate high frequency noise. The values can be modified
to optimize transient response once the final PCB layout
is done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because their various types and values determine
the loop feedback factor gain and phase. An output current
pulse of 20% to 100% of full load current having a rise
time of 1μs to 10μs will produce output voltage and ITH
pin waveforms that will give a sense of the overall loop
stability without breaking the feedback loop. The general
goal of OPTI-LOOP compensation is to realize a fast but
stable ITH response with minimal output droop due to
the load step. For a detailed explanation of OPTI-LOOP
compensation, refer to Application Note 76.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, VOUT im-
mediately shifts by an amount equal to ∆ILOAD
• ESR, where
ESR is the effective series resistance of COUT
. ∆ILOAD also
begins to charge or discharge COUT
, generating a feedback
error signal used by the regulator to return VOUT to its
steady-state value. During this recovery time, VOUT can
be monitored for overshoot or ringing that would indicate
a stability problem.
Connecting a resistive load in series with a power MOSFET,
then placing the two directly across the output capacitor
and driving the gate with an appropriate signal generator
is a practical way to produce a realistic load-step condi-
tion. The initial output voltage step resulting from the step
change in output current may not be within the bandwidth
of the feedback loop, so this signal cannot be used to
determine phase margin. This is why it is better to look
at the ITH pin signal which is in the feedback loop and
is the filtered and compensated feedback loop response.
The gain of the loop increases with RITH and the band-
width of the loop increases with decreasing CITH1. If RITH
is increased by the same factor that CITH1 is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range of
LTC3863
23
Rev. B
For more information www.analog.com
APPLICATIONS INFORMATION
the feedback loop. The output voltage settling behavior is
related to the stability of the closed-loop system and will
demonstrate overall performance of the regulator.
In some applications, a more severe transient can be caused
by switching in loads with large (>10μF) input capacitors.
If the switch connecting the load has low resistance and
is driven quickly, then the discharged input capacitors are
effectively put in parallel with COUT
, causing a rapid drop in
VOUT
. No regulator can deliver enough current to prevent
this problem. The solution is to limit the turn-on speed of
the load switch driver. A Hot Swap™ controller is designed
specifically for this purpose and usually incorporates cur-
rent limiting, short-circuit protection and soft-start.
Large-Signal Effects on ITH
Inverting controllers have a wide range of applications
and operating conditions which affect compensation.
Low switching frequencies and the inverting buck-boost
right-half-plane zero can result in very low gain crossover
frequency requirements. Low crossover frequencies often
require a compensation RITH and CITH that are too small for
the error amplifier output drive current on ITH of 100µA.
The effect causes ITH to appear clamped in response
to a transient load current step which causes excessive
output droop.
An RITH greater than 20k allows ITH to swing 1.5V with
margin for temperature and part to part variation and
should never have this issue. In applications with less
severe transient load step requirements, RITH can safely
be set as low as 10k. We do not recommend less than
10k in any application. If RITH is too small then either
the operating frequency will need to be increased or the
output capacitor increased to increase the RITH required
to stabilize the system. We strongly recommend that any
system with an RITH less than 20k be experimentally veri-
fied with worst-case load steps.
Design Example
Consider an inverting converter with the following speci-
fications:
VIN = 4.5V to 55V, VOUT = –5V, IOUT(MAX) = 1.8A, and
f = 320kHz (Figure 7).
The output voltage is programmed according to:
VOUT =–0.8V • RFB1
RFB2
Figure 7. Design Example (4.5V to 55V Input, –5V, 1.8A at 320kHz)
320kHz
16mΩ
L1
12µH
Q1 D1
CAP
0.47µF
PGND
LTC3863
3863 F07
SS
ITH
FREQ
SGND
RUN VIN
PLLIN/MODE
SENSE
GATE
VFBN
VFB
10k
52.3k 187k
COUT3
100µF
20V
VOUT
–5V
1.8A
30.1k
CIN1: CDE AFK686M63G24T-F
CIN2: TDK CGA6M3X7S2A475K
COUT1: TDK C4532X7R1C336M
COUT3
: PANASONIC 20SVP100M
D1: VISHAY SS8PH9-M3/87A
L1: MSS1278-123ML
Q1: VISHAY Si7469DP
VIN
4.5V TO 55V
CIN1
68µF
63V
CIN2
4.7µF
100V
×2
15nF
220pF
0.1µF
COUT1
33µF
16V
×2
12pF
+
+
LTC3863
24
Rev. B
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APPLICATIONS INFORMATION
If RFB1 is chosen to be 187k, then RFB2 needs to be 30.1k.
The FREQ pin is tied to signal ground in order to program
the switching frequency to 350kHz. The on-time required
to generate –5V output from 55V VIN in continuous mode
can be calculated as:
tON(CCM) =
5V
+
0.5V
320kHz • 55V +5V +0.5V
( )
=260ns
This on-time, tON, is larger than LTC3863’s minimum on-
time with sufficient margin to prevent cycle skipping. Use
a lower frequency if a larger on-time margin is needed to
account for variations from minimum on-time and switch-
ing frequency. As load current decreases, the converter
will eventually start cycle skipping.
Next, set the inductor value such that the inductor ripple
current is 60% of the average inductor current at maximum
VIN = 55V and full load = 1.8A:
L=55V2• 5V +0.5V
( )
0.6 •1.8A • 320kHz • 55V +5V +0.5V
( )
2≈13.1µH
Select a standard value of 12μH.
The resulting ripple current at minimum VIN of 4.5V is:
∆IL=4.5V • 5V +0.5V
( )
12µH • 320kHz • 4.5V +5V +0.5V
( )
=0.644A
The boundary output current for continuous/discontinuous
mode is calculated:
IOUT(CDB) =55V 2•(5V +0.5V)
2 • 12µH • 320kHz • 55V +5V +0.5V
( )
2=0.59A
The maximum inductor peak current occurs at minimum
VIN of 4.5V and full load of 1.8A where LTC3863 operates
in continuous mode is:
IL(PEAK _MAX) =1.8A • 4.5V +5V +0.5V
( )
4.5V +∆IL
2
=4A +0.644A
2
≈4.32A
Next, set the RSENSE resistor value to ensure that the
converter can deliver the maximum peak inductor current
of 4.32A with sufficient margin to account for component
variations and worst-case operating conditions. Using a
30% margin factor:
RSENSE =95mV
1.3 • 4.32A
=16.9mΩ
Use a more readily available 16mΩ sense resistor. This
results in peak inductor current limit:
IL(PEAK) =95mV
16mΩ
=5.94A
Choose an inductor that has rated saturation current higher
than 5.94A with sufficient margin.
The output current limit can be calculated from the peak
inductor current limit and its minimum occurs at minimum
VIN of 5V:
I
LIMIT(MIN) =95mV
16mΩ–0.644A
2
⎛
⎝
⎜⎞
⎠
⎟•5V
4.5V +5V +0.5V
( )
=2.8A
In this example, 2.8A is the maximum output current the
switching regulator can support at VIN = 4.5V. It is larger
than the full load of 1.8A by a margin of 1A. If a larger
margin is needed, use a smaller RSENSE.
LTC3863
25
Rev. B
For more information www.analog.com
Next choose a P-channel MOSFET with the appropriate
BVDSS and ID rating. The BVDSS rating should be greater
than (55V + 5V + VD) with sufficient margin. In this ex-
ample, a good choice is the Vishay Si7469DP (BVDSS =
80V, ID = 10A, RDS(ON) = 30mΩ, ρ100°C = 1.8, VMILLER =
3.2V, CMILLER = 235pF, θJA = 24°C/W). The highest power
dissipation and the resulting junction temperature for the
P-channel MOSFET occurs at the minimum VIN of 5V and
maximum output current of 1.8A. They can be calculated
at TA = 70°C as follows:
D=5V +0.5V
4.5V +5V +0.5V ≈0.55
PPMOS =0.55 • 1.8A
1– 0.55
⎛
⎝
⎜⎞
⎠
⎟
2
•1.8 • 30mΩ
+320kHz • 235pF • 4.5V+| –5V | +0.5V
( )
2
2
•1.8A
1– 0.55
( )
•0.9Ω
4.5V – 3.2V +2Ω
3.2V
⎛
⎝
⎜⎞
⎠
⎟
≈0.475W +0.020W ≈0.495W
TJ = 70°C + 0.495W • 24°C/W = 82°C
The same calculations can be repeated for VIN(MAX) = 55V:
D=5V +0.5V
55V +5V +0.5V ≈0.091
PPMOS ≈0.091• 1.8A
1– 0.091
⎛
⎝
⎜⎞
⎠
⎟
2
•1.8 • 30mΩ
+320kHz • 235pF • 55V+| –5V | +0.5V
( )
2
2
•1.8A
1– 0.091
( )
•0.9Ω
5V – 3.2V +2Ω
3.2V
⎛
⎝
⎜⎞
⎠
⎟
≈0.019W +0.39W ≈0.411W
TJ = 70°C + 0.411W • 24°C/W = 80°C
Next choose an appropriate Schottky diode that will handle
the power requirements. The reverse voltage of the diode,
VR, should be greater than (55V + 5V). The Fairchild
S38 Schottky diode is selected (VF (3A,125°C) = 0.45V,
VR = 80V, θJA = 55°C/W) for this application. The power
dissipation and junction temperature at TA = 70° and full
load = 1.8A can be calculated as:
PDIODE = 1.8A • 0.45V = 0.81W
TJ = 70°C + 0.81W • 55°C/W = 114°C
These power dissipation calculations show that careful
attention to heat sinking will be necessary.
For the input bypass capacitors, choose low ESR ceramic
capacitors that can handle the maximum RMS current at
the minimum VIN of 4.5V:
ICIN(RMS) ≈1.8A • | –5V |
4.5V =1.9A
COUT will be selected based on the ESR that is required
to satisfy the output voltage ripple requirement. For this
design, two 47μF ceramic capacitors are chosen to offer
low ripple in both normal operation and in Burst Mode
operation.
The selected COUT must support the maximum RMS
operating current at a minimum VIN of 4.5V:
ICIN(RMS) ≈1.8A • | –5V |
4.5V
=1.9A
A soft-start time of 8ms can be programmed through a
0.1μF capacitor on the SS pin:
CSS =
8ms •10µA
0.8V
=0.1µF
Loop compensation components on the ITH pin are chosen
based on load step transient behavior (as described under
OPTI-LOOP Compensation) and is optimized for stability. A
pull-up resistor is used on the RUN pin for FMEA compli-
ance (see Failure Modes and Effects Analysis).
APPLICATIONS INFORMATION
LTC3863
26
Rev. B
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APPLICATIONS INFORMATION
An application with complementary dual outputs of ±5V
can be designed by using two LTC3863 parts with one
configured into an inverting regulator and the other into
a step-down buck regulator as shown in Figure11. Refer
to LTC3864 data sheet for the actual design of a buck
output of 5V.
Gate Driver Component Placement,
Layout and Routing
It is important to follow recommended power supply PC
board layout practices such as placing external power ele-
ments to minimize loop area and inductance in switching
paths. Be careful to pay particular attention to gate driver
component placement, layout and routing.
The effective CCAP capacitance should be greater than
0.1µF minimum in all operating conditions. Operating
voltage and temperature both decrease the rated capaci-
tance to varying degrees depending on dielectric type. The
LTC3863 is a PMOS controller with an internal gate driver
and boot-strapped LDO that regulates the differential CAP
voltage (VIN – VCAP) to 8V nominal. The CCAP capacitance
needs to be large enough to assure stability and provide
cycle-to-cycle current to the PMOS switch with minimum
series inductance. We recommend a ceramic 0.47µF 16V
capacitor with a high quality dielectric such as X5R or
X7R. Some high current applications with large Qg PMOS
switches may benefit from an even larger CCAP capacitance.
Figure 8 shows the LTC3863 Generic Application Sche-
matic which includes an optional current sense filter and
series gate resistor. Figure 9 illustrates the recommended
gate driver component placement, layout and routing of
the GATE, VIN, SENSE and CAP pins and key gate driver
components. It is recommended that the gate driver layout
follow the example shown in Figure 9 to assure proper
operation and long term reliability.
The LTC3863 gate driver should connect to the external
power elements in the following manner. First route the
VIN pin using a single low impedance isolated trace to
the positive RSENSE resistor PAD without connection to
the VIN plane. The reason for this precaution is that the
CSF
L1
Q1 D1
CAP
CCAP
PGND
LTC3863
3863 F08
SS
ITH
FREQ
SGND
GROUND
PLANE
TO PGND
RUN VIN
PLLIN/MODE
SENSE
GATE
VFBN
VFB
RITH
RSF
RSENSE
RGATE
RFREQ RFB1
RFB2
VOUT
VIN
CIN
+
–
CITH
CPITH
CINB
CSS
COUT
CFB2
Figure 8. LTC3863 Generic Application Schematic with Optional
Current Sense Filter and Series Gate Resistor
RGATE
TO Q1 GATE
TO RSENSE+
3863 F09
CINB
CCAP
GATE
SENSE
CAP
VIN
CSF
RSF
TO RSENSE–
Figure 9. LTC3863 Recommended Gate Driver PC Board
Placement, Layout and Routing
VIN pin is internally Kelvin connected to the current sense
comparator, internal VIN power and the PMOS gate driver.
Connecting the VIN pin to the VIN power plane adds noise
and can result in jitter or instability. Figure 9 shows a single
VIN trace from the positive RSENSE pad connected to CSF,
CCAP, VIN pad and CINB. The total trace length to RSENSE
should be minimized and the capacitors CCF, CCAP and
CINB should be placed near the VIN pin of the LTC3863.
CCAP should be placed near the VIN and CAP pins. Figure 9
shows CCAP placed adjacent to the VIN and CAP pins with
LTC3863
27
Rev. B
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APPLICATIONS INFORMATION
SENSE routed between the pads. This is the recommended
layout and results in the minimum parasitic inductance.
The gate driver is capable of providing high peak current.
Parasitic inductance in the gate drive and the series in-
ductance between VIN to CAP can cause a voltage spike
between VIN and CAP on each switching cycle. The voltage
spike can result in electrical over-stress to the gate driver
and can result in gate driver failures in extreme cases. It
is recommended to follow the example shown in Figure 9
for the placement of CCAP as close as is practical.
RGATE resistor pads can be added with a 0Ω resistor to
allow the damping resistor to be added later. The total
length of the gate drive trace to the PMOS gate should
be minimized and ideally be less than 1cm. In most cases
with a good layout the RGATE resistor is not needed. The
RGATE resistor should be located near the gate pin to re-
duce peak current through GATE and minimize reflected
noise on the gate pin.
The RSF and CSF pads can be added with a zero ohm resis-
tor for RSF and CSF not populated. In most applications,
external filtering is not needed. The current sense filter
RSF and CSF can be added later if noise if demonstrated
to be a problem.
The bypass capacitor CINB is used to locally filter the
VIN supply. CINB should be tied to the VIN pin trace and
to the PGND exposed pad. The CINB positive pad should
connect to RSENSE positive though the VIN pin trace. The
CINB ground trace should connect to the PGND exposed
pad connection.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3863.
1. Multilayer boards with dedicated ground layers are
preferable for reduced noise and for heat sinking pur-
poses. Use wide rails and/or entire planes for VIN, VOUT
and GND for good filtering and minimal copper loss. If
a ground layer is used, then it should be immediately
below (and/or above) the routing layer for the power
train components which consist of CIN, sense resistor,
P-channel MOSFET, Schottky diode, inductor, and COUT.
Flood unused areas of all layers with copper for better
heat sinking.
2. Keep signal and power grounds separate except at the
point where they are shorted together. Short the signal
and power ground together only at a single point with a
narrow PCB trace (or single via in a multilayer board).
All power train components should be referenced to
power ground and all small-signal components (e.g.,
CITH1, RFREQ, CSS etc.) should be referenced to the
signal ground.
3. Place CIN, sense resistor, P-channel MOSFET, induc-
tor, and primary COUT capacitors close together in
one compact area. The junction connecting the drain
of the P-channel MOSFET, cathode of the Schottky,
and (+) terminal of the inductor (this junction is com-
monly referred to as switch or phase node) should be
compact but be large enough to handle the inductor
currents without large copper losses. Place the sense
resistor and source of P-channel MOSFET as close
as possible to the (+) plate of the CIN capacitor(s)
that provides the bulk of the AC current (these are
normally the ceramic capacitors), and connect the (–)
terminal of the inductor as close as possible to the
(–) terminal of the same CIN capacitor(s). The high
dI/dt loop formed by CIN, the MOSFET, and the Schottky
diode should have short leads and PCB trace lengths to
minimize high frequency EMI and voltage stress from
inductive ringing. The (+) terminal of the primary COUT
capacitor(s) which filter the bulk of the inductor ripple
current (these are normally the ceramic capacitors)
should also be connected close to the (–) terminal of CIN.
4. Place Pins 7 to 12 facing the power train components.
Keep high dV/dt signals on GATE and switch away from
sensitive small-signal traces and components.
5. Place the sense resistor close to the (+) terminal of CIN
and source of P-channel MOSFET. Use a Kelvin (4-wire)
connection across the sense resistor and route the traces
together as a differential pair into the VIN and SENSE
pins. An optional RC filter could be placed near the VIN
and SENSE pins to filter the current sense signal.
LTC3863
28
Rev. B
For more information www.analog.com
6. Place the resistive feedback divider RFB1/2 as close as
possible to the VFB and VFBN pins. The (–) terminal
of the feedback divider should connect to the output
regulation point and the (+) terminal of the feedback
divider should connect to VFB.
7. Place the ceramic CCAP capacitor as close as possible to
the VIN and CAP pins. This capacitor provides the gate
discharging current for the power P-channel MOSFET.
8.
Place small signal components as close to their respective
pins as possible. This minimizes the possibility of PCB
noise coupling into these pins. Give priority to VFB, ITH,
and FREQ pins. Use sufficient isolation when routing a
clock signal into the PLLIN /MODE pin so that the clock
does not couple into sensitive small-signal pins.
Failure Mode and Effects Analysis (FMEA)
A FMEA study on the LTC3863 has been conducted through
adjacent pin opens and shorts. The device was tested in
a step-down application (Figure 15) from VIN = 12V to
VOUT = –5V with a current load of 2A on the output. One
group of tests involved the application being monitored
while each pin was disconnected from the PC board
and left open while all other pins remained intact. The
other group of tests involved each pin being shorted to
its adjacent pins while all other pins were connected as
it would be normally in the application. The results are
shown in Table 2.
For FMEA compliance, the following design implementa-
tions are recommended:
• If the RUN pin is being pulled up to a voltage greater
than 6V, then it is done so through a pull-up resistor
(100k to 1M) so that the VFBN pin is not damaged in
case of a RUN to VFBN short.
• The gate of the external P-channel MOSFET should be
pulled through a resistor (20k to 100k) to the input sup-
ply, VIN so that the P-channel MOSFET is guaranteed
to turn off in case of a GATE open.
• To protect against the VFBN open condition it is neces-
sary to add an output shutdown clamp. The output
shutdown clamp is comprised of a Zener, VZ, NPN and
Zener bias resistor, RZ, to ground as found in Figure10.
The clamp voltage will be the Zener forward voltage VZ
plus a VBE. The clamp needs to be designed such that
the worst-case minimum Zener voltage is less than
the maximum operating voltage. The worst-case Zener
leakage current times the Zener bias resistor should not
exceed 200mV.
CZ
2N3904
SS
RZVZ
–VOUT
3863 F10
Figure 10.
LTC3863
29
Rev. B
For more information www.analog.com
APPLICATIONS INFORMATION
Table 2
FAILURE MODE VOUT IOUT IVIN f
RECOVERY
WHEN
FAULT IS
REMOVED? BEHAVIOR
None –5V 1A 453mA 350kHz N/A Normal Operation.
Pin Open
Open Pin 1 (PLLIN/MODE) –5V 1A 453mA 350kHz OK Pin already left open in normal application, so no difference.
Open Pin 2 (FREQ) –5V 1A 453mA 535kHz OK Frequency jumps to default open value.
Open Pin 3 (GND) –5V 1A 453mA 350kHz OK Exposed pad still provides GND connection to device.
Open Pin 4 (SS) –5V 1A 453mA 350kHz OK External soft-start removed, but internal soft-start still available.
Open Pin 5 (VFB) 0V 0A 0.7mA 0kHz OK Controller stops switching. VFB internally self biases HI to prevent
switching.
Open Pin 6 (ITH) –5V 1A 507mA 40kHz OK Output still regulating, but the switching is erratic. Loop not stable.
Open Pin 7 (VFBN) –6V pk 1A 502mA 350kHz OK Use a 5.1V Zener VZ, 10k RZ and 0.01µF CZ. Output Voltage is –6V
peak and averages –4.9V.
Open Pin 8 (RUN) –5V 1A 453mA 350kHz OK Controller does not start-up.
Open Pin 9 (CAP) –5V 1A 453mA 350kHz OK More jitter during switching, but regulates normally.
Open Pin 10 (SENSE) 0V 0A 0.7mA 0kHz OK SENSE internally prebiases to 0.6V below VIN. This prevents
controller from switching.
Open Pin 11 (VIN) –5.4V 1A 597mA 20kHz OK VIN able to bias internally through SENSE. Regulates with high
VOUT ripple.
Open Pin 12 (GATE) 0V 0A 0.7mA 0kHz OK Gate does not drive external power FET, preventing output
regulation.
Open Pin 13 (PGND) –5V 453mA 350kHz OK Pin 3 (GND) still provides GND connection to device.
Pins Shorted
Short Pins 1, 2
(PLLIN/MODE and FREQ)
–5V 1A 453mA 350kHz OK Burst Mode operation disabled, but runs normally as in pulse-
skipping mode.
Short Pins 2, 3
(FREQ and GND)
–5V 1A 453mA 0kHz OK FREQ already shorted to GND, so regulates normally.
Short Pins 3, 4
(GND and SS)
0V 0A 0.7mA 0kHz OK SS short to GND prevents device from starting up.
Short Pins 4, 5
(SS and VFB)
–1V(DC)
–3VP-P
50mA 9mA Erratic OK VOUT oscillates from 0V to 3V.
Short Pins 5, 6
(VFB and ITH)
–3.15V 625mA 181mA 350kHz OK Controller loop does not regulate to proper output voltage.
Short Pins 7, 8
(VFBN and RUN)
5V 0A 860µA 350kHz OK Controller does not start-up.
Short Pins 8, 9
(RUN and CAP)
–5V 1A 453mA 350kHz OK Able to start-up and regulate normally.
Short Pins 9, 10
(CAP and SENSE)
0V 0A 181mA 0kHz OK CAP ~ VIN, which prevents turning on external P-MOSFET.
Short Pins 10, 11
(SENSE and VIN)
–5V 1A 453mA 50kHz OK Regulates with high VOUT ripple.
Short Pins 11, 12
(VIN and GATE)
0V 0A 29mA 0kHz OK Power MOSFET is always kept OFF, preventing regulation.
LTC3863
30
Rev. B
For more information www.analog.com
Figure 11. Design Example, 4.5V to 55V Input, ±5V, 1.8A at 320kHz
Positive 5V Efficiency Negative 5V Efficiency
Positive 5V Gain/Phase Negative 5V Gain/Phase
TYPICAL APPLICATIONS
16mΩ
L1
12µH
Q1 D1
CAP
0.47µF
PGND
LTC3863
3863 F11a
SS
ITH
FREQ
SGND
RUN VIN
PLLIN/MODE
SENSE
GATE
VFBN
VFB
10k
52.3k 187k
COUT3
100µF
20V
VOUT
–5V
1.8A
30.1k
D2: DIODES SBR3U100LP-7
L2: TOKO B1134AS-100M
Q2: FAIRCHILD FDMC5614P
COUT4: TDK C4532X5R0J07M
COUT5: PANASONIC EEE-FK1V221P
CIN1: CDE AFK686M63G24T-F
CIN2: TDK CGA6M3X7S2A475K
COUT1 TDK C4532X7R1C336M
COUT3 PANASONIC 20SVP100M
D1: VISHAY SS8PH9-M3/87A
L1: MSS1278-123ML
Q1: VISHAY Si7469DP
VIN*
4.5V TO 55V
CIN1
68µF
63V
CIN2
4.7µF
100V
×2
15nF
220pF
0.1µF0.1µF
0.1µF
COUT1
33µF
16V
×2
12pF
25mΩ
L2
10µH
Q2
D2
CAP
0.47µF
PGND
LTC3864
SS
ITH
FREQ
SGND
RUN
VIN
PLLIN/MODE
SENSE
GATE
PGOOD
VFB
15k
52.3k
COUT5
220µF
35V
COUT4
100µF
6.3V
*VOUT FOLLOWS VIN
WHEN 3.5V < VIN < 5.2V
NOTE: LTC3863 CAN BE USED IN PLACE
OF LTC3864 IF VFBN IS TIED > 2V
VOUT*
5V
1.8A 10nF
220pF
422k
80.6k
LTC6908-1
V+SYNC1
GND SYNC2
SET MOD
320kHz
316k
+
+
+
Gain/Phase Measurements Taken with OMICRON Lab Bode 100 Vector Network Analyzer.
LOAD CURRENT (A)
0.002
40
EFFICIENCY (%)
POWER LOSS (W)
50
60
70
80
0.02 0.2 2
3863 F11b
30
20
10
0
90
100
4
5
6
7
8
3
2
1
0
9
10
EFFICIENCY
POWER LOSS
VIN = 12V
VOUT = 5V
PULSE-SKIPPING MODE
Burst Mode OPERATION
FREQUENCY (kHz)
1
–30
GAIN (dB)
PHASE (DEG)
–10
10
30
50
10 100
3863 F11c
70
–20
0
20
40
60
–45
–15
15
0
45
75
105
–30
PHASE
GAIN
30
60
90
LOAD CURRENT (A)
0.002
40
EFFICIENCY (%)
POWER LOSS (W)
60
90
80
0.02 0.2 2
3863 F11d
20
30
50
70
10
0
4
6
9
8
2
3
5
7
1
0
EFFICIENCY
POWER LOSS
VIN = 12V
VOUT = –5V
PULSE-SKIPPING MODE
Burst Mode OPERATION
FREQUENCY (kHz)
1
–30
GAIN (dB)
PHASE (DEG)
–20
–10
0
10
20
30
40
50
10 100
3863 F11e
60
–45
–30
–15
0
15
30
45
60
75
90
PHASE
GAIN
LTC3863
31
Rev. B
For more information www.analog.com
TYPICAL APPLICATIONS
Figure 12. 5V to 23V Input, –18V/700mA Output, 750kHz Inverting Converter
Efficiency Gain/Phase
Gain/Phase Measurements Taken with OMICRON Lab Bode 100 Vector Network Analyzer.
750kHz
25mΩ
L1
15µH
Q1 D1
CAP
0.47µF
PGND
LTC3863
3863 F12a
SS
ITH
FREQ
SGND
RUN VIN
PLLIN/MODE
SENSE
GATE
VFBN
VFB
36.5k
100k 191k
VOUT
–18V
700mA
8.45k
CIN1: NICHICON UCJ1H101MCL1GS
CIN2: TDK C3225X7R1E108M
COUT1: MURATA GRM32DR61E106KA12L
COUT3: PANASONIC 20SVO100M
D1: DIODES SBR8U60P5
L1: WURTH 744770115
Q1: VISHAY SI7469DP
VIN
5V TO 23V
CIN2
10µF
25V
×2
COUT1
10µF
25V
×2
CIN1
100µF
50V
COUT3
100µF
20V
4.7nF
0.1µF
50pF
47pF
+
+
LOAD CURRENT (A)
0.001
40
EFFICIENCY (%)
POWER LOSS (W)
60
90
80
0.01 0.1 1
3863 F12b
20
30
50
70
10
0
4
6
9
8
2
3
5
7
1
0
EFFICIENCY
POWER LOSS
VIN = 12V
VOUT = –18V
PULSE-SKIPPING MODE
Burst Mode OPERATION
FREQUENCY (kHz)
1
–30
GAIN (dB)
PHASE (DEG)
–20
–10
0
10
20
30
40
50
10 100
3863 F12c
60
–45
–30
–15
0
15
30
45
60
75
90
PHASE
GAIN
VIN = 12V
VOUT = –18V
LTC3863
32
Rev. B
For more information www.analog.com
TYPICAL APPLICATIONS
Figure 13. 3.5V to 28V Input, –0.4V/200mA Output, 80kHz Inverting Converter
Efficiency Gain/Phase
Gain/Phase Measurements Taken with OMICRON Lab Bode 100 Vector Network Analyzer.
80kHz
82mΩ
L1
15µH
Q1 D1
CAP
0.47µF
PGND
LTC3863
3863 F13a
SS
ITH
FREQ
SGND
RUN VIN
PLLIN/MODE
SENSE
GATE
VFBN
VFB
5k
61.9k 95.3k
VOUT
–0.4V
200mA
191k
CIN1: NICHICON UCJ1H101MCL1GS
CIN2: MURATA GRM32ER71H108H
COUT1: TDK C4532X7R1C336M
COUT3: PANASONIC 16TQC150MYF
D1: DIODES B540C-13-F
L1: WURTH 7447779115
Q1: FAIRCHILD FDMC5614P
VIN
3.5V TO 28V
CIN1
100µF
50V
COUT1
10µF
25V
×2
CIN2
10µF
50V
×2
COUT3
100µF
20V
3.3nF
0.1µF
82pF
10pF
+
+
LOAD CURRENT (A)
EFFICIENCY (%)
POWER LOSS (W)
50
40
30
3863 F13b
0
20
10
0.5
0.4
0.3
0
0.2
0.1
0.2
0.002 0.02
EFFICIENCY
POWER LOSS
VIN = 12V
VOUT = –0.4V
PULSE-SKIPPING MODE
Burst Mode OPERATION
FREQUENCY (kHz)
1
–30
GAIN (dB)
PHASE (DEG)
–20
–10
0
10
20
30
40
50
10 100
3863 F13c
60
–45
–30
–15
0
15
30
45
60
75
90
PHASE
GAIN
VIN = 12V
VOUT = –0.4V
LTC3863
33
Rev. B
For more information www.analog.com
TYPICAL APPLICATIONS
Efficiency Gain/Phase
Figure 14. 12V to 42V Input, –48V/300mA Output, 440kHz Inverting Converter
Gain/Phase Measurements Taken with OMICRON Lab Bode 100 Vector Network Analyzer.
440kHz
27mΩ
L1
10µH
Q1 D1
CAP
0.47µF
PGND
LTC3863
3863 F14a
SS
ITH
FREQ
SGND
RUN VIN
PLLIN/MODE
SENSE
GATE
VFBN
VFB
1M
64.9k 196k
VOUT
–48V
300mA
3.32k
CIN1: NICHICON UCJ1H101MCL1GS
CIN2: MURATA GRM32ER71H106H
COUT1: TDK CGA6M3X7S2A475K
COUT3: UCC EMVH630ARA101MKE
D1: DIODES PDS5100H
L1: WURTH 744314101
Q1: VISHAY SI7113DN
VIN
12V TO 42V
CIN1
100µF
50V
COUT1
4.7µF
100V
×2
CIN2
10µF
50V
×2
COUT3
100µF
63V
18nF
0.1µF
100pF
+
+
LOAD CURRENT (A)
0.001
40
EFFICIENCY (%)
POWER LOSS (W)
60
90
80
0.01 0.1
3863 F14b
20
30
50
70
10
0
4
6
9
8
2
3
5
7
1
0
EFFICIENCY
POWER LOSS
VIN = 24V
VOUT = –48V
PULSE-SKIPPING MODE
Burst Mode OPERATION
FREQUENCY (kHz)
2
–30
GAIN (dB)
PHASE (DEG)
–10
10
30
50
20 200
3863 F14c
70
–20
0
20
40
60
–45
–15
15
0
45
75
105
–30
PHASE
GAIN
30
60
90
VIN = 24V
VOUT = –48V
LTC3863
34
Rev. B
For more information www.analog.com
Figure 15. 4.5V to 16V Input, –5V/1.7A, –12V/1A Output, 350kHz Inverting Converter
TYPICAL APPLICATIONS
350kHz
16mΩ
L1
10µH
Q1 D1
CAP
0.47µF
PGND
LTC3863
3863 F15a
SS
ITH
FREQ
SGND
RUN VIN
PLLIN/MODE
SENSE
GATE
VFBN
VFB
14.7k
61.9k
RFBO
698k
VOUT
–5V 1.7A (SHORT RFBO)
–12V 1A
80.6k
CIN1: PANASONIC 20SVP100M
CIN2: TDK C3225X7R1E106M
COUT1: TDK C4532X7R1C336M
COUT3: PANASONIC 16TQC150MYF
D1: DIODES B540C
L1: TOKO 919AS-100M
Q1: VISHAY SI7129DN-T1-GE3
VIN
4.5V TO 16V
CIN1
100µF
20V
COUT1
33µF
16V
×2
CIN2
10µF
25V
×2
COUT3
150µF
16V
×2
27nF
0.1µF
390pF
68pF
511k
+
+
–5V Efficiency –12V Efficiency
LOAD CURRENT (A)
0.002
40
EFFICIENCY (%)
POWER LOSS (W)
60
90
80
0.02 0.2 2
3863 F15b
20
30
50
70
10
0
4
6
9
8
2
3
5
7
1
0
EFFICIENCY
POWER LOSS
VIN = 12V
VOUT = –5V
PULSE-SKIPPING MODE
Burst Mode OPERATION
LOAD CURRENT (A)
0.002
40
EFFICIENCY (%)
POWER LOSS (W)
60
90
80
0.02 0.2 2
3863 F15b
20
30
50
70
10
0
4
6
9
8
2
3
5
7
1
0
EFFICIENCY
POWER LOSS
VIN = 12V
VOUT = –12V
PULSE-SKIPPING MODE
Burst Mode OPERATION
LTC3863
35
Rev. B
For more information www.analog.com
PACKAGE DESCRIPTION
4.00 ±0.10
(2 SIDES)
3.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.70 ±0.10
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
2.50 REF
16
127
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(UE12/DE12) DFN 0806 REV D
2.50 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.20 ±0.05
0.70 ±0.05
3.60 ±0.05
PACKAGE OUTLINE
3.30 ±0.10
0.25 ±0.05
0.50 BSC
1.70 ±0.05
3.30 ±0.05
0.50 BSC
0.25 ±0.05
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695 Rev D)
LTC3863
36
Rev. B
For more information www.analog.com
PACKAGE DESCRIPTION
MSOP (MSE12) 0911 REV F
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.22 –0.38
(.009 – .015)
TYP
0.86
(.034)
REF
0.650
(.0256)
BSC
12
12 11 10 9 8 7
7
DETAIL “B”
16
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
RECOMMENDED SOLDER PAD LAYOUT
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
2.845 ±0.102
(.112 ±.004)
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102
(.065 ±.004)
0.1016 ±0.0508
(.004 ±.002)
1 2 3 4 5 6
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.406 ±0.076
(.016 ±.003)
REF
4.90 ±0.152
(.193 ±.006)
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.12 REF
0.35
REF
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
0.42 ±0.038
(.0165 ±.0015)
TYP
0.65
(.0256)
BSC
MSE Package
12-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1666 Rev F)
LTC3863
37
Rev. B
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 6/14 PLL/MODE, VFNB and ITH Pin Descriptions Updated
Added Paragraph Discussing RFB2 Sizing and Equation
Updated VOUT and ∆IL Equations
Updated IOUT(CDB), IL(PEAK_MAX) and RSENSE Equations
8
13
23
24
B 7/19 Fixed IL Formula 24
LTC3863
38
Rev. B
For more information www.analog.com
07/19
www.analog.com
ANALOG DEVICES, INC. 2013–2019
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LTC3864 Low IQ, High Voltage Step-Down DC/DC Controller
with 100% Duty Cycle
Fixed Frequency 50kHz to 850kHz, 3.5V≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ VIN,
IQ = 40µA, MSOP-12E, 3mm × 4mm DFN-12
LTC3891 60V, Low IQ, Synchronous Step-Down DC/DC
Controller
PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 24V,
IQ = 50µA
LTC3890/LTC3890-1
LTC3890-2/LTC3890-3
60V, Low IQ, Dual 2-Phase Synchronous
Step-Down DC/DC Controller
PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 24V,
IQ = 50µA
LTC3630 High Efficiency, 65V, 500mA Synchronous
Step-Down Regulator
4V ≤ VIN ≤ 65V, 0.8V ≤ VOUT ≤ VIN, IQ = 12µA, 3mm × 5mm DFN-16 and
MSOP-16E
LTC3834/LTC3834-1
LTC3835/LTC3835-1
Low IQ, Single Output Synchronous Step-Down
DC/DC Controllers with 99% Duty Cycle
PLL Fixed Frequency 140kHz to 650kHz, 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 10V,
IQ = 30µA/80µA
LT3758A High Input Voltage, Boost, Flyback, SEPIC and
Inverting Controller
5.5V ≤ VIN ≤ 100V, Positive or Negative VOUT, 3mm × 3mm DFN-10 and
MSOP-10E
LTC3826/LTC3826-1 Low IQ, Dual Output 2-Phase Synchronous
Step-Down DC/DC Controllers with 99% Duty Cycle
PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 10V,
IQ = 30µA
LTC3859AL Low IQ, Triple Output Buck/Buck/Boost
Synchronous DC/DC Controller
All Outputs Remain in Regulation Through Cold Crank 2.5V ≤ VIN ≤ 38V,
VOUT(BUCKS) Up to 24V, VOUT(BOOST) Up to 60V, IQ = 28µA
Efficiency
Gain/Phase
Figure 16. 12V to 40V Input, –150V/40mA Output, 320kHz Inverting Converter
320kHz
39mΩ
L1
15µH
Q1 D1
CAP
0.47µF
PGND
LTC3863
3863 F16a
SS
ITH
FREQ
SGND
RUN VIN
PLLIN/MODE
SENSE
GATE
VFBN
VFB
845k
52.3k
1M
VOUT
–150V
40mA
10.7k
CIN1: CDE AFK686M63G24T-F
CIN2: MURATA GRM32ER71H106H
COUT1: TDK CGA8P3X7T2E105K/SOFT
COUT3: LELON VEJ-470M2DTR-1616
D1: ON SEMI MBRS3201T3G
L1: TOKO 1217AS-H-150M
Q1: VISHAY SI7119
VIN
12V TO 40V
CIN3
68µF
63V
COUT1
1µF
250V
×2
CIN2
10µF
50V
×2
COUT3
47µF
200V
180pF
0.1µF
1.8pF
3.3pF
1M
+
+
LOAD CURRENT (A)
0.001
40
EFFICIENCY (%)
POWER LOSS (W)
60
90
80
0.01 0.1
3863 F16b
20
30
50
70
10
0
4
6
9
8
2
3
5
7
1
0
EFFICIENCY
POWER LOSS
VIN = 24V
VOUT = –150V
PULSE-SKIPPING MODE
Burst Mode OPERATION
FREQUENCY (Hz)
0.1
0
EFFICIENCY (%)
PHASE (DEG)
10
20
1 10 100
3963 F16c
–10
–20
40
30
–5
5
15
–15
35
25
15
45
75
–15
–45
135
105
0
30
60
–30
120
90
PHASE
GAIN
VIN = 24V
VOUT = –150V
Gain/Phase Measurements Taken with OMICRON Lab Bode 100 Vector Network Analyzer.