KM616FV2000, KM616FS2000, KM616FR2000 Family CMOS SRAM ocument Title 128K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Design target October 2, 1996 Advance 0.1 Initial draft - Add KM616FV2000 Family - Erase KM616FU1000 Family and KM616FS1000 Family supprot 2.3~3.3V operating Vcc. - Concept change high power version to low low power version ISB1=10A(Max) - Add super low power version with special handling ISB1=2.0A(Max) - Reduce Icc & Icc1 Write : 25mA to 20mA at Vcc=3.6V(Max) December 1, 1996 Preliminary 1.0 Finalize - Change datasheet format - Erase reverse type package March 4, 1998 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 1.0 March 1998 KM616FV2000, KM616FS2000, KM616FR2000 Family CMOS SRAM 128Kx16 bit Super Low Power and Low Voltage Full CMOS Static RAM FEATURES GENERAL DESCRIPTION * Process Technology : Full CMOS * Organization : 128Kx16 * Power Supply Voltage KM616FV2000 Family : 3.0V ~ 3.6V KM616FS2000 Family : 2.3V ~ 3.3V KM616FR2000 Family : 1.8V ~ 2.7V * Low Data Retention Voltage : 1.5V(Min) * Three state output status and TTL Compatible * Package Type : 44-TSOP2-400F The KM616FV2000, KM616FS2000 and KM616FR2000 families are fabricated by SAMSUNGs advanced Full CMOS process technology. The families support various operating temperature ranges for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range Speed(ns) 3.0~3.6V 701)/85@VCC=3.30.3V KM616FV2000 KM616FS2000 Commercial(0~70C) 2.3~3.3V Standby (ISB1, Max) 80mA 1) 50mA 120 /150@VCC=2.50.2V 1.8~2.7V 3001)@VCC=2.00.2V KM616FV2000I 3.0~3.6V 701)/85@VCC=3.30.3V Industrial(-40~85C) 2.3~3.3V KM616FR2000I 1.8~2.7V PKG Type 80mA 85@VCC=3.00.3V KM616FR2000 KM616FS2000I Operating (ICC2, Max) 10A2) 20mA 80mA 85@VCC=3.00.3V 80mA 1201)/150@VCC=2.50.2V 50mA 3001)@VCC=2.00.2V 20mA 44-TSOP2Forward 1. The parameter is measured with 30pF test load. 2. Super low power product=2A with special handling. PIN DESCRIPTION A4 A3 A2 A1 A0 CS I/OI I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44-TSOP2 Forward 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 FUNCTIONAL BLOCK DIAGRAM A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 N.C A8 A9 A10 A11 N.C Clk gen. Precharge circuit. A4 Vcc Vss A3 A2 A1 A0 Row select Memory array 1024 rows 128x16 columns Data cont I/O Circuit Column select A16 A14 A15 A12 A13 I/O1~I/O8 Data cont I/O9~I/O16 Data cont Name Function Name Function CS Chip Select Input LB Lower Byte(I/O1~8) OE Output Enable Input UB Upper Byte(I/O9~16) WE Write Enable Input Vcc Power Address Inputs Vss Ground N.C. No Connection A0~A16 A9 A8 A5 A6 A7 A11 A10 WE OE UB I/O1~I/O16 Data Inputs/Outputs Control logic LB CS SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 1.0 March 1998 KM616FV2000, KM616FS2000, KM616FR2000 Family CMOS SRAM PRODUCT LIST Commercial Temperature Products(0~70C) Part Name Industrial Temperature Products(-40~85C) Function Part Name Function KM616FV2000T-7 KM616FV2000T-8 44-TSOP2 F, 70ns, 3.3V, LL 44-TSOP2 F, 85ns, 3.3V, LL KM616FV2000TI-7 KM616FV2000TI-8 44-TSOP2 F, 70ns, 3.3V, LL 44-TSOP2 F, 85ns, 3.3V, LL KM616FS2000T-12 KM616FS2000T-15 44-TSOP2 F, 120/85ns, 2.5/3.0V, LL 44-TSOP2 F, 150/85ns, 2.5/3.0V, LL KM616FS2000TI-12 KM616FS2000TI-15 44-TSOP2 F, 120/85ns, 2.5/3.0V, LL 44-TSOP2 F, 150/85ns, 2.5/3.0V, LL KM616FR2000T-30 44-TSOP2 F, 300ns, 2.0/2.5V, LL KM616FR2000TI-30 44-TSOP2 F, 300ns, 2.0/2.5V, LL FUNCTIONAL DESCRIPTION CS OE WE LB UB I/O1~8 I/O9~16 Mode Power X 1) X 1) High-Z High-Z Deselected Standby 1) X 1) High-Z High-Z Output Disabled Active High-Z High-Z Output Disabled Active H X L H H X L X1) X1) H H L L H L H Dout High-Z Lower Byte Read Active L L H H L High-Z Dout Upper Byte Read Active L L H L L Dout Dout Word Read Active L X1) L L H Din High-Z Lower Byte Write Active L X 1) L H L High-Z Din Upper Byte Write Active L X1) L L L Din Din Word Write Active 1) X 1) 1. X means dont care. (Must be in low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Soldering temperature and time Symbol Ratings Unit Remark VIN,VOUT -0.2 to 3.6V 2) V - VCC -0.2 to 4.0V3) V - PD 1.0 W - TSTG -55 to 150 C - TA 0 to 70 C KM616FV2000, KM616FS2000, KM616FR2000 -40 to 85 C KM616FV2000I, KM616FS2000I, KM616FR2000I - - TSOLDER 260C, 5sec (Lead Only) 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VIN/VOUT=-0.2 to 3.9V for KM616FV2000 Family. 3. VCC=-0.2 to 4.6V for KM616FV2000 Family 3 Revision 1.0 March 1998 KM616FV2000, KM616FS2000, KM616FR2000 Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS1) Item Symbol Supply voltage Vcc Ground Product Min Typ Max KM616FV2000 Family 3.0 3.3 3.6 KM616FS2000 Family 2.3 2.5/3.0 3.3 KM616FR2000 Family 1.8 2.0/2.5 2.7 0 0 0 V - Vcc+0.22) V - 0.4 V Vss All Family KM616FV2000 Family Input high voltage VIH KM616FS2000 Family KM616FR2000 Family Vcc=3.30.3V 2.2 Vcc=3.00.3V 2.2 Vcc=2.50.2V 2.0 Vcc=2.50.2V 2.0 Vcc=2.00.2V Input low voltage VIL Unit V 1.6 All Family -0.23) Note 1 Commercial Product : TA=0 to 70C, unless otherwise specified Industrial Product : TA=-40 to 85C, unless otherwise specified 2. Overshoot : Vcc + 1.0V in case of pulse width 20ns 3. Undershoot : -1.0V in case of pulse width 20ns 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25C) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Item Min Typ Max Unit ILI VIN=Vss to Vcc -1 - 1 A Output leakage current ILO CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 - 1 A Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIL or VIH, Read - - 3 mA ICC1 Cycle time=1s, 100% duty, IIO=0mA, CS0.2V, VIN0.2V or VINVCC-0.2V Read - - 7 Write - - 20 Input leakage current Symbol Test Conditions Average operating current ICC2 Output low voltage VOL Vcc=3.3V@70ns - - 70 Vcc=2.7V@120ns - - 60 Vcc=2.2V@300ns - - 20 2.1mA at Vcc=3.0/3.3V - - 0.4 0.5mA at Vcc=2.5V - - 0.4 Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIL or VIH IOL 0.33mA at Vcc=2.0V Output high voltage VOH IOH - - 0.4 -1.0mA at Vcc=3.0/3.3V 2.4 - - -0.5mA at Vcc=2.5V 2.0 - - -0.44mA at Vcc=2.0V 1.6 - - mA mA V V Standby Current(TTL) ISB CS=VIH, Other inputs=VIL or VIH - - 0.3 mA Standby Current(CMOS) ISB1 CSVcc-0.2V, Other inputs=0~Vcc - - 101) A 1. Super low power product=2A with special handling. 4 Revision 1.0 March 1998 KM616FV2000, KM616FS2000, KM616FR2000 Family CMOS SRAM AC OPERATING CONDITIONS VTM3) TEST CONDITIONS (Test Load and Test Input/Output Reference) R12) Input pulse level : 0.4 to 2.2V for Vcc=3.3V, 3.0V, 2.5V 0.4 to 1.8V for Vcc=2.0V Input rising and falling time : 5ns Input and output reference voltage : 1.5V for Vcc=3.3V, 3.0V 1.1V for Vcc=2.5V 0.9V for Vcc=2.0V Output load (See right) : CL=100pF+1TTL CL=30pF+1TTL CL1) R23) 1. Including scope and jig capacitance 2. R1=3070, R2=3150 3. VTM =2.8V for VCC=3.0/3.3V =2.3V for VCC=2.5V =1.8V for VCC=2.0V AC CHARACTERISTICS (Commercial product :TA=0 to 70C, Industrial product : TA=-40 to 85C KM616FV2000 Family : Vcc=3.0~3.6V, KM616FS2000 Family : Vcc=2.3~3.3V, KM616FR2000 Family : Vcc=1.8~2.7V) Speed Bins Parameter List Symbol 85ns 120ns 150ns 300ns Units Min Max Min Max Min Max Min Max Min Max tRC 70 - 85 - 120 - 150 - 300 - ns Address access time tAA - 70 - 85 - 120 - 150 - 300 ns Chip select to output tCO - 70 - 85 - 120 - 150 - 300 ns Output enable to valid output tOE - 35 - 45 - 60 - 75 - 150 ns UB, LB Access Time tBA - 35 - 45 - 60 - 75 - 150 ns Chip select to low-Z output tLZ 10 - 10 - 20 - 20 - 50 - ns Output enable to low-Z output tOLZ, tBLZ 5 - 5 - 20 - 20 - 30 - ns Chip disable to high-Z output tHZ 0 25 0 25 0 35 0 40 0 60 ns tOHZ, tBHZ 0 25 0 25 0 35 0 40 0 60 ns tOH 10 - 15 - 15 - 15 - 30 - ns Write cycle time tWC 70 - 85 - 120 - 150 - 300 - ns Chip select to end of write tCW 60 - 70 - 100 - 120 - 300 - ns Read cycle time Read 70ns Output disable to high-Z output Output hold from address change Address set-up time tAS 0 - 0 - 0 - 0 - 0 - ns Address valid to end of write tAW 65 - 70 - 100 - 120 - 300 - ns Write pulse width tWP 55 - 60 - 80 - 100 - 200 - ns tBW 65 - 70 - 100 - 120 - 300 - ns Write recovery time tWR 0 - 0 - 0 - 0 - 0 - ns Write to output high-Z tWHZ 0 25 0 25 0 35 0 40 0 60 ns Data to write time overlap tDW 30 - 35 - 50 - 60 - 120 - ns Write UB, LB Valid to End of Write Data hold from write time tDH 0 - 0 - 0 - 0 - 0 - ns End write to output low-Z tOW 5 - 5 - 5 - 5 - 20 - ns DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Vcc for data retention VDR CSVcc-0.2V Data retention current IDR Vcc=3.0V, CSVcc-0.2V Data retention set-up time tSDR Recovery time tRDR See data retention waveform Min Typ Max Unit 1.5 - 3.6 V A - - 101) 0 - - tRC - - ns 1. Super low power product=2A with special handling. 5 Revision 1.0 March 1998 KM616FV2000, KM616FS2000, KM616FR2000 Family CMOS SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO CS tHZ tBA UB, LB tBHZ tOE OE tOLZ tBLZ Data out High-Z tOHZ tLZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 1.0 March 1998 KM616FV2000, KM616FS2000, KM616FR2000 Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) tWR(4) CS tAW tBW UB, LB tWP(1) WE tAS(3) tDW Data in High-Z tDH tWHZ Data out High-Z Data Valid tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS tAW tBW UB, LB tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z 7 Revision 1.0 March 1998 KM616FV2000, KM616FS2000, KM616FR2000 Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled) tWC Address tCW(2) tWR(4) CS tAW tBW UB, LB tAS(3) tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high. DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 3.0/2.7/2.3/1.8V 2.2V VDR CSVCC - 0.2V CS GND 8 Revision 1.0 March 1998 KM616FV2000, KM616FS2000, KM616FR2000 Family PACKAGE DIMENSIONS CMOS SRAM Unit : millimeter(inch) 44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F) 0~8 0.25 ( ) 0.010 #44 #23 10.16 0.400 0.45 ~0.75 0.018 ~ 0.030 11.760.20 0.4630.008 ( 0.50 ) 0.020 #1 #22 1.000.10 0.0390.004 1.20 MAX. 0.047 ( 0.805 ) 0.032 0.350.10 0.0140.004 0.80 0.0315 0.05 MIN. 0.002 18.81 MAX. 0.741 18.41.10 0.7250.004 9 0 + 0.1 5 - 0.0 04 .0 +0 02 .006 - 0.0 0.15 0 0.10 0.004 MAX Revision 1.0 March 1998