LTC4307-1
1
43071fa
High Defi nition Multimedia
Interface (HDMI) Level-
Shifting 2-Wire Bus Buffer
The LTC4307-1 is a 2-wire bus buffer that provides ca-
pacitance buffering between input and output. The HDMI
specifi cation requires that devices have less than 50pF of
input capacitance on their DDC bus lines. The LTC4307-1’s
capacitance buffering feature, in conjunction with its
sub-10pF data and clock input capacitance, allows HDMI
components to easily meet the 50pF requirement and
tolerate high capacitance on the internal bus.
The LTC4307-1 also provides level-shifting between 3.3V
and 5V systems to allow lower voltage HDMI transmitters,
receivers and EEPROM to interface to the 5V DDC bus.
READY is an open-drain digital output fl ag that indicates
whether or not the input and output busses are connected
and can interface to the HDMI hot plug detect (HPD) signal.
When driven high, the ENABLE digital input allows the
LTC4307-1 to connect after a stop bit or bus idle. Driving
ENABLE low breaks the connection between the input and
output busses.
■ HDMI
■ 3.3V/5V Level Translation
■ Capacitance Buffer/Bus Extender
■ Bidirectional Buffer for Display Data Channel (DDC)
■ Compliant with HDMI Specifi cation Version 1.3
DDC Capacitance Requirement
■ Level Translation Between 3.3V and 5V
■ ±5kV Human Body Model ESD Protection
■ 60mV Buffer Offset Independent of Load
■ Compatible with Non-Compliant VOL I2C Devices
■ Isolates Input SDA and SCL Line from Output
■ Compatible with I2CTM, I2C Fast Mode and SMBus
■ READY Open-Drain Output
■ High Impedance SDA, SCL Pins for VCC = 0V
■ Small 8-Lead (3mm × 3mm) DFN and 8-Lead MSOP
Packages
APPLICATIO S
U
FEATURES DESCRIPTIO
U
TYPICAL APPLICATIO
U
Rising Edge from Asserted Low
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected b
y
U.S. Patents
,
includin
g
7032051
,
6356140
,
6650174
LTC4307-1
GND
VCC
SDAIN
SCLIN
1.8k1.8k 10k10k
0.1μF
43071 TA01a
3.3V
5V
DDC GROUND
TV (SINK)DVD PLAYER (SOURCE)
<50pF
HDMI RX
IC
HDMI
CABLE
EEPROM
SDAOUT
SCLOUT
ENABLE μC
HDMI TX
IC
100ns/DIV
00 100 200 300 400 600500
200mV/DIV
200
400
600
800
1000
43071 TA01b
SDAOUT
SDAIN
LOW
OFFSET
LTC4307-1
2
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VCC to GND ................................................. – 0.3V to 6V
SDAIN, SCLIN, SDAOUT, SCLOUT,
READY, ENABLE .......................................... –0.3V to 6V
Maximum Sink Current (SDAIN, SCLIN, SDAOUT,
SCLOUT, READY) .............................................. 50mA
Operating Temperature Range
LTC4307C ................................................ 0°C to 70°C
LTC4307I .............................................– 40°C to 85°C
(Notes 1, 6)
The
● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 3.3V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply
VCC Positive Supply Voltage ●2.3 5.5 V
ICC Supply Current VCC = 5.5V, VSCLOUT = VSDAOUT = 0V (Note 5) ●811 mA
ISD Shutdown Supply Current VCC = 5.5V, ENABLE = GND, SDA, SCL = 5.5V ●900 1200 μA
tIDLE Bus Idle Time ●55 95 175 μs
ELECTRICAL CHARACTERISTICS
ABSOLUTE AXI U RATI GS
W
WW
U
Storage Temperature Range
DFN ....................................................– 65°C to 125°C
MSOP ................................................– 65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MSOP ............................................................... 300°C
TOP VIEW
9
DD PACKAGE
8-LEAD
(
3mm × 3mm
)
PLASTIC DFN
5
6
7
8
4
3
2
1ENABLE
SCLOUT
SCLIN
GND
VCC
SDAOUT
SDAIN
READY
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
1
2
3
4
ENABLE
SCLOUT
SCLIN
GND
8
7
6
5
VCC
SDAOUT
SDAIN
READY
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 200°C/W
PIN CONFIGURATION
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4307CDD-1#PBF LTC4307CDD-1#TRPBF LDBP 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LTC4307IDD-1#PBF LTC4307IDD-1#TRPBF LDBP 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LTC4307CMS8-1#PBF LTC4307CMS8-1#TRPBF LTDBN 8-Lead Plastic MSOP 0°C to 70°C
LTC4307IMS8-1#PBF LTC4307IMS8-1#TRPBF LTDBN 8-Lead Plastic MSOP –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
LTC4307-1
3
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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VTHR_ENABLE ENABLE Threshold 0.8 1.4 2 V
IENABLE ENABLE Input Current ENABLE from 0V to VCC ●0.1 ±5 μA
tPLH_EN ENABLE Delay Off-On VCC = 3.3V (Figure 1) 95 μs
tPHL_EN ENABLE Delay On-Off VCC = 3.3V (Note 3) (Figure 1) 10 ns
tPLH_READY READY Delay Off-On VCC = 3.3V (Note 3) (Figure 1) 10 ns
tPHL_READY READY Delay On-Off VCC = 3.3V (Note 3) (Figure 1) 10 ns
VOL_READY READY Output Low Voltage IPULLUP = 3mA, VCC = 2.3V ●0.4 V
IOFF_READY READY Off Leakage Current VCC = READY = 5.5V ●0.1 ±5 μA
Propagation Delay
tPHL SDA/SCL Propagation Delay High to Low CLOAD = 50pF, 2.7k to VCC on SDA, SCL,
VCC = 3.3V (Notes 2, 3) (Figure 1)
70 ns
tPLH SDA/SCL Propagation Delay Low to High CLOAD = 50pF, 2.7k to VCC on SDA, SCL,
VCC = 3.3V (Notes 2, 3) (Figure 1)
10 ns
tFALL SDA/SCL Transition Time High to Low CLOAD = 100pF, 10k to VCC on SDA, SCL,
VCC = 3.3V (Notes 3, 4) (Figure 1)
30 300 ns
Input-Output Connection
VOS Input-Output Offset Voltage 2.7k to VCC on SDA, SCL, VCC = 3.3V,
Driven SDA, SCL = 0.2V
●20 60 100 mV
VTHR SDA, SCL Logic Input Threshold Voltage Rising Edge 0.45VCC 0.55VCC 0.65VCC V
VHYS SDA, SCL Logic Input Threshold Voltage
Hysteresis
(Note 3) 50 mV
CIN Digital Input Capacitance SDAIN, SDAOUT,
SCLIN, SCLOUT
(Note 3) 10 pF
ILEAK Input Leakage Current SDA, SCL, Pins ●±5 μA
VOL Output Low Voltage SDA, SCL Pins, ISINK = 4mA,
SDAIN/SCLIN = 0.2V, VCC = 2.7V
●0 0.4 V
2.7k to VCC on SDA, SCL, VCC = 3.3V,
Driven SDA, SCL = 0.1V
●120 160 205 mV
VILMAX Buffer Input Logic Low Voltage VCC = 3.3V ●1.2 V
Timing Characteristics
fI2C,MAX I2C Maximum Operating Frequency (Note 3) 400 600 kHz
tBUF Bus Free Time Between Stop and Start
Condition
(Note 3) 1.3 μs
tHD,STA Hold Time After (Repeated) Start Condition (Note 3) 100 ns
tSU,STA Repeated Start Condition Set-Up Time (Note 3) 0 ns
tSU,STO Stop Condition Set-Up Time (Note 3) 0 ns
tHD,DATI Data Hold Time Input (Note 3) 0 ns
tSU,DAT Data Set-Up Time (Note 3) 100 ns
The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 3.3V, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: See “Propagation Delays” in the Operations section for a
discussion of tPHL and tPLH as a function of pull-up resistance and bus
capacitance.
Note 3: Determined by design, not tested in production.
Note 4: Measure points are 0.3 • VCC and 0.7 • VCC.
Note 5: ICC test performed with connection circuitry active.
Note 6: All currents into pins are positive; all voltages are referenced to
GND unless otherwise specifi ed.
LTC4307-1
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ENABLE, CONNECT, READY Timing
Rising and Falling Propagation Delay and Rise and Fall Times for SDAIN, SDAOUT and SCLIN, SCLOUT
Figure 1. Timing Diagrams
TIMING DIAGRAMS
tPLH_EN
ENABLE
CONNECT
READY
tPLH_READY tPHL_READY
tPHL_EN
4307 F01a
tPLH
SDAIN/SCLIN
SDAOUT/SCLOUT
tPHL tRISE tFALL
tRISE tFALL
4307 F01b
LTC4307-1
5
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ICC vs Temperature ISD vs Temperature
Input-Output High to Low
Propagation Delay vs COUT
C
onnec
ti
on
Ci
rcu
it
ry
V
OUT –
V
IN
(
V
OS)
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TA = 25°C, VCC = 3.3V, unless otherwise indicated.
Input-Output High to Low
Propagation Delay vs Temperature
TEMPERATURE (°C)
–50
ICC (mA)
6.8
7.1
7.4
25 75
4307 G01
6.5
6.2
5.9 –25 0 50
7.7
8.0
8.3
100
VCC = 5.5V
VCC = 3.3V
VCC = 2.3V
TEMPERATURE (°C)
–50
700
ISD (μA)
750
800
850
–25 025 50
4307 G02
75
900
950
100
VCC = 5.5V
VCC = 3.3V
VCC = 2.3V
TEMPERATURE (°C)
–50
0
tPHL (ns)
20
40
60
80
100
–25 02550
4307 G03
75 100
CIN = COUT = 50pF
RPULLUPIN = RPULLUPOUT = 10k
VCC = 5.5V
VCC = 3.3V
VCC = 2.3V
COUT (pF)
0
tPHL (ns)
130
120
110
100
90
80
70
60
800
4307 G04
200 400 600 1000
CIN = 50pF
RPULLUPIN = RPULLUPOUT = 10k
VCC = 5.5V
VCC = 3.3V
RPULLUP (kΩ)
1
45
55
VOUT – VIN (mV)
65
75
85
2345
4307 G05
678910
LTC4307-1
6
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PI FU CTIO S
UUU
ENABLE (Pin 1): Connection Enable Input. This is a 1.4V
digital threshold input pin. For normal operation pull or tie
ENABLE high. Driving ENABLE below 0.8V isolates SDAIN
from SDAOUT, SCLIN from SCLOUT and asserts READY
low. A rising edge on ENABLE after a fault has occurred
forces a connection between SDAIN, SDAOUT and SCLIN,
SCLOUT. Connect to VCC if unused.
SCLOUT (Pin 2): Serial Clock Output. Connect this pin to
the clock line of a DDC bus. A pull-up resistor should be
connected between this pin and a supply voltage greater
than or equal to the VCC voltage.
SCLIN (Pin 3): Serial Clock Input. Connect this pin to
the clock line of a DDC bus. A pull-up resistor should be
connected between this pin and a supply voltage greater
than or equal to the VCC voltage.
GND (Pin 4): Device Ground. Connect this pin to a ground
plane for best results.
READY (Pin 5): Connection READY Status Output. The
READY pin is an open-drain N-channel MOSFET output that
pulls low when ENABLE is low, or when the start-up and
connection sequence described in the Operation section
has not been completed. READY goes high when ENABLE
is high and a connection is made. READY can be used to
control the HDMI HPD signal. Connect a pull-up resistor,
typically 10k, from this pin to VCC to provide the pull-up.
This pin can be fl oated if unused.
SDAIN (Pin 6): Serial Data Input. Connect this pin to the
data line of a DDC bus. A pull-up resistor should be con-
nected between this pin and a supply voltage greater than
or equal to the VCC voltage.
SDAOUT (Pin 7): Serial Data Output. Connect this pin to
the data line of a DDC bus. A pull-up resistor should be
connected between this pin and a supply voltage greater
than or equal to the VCC voltage.
VCC (Pin 8): Supply Voltage Input. Place a bypass capacitor
of at least 0.01μF close to VCC for best results.
Exposed Pad (Pin 9, DFN Package Only): Exposed Pad
may be left open or connected to device ground.
LTC4307-1
7
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BLOCK DIAGRA
W
Low Offset Level-Shifting 2-Wire Bus Buffer
0.55VCC
0.55VCC
1.4V
UVLO
0.55VCC
0.55VCC
CONNECT
CONNECT
SDAIN
6
SLEW RATE
DETECTOR
CONNECT
CONNECT
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
CONNECT
SDAOUT 7
VCC 8
SCLIN
3
CONNECT
SCLOUT 2
READY 5
LOGIC
ENABLE
1
GND
43071 BD
4
95μs
DELAY
+
+
–
–
+
–
+
–
+
–
LTC4307-1
8
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Figure 2. Input-Output Falling Edge Waveforms
OPERATION
INPUT SIDE
150pF
1V/DIV
OUTPUT SIDE
50pF
1V/DIV
200ns/DIV 43071 F02
Start-Up
When the LTC4307-1 fi rst receives power on its VCC pin
during power-up, it starts in an undervoltage lockout
(UVLO) state, ignoring any activity on the SDA or SCL
pins until VCC rises above 2V (typ). This is to ensure that
the LTC4307-1 does not try to function until it has enough
voltage to do so.
Once the LTC4307-1 comes out of UVLO, it monitors both
2-wire busses for either a stop bit or bus idle condition to
indicate the completion of data transactions. When both
sides are idle or one side has a stop bit condition while the
other is idle, the input-to-output connection circuitry is acti-
vated, joining SDAIN to SDAOUT and SCLIN to SCLOUT.
Connection Circuitry
Once the connection circuitry is activated, the functionality
of the SDAIN and SDAOUT pins is identical. A low forced
on either pin at any time results in both pin voltages being
low. The LTC4307-1 is tolerant of I2C bus DC logic low
voltages up to the 0.3VCC VIL I2C specifi cation.
When the LTC4307-1 senses a rising edge on the bus,
it deactivates its pull-down devices for bus voltages as
low as 0.48V. Care must be taken to ensure that devices
participating in clock stretching or arbitration force logic
low voltages below 0.48V at the LTC4307-1 inputs.
SDAIN and SDAOUT enter a logic high state only when
all devices on both SDAIN and SDAOUT release high.
The same is true for SCLIN and SCLOUT. This important
feature ensures that clock stretching, clock synchroniza-
tion, arbitration and the acknowledge protocol always
work, regardless of how the devices in the system are
tied to the LTC4307-1.
Another key feature of the connection circuitry is that it
provides bidirectional buffering, keeping the capacitances
of the two 2-wire busses isolated from each other. Plac-
ing an LTC4307-1 close to an HDMI port inside an HDMI
transmitter or receiver allows the HDMI device to pass
the capacitance compliance specifi cation. Because of this
isolation, the waveforms on SDAIN and SCLIN look slightly
different than the corresponding waveforms on SDAOUT
and SCLOUT as described here.
Input to Output Offset Voltage
When a logic low voltage, VLOW1, is driven on any of the
LTC4307-1’s data or clock pins, the LTC4307-1 regulates
the voltage on the opposite data or clock pins to a slightly
higher voltage, typically 60mV above VLOW1. This offset is
practically independent of pull-up current (see the Typical
Performance curves).
Propagation Delays
During a rising edge, the rise time on each side is de-
termined by the bus pull-up resistor and the equivalent
capacitance on the line. If the pull-up resistors are the
same, a difference in rise time occurs which is directly
proportional to the difference in capacitance between
the two sides. Users must account for differences in the
RC time constants between the two 2-wire busses and
ensure that all system timing specifi cations are met on
both busses.
There is a fi nite propagation delay through the connection
circuitry for falling waveforms. Figure 2 shows the falling
edge waveforms for VCC = 5.5V, a 10k pull-up resistor on
each side, 150pF parasitic capacitance on the input bus and
50pF on the output pins. An external N-channel MOSFET
device pulls down the voltage on the side with 150pF
capacitance; the LTC4307-1 pulls down the voltage on the
opposite side with a delay of 80ns. This delay is always
positive and is a function of supply voltage, temperature
and the pull-up resistors and equivalent bus capacitances
on both sides of the bus. The Typical Performance Charac-
teristics section shows propagation delay as a function of
temperature and voltage for 10k pull-up resistors and 50pF
equivalent capacitance on both sides of the part. Also, the
tPHL vs COUT curve for VCC = 5.5V shows that increasing the
LTC4307-1
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OPERATION
Figure 3 shows the LTC4307-1 in a capacitance buffering
application. Due to the LTC4307-1’s capacitance buffering
feature and sub-10pF input capacitance, this application
circuit passes the HDMI 50pF maximum DDC capacitance
specifi cation easily when the LTC4307-1 is located right at
the HDMI connector interface as shown. The capacitance
of the internal bus connected to the SDAIN and SCLIN
pins may be much larger than 50pF, but because of the
LTC4307-1’s capacitance buffering, the internal bus ca-
pacitance is isolated from the HDMI connector.
APPLICATIONS INFORMATION
In HDMI, the sink device pulls the hot plug detect HPD
signal high to tell the source that it is ready to accept
commands through the DDC. This signal can be controlled
through the READY pin of the LTC4307-1 to prevent the
possibility of erroneous attempts by the source to contact
the sink before the sink is ready to return its extended
display identifi cation data (EDID). The READY pin only
goes high after 5V is applied and the LTC4307-1 ENABLE
pin is pulled high by the HDMI receiver IC, a controller in
the sink, or the 5V line itself.
capacitance from 50pF to 150pF results in a tPHL increase
from 81ns to 91ns. Larger output capacitances translate
to longer delays (up to 125ns). Users must quantify the
difference in propagation times for a rising edge versus
a falling edge in their systems and adjust setup and hold
times accordingly.
READY Digital Output
This pin provides a digital fl ag which is low when either
ENABLE is low or the start-up sequence described earlier
in this section has not been completed. READY goes high
when ENABLE is high and the input and output 2-wire
busses are connected. The pin is driven by an open-drain
pull-down capable of sinking 3mA while holding 0.4V on
the pin. Connect a resistor to VCC to provide the pull-up.
READY can be used to control the HDMI hot plug detect
(HPD) signal to prevent the possibility of erroneous at-
tempts by the source to contact the sink before the sink
is ready to communicate.
ENABLE
When the ENABLE pin is driven below 0.8V with respect to
the LTC4307-1’s ground, the input 2-wire bus is discon-
nected from the output 2-wire bus and the READY pin is
internally pulled low. When the pin is driven above 2V,
the part waits for data transactions on both 2-wire bus-
ses to be complete (as described in the Start-Up section)
before connecting the two sides. At this time the internal
pull-down on READY releases.
LTC4307 and LTC4307-1 Feature Differences
The LTC4307-1 HDMI level-shifting 2-wire bus buffer is
specifi cally intended for HDMI applications. Features in
the general purpose LTC4307 device that are not required
in HDMI systems have been removed. In addition, level-
shifting functionality has been added to the LTC4307-1
to allow 3.3V HDMI devices to interface safely to the 5V
HDMI DDC bus. See Table 1 for a list of the differences
between the LTC4307 and LTC4307 -1.
Table 1. Differences Between the LTC4307 and the LTC4307-1
SPECIFICATION LTC4307 LTC4307-1 COMMENTS ON LTC4307-1
Pre-charge Yes No HDMI DDC Lines are Not Hot Swapped
Level Shifting No Yes,
2.2V to 5.5V
Provides Communication Between 3.3V and 5V DDC Busses,
Protects 3.3V Devices from 5V Supply
Stuck Bus Disconnect and Recovery Yes No Stuck Busses, Not an Issue in HDMI Systems
Rise Time Accelerators Yes No Complies with HDMI Specifi cation Version 1.3 DDC Capacitance
Requirement
LTC4307-1
10
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APPLICATIONS INFORMATION
Figure 3. The LTC4307-1 in HDMI Capacitance Buffering Application
Figure 4. The LTC4307-1 in a Level Shifting and Capacitance Buffering HDMI Application with Backup 3.3V
Figure 4 shows the LTC4307-1 being used for capacitance
buffering and 5V to 3.3V level shifting. In this application,
the EEPROM is powered by a backup 3.3V supply that is
available when the component is turned off. The EDID in
the EEPROM should be available for reading even when
a component’s power is off.
Although the applications shown in this section are for
HDMI receive channels, the LTC4307-1 can also be used
in HDMI transmit channels with equal success as shown
in the Typical Application on the last page of this data
sheet.
LTC4307-1
GND
READY
SDAOUT
SCLOUT
R6
100k
R5
1k
R4
47k
C1
0.1μF
R2
1.8k
R3
100k
R1
1.8k
5V
TO
HDMI
TX IC
SDA
SCL
HPD
DDC/CEC
GROUND
5V
DDC
HDMI SINK
(DIGITAL TV)
HDMI SOURCE
(DVD PLAYER)
R7
10k
R8
10k R9
10k
R10
10k
43071 F03
3.3V
HDMI
RX IC
EEPROM
HDMI CABLE
VCC
SCL SDA GND
VCC
SDAIN
SCLIN
ENABLE
LTC4307-1
GND
READY
SDAIN
SCLIN
R5
100k
R6
10k
R7
10k
C1
0.1μF
R3
47k
R4
47k
R1
1.8k
R2
1.8k
5V
TO
HDMI
TX IC
SDA
SCL
DDC/CEC
GROUND
5V
DDC
HDMI REPEATER
(DIGITAL RECEIVER)
HDMI SOURCE
(DVD PLAYER)
43071 F04
HDMI
RX IC
EEPROMBACKUP 3.3V
HDMI CABLE
VCC
SWITCHED
3.3V
SCL SDA
VCC
SDAOUT
SCLOUT
ENABLE
μC
LTC4307-1
11
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
2.38 ±0.10
(2 SIDES)
14
85
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(DD8) DFN 1203
0.25 ± 0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)
2.15 ±0.05
0.50
BSC
0.675 ±0.05
3.5 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
PACKAGE DESCRIPTION
MSOP (MS8) 0307 REV F
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.1016 ± 0.0508
(.004 ± .002)
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
12
34
4.90 ± 0.152
(.193 ± .006)
8765
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
0.52
(.0205)
REF
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.038
(.0165 ± .0015)
TYP
0.65
(.0256)
BSC
LTC4307-1
12
43071fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2007
LT 0208 REV A • PRINTED IN USA
PART NUMBER DESCRIPTION COMMENTS
LTC1380/LTC1393 Single-Ended 8-Channel/Differential 4-Channel Analog
MUX with SMBus Interface
Low RON: 35Ω Single Ended/70Ω Differential, Expandable to 32 Single
or 16 Differential Channels
LTC1427-50 Micropower, 10-Bit Current Output DAC with SMBus
Interface
Precision 50μA ±2.5% Tolerance Over Temperature, Four Selectable
SMBus Addresses, DAC Powers Up at Zero or Midscale
LTC1623 Dual High Side Switch Controller with SMBus Interface Eight Selectable Addresses/16-Channel Capability
LTC1663 SMBus Interface 10-Bit Rail-to-Rail Micropower DAC DNL < 0.75LSB Max, 5-Lead SOT-23 Package
LTC1694/LTC1694-1 SMBus Accelerator Improved SMBus/I2C Rise Time, Ensures Data Integrity with Multiple
SMBus/I2C Devices
LTC1695 SMBus/I2C Fan Speed Controller in ThinSOTTM Package 0.75Ω PMOS 180mA Regulator, 6-Bit DAC
LT1786F SMBus Controlled CCFL Switching Regulator 1.25A, 200kHz Floating or Grounded Lamp Confi gurations
LTC1840 Dual I2C Fan Speed Controller Two 100μA 8-Bit DACs, Two Tach Inputs, Four GPIO
LTC4300A-1/
LTC4300A-2/
LTC4300A-3
Hot Swappable 2-Wire Bus Buffers LTC4300A-1: Bus Buffer with READY, ACC and ENABLE
LTC4300A-2: Dual Supply Bus Buffer with READY and ACC
LTC4300A-3: Dual Supply Bus Buffer with READY and ENABLE
LTC4301 Supply Independent Hot Swappable 2-Wire Bus Buffer Supply Independent
LTC4301L Hot Swappable 2-Wire Bus Buffer with Low Voltage
Level Translation
Allows Bus Pull-Up Voltages as Low as 1V on SDAIN and SCLIN
LTC4302-1/LTC4302-2 Addressable 2-Wire Bus Buffer Address Expansion, GPIO, Software Controlled
LTC4303/LTC4304 Hot Swappable 2-Wire Bus Buffers with Stuck Bus
Recovery
Provides Automatic Clocking to Free Stuck I2C Busses
LTC4305/LTC4306 2-/4-Channel, 2-Wire Bus Multiplexers with
Capacitance Buffering
2/4 Selectable Downstream Busses, Stuck Bus Disconnect, Rise Time
Accelerators, Fault Reporting, ±10kV HBM ESD Tolerance
LTC4307 Low Offset Hot-Swappable 2-Wire Bus Buffer with
Stuck Bus Recovery
60mV Buffer Offset, 30ms Stuck Bus Disconnect and Recovery
ThinSOT is a trademark of Linear Technology Corporation
RELATED PARTS
TYPICAL APPLICATION
LTC4307-1LTC4307-1
GND GND
READY
SDAIN
SCLIN
READY
SDAOUT
SCLOUT
R6
10k
R3
10k
R4
1.8k
R5
1.8k
R1
10k
R2
10k
R7
10k
C2
0.1μF
C1
0.1μF
43071 TA02
3.3V5V
DDC GROUND
TV (SINK)DVD PLAYER (SOURCE)
<50pF
HDMI RX
IC
HDMI TX
IC
HDMI
CABLE
EEPROM
VCC
SDAOUT
SCLOUT
VCC
SDAIN
SCLIN
ENABLE ENABLE μC
HDMI Application with LTC4307-1’s Providing Capacitance Buffering
On Both the Transmit and Receive Channels
