1
Data sheet acquired from Harris Semiconductor
SCHS207G
Features
• Onboard Oscillator
• Common Reset
• Negative-Edge Clocking
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating T emperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il≤1µA at VOL, VOH
Description
The ’HC4060 and ’HCT4060 each consist of an oscillator
section and 14 ripple-carry binary counter stages. The
oscillator configuration allows design of either RC or crystal
oscillator circuits. A Master Reset input is provided which
resets the counter to the all-0’s state and disables the
oscillator. A high level on the MR line accomplishes the reset
function. All counter stages are master-slave flip-flops. The
state of the counter is advanced one step in binary order on
the negative transition of φI (and φO). All inputs and outputs
are buffered. Schmitt trigger action on the input-pulse-line
permits unlimited rise and fall times.
In order to achieve a symmetrical waveform in the oscillator
section the HCT4060 input pulse switch points are the same
as in the HC4060; only the MR input in the HCT4060 has
TTL switching levels.
Pinout CD54HC4060, CD54HCT4060 (CERDIP)
CD74HC4060 (PDIP, SOIC, TSSOP)
CD74HCT4060 (PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER TEMP. RANGE
(oC) PACKAGE
CD54HC4060F3A -55 to 125 16 Ld CERDIP
CD54HCT4060F3A -55 to 125 16 Ld CERDIP
CD74HC4060E -55 to 125 16 Ld PDIP
CD74HC4060M -55 to 125 16 Ld SOIC
CD74HC4060MT -55 to 125 16 Ld SOIC
CD74HC4060M96 -55 to 125 16 Ld SOIC
CD74HC4060PW -55 to 125 16 Ld TSSOP
CD74HC4060PWR -55 to 125 16 Ld TSSOP
CD74HC4060PWT -55 to 125 16 Ld TSSOP
CD74HCT4060E -55 to 125 16 Ld PDIP
CD74HCT4060M -55 to 125 16 Ld SOIC
CD74HCT4060MT -55 to 125 16 Ld SOIC
CD74HCT4060M96 -55 to 125 16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
Q12
Q13
Q14
Q6
Q5
Q7
GND
Q4
VCC
Q8
Q9
MR
φI
φO
φO
Q10
February 1998 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
CD54HC4060, CD74HC4060,
CD54HCT4060, CD74HCT4060
High-Speed CMOS Logic
14-Stage Binary Counter with Oscillator
[
/Title
(
CD74
H
C406
0
,
C
D74
H
CT40
6
0)
/
Sub-
j
ect
(
High
S
peed
C
MOS
2
Functional Diagram
φI
Q4
Q5
Q6
Q7
Q9
Q12
Q14
φO
φO
MR
Q13
Q10
Q8
14-STAGE
RIPPLE
COUNTER
AND
OSCILLATOR
GND = 8
VCC = 16
7
5
4
6
13
1
3
2
15
14
12
11
9
10
FIGURE 1. LOGIC BLOCK DIAGRAM
TRUTH TABLE
øI MR OUTPUT STATE
↑L No Change
↓L Advance to Next State
X H All Outputs are Low
ø1Q1
FF1
ø1 Q1
R
ø4Q4
FF4
ø4 Q4
R
ø14 Q14
FF14
ø14 Q14
R
ø5 Q13
FF5 - FF13
ø5 Q13
R
723
5, 4, 6, 14, 13, 15, 1
Q5 - Q10, Q12
MR 12
11
10
9
Q14
Q13
Q4
øO
øO
ø1
CD54/74HC4060, CD54/74HCT4060
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 1) θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . 108
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage Q Outputs
CMOS Loads
VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage Q Outputs
TTL Loads
- - ---- - - -V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage Q Outputs
CMOS Loads
VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage Q Outputs
TTL Loads
- - ---- - - -V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
High-Level Output
Voltage φO Output
(Pin 10)
CMOS Loads
VOH VCC or
GND -0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
CD54/74HC4060, CD54/74HCT4060
4
High-Level Output
Voltage φO Output
(Pin 10)
TTL Loads
(Note 2)
VOH VCC or
GND -2.6 4.5 3.98 - - 3.84 - 3.7 - V
-3.3 6 5.48 - - 5.34 - 5.2 - V
Low-Level Output
Voltage φO Output
(Pin 10)
CMOS Loads
VOL VCC or
GND 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low-Level Output
Voltage φO Output
(Pin 10)
TTL Loads
VOL VCC or
GND 2.6 4.5 - - 0.26 - 0.33 - 0.4 V
3.3 6 - - 0.26 - 0.33 - 0.4 V
High-Level Output
Voltage φO Output
(Pin 9)
TTL Loads
VOH VIL or VIH -3.2 4.5 3.98 - - 3.84 - 3.7 - V
-4.2 6 5.48 - - 5.34 - 5.2 - V
Low-Level Output
Voltage φO Output
(Pin 9)
TTL Loads
VOL VIL or VIH -2.6 4.5 - - 0.26 - 0.33 - 0.4 V
-3.3 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC or
GND -6--±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 6 - - 8 - 80 - 160 µA
HCT TYPES
High Level Input
Voltage VIH - - 4.5 to
5.5 2--2 - 2 - V
Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage Q Outputs
CMOS Loads
VOH VIH or VIL
(Note 3) -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage Q Outputs
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage Q Outputs
CMOS Loads
VOL VIH or VIL
(Note 3) 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage Q Outputs
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
High-Level Output
Voltage φO Output
(Pin 10)
CMOS Loads
VOH VCC or
GND -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High-Level Output
Voltage φO Output
(Pin 10)
TTL Loads (Note 2)
VOH VCC or
GND -2.6 4.5 3.98 - - 3.84 - 3.7 - V
Low-Level Output
Voltage φO Output
(Pin 10)
CMOS Loads
VOL VCC or
GND 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
CD54/74HC4060, CD54/74HCT4060
5
Low-Level Output
Voltage φO Output
(Pin 10)
TTL Loads
VOL VCC or
GND 2.6 4.5 - - 0.26 - 0.33 - 0.4 V
High-Level Output
Voltage φO Output
(Pin 9)
TTL Loads
VOH VIL or VIH -3.2 4.5 3.98 - - 3.84 - 3.7 - V
Low-Level Output
Voltage φO Output
(Pin 9)
TTL Loads
VOL VIH or VIL
(Note 3) 3.2 4.5 - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIAny
Voltage
Between
VCC and
GND
- 5.5 - ±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 5.5 - - 8 - 80 - 160 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆ICC
(Note 4) VCC
- 2.1 - 4.5 to
5.5 - 100 360 - 450 - 490 µA
NOTES:
2. Limits not valid when pin 12 (instead of pin 11) is used as control input.
3. For pin 11 VIH = 3.15V, VIL = 0.9V.
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
MR 0.35
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifica-
tions Table, e.g. 360µA max at 25oC.
Prerequisite for Switching Specifications
PARAMETER SYMBOL VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
HC TYPES
Maximum Input Pulse
Frequency fmax 2 6 - - 5 - - 4 - - MHz
4.5 30 - - 25 - - 20 - - MHz
6 35 - - 29 - - 23 - - MHz
Input Pulse Width tW2 80 - - 100 - - 120 - - ns
4.5 16 - - 20 - - 24 - - ns
614--17- -20--ns
Reset Removal Time tREM 2 100 - - 125 - - 150 - - ns
4.5 20 - - 25 - - 30 - - ns
617--21- -26--ns
CD54/74HC4060, CD54/74HCT4060
6
Reset Pulse Width tW2 80 - - 100 - - 120 - - ns
4.5 16 - - 20 - - 24 - - ns
614--17- -20--ns
HCT TYPES
Maximum Input,
Pulse Frequency fmax 4.5 30 - - 25 - - 20 - - MHz
Input Pulse Width tW4.5 16 - - 20 - - 24 - - ns
Reset Removal Time tREM 4.5 26 - - 33 - - 39 - - ns
Reset Pulse Width tW4.5 25 - - 31 - - 38 - - ns
Prerequisite for Switching Specifications (Continued)
PARAMETER SYMBOL VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
Switching Specifications Input tr, tf= 6ns
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay tPLH, tPHL CL = 50pF 2 - - 300 - 375 - 450 ns
φI to Q4 4.5 - - 60 - 75 - 90 ns
CL = 15pF 5 - 25 - - - - - ns
CL = 50pF 6 - - 51 - 64 - 78 ns
Qn to Qn+1 tPLH, tPHL CL = 50pF 2 - - 80 - 100 - 120 ns
4.5 - - 16 - 20 - 24 ns
CL = 15pF 5 - 6 - - - - - ns
CL = 50pF 6 - - 14 - 17 - 20 ns
MR to QntPHL CL = 50pF 2 - - 175 - 220 - 265 ns
4.5 - - 35 - 44 - 53 ns
CL = 15pF 5 - 14 - - - - - ns
CL = 50pF 6 - - 30 - 37 - 45 ns
Output Transition Time tTHL, tTLH CL = 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Input Capacitance CI
(TBD)
Propagation Dissipation
Capacitance (Notes 5, 6) CPD ---40-----pF
HCT TYPES
Propagation Delay tPLH, tPHL CL = 50pF 2- - - - - - - -ns
φI to Q4 4.5 - - 66 - 83 - 100 ns
CL = 15pF 5 - 25 - - - - - -ns
CL = 50pF 6 - - - - - - - -ns
CD54/74HC4060, CD54/74HCT4060
7
Qn to Qn+1 tPLH, tPHL CL = 50pF 2 - - - - - - - ns
4.5 - - 16 - 20 - 24 ns
CL = 15pF 5 - 6 - - - - - ns
CL = 50pF 6 - - - - - - - ns
MR to QntPHL CL = 50pF 2 - - - - - - - ns
4.5 - - 44 - 55 - 66 ns
CL = 15pF 5 - 17 - - - - - ns
CL = 50pF 6 - - - - - - - ns
Output Transition Time tTHL, tTLH CL = 50pF 2 - - - - - - - ns
4.5 - - 15 - 19 - 22 ns
6-------ns
Input Capacitance CI
(TBD)
Propagation Dissipation
Capacitance (Notes 5, 6) CPD ---40-----pF
NOTES:
5. CPD is used to determine the dynamic power consumption, per package.
6. PD = CPD VCC2 fi∑(CL VCC2 fi/M) where M = 21, 22, 23, ...214, fi = input frequency, CL = output load capacitance.
Switching Specifications Input tr, tf= 6ns (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC-40oC TO
85oC-55oC TO
125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
TYPICAL LIMIT VALUES FOR RX AND CX
PARAMETER TEST
CONDITIONS VOLTAGE
TYPICAL
MAXIMUM
LIMITS
RX Minimum CX > 1000pF 2 1KΩ
CX > 10pF 4.5
CX > 10pF 6
RX Maximum CX > 10pF 2 20MΩ
CX > 10pF 4.5
CX > 10pF 6
CX Minimum RX > 10KΩ2 10pF
RX > 10KΩ4.5
RX > 10KΩ6
RX = 1KΩ2 1000pF
RX = 1KΩ4.5 10pF
RX = 1KΩ6 10pF
Maximum
Astable Oscillator
Frequency
CX = 1000pF,
RX = 1KΩ2 0.5MHz
(Note 7)
CX = 100pF,
RX = 1KΩ4.5 3MHz
(Note 7)
CX = 100pF,
RX = 1KΩ6 3MHz
(Note 7)
NOTE:
7. At very high frequencies f = 1/2.2 RXCXno longer gives an
accurate approximation.
NOTE: OSC Frequency ≈ 1/2.2 RXCX
For 1MΩ > RX > 1KΩ, CX > 10pF, f < 1MHz
FIGURE 2. FREQUENCY OF ON-BOARD OSCILLATOR AS A
FUNCTION OF CX AND RX
102
10
1
10-1
10-2
10-3
10-4
10-5 10-1 10010 102103104105106
OSCILLATOR FREQUENCY (Hz)
CX (µF)
TA = 25oC
RX = 1KΩ
10KΩ
100KΩ
1MΩ
10MΩ
CD54/74HC4060, CD54/74HCT4060
8
Typical Performance Curves
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 3. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 4. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 5. HC AND HCT TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC FIGURE 6. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
CLOCK 90% 50%
10% GND
VCC
trCLtfCL
50% 50%
tWL tWH
10%
tWL + tWH =fCL
I
CLOCK 2.7V 1.3V
0.3V GND
3V
trCL= 6ns tfCL= 6ns
1.3V 1.3V
tWL tWH
0.3V
tWL + tWH =fCL
I
tPHL tPLH
tTHL tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns tf = 6ns
90%
tPHL tPLH
tTHL tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns tf = 6ns
90%
CD54/74HC4060, CD54/74HCT4060
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-8768001EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8768001EA
CD54HC4060F3A
5962-8977101EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8977101EA
CD54HCT4060F3A
CD54HC4060F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8768001EA
CD54HC4060F3A
CD54HCT4060F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8977101EA
CD54HCT4060F3A
CD74HC4060E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4060E
CD74HC4060EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4060E
CD74HC4060M ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4060M
CD74HC4060M96 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4060M
CD74HC4060M96E4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4060M
CD74HC4060M96G4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4060M
CD74HC4060ME4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4060M
CD74HC4060MG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4060M
CD74HC4060MT ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4060M
CD74HC4060MTE4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4060M
CD74HC4060MTG4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4060M
CD74HC4060PW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4060
CD74HC4060PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4060
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CD74HC4060PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4060
CD74HC4060PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4060
CD74HC4060PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4060
CD74HC4060PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4060
CD74HC4060PWT ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4060
CD74HC4060PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4060
CD74HC4060PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4060
CD74HCT4060E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4060E
CD74HCT4060EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4060E
CD74HCT4060M ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4060M
CD74HCT4060M96 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4060M
CD74HCT4060M96E4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4060M
CD74HCT4060M96G4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4060M
CD74HCT4060ME4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4060M
CD74HCT4060MG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4060M
CD74HCT4060MT ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4060M
CD74HCT4060MTE4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4060M
CD74HCT4060MTG4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4060M
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC4060, CD54HCT4060, CD74HC4060, CD74HCT4060 :
•Catalog: CD74HC4060, CD74HCT4060
•Military: CD54HC4060, CD54HCT4060
NOTE: Qualified Version Definitions:
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 4
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74HC4060M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4060PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HC4060PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HCT4060M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC4060M96 SOIC D 16 2500 333.2 345.9 28.6
CD74HC4060PWR TSSOP PW 16 2000 367.0 367.0 35.0
CD74HC4060PWT TSSOP PW 16 250 367.0 367.0 35.0
CD74HCT4060M96 SOIC D 16 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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