SY89833ALMG - Micrel - Product.Network

SY89833AL

3.3V Low Noise Ultra-Precision 1:4 LVDS

Fanout Buffer/Translator with Internal

Termination

Precision Edge is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

March 2009 M9999-032609-

hbwhelp@micrel.com or (408) 955-1690

General Description

The SY89833AL is a lower noise version of the SY89833L

3.3V, high-speed 2GHz Low Voltage Differential Swing

(LVDS) 1:4 fanout buffer. Within device skew is

guaranteed to be less than 20ps over supply voltage and

temperature.

The differential input buffer has a unique internal

termination design that allows access to the termination

network through a VT pin. This feature allows the device to

easily interface to different logic standards. A VREF-AC

reference is included for AC-coupled applications.

The SY89833AL is part of Micrel’s high-speed clock

synchronization family. For 2.5V applications, the

SY89832U provides similar functionality while operating

from a 2.5V ±5% supply. For applications that require a

different I/O combination, consult the Micrel website at:

www.micrel.com, and choose from a comprehensive

product line of high-speed, low-skew fanout buffers,

translators and clock generators. Datasheets and support

documentation can be found on Micrel’s web site at:

www.micrel.com.

Functional Block Diagram

Precision Edge®

Features

• Guaranteed AC performance over temperature

and voltage:

– DC-to > 2GHz throughput

– <470ps propagation delay (IN-to-Q)

– <20ps within-device skew

– <190ps rise/fall times

• Improved Ultra-low jitter design:

– <1psRMS cycle-to-cycle jitter

– <10psPP total jitter

– <1psRMS random jitter

– <10psPP deterministic jitter

– <0.635ps @ 156.25MHz (Integrated from 12kHz to

20MHz)

• Unique input termination and VT pin accepts DC- and

AC-coupled inputs

• High-speed LVDS outputs

• 3.3V power supply operation

• Industrial temperature range: –40°C to +85°C

• Available in 16-pin (3mm x 3mm) QFN package

Applications

• Processor clock distribution

• SONET clock distribution

• Fibre Channel clock distribution

• Gigabit Ethernet clock distribution

Micrel, Inc. SY89833AL

March 2009 2 M9999-032609-

hbwhelp@micrel.com or (408) 955-1690

Ordering Information(1)

Part Number Package

Type Operating Range Package Marking Lead

Finish

SY89833ALMI QFN-16 Industrial 833A Sn-Pb

SY89833ALMITR(2) QFN-16 Industrial 833A Sn-Pb

SY89833ALMG(3) QFN-16 Industrial 833A with

Pb-Free bar-line indicator

NiPdAu

Pb-Free

SY89833ALMGTR(2, 3) QFN-16 Industrial 833A with

Pb-Free bar-line indicator

NiPdAu

Pb-Free

Notes:

1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.

2. Tape and Reel.

3. Pb-Free package is recommended for new designs.

Pin Configuration

16-Pin

Truth Table

IN /IN EN Q /Q

0 1 1 0 1

1 0 1 1 0

X X 0 0(1) 1

(1)

Note:

1. On next negative transition of the input signal (IN).

Micrel, Inc. SY89833AL

March 2009 3 M9999-032609-

hbwhelp@micrel.com or (408) 955-1690

Pin Description

Pin Number Pin Name Pin Function

15, 16

1, 2

3, 4

5, 6

Q0, /Q0

Q1, /Q1

Q2, /Q2

Q3, /Q3

LVDS Differential Outputs: Normally terminated with 100Ω across the pair (Q,

/Q). See “LVDS Outputs” section, Figure 2a. Unused outputs should be

terminated with a 100Ω resistor across each pair.

8 EN

This single-ended TTL/CMOS-compatible input functions as a synchronous

output enable. The synchronous enable ensures that enable/disable will only

occur when the outputs are in a logic LOW state. Note that this input is internally

connected to a 25kΩ pull-up resistor and will default to logic HIGH state

(enabled) if left open.

9, 12 /IN, IN Differential Input: This input pair is the differential signal input to the device.

Input accepts AC- or DC-Coupled differential signals as small as 100mV. Each

pin of the pair internally terminates to a VT pin through 50Ω. Note that this input

will default to an intermediate state if left open. Please refer to the “Input

Interface Applications” section for more details.

10 VREF-AC

Reference Voltage: This output biases to VCC–1.4V. It is used when AC-

Coupling the input (IN, /IN). For AC-Coupled applications, connect VREF-AC to

VT pin and bypass with 0.1µF low ESR capacitor to VCC. See “Input Interface

Applications” section for more details. Maximum sink/source current is ±1.5mA.

Due to the limited drive capability, each VREF-AC pin is only intended to drive its

respective VT pin.

11 VT

Input Termination Center-Tap: Each side of the differential input pair terminates

to the VT pin. The VT pin provides a center-tap to a termination network for

maximum interface flexibility. See “Input Interface Applications” section for more

details.

13 GND

Ground. GND pin and exposed pad must be connected to the most negative

potential of the device ground.

7, 14 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors and

place as close to each VCC pin as possible.

Micrel, Inc. SY89833AL

March 2009 4 M9999-032609-

hbwhelp@micrel.com or (408) 955-1690

Absolute Maximum Ratings(1)

Supply Voltage (VCC).................................... –0.5V to +4.0V

Input Voltage (VIN)................................. –0.5V to VCC +0.3V

LVDS Output Current (IOUT).......................................±10mA

Input Current

Source or Sink Current on (IN, /IN) ....................±50mA

VT Current

Source or Sink Current on (VT).............……….±100mA

VREF-AC Current

Source or Sink Current on (VREF-AC) .....................±2mA

Maximum Operating Junction Temperature............... 125°C

Lead Temperature (soldering, 20sec.)....................... 260°C

Storage Temperature (Ts) .........................–65°C to +150°C

Operating Ratings(2)

Supply Voltage (VCC).................................. +3.0V to +3.60V

Ambient Temperature (TA) ..........................–40°C to +85°C

Junction Thermal Resistance (3)

QFN (θJA)

Still-Air.........................................................75°C/W

QFN (ψJB)...........................................................33°C/W

Electrical Characteristics(4)

TA = –40°C to +85°C, unless otherwise noted.

Symbol Parameter Condition Min Typ Max Units

VCC Power Supply Voltage Range 3.0 3.3 3.6 V

ICC Power Supply Current No load, max. VCC. 75 100 mA

RIN Input Resistance (IN-to-VT) 45 50 55 Ω

RDIFF-IN Differential Input Resistance

(IN-to-/IN)

90 100 110 Ω

VIH Input HIGH Voltage

(IN-to-/IN)

1.2 VCC V

VIL Input LOW Voltage

(IN-to-/IN)

0 VIH–0.1 V

VIN Input Voltage Swing

(IN-to-/IN)

See Figure 2c. 0.1 1.7 V

VDIFF_IN Differential Input Voltage See Figure 2d. 0.2 V

|IIN| Input Current

(IN, /IN)

Note 5 45 mA

VREF-AC Reference Voltage VCC–1.525 VCC–1.425 VCC–1.325 V

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied

at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.

3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. ψJB and θJA values

are determined for a 4-layer board in still-air number, unless otherwise stated.

4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

5. Due to the internal termination (see "Input Stage" section) the input current depends on the applied voltages at IN, /IN and VT inputs. Do not apply a

combination of voltages that causes the input current to exceed the maximum limit!

Micrel, Inc. SY89833AL

March 2009 5 M9999-032609-

hbwhelp@micrel.com or (408) 955-1690

LVDS Outputs DC Electrical Characteristics(6)

VCC = 3.3V ±10%, RL = 100Ω across the output, TA = –40°C to +85°C, unless otherwise noted.

Symbol Parameter Condition Min Typ Max Units

VOUT Output Voltage Swing See Figure 2c. 250 325 mV

VDIFF_OUT Differential Output Voltage Swing See Figure 2d. 500 650 mV

VOCM Output Common Mode Voltage 1.125 1.275 V

ΔVOCM Change in Common Mode Voltage –50 50 mV

LVTTL/CMOS DC Electrical Characteristics(6)

VCC = 3.3V ±10%, TA = –40°C to +85°C, unless otherwise noted.

Symbol Parameter Condition Min Typ Max Units

VIH Input HIGH Voltage 2.0 VCC V

VIL Input LOW Voltage 0 0.8 V

IIH Input HIGH Current –125 30 µA

IIL Input LOW Current –300 µA

Notes:

6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

Micrel, Inc. SY89833AL

March 2009 6 M9999-032609-

hbwhelp@micrel.com or (408) 955-1690

AC Electrical Characteristics(7)

VCC = 3.3V ±10%, RL = 100Ω across the output, TA = –40°C to +85°C, unless otherwise noted.

Symbol Parameter Condition Min Typ Max Units

fMAX Maximum Frequency VOUT ≥ 200mV 2.0 GHz

tPD Propagation Delay 250 470 ps

Note 8 5 20 ps

tSKEW Within-Device Skew

Part-to-Part Skew Note 9 200 ps

tS Set-Up Time Note 10 400 ps

tH Hold Time Note 10 400 ps

Data

Random Jitter (RJ)

Deterministic Jitter (DJ)

Note 11

Note 12

psRMS

psPP

Clock

Cycle-to-Cycle Jitter

Total Jitter (TJ)

Note 13

Note 14

psRMS

psPP

f = 622.08MHz, Note 15 0.07 psRMS

tJITTER

Additive Phase Jitter f = 156.25MHz, Note 15 0.635 psRMS

tr, tf Output Rise/Fall Times

(20% to 80%) At full output swing. 60 110 190 ps

Duty Cycle Differential I/O 47 53 %

Notes:

7. High-frequency AC parameters are guaranteed by design and characterization.

8. Within device skew is measured between two different outputs under identical input transitions.

9. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective

inputs.

10. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications,

set-up and hold times do not apply.

11. Random jitter is measured with a K28.7 pattern, measured at ≤fMAX.

12. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 223–1 PRBS pattern.

13. Cycle-to-cycle jitter definition: The variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn –

Tn+1, where T is the time between rising edges of the output signal.

14. Total jitter definition: with an ideal clock input frequency of ≤ fMAX (device), no more than one output edge in 1012 output edges will deviate by

more than the specified peak-to-peak jitter value.

15. Integrated over the range of 12kHz to 20MHz.

Timing Diagrams

Micrel, Inc. SY89833AL

March 2009 7 M9999-032609-

hbwhelp@micrel.com or (408) 955-1690

Typical Characteristics

VCC = 3.3V, GND = 0V, VIN = 400mV, RL = 100Ω across the outputs, TA = 25ºC, unless otherwise stated.

Micrel, Inc. SY89833AL

March 2009 8 M9999-032609-

hbwhelp@micrel.com or (408) 955-1690

Functional Characteristics

VCC = 3.3V, GND = 0V, VIN = 400mV, RL = 100Ω across the outputs, TA = 25ºC, unless otherwise stated.

Micrel, Inc. SY89833AL

March 2009 9 M9999-032609-

hbwhelp@micrel.com or (408) 955-1690

Input Stage

Figure 1. Simplified Differential Input Buffer

LVDS Outputs

LVDS specifies a small swing of 325mV typical, on a

nominal 1.20V common mode above ground. The common

mode voltage has tight limits to permit large variations in

ground noise between an LVDS driver and receiver.

Figure 2a. LVDS Differential Measuremen t

Figure 2b. LVDS Commo n Mode Measurement

Figure 2c. Single-Ended Swing

Figure 2d. Differential Swing

Micrel, Inc. SY89833AL

March 2009 10 M9999-032609-

hbwhelp@micrel.com or (408) 955-1690

Input Interface Applications

Figure 3a. DC-Coupled

CML Input Interface

Option: May connect VT to VCC

Figure 3b. AC-Coupled

CML Input Interface

Figure 3c. DC-Coupled

LVPECL Input Interface

Figure 3d. AC-Coupled

LVPECL Input Interface

Figure 3e. LVDS Input Interface

Related Product an d Support Documentation

Part Number Function Datasheet Link

SY89830U 2.5V/3.3V/5V 2.5GHz 1:4 PECL/ECL

Clock Driver with 2:1 Differential Input MUX

http://www.micrel.com/product-info/products/sy89830u.shtml

SY89831U Ultra-Precision 1:4 LVPECL Fanout

Buffer/Translator with Internal Termination

http://www.micrel.com/product-info/products/sy89831u.shtml

SY89832U 2.5V Ultra-Precision 1:4 LVDS Fanout

Buffer/Translator with Internal Termination

http://www.micrel.com/product-info/products/sy89832u.shtml

SY89834U 2.5/3.3V Two Input, 1GHz LVTTL/CMOS-to-

LVPECL 1:4 Fanout Buffer/Translator

http://www.micrel.com/product-info/products/sy89834u.shtml

SY89833L 3.3V Ultra-Precision 1:4 LVDS Fanout

Buffer/Translator with Internal Termination

http://www.micrel.com/page.do?page=/product-

info/products/sy89833l.shtml

HBW Solutions New Products and Termination App. Note http://www.micrel.com/product-info/as/solutions.shtml

Micrel, Inc. SY89833AL

March 2009 11 M9999-032609-

hbwhelp@micrel.com or (408) 955-1690

Package Information

16-Pin QFN

Micrel, Inc. SY89833AL

March 2009 12 M9999-032609-

hbwhelp@micrel.com or (408) 955-1690

PCB Thermal Consideratio n fo r 16-Pin QFN Package

(Always solder, or eq uivalent, the exposed pad to the PCB)

Package Notes:

1. Package meets Level 2 moisture sensitivity classification, and are shipped in dry-pack form.

2. Exposed pads must be soldered to a ground for proper thermal management.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its

use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product

can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant

into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A

Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully

indemnify Micrel for any damages resulting from such use or sale.

orated.