May 2001
2001 Fairchild Semiconductor Corporation FDS4501H Rev C(W)
FDS4501H
Complementary PowerTrench Half-Bridge MOSFET
General Description
This complementary MOSFET half-bridge device is
produced using Fairchild’s advanced PowerTrench
process that has been especially tailored to minimize
the on-state resistance and yet maintain low gate
charge for superior switching performance.
Applications
• DC/DC converter
• Power management
• Load switch
• Battery protection
Features
• Q1: N-Channel
9.3A, 30V RDS(on) = 18 mΩ @ VGS = 10V
RDS(on) = 23 mΩ @ VGS = 4.5V
• Q2: P-Channel
–5.6A, –20V RDS(on) = 46 mΩ @ VGS = –4.5V
RDS(on) = 63 mΩ @ VGS = –2.5V
S
D
S
S
SO-8
D
D
D
G
DDDD
S1
G1
S2
G2
SO-8
4
3
2
1
5
6
7
8
Q1
Q2
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol Parameter Q1 Q2 Units
VDSS Drain-Source Voltage 30 –20 V
VGSS Gate-Source Voltage ±20 ±8 V
ID Drain Current - Continuous (Note 1a) 9.3 –5.6 A
- Pulsed 20 –20
PD Power Dissipation for Single Operation (Note 1a) 2.5 W
(Note 1b) 1.2
(Note 1c) 1
TJ, TSTG Operating and Storage Junction Temperature Range –55 to +150 °C
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 50 °C/W
RθJC Thermal Resistance, Junction-to-Case (Note 1) 25 °C/W
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
FDS4501H FDS4501H 13” 12mm 2500 units
FDS4501H
FDS4501H Rev C(W)
Electrical Characteristics TA = 25°C unless otherwise noted
Symbol Parameter Test Conditions Type Min Typ Max Units
Off Characteristics
BVDSS Drain-Source Breakdown
Voltage VGS = 0 V, ID = 250 µA
VGS = 0 V, ID = –250 µA Q1
Q2 30
–20 V
∆BVDSS
∆TJ Breakdown Voltage
Temperature Coefficient ID = 250 µA, Referenced to 25°C
ID = –250 µA, Referenced to 25°C Q1
Q2
24
–13 mV/°C
IDSS Zero Gate Voltage Drain
Current VDS = 24 V, VGS = 0 V
VDS = –16 V, VGS = 0 V Q1
Q2 1
–1 µA
IGSS Gate-Body Leakage VGS = +20 V, VDS = 0 V
VGS = +8 V, VDS = 0 V Q1
Q2 +100
+100 nA
On Characteristics (Note 2)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA
VDS = VGS, ID = –250 µA Q1
Q2 1
–0.4 1.6
–0.7 3
–1.5 V
∆VGS(th)
∆TJ Gate Threshold Voltage
Temperature Coefficient ID = 250 µA, Referenced to 25°C
ID = –250 µA, Referenced to 25°C Q1
Q2 –4
3 mV/°C
RDS(on) Static Drain-Source
On-Resistance VGS = 10 V, ID = 9.3 A
VGS = 10 V, ID = 9.3 A, TJ = 125°C
VGS = 4.5 V, ID = 7.6 A
VGS = –4.5 V, ID = –5.6 A
VGS = –4.5 V, ID = –5.6 A, TJ = 125°C
VGS = –2.5 V, ID = –5.0 A
Q1
Q2
14
21
17
36
49
47
18
29
23
46
80
63
mΩ
ID(on) On-State Drain Current VGS = 10 V, VDS = 5 V
VGS = –4.5 V, VDS = –5 V Q1
Q2 20
–20 A
gFS Forward Transconductance VDS = 5 V, ID = 9.3 A
VDS = 5 V, ID = –5.6 A Q1
Q2 28
16 S
Dynamic Characteristics
Ciss Input Capacitance Q1
Q2 1958
1312 pF
Coss Output Capacitance Q1
Q2 424
240 pF
Crss Reverse Transfer Capacitance
VDS = 10 V, VGS = 0 V,
f = 1.0 MHz
Q1
Q2 182
106 pF
FDS4501H
FDS4501H Rev C(W)
Electrical Characteristics (continued) TA = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Switching Characteristics (Note 2)
td(on) Turn-On Delay Time
Q1
Q2 15
15 27
27 ns
tr Turn-On Rise Time
Q1
Q2 5
15 10
27 ns
td(off) Turn-Off Delay Time
Q1
Q2 38
40 61
64 ns
tf Turn-Off Fall Time
Q1
VDD = 15 V, ID = 1 A,
VGS = 10V, RGEN = 6 Ω
Q1
VDD = –10 V, ID = –1 A,
VGS = –4.5V, RGEN = 6 Ω Q1
Q2 10
25 20
40 ns
Qg Total Gate Charge
Q1
Q2 17
13 27
21 nC
Qgs Gate-Source Charge
Q1
Q2 4
2.5 nC
Qgd Gate-Drain Charge
Q1
VDS = 15 V, ID = 9.3 A, VGS = 4.5 V
Q2
VDS = 15 V, ID = –2.4 A,VGS = –4.5 V
Q1
Q2 5
2.0 nC
Drain-Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain-Source Diode Forward Current Q1
Q2 2.1
–2.1 A
VSD Drain-
Voltage VGS = 0 V, IS = 2.1 A (Note 2)
VGS = 0 V, IS = –2.1 A (Note 2) Q1
Q2 1.2
–1.2 V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
a) 50°C/W when
mounted on a
1 in2 pad of 2 oz
copper
b) 105°C/W when
mounted on a 0.04
in2 pad of 2 oz
copper
c) 125°C/W when mounted on a
minimum pad.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
FDS4501H Rev C(W)
Typical Characteristics: Q2
0
3
6
9
12
15
00.5 11.5 22.5
-VDS , DRAIN-SOURCE VOLTAGE (V)
-1.8V
-2.0V
-2.5V
-1.5V
VGS = -4.5V
-3.0V
0.5
1
1.5
2
2.5
3
3.5
4
0 3 6 9 12 15
-ID, DRAIN CURRENT (A)
VGS = -1.5V
-2.0V
-2.5V
-4.5V
-3.0V
-1.8V
Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
-50 -25 0 25 50 75 100 125 150
TJ
, JUNCTION TEMPERATURE (oC)
ID = -2.4A
VGS = -4.5V
0.02
0.04
0.06
0.08
0.1
0.12
0.14
12345
-VGS, GATE TO SOURCE VOLTAGE (V)
ID = -1.2 A
TA = 125oC
TA = 25oC
Figure 3. On-Resistance Variation with
Temperature. Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
0
3
6
9
12
15
00.5 11.5 22.5 3
-VGS, GATE TO SOURCE VOLTAGE (V)
TA = 125oC25oC
VDS = - 5V
-55oC
0.0001
0.001
0.01
0.1
1
10
100
00.2 0.4 0.6 0.8 11.2 1.4
-V SD, BODY DIODE FORWARD VOLTAGE (V)
TA = 125oC
25oC
-55oC
VGS = 0V
Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
FDS4501H
FDS4501H Rev C(W)
Typical Characteristics: Q2
0
1
2
3
4
5
0 2 4 6 8 10 12 14
Qg, GATE CHARGE (nC)
ID = -2.4A VDS = -5V
-15V
-10V
0
400
800
1200
1600
2000
0 5 10 15 20
-VDS , DRAIN TO SOURCE VOLTAGE (V)
CISS
C
RSS
COSS
f = 1MHz
VGS = 0 V
Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics.
0.01
0.1
1
10
100
0.1 1 10 100
-VDS , DRAIN-SOURCE VOLTAGE (V)
DC 10s1s
100ms
RDS(ON) LIMIT
VGS =-4.5V
SINGLE PULSE
RθJA = 125oC/W
TA = 25oC
1ms
10ms
0
5
10
15
20
0.01 0.1 1 10 100 1000
t1, TIME (sec)
SINGLE PULSE
RθJA = 125°C/W
TA = 25°C
Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum
Power Dissipation.
FDS4501H
FDS4501H Rev C(W)
Typical Characteristics: Q1
0
3
6
9
12
15
18
21
00.5 11.5 2
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 10.0V
4.5V
2.5V
3.0V
6.0V 3.5V
0.5
1
1.5
2
2.5
3
3.5
4
0 5 10 15 20 25
ID
, DIRAIN CURRENT (A)
VGS = 2.5V
4.5V 6.0V
3.0V
3.5V
10V
Figure 11. On-Region Characteristics. Figure 12. On-Resistance Variation with
Drain Current and Gate Voltage.
0.6
0.8
1
1.2
1.4
1.6
-50 -25 0 25 50 75 100 125 150
TJ
, JUNCTION TEMPERATURE (oC)
ID = 9.3A
VGS = 10V
0
0.02
0.04
0.06
0.08
22.5 33.5 44.5 5
VGS, GATE TO SOURCE VOLTAGE (V)
ID = 4.7A
TA = 125oC
TA = 25oC
Figure 13. On-Resistance Variation with
Temperature. Figure 14. On-Resistance Variation with
Gate-to-Source Voltage.
0
5
10
15
20
25
11.5 22.5 33.5
VGS, GATE TO SOURCE VOLTAGE (V)
TA = -55oC25oC
125oC
VDS = 5.0V
0.0001
0.001
0.01
0.1
1
10
100
00.2 0.4 0.6 0.8 11.2
VSD , BODY DIODE FORWARD VOLTAGE (V)
VGS = 0V
TA = 125oC
25oC
-55oC
Figure 15. Transfer Characteristics. Figure 16. Body Diode Forward Voltage Variation
with Source Current and Temperature.
FDS4501H
FDS4501H Rev C(W)
Typical Characteristics Q1
0
2
4
6
8
10
0 5 10 15 20 25 30
Qg
, GATE CHARGE (nC)
ID = 9.3A VDS = 5V 10
15V
0
500
1000
1500
2000
2500
3000
0 5 10 15 20
VDS , DRAIN TO SOURCE VOLTAGE (V)
CISS
COSS
CRSS
f = 1 MHz
VGS = 0 V
Figure 17. Gate Charge Characteristics. Figure 18. Capacitance Characteristics.
0.01
0.1
1
10
100
0.01 0.1 1 10 100
VDS , DRAIN-SOURCE VOLTAGE (V)
DC10s1s
100ms
100µs
RDS(ON) LIMIT
VGS = 10V
SINGLE PULSE
RθJA = 125oC/W
TA = 25oC
10ms
1ms
0
5
10
15
20
25
30
0.01 0.1 1 10
t1, TIME (sec)
P(pk), PEAK TRANSIENT POWER (W)
SINGLE PULSE
RθJA = 125°C/W
TA = 25°C
Figure 19. Maximum Safe Operating Area. Figure 20. Single Pulse Maximum
Power Dissipation.
0.001
0.01
0.1
1
0.0001 0.001 0.01 0.1 1 10 100 1000
t1, TIME (sec)
RθJA(t) = r(t) + RθJA
RθJA = 125 oC/W
TJ - TA = P * RθJA(t)
Duty Cycle, D = t1 / t2
P(pk)
t
1
t
2
SINGLE PULSE
0.01
0.02
0.05
0.1
0.2
D = 0.5
Figure 21. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
FDS4501H
SOIC(8ld s) Packaging
Configuration: Figure 1.0
Components Leader Tape
1680mm minimum or
210 empty poc kets
Tr ailer Tape
640mm min imum or
80 empty poc kets
SOIC(8ld s) Tape Leader and Trailer
Configuration: Figure 2.0
Cover Tape
Carrier Tape
Note/Comments
Packaging Option
SOIC (8lds) Packaging Information
Standard
(no flow code) L86Z F011
Packaging type
Reel Size
TNR
13" Dia
Rail/Tube
-
TNR
13" Dia
Qty per Reel/Tube/Bag 2,500 95 4,000
Box Dimension (mm) 355x333x40 530x130x83 355x333x40
Max qty per Box 5,000 30,000 8,000
D84Z
TNR
7" Dia
500
193x183x80
2,000
Weig ht pe r un it (gm) 0.0774 0.0774 0.0774 0.0774
Weig ht pe r Reel (kg) 0.6060 -0.9696 0.1182
F63TNR Label sample
LOT: CBVK741B019
FSID: FDS9953A
D/C1: Z9842AB QTY1: SPEC REV:
SPEC:
QTY: 2500
D/C2: QTY2: CPN: N/F: F (F63TNR)3
F
852
NDS
9959
SOIC-8 Unit Orientation
F
852
NDS
9959
Pi n 1
Static Dissipative
Embossed Carrier Tape
F63TNR
Label
Antis tati c Cover Tape
Customized
Label
Packaging Description:
SOIC-8 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
2,5 00 uni t s pe r 13" o r 33 0c m d ia met er re el . Th e re el s are
dark blue in color and is made of polystyrene plastic (anti-
static coated). Other option comes in 500 units per 7" or
177cm diameter reel. This and some other options are
further described in the Packaging Information table.
These full reels are individually barcode labeled and
placed inside a standard intermediate box (illustrated in
figure 1.0) made of recyclable corrugated brown paper.
One box contains two reels maximum. And these boxes
are placed inside a barcode labeled shipping box which
com e s in di ffe re nt s iz es depe ndin g on th e nu mbe r of part s
shipped.
F
852
NDS
9959
F
852
NDS
9959
F
852
NDS
9959
Embossed ESD Marking
ATTENTION
OBSERVE PRECAUTIONS
FOR HANDLING
ELECTROSTATIC
SENSITIVE
DEVICES
Embossed ESD Marking
ATTENTION
OBSERVE
FOR HANDLING
ELECTROSTATIC
SENSITIVE
DEVICES
ATTENTION
OBSERVE
FOR HANDLING
ELECTROSTATIC
SENSITIVE
DEVICES
ATTENTION
OBSERVE
FOR HANDLING
ATTENTION
OBSERVE
FOR HANDLING
ATTENTION
OBSERVE PRECAUTIONS
FOR HANDLING
ELECTROSTATIC
SENSITIVE
DEVICES
193mm x 183mm x 80mm
Pizza Box for Standard Option
Barcode
Label
Barcode
Label
Barcode Label
355mm x 333mm x 40mm
Intermediate container for 13” reel option
SOIC-8 Tape and Reel Data
January 2001, Rev. C
©2001 Fairchild Semiconductor Corporation
1998 Fairchild Semiconductor Corporation
Dimensions are in millimeter
Pkg type
A0 B0 W D0 D1 E1 E2 F P1 P0 K0 T Wc Tc
SOIC(8lds)
(12mm)
5.30
+/-0.10 6.50
+/-0.10 12.0
+/-0.3 1.55
+/-0.05 1.60
+/-0.10 1.75
+/-0.10 10.25
min 5.50
+/-0.05 8.0
+/-0.1 4.0
+/-0.1 2.1
+/-0.10
0.450
+/-
0.150
9.2
+/-0.3 0.06
+/-0.02
P1
A0 D1
P0
F
W
E1
D0
E2
B0
Tc
Wc
K0
T
Dimensions are in inches and millimeters
Tape Siz e Reel
Option Dim A Dim B Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL)
12m m 7" Dia 7.00
177.8 0.059
1.5 512 +0.020/-0.008
13 +0.5/-0.2 0.795
20.2 2.165
55 0.488 +0.078/-0.000
12.4 +2/0 0.724
18.4 0.469 – 0.606
11.9 – 15.4
12m m 13" Dia 13.00
330 0.059
1.5 512 +0.020/-0.008
13 +0.5/-0.2 0.795
20.2 7.00
178 0.488 +0.078/-0.000
12.4 +2/0 0.724
18.4 0.469 – 0.606
11.9 – 15.4
See detail AA
Dim A
max
13" Diameter Option
7" Diameter Option
Dim A
Max
See detail AA
W3
W2 max Measured at Hub
W1 Measured at Hub
Dim N
Dim D
min
Dim C
B Min
DETAIL AA
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
20 deg maximum component rotation
0.5mm
maximum
0.5mm
maximum
Sketch C (Top View)
Component lateral movement
Typical
component
cavity
center line
20 deg maximum
Typical
component
center line
B0
A0
Sketch B (Top View)
Component Rotation
Sketch A (Side or Front Sectional View)
Component Rotation
User Direction of Feed
SOIC(8ld s) Embossed Carrier Tape
Configuration: Figure 3.0
SOIC(8ld s) Reel Confi gu rat ion: Figure 4.0
SOIC-8 Tape and Reel Data, continued
January 2001, Rev. C
SOIC-8 (FS PKG Code S1)
1 : 1
Scale 1:1 on letter size paper
D i m ens ion s sh own belo w are i n:
inches [m illimet ers ]
Part Weight per unit (gram): 0.0774
SOIC-8 Package Dimensions
September 1998, Rev. A
9
©2000 Fairchild Semiconductor International
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF F AIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT ST A TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN T O IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PA TENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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