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FEATURES
Converts CMOS RAM into nonvolatile
memories
Unconditionally write protects when VCC is
out of tolerance
Automatically switches to battery when
power fail occurs
Space saving 8-pin PDIP or 8-pin 150 mil SO
Packages
Consumes less than 100nA of battery current
PIN ASSIGNMENT
PIN DESCRIPTION
VCCI - Input +5 Volt Supply
VCCO - RAM Power (VCC) Supply
CEI
- Chip Enable Input
NC - No Connection
CEO
- Chip Enable Output
VBAT - + Battery
GND - Ground
DESCRIPTION
The DS1218 is a CMOS circuit which solves the application problems of converting CMOS RAM into
nonvolatile memory. Incoming power is monitored for an out-of-tolerance condition. When such a
condition is detected, the chip enable output is inhibited to accomplish write protection and the battery is
switched on to supply RAM with uninterrupted power. Special circuitry uses a low-leakage CMOS
process which affords precise voltage detection at extremely low battery consumption. The 8-pin package
keeps PC board real estate requirements to a minimum. By combining the DS1218 nonvolatile controller
chip with a full CMOS memory and lithium batteries, 10 years of nonvolatile RAM operation can be
achieved.
OPERATION
The DS1218 Nonvolatile Controller performs the circuit functions required to battery back-up a RAM.
First, a switch is provided to direct power from the battery or VCCI supply, depending on which is greater.
This switch has a voltage drop of less than 0.2V. The second function which the nonvolatile controller
provides is power-fail detection. The DS1218 constantly monitors the VCC supply. When VCCI falls to
1.26 times the battery voltage, a precision comparator outputs a power-fail detect signal to the chip enable
logic. The third function of write protection is accomplished by holding the chip enable output signal to
within 0.2V of the VCCI or battery supply, when a power-fail condition is detected.
During nominal supply conditions, the chip enable output will follow chip enable input with a maximum
propagation delay of 10 ns.
DS1218
Nonvolatile Controller
VCCO
NC
NC
GND
VCCI
VBAT
CEO
CEI
1
2
3
4
8
7
6
5
19-6295; Rev 6/12
DS1218
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ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground -0.5V to +7.0V
Operating Temperature Range 0°C to +70°C
Storage Temperature Range -55°C to +125°C
Soldering Temperature (reflow, SO) +260°C
Lead Temperature (soldering, 10s) +300°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of
time may affect reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
PDIP
Junction-to-Ambient Thermal Resistance (θJA).…………………...……………………....110°C/W
Junction-to-Case Thermal Resistance (θJC)…………………………………………………40°C/W
SO
Junction-to-Ambient Thermal Resistance (θJA).…………………………………………...136°C/W
Junction-to-Case Thermal Resistance (θJC)…………………………………………………38°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board for the SO. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
RECOMMENDED OPERATING CONDITIONS (0°C to +70°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Supply
VCCI
4.5
5.0
5.5
V
2
Logic 1
VIH
2.0
5.5
V
2
Logic 0
VIL
-0.3
0.8
V
2
Battery Supply
VBAT
2.5
3.0
3.5
V
2
DC ELECTRICAL CHARACTERISTICS (0°C to +70°C; VCCI = 5V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Active Current
ICCI
2
5
mA
4
Battery Current
IBAT
100
nA
4, 5
RAM Current
(VCCO1 ≥ VCCI -0.3V)
I
CCO
80
mA
6
RAM Current
(VCCO ≥ VCCI -0.2V)
I
CCO
70
mA
Input Leakage
IIL
-1.0
+1.0
µA
CEO
Output @ 2.4V
I
OH
-1.0
mA
CEO
Output @ 0.4V
I
OL
4.0
mA
VCC Trip Point
VCCTP
1.26xVBAT
CAPACITANCE (TA = +25°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Capacitance
CIN
5
pF
Output Capacitance
COUT
7
pF
DS1218
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AC ELECTRICAL CHARACTERISTICS (0°C to +70°C; VCC = 5.0V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
CE
Propagation Delay
t
PD
4
10
ns
3
Recovery at Power-up
tREC
0.2
2
ms
VCC Slew Rate
tF
500
µs
CE
Pulse Width
t
CE
1.5
µs
7, 8
DS1218
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TIMING DIAGRAM: POWER-UP
TIMING DIAGRAM: POWER-DOWN
DS1218
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NOTES:
2. All voltages referenced to ground.
3. Measured with a load as shown in Figure 1.
4. Outputs open.
5. Drain from battery when VCC < VBAT.
6. Maximum amount of current which can be drawn through pin 1 of the controller.
7. tCE max must be met to ensure data integrity on power loss.
8.
CEO
can only sustain leakage current in the battery backup mode.
OUTPUT LOAD Figure 1
DS1218
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ORDERING INFORMATION
PART
TEMP
RANGE
PIN-
PACKAGE
DS1218+
0°C to +70°C
8 PDIP
DS1218S+
0°C to +70°C
8 SO
+Denotes a lead(Pb)-free/RoHS-compliant package.
PACKAGE INFORMATION
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
8 PDIP
P8+1
21-0043
8 SO
S8+2
21-0041
90-0096
DS1218
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Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim
reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, Inc. 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
6/12
Added lead temperature and soldering temperature information to
the Absolute Maximum Ratings section; added the Package
Thermal Characteristics section; added the Ordering Information
and Package Information sections
2, 6
