DSP Microcomputer ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L PERFORMANCE FEATURES SYSTEM INTERFACE FEATURES Up to 19 ns instruction cycle time, 52 MIPS sustained performance Single-cycle instruction execution Single-cycle context switch 3-bus architecture allows dual operand fetches in every instruction cycle Multifunction instructions Power-down mode featuring low CMOS standby power dissipation with 400 CLKIN cycle recovery from power-down condition Low power dissipation in idle mode 16-bit internal DMA port for high-speed access to on-chip memory (mode selectable) 4M-byte memory interface for storage of data tables and program overlays (mode selectable) 8-bit DMA to byte memory for transparent program and data memory transfers (mode selectable) Programmable memory strobe and separate I/O memory space permits "glueless" system design Programmable wait state generation 2 double-buffered serial ports with companding hardware and automatic data buffering Automatic booting of on-chip program memory from bytewide external memory, for example, EPROM, or through internal DMA Port 6 external interrupts 13 programmable flag pins provide flexible system signaling UART emulation through software SPORT reconfiguration ICE-Port emulator interface supports debugging in final systems INTEGRATION FEATURES ADSP-2100 family code compatible (easy to use algebraic syntax), with instruction set extensions Up to 160K bytes of on-chip RAM, configured Up to 32K words program memory RAM Up to 32K words data memory RAM Dual-purpose program memory for both instruction and data storage Independent ALU, multiplier/accumulator, and barrel shifter computational units 2 independent data address generators Powerful program sequencer provides zero overhead looping conditional instruction execution Programmable 16-bit interval timer with prescaler 100-lead LQFP and 144-ball BGA POWER-DOWN CONTROL FULL MEMORY MODE MEMORY DATA ADDRESS GENERATORS DAG1 DAG2 PROGRAM SEQUENCER PROGRAM MEMORY UP TO 32K 24-BIT PROGRAMMABLE I/O AND FLAGS DATA MEMORY UP TO 32K 16-BIT PROGRAM MEMORY ADDRESS EXTERNAL DATA BUS DATA MEMORY ADDRESS BYTE DMA CONTROLLER PROGRAM MEMORY DATA OR DATA MEMORY DATA ARITHMETIC UNITS ALU MAC SHIFTER EXTERNAL ADDRESS BUS EXTERNAL DATA BUS SERIAL PORTS SPORT0 TIMER SPORT1 ADSP-2100 BASE ARCHITECTURE INTERNAL DMA PORT HOST MODE Figure 1. Functional Block Diagram ICE-Port is a trademark of Analog Devices, Inc. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved. ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L TABLE OF CONTENTS Performance Features ............................................... 1 Specifications ........................................................ 21 Integration Features ................................................. 1 Operating Conditions ........................................... 21 System Interface Features ........................................... 1 Electrical Characteristics ....................................... 21 Table of Contents ..................................................... 2 Absolute Maximum Ratings ................................... 22 Revision History ...................................................... 2 Package Information ............................................ 22 General Description ................................................. 3 ESD Sensitivity ................................................... 22 Architecture Overview ........................................... 3 Timing Specifications ........................................... 22 Modes Of Operation .............................................. 4 Power Supply Current .......................................... 36 Interrupts ........................................................... 5 Power Dissipation ............................................... 37 Low Power Operation ............................................ 6 Output Drive Currents ......................................... 40 System Interface ................................................... 7 Power-Down Current ........................................... 41 Reset .................................................................. 8 Capacitive Loading - ADSP-2184L, ADSP-2186L ........ 42 Memory Architecture ............................................ 8 Capacitive Loading - ADSP-2185L, ADSP-2187L ........ 42 Bus Request and Bus Grant ................................... 13 Test Conditions .................................................. 43 Flag I/O Pins ..................................................... 13 Environmental Conditions .................................... 43 Instruction Set Description ................................... 14 LQFP Package Pinout ........................................... 44 Development System ........................................... 14 BGA Package Pinout ............................................ 45 Additional Information ........................................ 16 Outline Dimensions ................................................ 46 Pin Descriptions .................................................... 17 Surface Mount Design .......................................... 47 Memory Interface Pins ......................................... 18 Ordering Guide ..................................................... 47 Terminating Unused Pins ..................................... 19 REVISION HISTORY 1/08--Rev. C This revision of the ADSP-2184L/ADSP-2185L/ ADSP-2186L/ADSP-2187L processor data sheet combines the ADSP-2184L, ADSP-2185L, ADSP-2186L, and ADSP-2187L. This version also contains new RoHS compliant packages. Rev. C | Page 2 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L GENERAL DESCRIPTION The ADSP-218xL series consists of four single chip microcomputers optimized for digital signal processing applications. The functional block diagram for the ADSP-218xL series members appears in Figure 1 on Page 1. All series members are pin-compatible and are differentiated solely by the amount of on-chip SRAM. This feature, combined with ADSP-21xx code compatibility, provides a great deal of flexibility in the design decision. Specific family members are shown in Table 1. ARCHITECTURE OVERVIEW Table 1. ADSP-218xL DSP Microcomputer Family The functional block diagram is an overall block diagram of the ADSP-218xL series. The processor contains three independent computational units: the ALU, the multiplier/accumulator (MAC), and the shifter. The computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add, and multiply/subtract operations with 40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. Device ADSP-2184L ADSP-2185L ADSP-2186L ADSP-2187L Program Memory (K words) 4 16 8 32 Data Memory (K words) 4 16 8 32 ADSP-218xL series members combine the ADSP-2100 family base architecture (three computational units, data address generators, and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, flag I/O, extensive interrupt capabilities, and on-chip program and data memory. ADSP-218xL series members integrate up to 160K bytes of onchip memory configured as up to 32K words (24-bit) of program RAM, and up to 32K words (16-bit) of data RAM. Powerdown circuitry is also provided to meet the low power needs of battery-operated portable equipment. The ADSP-218xL is available in 100-lead LQFP and 144-ball BGA packages. Fabricated using high-speed, low-power, CMOS processes, ADSP-218xL series members operate with a 19 ns instruction cycle time (ADSP-2185L and ADSP-2187L) or a a 25 ns instruction cycle time (ADSP-2184L and ADSP-2186L). Every instruction can execute in a single processor cycle. The ADSP-218xL series instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a single processor cycle. The ADSP-218xL assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development. The shifter can be used to efficiently implement numeric format control, including multiword and block floating-point representations. The internal result (R) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle. A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine calls, and returns in a single cycle. With internal loop counters and loop stacks, ADSP-218xL series members execute looped code with zero overhead; no explicit jump instructions are required to maintain loops. * Generate the next program address Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four address pointers. Whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four possible modify registers. A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. * Fetch the next instruction Five internal buses provide efficient data transfer: The ADSP-218xL's flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle, ADSP-218xL series members can: * Perform one or two data moves * Program Memory Address (PMA) Bus * Update one or two data address pointers * Program Memory Data (PMD) Bus * Perform a computational operation * Data Memory Address (DMA) Bus This takes place while the processor continues to: * Data Memory Data (DMD) Bus * Receive and transmit data through the two serial ports * Result (R) Bus * Receive and/or transmit data through the internal DMA port * Receive and/or transmit data through the byte DMA port * Decrement timer Rev. C | Page 3 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (PMD and DMD) share a single external data bus. Byte memory space and I/O memory space also share the external buses. Program memory can store both instructions and data, permitting ADSP-218xL series members to fetch two operands in a single cycle, one from program memory and one from data memory. ADSP-218xL series members can fetch an operand from program memory and the next instruction in the same cycle. In lieu of the address and data bus for external memory connection, ADSP-218xL series members can be configured for 16-bit Internal DMA port (IDMA port) connection to external systems. The IDMA port is made up of 16 data/address pins and five control pins. The IDMA port provides transparent, direct access to the DSP's on-chip program and data RAM. An interface to low cost, byte-wide memory is provided by the Byte DMA port (BDMA port). The BDMA port is bidirectional and can directly address up to four megabytes of external RAM or ROM for off-chip storage of program overlays or data tables. The byte memory and I/O memory space interface supports slow memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain control of external buses with bus request/grant signals (BR, BGH, and BG). One execution mode (Go Mode) allows the ADSP-218xL to continue running from on-chip memory. Normal execution mode requires the processor to halt while buses are granted. ADSP-218xL series members can respond to eleven interrupts. There can be up to six external interrupts (one edge-sensitive, two level-sensitive, and three configurable) and seven internal interrupts generated by the timer, the serial ports (SPORT), the BDMA port, and the power-down circuitry. There is also a master RESET signal. The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. Each serial port can generate an internal programmable serial clock or accept an external serial clock. ADSP-218xL series members provide up to 13 general-purpose flag pins. The data input and output pins on SPORT1 can be alternatively configured as an input flag and an output flag. In addition, eight flags are programmable as inputs or outputs, and three flags are always outputs. A programmable interval timer generates periodic interrupts. A 16-bit count register (TCOUNT) decrements every n processor cycle, where n is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD). Rev. C | Page 4 of 48 | Serial Ports ADSP-218xL series members incorporate two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Following is a brief list of the capabilities of the ADSP-218xL SPORTs. For additional information on Serial Ports, refer to the ADSP-218x DSP Hardware Reference. * SPORTs are bidirectional and have a separate, doublebuffered transmit and receive section. * SPORTs can use an external serial clock or generate their own serial clock internally. * SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame synchronization signals internally or externally generated. Frame sync signals are active high or inverted, with either of two pulse widths and timings. * SPORTs support serial data word lengths from 3 bits to 16 bits and provide optional A-law and -law companding, according to CCITT recommendation G.711. * SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer. * SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. An interrupt is generated after a data buffer transfer. * SPORT0 has a multichannel interface to selectively receive and transmit a 24-word or 32-word, time-division multiplexed, serial bitstream. * SPORT1 can be configured to have two external interrupts (IRQ0 and IRQ1) and the FI and FO signals. The internally generated serial clock may still be used in this configuration. MODES OF OPERATION The ADSP-218xL series modes of operation appear in Table 2. Only the ADSP-2187L provides Mode D operation Setting Memory Mode Memory Mode selection for the ADSP-218xL series is made during chip reset through the use of the Mode C pin. This pin is multiplexed with the DSP's PF2 pin, so care must be taken in how the mode selection is made. The two methods for selecting the value of Mode C are active and passive. Passive Configuration Passive Configuration involves the use of a pull-up or pulldown resistor connected to the Mode C pin. To minimize power consumption, or if the PF2 pin is to be used as an output in the DSP application, a weak pull-up or pull-down resistance, on the order of 10 k, can be used. This value should be sufficient to pull the pin to the desired level and still allow the pin to operate as a programmable flag output without undue strain on the processor's output driver. For minimum power consumption January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Table 2. Modes of Operation 1 2 Mode D1 X Mode C 0 Mode B 0 Mode A 0 X 0 1 0 0 1 0 0 0 1 0 1 1 1 0 0 1 1 0 1 Booting Method BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Full Memory Mode.2 No automatic boot operations occur. Program execution starts at external memory location 0. Chip is configured in Full Memory Mode. BDMA can still be used, but the processor does not automatically use or wait for these operations. BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Host Mode. IACK has active pull-down. (Requires additional hardware.) IDMA feature is used to load any internal memory as desired. Program execution is held off until the host writes to internal program memory location 0. Chip is configured in Host Mode. IACK has active pull-down.2 BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Host Mode; IACK requires external pull-down. (Requires additional hardware.) IDMA feature is used to load any internal memory as desired. Program execution is held off until the host writes to internal program memory location 0. Chip is configured in Host Mode. IACK requires external pull-down.2 Mode D applies to the ADSP-2187L processor only. Considered as standard operating settings. Using these configurations allows for easier design and better memory management. during power-down, reconfigure PF2 to be an input, as the pullup or pull-down resistance will hold the pin in a known state, and will not switch. Active Configuration Active Configuration involves the use of a three-statable external driver connected to the Mode C pin. A driver's output enable should be connected to the DSP's RESET signal such that it only drives the PF2 pin when RESET is active (low). When RESET is deasserted, the driver should be three-state, thus allowing full use of the PF2 pin as either an input or output. To minimize power consumption during power-down, configure the programmable flag as an output when connected to a threestated buffer. This ensures that the pin will be held at a constant level, and will not oscillate should the three-state driver's level hover around the logic switching point. IDMA ACK Configuration (ADSP-2187L Only) Mode D = 0 and in Host Mode: IACK is an active, driven signal and cannot be "wire-OR'ed." Mode D = 1 and in Host Mode: IACK is an open drain and requires an external pull-down, but multiple IACK pins can be "wire-OR'ed" together. INTERRUPTS The interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead. ADSP-218xL series members provide four dedicated external interrupt input pins: IRQ2, IRQL0, IRQL1, and IRQE (shared with the PF7-4 pins). In addition, SPORT1 may be reconfigured for IRQ0, IRQ1, FI, and FO, for a total of six external interrupts. The ADSP-218xL also supports internal interrupts Rev. C | Page 5 of 48 | from the timer, the byte DMA port, the two serial ports, software, and the power-down control circuit. The interrupt levels are internally prioritized and individually maskable (except power-down and reset). The IRQ2, IRQ0, and IRQ1 input pins can be programmed to be either level- or edge-sensitive. IRQL0 and IRQL1 are level-sensitive and IRQE is edge-sensitive. The priorities and vector addresses of all interrupts are shown in Table 3. Table 3. Interrupt Priority and Interrupt Vector Addresses Source Of Interrupt RESET (or Power-Up with PUCR = 1) Power-Down (Nonmaskable) IRQ2 IRQL1 IRQL0 SPORT0 Transmit SPORT0 Receive IRQE BDMA Interrupt SPORT1 Transmit or IRQ1 SPORT1 Receive or IRQ0 Timer Interrupt Vector Address (Hex) 0x0000 (highest priority) 0x002C 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 (lowest priority) Interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. Interrupts can be masked or unmasked with the IMASK register. January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Individual interrupt requests are logically AND'ed with the bits in IMASK; the highest priority unmasked interrupt is then selected. The power-down interrupt is nonmaskable. ADSP-218xL series members mask all interrupts for one instruction cycle following the execution of an instruction that modifies the IMASK register. This does not affect serial port autobuffering or DMA transfers. The interrupt control register, ICNTL, controls interrupt nesting and defines the IRQ0, IRQ1, and IRQ2 external interrupts to be either edge- or level-sensitive. The IRQE pin is an external edge-sensitive interrupt and can be forced and cleared. The IRQL0 and IRQL1 pins are external level sensitive interrupts. The IFC register is a write-only register used to force and clear interrupts. On-chip stacks preserve the processor status and are automatically maintained during interrupt handling. The stacks are 12 levels deep to allow interrupt, loop, and subroutine nesting. The following instructions allow global enable or disable servicing of the interrupts (including power-down), regardless of the state of IMASK: ENA INTS; DIS INTS; Disabling the interrupts does not affect serial port autobuffering or DMA. When the processor is reset, interrupt servicing is enabled. LOW POWER OPERATION * Support for crystal operation includes disabling the oscillator to save power (the processor automatically waits approximately 4096 CLKIN cycles for the crystal oscillator to start or stabilize), and letting the oscillator run to allow 400 CLKIN cycle start-up. * Power-down is initiated by either the power-down pin (PWD) or the software power-down force bit. Interrupt support allows an unlimited number of instructions to be executed before optionally powering down. The powerdown interrupt also can be used as a nonmaskable, edgesensitive interrupt. * Context clear/save control allows the processor to continue where it left off or start with a clean context when leaving the power-down state. * The RESET pin also can be used to terminate power-down. * Power-down acknowledge pin (PWDACK) indicates when the processor has entered power-down. Idle When the ADSP-218xL is in the Idle Mode, the processor waits indefinitely in a low-power state until an interrupt occurs. When an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the IDLE instruction. In Idle Mode IDMA, BDMA, and autobuffer cycle steals still occur. Slow Idle ADSP-218xL series members have three low-power modes that significantly reduce the power dissipation when the device operates under standby conditions. These modes are: * Idle The IDLE instruction is enhanced on ADSP-218xL series members to let the processor's internal clock signal be slowed, further reducing power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the IDLE instruction. * Slow Idle The format of the instruction is: * Power-Down IDLE (n); The CLKOUT pin may also be disabled to reduce external power dissipation. Power-Down ADSP-218xL series members have a low-power feature that lets the processor enter a very low-power dormant state through hardware or software control. Following is a brief list of powerdown features. Refer to the ADSP-218x DSP Hardware Reference, "System Interface" chapter, for detailed information about the power-down feature. * Quick recovery from power-down. The processor begins executing instructions in as few as 400 CLKIN cycles. * Support for an externally generated TTL or CMOS processor clock. The external clock can continue running during power-down without affecting the lowest power rating and 400 CLKIN cycle recovery. Rev. C | Page 6 of 48 | where n = 16, 32, 64, or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While it is in this state, the processor's other internal clock signals, such as SCLK, CLKOUT, and timer clock, are reduced by the same ratio. The default form of the instruction, when no clock divisor is given, is the standard IDLE instruction. When the IDLE (n) instruction is used, it effectively slows down the processor's internal clock and thus its response time to incoming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an enabled interrupt is received, ADSP-218xL series members remain in the idle state for up to a maximum of n processor cycles (n = 16, 32, 64, or 128) before resuming normal operation. When the IDLE (n) instruction is used in systems that have an externally generated serial clock (SCLK), the serial clock rate may be faster than the processor's reduced internal clock rate. Under these conditions, interrupts must not be generated at a January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles). power-down state. For additional information, refer to the ADSP-218x DSP Hardware Reference, for detailed information on this power-down feature. SYSTEM INTERFACE If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected to the processor's CLKIN input. When an external clock is used, the XTAL pin must be left unconnected. Figure 2 shows typical basic system configurations with the ADSP-218xL series, two serial devices, a byte-wide EPROM, and optional external program and data overlay memories (mode-selectable). Programmable wait state generation allows the processor to connect easily to slow peripheral devices. ADSP-218xL series members also provide four external interrupts and two serial ports or six external interrupts and one serial port. Host Memory Mode allows access to the full external data bus, but limits addressing to a single address bit (A0). Through the use of external hardware, additional system peripherals can be added in this mode to generate and latch address signals. ADSP-218xL series members use an input clock with a frequency equal to half the instruction rate; a 40 MHz input clock yields a 12.5 ns processor cycle (which is equivalent to 80 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction clock rate, which is indicated by the CLKOUT signal when enabled. Because ADSP-218xL series members include an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 3. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. To provide an adequate feedback path around the internal amplifier circuit, place a resistor in parallel with the circuit, as shown in Figure 3. Clock Signals ADSP-218xL series members can be clocked by either a crystal or a TTL-compatible clock signal. The CLKIN input cannot be halted, changed during operation, nor operated below the specified frequency during normal operation. The only exception is while the processor is in the A clock output (CLKOUT) signal is generated by the processor at the processor's cycle rate. This can be enabled and disabled by the CLKODIS bit in the SPORT0 Autobuffer Control Register. FULL MEMORY MODE 1/2 CLOCK OR CRYSTAL ADSP-218xL SERIAL DEVICE 1/2 CLOCK OR CRYSTAL CLKIN XTAL ADDR13-0 14 FL0-2 SERIAL DEVICE HOST MEMORY MODE ADSP-218xL A13-0 D23-16 IRQ2/PF7 IRQE/PF4 DATA23-0 IRQL0/PF5 BMS IRQL1/PF6 WR MODE D/PF3 RD MODE C/PF2 MODE A/PF0 MODE B/PF1 IOMS SPORT1 SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO PMS DR1 OR FI DMS CMS SPORT0 SCLK0 BR RFS0 BG TFS0 BGH DT0 PWD DR0 PW DACK 24 CLK IN XTAL A0-A21 FL0-2 BYTE MEMORY D15-8 DATA CS ADDR DATA CS A13-0 er int DATA D23-0 em yst s ert Ins d ace fADDR I/O SPACE (PERIPHERALS) 2048 LOCATIONS ia m gra 1 IRQ2/PF7 IRQE/PF4 DATA23-8 IRQL0/PF5 IRQL1/PF6 BMS MODE D/PF3 WR MODE C/PF2 RD MODE A/PF0 MODE B/PF1 A10-0 D23-8 A0 re he SPORT1 SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO DR1 OR FI SERIAL DEVICE OVERLAY MEMORY TWO 8K PM SEGMEN TS TWO 8K DM SEGMEN TS SPORT0 SCLK0 RFS0 TFS0 DT0 DR0 SERIAL DEVICE SYSTEM INTERFACE OR CONTROLLER 16 IOMS PMS DMS CMS BR BG BGH PWD IDMA PORT PW DACK IRD/D6 IWR/D7 IS/D4 IAL/D5 IACK/D3 IAD15-0 NOTE: MODE D APPLIES TO THE ADSP-2187L P ROCES SOR ON LY Figure 2. Basic System Interface Rev. C | Page 7 of 48 | January 2008 16 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L sequence is performed. The first instruction is fetched from onchip program memory location 0x0000 once boot loading completes. 1M MEMORY ARCHITECTURE XTAL CLKIN The ADSP-218xL series provides a variety of memory and peripheral interface options. The key functional groups are Program Memory, Data Memory, Byte Memory, and I/O. Refer to Figure 4 through Figure 7 for PM and DM memory allocations in the ADSP-218xL series. CLKOUT DSP Figure 3. External Crystal Connections Program Memory Program Memory (Full Memory Mode) is a 24-bit-wide space for storing both instruction opcodes and data. The member DSPs of this series have up to 32K words of Program Memory RAM on chip, and the capability of accessing up to two 8K external memory overlay spaces, using the external data bus. RESET The RESET signal initiates a master reset of the ADSP-218xL. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power-up, the clock continues to run and does not require stabilization time. Program Memory (Host Mode) allows access to all internal memory. External overlay access is limited by a single external address line (A0). External program execution is not available in Host Mode due to a restricted data bus that is only 16 bits wide. The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 2000 CLKIN cycles ensures that the PLL has locked, but does not include the crystal oscillator start-up time. During this power-up sequence, the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the minimum pulse width specification (tRSP). Data Memory Data Memory (Full Memory Mode) is a 16-bit-wide space used for the storage of data variables and for memory-mapped control registers. The ADSP-218xL series has up to 32K words of Data Memory RAM on-chip. Part of this space is used by 32 memory-mapped registers. Support also exists for up to two 8K external memory overlay spaces through the external data bus. The RESET input contains some hysteresis; however, if an RC circuit is used to generate the RESET signal, the use of an external Schmitt trigger is recommended. All internal accesses complete in one cycle. Accesses to external memory are timed using the wait states specified by the DWAIT register. The master reset sets all internal stack pointers to the empty stack condition, masks all interrupts, and clears the MSTAT register. When RESET is released, if there is no pending bus request and the chip is configured for booting, the boot-loading Data Memory (Host Mode) allows access to all internal memory. External overlay access is limited by a single external address line (A0). PROGRAM MEMORY MODEB = 1 0x3FFF PROGRAM MEMORY MODEB = 0 0x3FFF 0x3FFF PM OVERLAY 1,2 (EXTERNAL PM) RESERVED PM OVERLAY 0 (RESERVED) 0x2000 0x1FFF 0x2000 0x1FFF 32 MEMORY-MAPPED CONTROL REGISTERS 0x3FE0 0x3FDF 0x3000 0x2FFF INTERNAL DM DM OVERLAY 1,2 (EXTERNAL DM) 0x1000 0x0FFF DM OVERLAY 0 (RESERVED) INTERNAL PM 0x0000 0x0000 0x0000 Figure 4. ADSP-2184 Memory Architecture Rev. C | 4064 RESERVED WORDS 0x2000 0x1FFF RESERVED EXTERNAL PM DATA MEMORY Page 8 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L PROGRAM MEMORY MODEB = 1 0x3FFF PROGRAM MEMORY MODEB = 0 0x3FFF 0x3FFF PM OVERLAY 1,2 (EXTERNAL PM) RESERVED DATA MEMORY 32 MEMORY-MAPPED CONTROL REGISTERS 0x3FE0 0x3FDF PM OVERLAY 0 (INTERNAL PM) 0x2000 0x1FFF 0x2000 0x1FFF EXTERNAL PM INTERNAL DM 0x2000 0x1FFF DM OVERLAY 1,2 (EXTERNAL DM) INTERNAL PM DM OVERLAY 0 (INTERNAL DM) 0x0000 0x0000 0x0000 Figure 5. ADSP-2185 Memory Architecture PROGRAM MEMORY MODEB = 1 0x3FFF PROGRAM MEMORY MODEB = 0 0x3FFF 0x3FFF PM OVERLAY 1,2 (EXTERNAL PM) RESERVED DATA MEMORY 32 MEMORY-MAPPED CONTROL REGISTERS 0x3FE0 0x3FDF PM OVERLAY 0 (RESERVED) 0x2000 0x1FFF 0x2000 0x1FFF EXTERNAL PM INTERNAL DM 0x2000 0x1FFF DM OVERLAY 1,2 (EXTERNAL DM) INTERNAL PM DM OVERLAY 0 (RESERVED) 0x0000 0x0000 0x0000 Figure 6. ADSP-2186 Memory Architecture PROGRAM MEMORY MODEB = 1 0x3FFF PROGRAM MEMORY MODEB = 0 0x3FFF 0x3FFF PM OVERLAY 1,2 (EXTERNAL PM) RESERVED DATA MEMORY 32 MEMORY-MAPPED CONTROL REGISTERS 0x3FE0 0x3FDF PM OVERLAY 0,4,5 (INTERNAL PM) 0x2000 0x1FFF 0x2000 0x1FFF EXTERNAL PM INTERNAL DM 0x2000 0x1FFF DM OVERLAY 1,2 (EXTERNAL DM) INTERNAL PM DM OVERLAY 0,4,5 (INTERNAL DM) 0x0000 0x0000 0x0000 Figure 7. ADSP-2187 Memory Architecture Rev. C | Page 9 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Table 4. PMOVLAY Bits Processor ADSP-2184L ADSP-2185L ADSP-2186L ADSP-2187L All Processors All Processors PMOVLAY No internal overlay region 0 No internal overlay region 0, 4, 5 1 2 Memory Not Applicable A13 Not applicable A12-0 Not applicable Internal overlay Not applicable Not applicable Not applicable Not applicable Not applicable Internal overlay External overlay 1 External overlay 2 Not applicable 0 1 Not applicable 13 LSBs of address between 0x2000 and 0x3FFF 13 LSBs of address between 0x2000 and 0x3FFF Table 5. DMOVLAY Bits Processor ADSP-2184L ADSP-2185L ADSP-2186L ADSP-2187L All Processors All Processors DMOVLAY No internal overlay region 0 No internal overlay region 0, 4, 5 1 2 Memory Not applicable A13 Not applicable A12-0 Not applicable Internal overlay Not applicable Not applicable Not applicable Not applicable Not applicable Internal overlay External overlay 1 External overlay 2 Not applicable 0 1 Not applicable 13 LSBs of address between 0x0000 and 0x1FFF 13 LSBs of address between 0x0000 and 0x1FFF I/O Space (Full Memory Mode) ADSP-218xL series members support an additional external memory space called I/O space. This space is designed to support simple connections to peripherals (such as data converters and external registers) or to bus interface ASIC data registers. I/O space supports 2048 locations of 16-bit wide data. The lower eleven bits of the external address bus are used; the upper three bits are undefined. Two instructions were added to the core ADSP-2100 family instruction set to read from and write to I/O memory space. The I/O space also has four dedicated 3-bit wait state registers, IOWAIT0-3 as shown in Figure 8, which specify up to seven wait states to be automatically generated for each of four regions. The wait states act on address ranges, as shown in Table 6. Note: In Full Memory Mode, all 2048 locations of I/O space are directly addressable. In Host Memory Mode, only address pin A0 is available; therefore, additional logic is required externally to achieve complete addressability of the 2048 I/O space locations. Table 6. Wait States Address Range 0x000-0x1FF 0x200-0x3FF 0x400-0x5FF 0x600-0x7FF Wait State Register IOWAIT0 IOWAIT1 IOWAIT2 IOWAIT3 WAIT STATE CONTROL 15 14 13 12 11 10 0 1 1 DWAIT 1 1 1 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 IOWAIT3 IOWAIT2 IOWAIT1 DM(0x3FFE) IOWAIT0 RESERVED Figure 8. Wait State Control Register Composite Memory Select ADSP-218xL series members have a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space. The CMS signal is generated to have the same timing as each of the individual memory select signals (PMS, DMS, BMS, IOMS) but can combine their functionality. Each bit in the CMSSEL register, when set, causes the CMS signal to be asserted when the selected memory select is asserted. For example, to use a 32K word memory to act as both program and data memory, set the PMS and DMS bits in the CMSSEL register and use the CMS pin to drive the chip select of the memory, and use either DMS or PMS as the additional address bit. The CMS pin functions like the other memory select signals with the same timing and bus request logic. A 1 in the enable bit causes the assertion of the CMS signal at the same time as the selected memory select signal. All enable bits default to 1 at reset, except the BMS bit. Rev. C | Page 10 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L See Figure 9 and Figure 10 for illustration of the programmable flag and composite control register and the system control register. PROGRAMMABLE FLAG AND COMPOSITE SELECT CONTROL 15 14 13 12 11 10 0 1 1 1 1 0 BMWAIT 9 8 7 6 5 4 3 2 1 0 1 1 0 0 0 0 0 0 0 0 CMSSEL 0 = DISABLE CMS 1 = ENABLE CMS RESERVED Byte Memory DMA (BDMA, Full Memory Mode) The byte memory DMA controller (Figure 11) allows loading and storing of program instructions and data using the byte memory space. The BDMA circuit is able to access the byte memory space while the processor is operating normally and steals only one DSP cycle per 8-, 16-, or 24-bit word transferred. DM(0x3FE6) BDMA CONTROL PFTYPE 0 = INPUT 1 = OUTPUT 15 14 13 12 11 10 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 0 0 DM (0x3FE3) (WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM) BMPAGE Figure 9. Programmable Flag and Composite Control Register BDMA OVERLAY BITS (SEE TABLE 12) SYSTEM CONTROL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 R ESERVED SET T O 0 1 0 RESERVED,ALW AYS SET TO 0 SPO RT0 ENABL E 0 = DISABL E 1 = ENABL E SPORT 1 ENABLE 0 = DISABLE 1 = ENABLE Figure 11. BDMA Control Register DM(0x3F FF) PW AIT PRO GRAM MEMOR Y W AIT ST ATES DISABLE BMS 0 = ENABL E BMS 1 = DISAB LE BMS BTYPE BDIR 0 = LOAD FROM BM 1 = STORE TO BM BCR 0 = RUN DURING BDMA 1 = HALT DURING BDMA The BDMA circuit supports four different data formats that are selected by the BTYPE register field. The appropriate number of 8-bit accesses are done from the byte memory space to build the word size selected. Table 7 shows the data formats supported by the BDMA circuit. Table 7. Data Formats SPO RT1 C ONF IGURE 0 = FI, FO , IRQ0, IRQ1, SCLK 1 = SPORT1 BTYPE 00 01 10 11 N OTE: RESERVED BITS ARE SHO WN O N A GRAY FIELD . THESE B ITS SHOUL D ALW AYS BE WR ITTEN W ITH Z EROS. Figure 10. System Control Register Byte Memory Select The ADSP-218xL's BMS disable feature combined with the CMS pin allows use of multiple memories in the byte memory space. For example, an EPROM could be attached to the BMS select, and a flash memory could be connected to CMS. Because at reset BMS is enabled, the EPROM would be used for booting. After booting, software could disable BMS and set the CMS signal to respond to BMS, enabling the flash memory. Byte Memory The byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. Byte memory is accessed using the BDMA feature. The byte memory space consists of 256 pages, each of which is 16K 8 bits. The byte memory space on the ADSP-218xL series supports read and write operations as well as four different data formats. The byte memory uses data bits 15-8 for data. The byte memory uses data bits 23-16 and address bits 13-0 to create a 22-bit address. This allows up to a 4 megabit 8 (32 megabit) ROM or RAM to be used without glue logic. All byte memory accesses are timed by the BMWAIT register. Rev. C | Internal Memory Space Program memory Data memory Data memory Data memory Word Size 24 16 8 8 Alignment Full word Full word MSBs LSBs Unused bits in the 8-bit data memory formats are filled with 0s. The BIAD register field is used to specify the starting address for the on-chip memory involved with the transfer. The 14-bit BEAD register specifies the starting address for the external byte memory space. The 8-bit BMPAGE register specifies the starting page for the external byte memory space. The BDIR register field selects the direction of the transfer. Finally, the 14-bit BWCOUNT register specifies the number of DSP words to transfer and initiates the BDMA circuit transfers. BDMA accesses can cross page boundaries during sequential addressing. A BDMA interrupt is generated on the completion of the number of transfers specified by the BWCOUNT register. The BWCOUNT register is updated after each transfer so it can be used to check the status of the transfers. When it reaches zero, the transfers have finished and a BDMA interrupt is generated. The BMPAGE and BEAD registers must not be accessed by the DSP during BDMA operations. The source or destination of a BDMA transfer is always on-chip program or data memory. When the BWCOUNT register is written with a nonzero value the BDMA circuit starts executing byte memory accesses with wait states set by BMWAIT. These accesses continue until the count reaches zero. When enough accesses have occurred to Page 11 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L create a destination word, it is transferred to or from on-chip memory. The transfer takes one DSP cycle. DSP accesses to external memory have priority over BDMA byte memory accesses. The BDMA Context Reset bit (BCR) controls whether the processor is held off while the BDMA accesses are occurring. Setting the BCR bit to 0 allows the processor to continue operations. Setting the BCR bit to 1 causes the processor to stop execution while the BDMA accesses are occurring, to clear the context of the processor, and start execution at address 0 when the BDMA accesses have completed. The BDMA overlay bits specify the OVLAY memory blocks to be accessed for internal memory. Set these bits as indicated in Figure 11. Note: BDMA cannot access external overlay memory regions 1 and 2. The BMWAIT field, which has 3 bits on ADSP-218xL series members, allows selection of up to 7 wait states for BDMA transfers. Internal Memory DMA Port (IDMA Port; Host Memory Mode) The IDMA Port provides an efficient means of communication between a host system and ADSP-218xL series members. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot, however, be used to write to the DSP's memory-mapped control registers. A typical IDMA transfer process is shown as follows: 1. Host starts IDMA transfer. 2. Host checks IACK control line to see if the DSP is busy. 3. Host uses IS and IAL control lines to latch either the DMA starting address (IDMAA) or the PM/DM OVLAY selection into the DSP's IDMA control registers. If Bit 15 = 1, the values of Bits 7-0 represent the IDMA overlay; Bits 14-8 must be set to 0. If Bit 15 = 0, the value of Bits 13-0 represent the starting address of internal memory to be accessed and Bit 14 reflects PM or DM for access. Set IDDMOVLAY and IDPMOVLAY bits in the IDMA overlay register as indicted in Table 8. 4. Host uses IS and IRD (or IWR) to read (or write) DSP internal memory (PM or DM). 5. Host checks IACK line to see if the DSP has completed the previous IDMA operation. 6. Host ends IDMA transfer. Table 8. IDMA/BDMA Overlay Bits Processor ADSP-2184L ADSP-2185L ADSP-2186L ADSP-2187L IDMA/BDMA PMOVLAY 0 0 0 0, 4, 5 IDMA/BDMA DMOVLAY 0 0 0 0, 4, 5 The IDMA port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. The IDMA port is completely asynchronous and can be written while the ADSP-218xL is operating at full speed. The DSP memory address is latched and then automatically incremented after each IDMA transaction. An external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. This increases throughput as the address does not have to be sent for each memory access. IDMA port access occurs in two phases. The first is the IDMA Address Latch cycle. When the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. The address specifies an on-chip memory location, the destination type specifies whether it is a DM or PM access. The falling edge of the IDMA address latch signal (IAL) or the missing edge of the IDMA select signal (IS) latches this value into the IDMAA register. Once the address is stored, data can be read from, or written to, the ADSP-218xL's on-chip memory. Asserting the select line (IS) and the appropriate read or write line (IRD and IWR respectively) signals the ADSP-218xL that a particular transaction is required. In either case, there is a one-processor-cycle delay for synchronization. The memory access consumes one additional processor cycle. Once an access has occurred, the latched address is automatically incremented, and another access can occur. Through the IDMAA register, the DSP can also specify the starting address and data format for DMA operation. Asserting the IDMA port select (IS) and address latch enable (IAL) directs the ADSP-218xL to write the address onto the IAD14-0 bus into the IDMA Control Register (Figure 12). If Bit 15 is set to 0, IDMA latches the address. If Bit 15 is set to 1, IDMA latches into the OVLAY register. This register, also shown in Figure 12, is memory-mapped at address DM (0x3FE0). Note that the latched address (IDMAA) cannot be read back by the host. The IDMA Overlay register applies to The ADSP-2187L processor only. When Bit 14 in 0x3FE7 is set to zero, short reads use the timing shown in Figure 26 on Page 34. When Bit 14 in 0x3FE7 is set to 1, timing in Figure 27 on Page 35 applies for short reads in Short Read Only Mode. Set IDDMOVLAY and IDPMOVLAY bits in the IDMA overlay register as indicated in Table 8. Refer to the ADSP-218x DSP Hardware Reference for additional details. Rev. C | Page 12 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Note: In Full Memory Mode, all locations of 4M-byte memory space are directly addressable. In Host Memory Mode, only address pin A0 is available, requiring additional external logic to provide address information for the byte. ID M A O VE R LA Y 15 14 13 12 11 10 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 R E SE R V ED S E T TO 0 ID D M OV LA Y R E SE R V ED S E T TO 0 SH O R T R E A D ON LY 0 = D IS A B LE 1 = E N A B LE D M (0x3FE 7) ID P M OV LA Y can load as much on-chip memory as desired. Program execution is held off until the host writes to on-chip program memory location 0. BUS REQUEST AND BUS GRANT ADSP-218xL series members can relinquish control of the data and address buses to an external device. When the external device requires access to memory, it asserts the Bus Request (BR) signal. If the ADSP-218xL is not performing an external memory access, it responds to the active BR input in the following processor cycle by: * Three-stating the data and address buses and the PMS, DMS, BMS, CMS, IOMS, RD, WR output drivers, ID M A C O N T R O L (U = U N D E FIN ED A T R ES E T) 15 14 13 12 11 10 0 U U U U U 9 8 7 6 5 4 3 2 1 0 U U U U U U U U U U * Asserting the bus grant (BG) signal, and D M (0x3FE 0) ID MA A A D D R ES S If Go Mode is enabled, the ADSP-218xL will not halt program execution until it encounters an instruction that requires an external memory access. ID M A D D ES TIN A T ION M EM O R Y TY PE R E SE R V ED S E T TO 0 0 = PM 1 = DM N O TE: R ES E R V ED B ITS A R E S H OW N ON A G R A Y F IE LD . T H ES E B ITS S H O U LD A L W A Y S B E W R ITTE N W ITH ZE R OS . Figure 12. IDMA OVLAY/Control Registers Bootstrap Loading (Booting) ADSP-218xL series members have two mechanisms to allow automatic loading of the internal program memory after reset. The method for booting is controlled by the Mode A, Mode B, and Mode C configuration bits. When the mode pins specify BDMA booting, the ADSP-218xL initiates a BDMA boot sequence when reset is released. The BDMA interface is set up during reset to the following defaults when BDMA booting is specified: the BDIR, BMPAGE, BIAD, and BEAD registers are set to 0, the BTYPE register is set to 0 to specify program memory 24-bit words, and the BWCOUNT register is set to 32. This causes 32 words of onchip program memory to be loaded from byte memory. These 32 words are used to set up the BDMA to load in the remaining program code. The BCR bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into on-chip program memory. Execution then begins at address 0. The ADSP-2100 Family development software (Revision 5.02 and later) fully supports the BDMA booting feature and can generate byte memory space-compatible boot code. The IDLE instruction can also be used to allow the processor to hold off execution while booting continues through the BDMA interface. For BDMA accesses while in Host Mode, the addresses to boot memory must be constructed externally to the ADSP-218xL. The only memory address bit provided by the processor is A0. IDMA Port Booting ADSP-218xL series members can also boot programs through its internal DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the ADSP-218xL boots from the IDMA port. IDMA feature Rev. C | * Halting program execution. If an ADSP-218xL series member is performing an external memory access when the external device asserts the BR signal, it will not three-state the memory interfaces nor assert the BG signal until the processor cycle after the access completes. The instruction does not need to be completed when the bus is granted. If a single instruction requires two external memory accesses, the bus will be granted between the two accesses. When the BR signal is released, the processor releases the BG signal, re-enables the output drivers, and continues program execution from the point at which it stopped. The bus request feature operates at all times, including when the processor is booting and when RESET is active. The BGH pin is asserted when an ADSP-218xL series member requires the external bus for a memory or BDMA access, but is stopped. The other device can release the bus by deasserting bus request. Once the bus is released, the ADSP-218xL deasserts BG and BGH and executes the external memory access. FLAG I/O PINS ADSP-218xL series members have eight general-purpose programmable input/output flag pins. They are controlled by two memory-mapped registers. The PFTYPE register determines the direction, 1 = output and 0 = input. The PFDATA register is used to read and write the values on the pins. Data being read from a pin configured as an input is synchronized to the ADSP-218xL's clock. Bits that are programmed as outputs will read the value being output. The PF pins default to input during reset. In addition to the programmable flags, ADSP-218xL series members have five fixed-mode flags, FI, FO, FL0, FL1, and FL2. FL0 to FL2 are dedicated output flags. FI and FO are available as an alternate configuration of SPORT1. Note: Pins PF0, PF1, PF2, and PF3 are also used for device configuration during reset. Page 13 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L INSTRUCTION SET DESCRIPTION * Fill and dump memory The ADSP-218xL series assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of the processor's unique architecture, offers the following benefits: * Source level debugging * The algebraic syntax eliminates the need to remember cryptic assembler mnemonics. For example, a typical arithmetic add instruction, such as AR = AX0 + AY0, resembles a simple equation. * Every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle. * The syntax is a superset ADSP-2100 Family assembly language and is completely source and object code compatible with other family members. Programs may need to be relocated to utilize on-chip memory and conform to the ADSP-218xL's interrupt vector and reset vector map. * Sixteen condition codes are available. For conditional jump, call, return, or arithmetic instructions, the condition can be checked and the operation executed in the same instruction cycle. The VisualDSP++ IDE lets programmers define and manage DSP software development. The dialog boxes and property pages let programmers configure and manage all of the ADSP-218xL development tools, including the syntax highlighting in the VisualDSP++ editor. This capability controls how the development tools process inputs and generate outputs. The ADSP-2189M EZ-KIT Lite(R) provides developers with a cost-effective method for initial evaluation of the powerful ADSP-218xL DSP family architecture. The ADSP-2189M EZ-KIT Lite includes a standalone ADSP-2189M DSP board supported by an evaluation suite of VisualDSP++. With this EZ-KIT Lite, users can learn about DSP hardware and software development and evaluate potential applications of the ADSP-218xL series. The ADSP-2189M EZ-KIT Lite provides an evaluation suite of the VisualDSP++ development environment with the C compiler, assembler, and linker. The size of the DSP executable that can be built using the EZ-KIT Lite tools is limited to 8K words. The EZ-KIT Lite includes the following features: * 75 MHz ADSP-2189M * Multifunction instructions allow parallel execution of an arithmetic instruction, with up to two fetches or one write to processor memory space, during a single instruction cycle. * Full 16-Bit Stereo Audio I/O with AD73322 Codec * RS-232 Interface * EZ-ICE(R) Connector for Emulator Control DEVELOPMENT SYSTEM * DSP Demonstration Programs Analog Devices' wide range of software and hardware development tools supports the ADSP-218xL series. The DSP tools include an integrated development environment, an evaluation kit, and a serial port emulator. VisualDSP++(R) is an integrated development environment, allowing for fast and easy development, debugging, and deployment. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy-to-use assembler that is based on an algebraic syntax; an archiver (librarian/library builder); a linker; a PROM-splitter utility; a cycle-accurate, instruction-level simulator; a C compiler; and a C run-time library that includes DSP and mathematical functions. Debugging both C and assembly programs with the VisualDSP++ debugger, programmers can: * Evaluation Suite of VisualDSP++ The ADSP-218x EZ-ICE Emulator provides an easier and more cost-effective method for engineers to develop and optimize DSP systems, shortening product development cycles for faster time-to-market. ADSP-218xL series members integrate on-chip emulation support with a 14-pin ICE-PortTM interface. This interface provides a simpler target board connection that requires fewer mechanical clearance considerations than other ADSP-2100 Family EZ-ICEs. ADSP-218xL series members need not be removed from the target system when using the EZ-ICE, nor are any adapters needed. Due to the small footprint of the EZ-ICE connector, emulation can be supported in final board designs.The EZ-ICE performs a full range of functions, including: * In-target operation * View mixed C and assembly code (interleaved source and object information) * Up to 20 breakpoints * Single-step or full-speed operation * Insert break points * Registers and memory values can be examined and altered * Set conditional breakpoints on registers, memory, and stacks * PC upload and download functions * Instruction-level emulation of program booting and execution * Trace instruction execution VisualDSP++ is a registered trademark of Analog Devices, Inc. Rev. C | Page 14 of 48 | EZ-KIT Lite is a registered trademark of Analog Devices, Inc. EZ-ICE is a registered trademark of Analog Devices, Inc. January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L * Complete assembly and disassembly of instructions The EZ-ICE connects to the target system via a ribbon cable and a 14-pin female plug. The female plug is plugged onto the 14pin connector (a pin strip header) on the target board. * C source-level debugging Designing an EZ-ICE-Compatible System Target Board Connector for EZ-ICE Probe ADSP-218xL series members have on-chip emulation support and an ICE-Port, a special set of pins that interface to the EZ-ICE. These features allow in-circuit emulation without replacing the target system processor by using only a 14-pin connection from the target system to the EZ-ICE. Target systems must have a 14-pin connector to accept the EZ-ICE's incircuit probe, a 14-pin plug. The EZ-ICE connector (a standard pin strip header) is shown in Figure 14. This connector must be added to the target board design to use the EZ-ICE. Be sure to allow enough room in the system to fit the EZ-ICE probe onto the 14-pin connector. One method of ensuring that the values located on the mode pins are those desired is to construct a circuit like the one shown in Figure 13. This circuit forces the value located on the Mode A pin to logic high, regardless of whether it is latched via the RESET or ERESET pin. ERESET RESET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 BG GND Issuing the chip reset command during emulation causes the DSP to perform a full chip reset, including a reset of its memory mode. Therefore, it is vital that the mode pins are set correctly PRIOR to issuing a chip reset command from the emulator user interface. If a passive method of maintaining mode information is being used (as discussed in Setting Memory Mode on Page 4), it does not matter that the mode information is latched by an emulator reset. However, if the RESET pin is being used as a method of setting the value of the mode pins, the effects of an emulator reset must be taken into consideration. EBG BR EBR KEY (NO PIN) EINT ELIN ELOUT ECLK EMS EE RESET ERESET TOP VIEW Figure 14. Target Board Connector for EZ-ICE The 14-pin, 2-row pin strip header is keyed at the Pin 7 location--Pin 7 must be removed from the header. The pins must be 0.025 inch square and at least 0.20 inch in length. Pin spacing should be 0.10.1 inch. The pin strip header must have at least 0.15 inch clearance on all sides to accept the EZ-ICE probe plug. Pin strip headers are available from vendors such as 3M, McKenzie, and Samtec. ADSP-218xL 1k Target Memory Interface MODE A/PF0 For the target system to be compatible with the EZ-ICE emulator, it must comply with the following memory interface guidelines: PROGRAMMABLE I/O Figure 13. Mode A Pin/EZ-ICE Circuit The ICE-Port interface consists of the following ADSP-218xL pins: EBR, EINT, EE, EBG, ECLK, ERESET, ELIN, EMS, and ELOUT. These ADSP-218xL pins must be connected only to the EZ-ICE connector in the target system. These pins have no function except during emulation, and do not require pull-up or pulldown resistors. The traces for these signals between the ADSP-218xL and the connector must be kept as short as possible, no longer than 3 inches. The following pins are also used by the EZ-ICE: BR, BG, RESET, and GND. The EZ-ICE uses the EE (emulator enable) signal to take control of the ADSP-218xL in the target system. This causes the processor to use its ERESET, EBR, and EBG pins instead of the RESET, BR, and BG pins. The BG output is three-stated. These signals do not need to be jumper-isolated in the system. Rev. C | Design the Program Memory (PM), Data Memory (DM), Byte Memory (BM), I/O Memory (IOM), and Composite Memory (CM) external interfaces to comply with worst-case device timing requirements and switching characteristics as specified in this data sheet. The performance of the EZ-ICE may approach published worst-case specification for some memory access timing requirements and switching characteristics. Note: If the target does not meet the worst-case chip specification for memory access parameters, the circuitry may not be able to be emulated at the desired CLKIN frequency. Depending on the severity of the specification violation, the system may be difficult to manufacture, as DSP components statistically vary in switching characteristic and timing requirements, within published limits. Restriction: All memory strobe signals on the ADSP-218xL (RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in the target system must have 10 k pull-up resistors connected when the EZ-ICE is being used. The pull-up resistors are necessary Page 15 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L because there are no internal pull-ups to guarantee their state during prolonged three-state conditions resulting from typical EZ-ICE debugging sessions. These resistors may be removed when the EZ-ICE is not being used. Target System Interface Signals When the EZ-ICE board is installed, the performance on some system signals changes. Design the system to be compatible with the following system interface signal changes introduced by the EZ-ICE board: * EZ-ICE emulation introduces an 8 ns propagation delay between the target circuitry and the DSP on the RESET signal. * EZ-ICE emulation introduces an 8 ns propagation delay between the target circuitry and the DSP on the BR signal. * EZ-ICE emulation ignores RESET and BR, when single-stepping. * EZ-ICE emulation ignores RESET and BR when in Emulator Space (DSP halted). * EZ-ICE emulation ignores the state of target BR in certain modes. As a result, the target system may take control of the DSP's external memory bus only if bus grant (BG) is asserted by the EZ-ICE board's DSP. ADDITIONAL INFORMATION This data sheet provides a general overview of ADSP-218xL series functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-218x DSP Hardware Reference and the ADSP-218x DSP Instruction Set Reference. Rev. C | Page 16 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L PIN DESCRIPTIONS ADSP-218xL series members are available in a 100-lead LQFP package and a 144-ball BGA package. In order to maintain maximum functionality and reduce package size and pin count, some serial port, programmable flag, interrupt and external bus pins have dual, multiplexed functionality. The external bus pins are configured during RESET only, while serial port pins are software configurable during program execution. Flag and interrupt functionality is retained concurrently on multiplexed pins. In cases where pin functionality is reconfigurable, the default state is shown in plain text in Table 9, while alternate functionality is shown in italics. Table 9. Common-Mode Pins Pin Name RESET BR BG BGH DMS PMS IOMS BMS CMS RD WR IRQ2/ PF7 IRQL1/ PF6 IRQL0/ PF5 IRQE/ PF4 Mode D2/ PF3 Mode C/ PF2 Mode B/ PF1 Mode A/ PF0 CLKIN XTAL CLKOUT SPORT0 SPORT1/ IRQ1-0, FI, FO PWD PWDACK FL0, FL1, FL2 VDDINT VDDEXT GND No. of Pins 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 I/O I I O O O O O O O O O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I O O I/O I/O 1 1 3 2 4 10 I O O I I I 1 1 1 1 1 1 1 Function Processor Reset Input Bus Request Input Bus Grant Output Bus Grant Hung Output Data Memory Select Output Program Memory Select Output Memory Select Output Byte Memory Select Output Combined Memory Select Output Memory Read Enable Output Memory Write Enable Output Edge- or Level-Sensitive Interrupt Request1 Programmable I/O Pin Level-Sensitive Interrupt Requests1 Programmable I/O Pin Level-Sensitive Interrupt Requests1 Programmable I/O Pin Edge-Sensitive Interrupt Requests1 Programmable I/O Pin Mode Select Input--Checked Only During RESET Programmable I/O Pin During Normal Operation Mode Select Input--Checked Only During RESET Programmable I/O Pin During Normal Operation Mode Select Input--Checked Only During RESET Programmable I/O Pin During Normal Operation Mode Select Input--Checked Only During RESET Programmable I/O Pin During Normal Operation Clock Input Quartz Crystal Output Processor Clock Output Serial Port I/O Pins Serial Port I/O Pins Edge- or Level-Sensitive Interrupts, FI, FO3 Power-Down Control Input Power-Down Acknowledge Control Output Output Flags Internal VDD (1.8 V) Power (LQFP) External VDD (1.8 V, 2.5 V, or 3.3 V) Power (LQFP) Ground (LQFP) Rev. C | Page 17 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Table 9. Common-Mode Pins (Continued) Pin Name VDDINT VDDEXT GND EZ-Port No. of Pins 4 7 20 9 I/O I I I I/O Function Internal VDD (3.3 V) Power (BGA) External VDD (3.3 V) Power (BGA) Ground (BGA) For Emulation Use 1 Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices or set as a programmable flag. 2 This mode applies to the ADSP-2187L only. 3 SPORT configuration determined by the DSP System Control Register. Software configurable. MEMORY INTERFACE PINS ADSP-218xL series members can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities. The operating mode is determined by the state of the Mode C pin during RESET and cannot be changed while the processor is running. Table 10 and Table 11 list the active signals at specific pins of the DSP during either of the two operating modes (Full Memory or Host). A signal in one table shares a pin with a signal from the other table, with the active signal determined by the mode that is set. For the shared pins and their alternate signals (e.g., A4/IAD3), refer to the package pinouts in Table 29 on Page 44 and Table 30 on Page 45. Table 10. Full Memory Mode Pins (Mode C = 0) Pin Name A13-0 D23-0 No. of Pins 14 24 I/O O I/O Function Address Output Pins for Program, Data, Byte, and I/O Spaces Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also used as Byte Memory Addresses.) Table 11. Host Mode Pins (Mode C = 1) Pin Name IAD15-0 A0 D23-8 IWR IRD IAL IS IACK 1 2 No. of Pins 16 1 16 1 1 1 1 1 I/O I/O O I/O I I I I O Function IDMA Port Address/Data Bus Address Pin for External I/O, Program, Data, or Byte Access1 Data I/O Pins for Program, Data, Byte, and I/O Spaces IDMA Write Enable IDMA Read Enable IDMA Address Latch Pin IDMA Select IDMA Port Acknowledge Configurable in Mode D2; Open Drain In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals. Mode D function available on ADSP-2187L only. Rev. C | Page 18 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L TERMINATING UNUSED PINS Table 12 shows the recommendations for terminating unused pins. Table 12. Unused Pin Terminations I/O 3-State (Z)2 O O O (Z) I/O (Z) O (Z) I/O (Z) I/O (Z) I I/O (Z) I I/O (Z) I I/O (Z) I I/O (Z) Reset State O O High-Z High-Z High-Z High-Z High-Z I High-Z I High-Z I High-Z I High-Z I/O (Z) I/O (Z) O (Z) O (Z) O (Z) O (Z) O (Z) O (Z) O (Z) I O (Z) O I/O (Z) High-Z High-Z O O O O O O O I O O I IRQL1/PF6 I/O (Z) I IRQL0/PF5 I/O (Z) I IRQE/PF4 I/O (Z) I PWD SCLK0 RFS0 DR0 TFS0 DT0 I I/O I/O I I/O O I I I I I O Pin Name1 XTAL CLKOUT A13-1 or IAD12-0 A0 D23-8 D7 or IWR D6 or IRD D5 or IAL D4 or IS D3 or IACK D2-0 or IAD15-13 PMS DMS BMS IOMS CMS RD WR BR BG BGH IRQ2/PF7 Rev. C | High-Z3 Caused By BR, EBR IS BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR IS BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR EE Page 19 of 48 | Unused Configuration Float Float4 Float Float Float Float Float High (Inactive) Float High (Inactive) Float Low (Inactive) Float High (Inactive) Float Float Float Float Float Float Float Float Float Float Float High (Inactive) Float Float Input = High (Inactive) or Program as Output, Set to 1, Let Float5 Input = High (Inactive) or Program as Output, Set to 1, Let Float5 Input = High (Inactive) or Program as Output, Set to 1, Let Float5 Input = High (Inactive) or Program as Output, Set to 1, Let Float5 High Input = High or Low, Output = Float High or Low High or Low High or Low Float January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Table 12. Unused Pin Terminations (Continued) Pin Name1 SCLK1 RFS1/IRQ0 DR1/FI TFS1/IRQ1 DT1/FO EE EBR EBG ERESET EMS EINT ECLK ELIN ELOUT I/O 3-State (Z)2 I/O I/O I I/O O I I O I O I I I O Reset State I I I I O I I O I O I I I O High-Z3 Caused By Unused Configuration Input = High or Low, Output = Float High or Low High or Low High or Low Float Float Float Float Float Float Float Float Float Float 1 CLKIN, RESET, and PF3-0/Mode D-A are not included in this table because these pins must be used. All bidirectional pins have three-stated outputs. When the pin is configured as an output, the output is High-Z (high impedance) when inactive. 3 High-Z = high impedance. 4 If the CLKOUT pin is not used, turn it OFF, using CLKODIS in SPORT0 autobuffer control register. 5 If the Interrupt/Programmable Flag pins are not used, there are two options: Option 1: When these pins are configured as INPUTS at reset and function as interrupts and input flag pins, pull the pins High (inactive). Option 2: Program the unused pins as OUTPUTS, set them to 1 prior to enabling interrupts, and let pins float. 2 Rev. C | Page 20 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L SPECIFICATIONS OPERATING CONDITIONS Parameter1 Min 3.0 0 VDD TAMB 1 K Grade (Commercial) Max 3.6 +70 Min 3.0 -40 B Grade (Industrial) Max 3.6 +85 Unit V C Specifications subject to change without notice. ELECTRICAL CHARACTERISTICS K and B Grades Parameter1 VIH Description Hi-Level Input Voltage2, 3 VIL VOH Lo-Level Input Voltage2, 3 Hi-Level Output Voltage2, 4, 5 VOL IIH IIL IOZH IOZL CI CO Lo-Level Output Voltage2, 4, 5 Hi-Level Input Current3 Lo-Level Input Current3 Three-State Leakage Current7 Three-State Leakage Current7 Input Pin Capacitance3, 6 Output Pin Capacitance6, 7, 9 Test Conditions @ VDD = Max @ VDD = Max @ VDD = Min @ VDD = Min, IOH = -0.5 mA @ VDD = Min, IOH = -100 A6 @ VDD = Min, IOL = 2.0 mA @ VDD = Max, VIN = VDD Max @ VDD = Max, VIN = 0 V @ VDD = Max, VIN = VDD Max8 @ VDD = Max, VIN = 0 V8 @ VIN = 3.5 V, fIN = 1.0 MHz, TAMB = 25C @ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25C 1 Min 2.0 2.2 Typ 0.8 1.35 VDD - 0.3 Specifications subject to change without notice. Bidirectional pins: D23-0, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A13-1, PF7-0. 3 Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD. 4 Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-FL0, BGH. 5 Although specified for TTL outputs, all ADSP-218xL outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads. 6 Guaranteed but not tested. 7 Three-statable pins: A13-A1, D23-D0, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF7-PF0. 8 0 V on BR. 9 Output pin capacitance is the capacitive load for any three-stated output pin. 2 Rev. C | Page 21 of 48 | January 2008 Max 0.4 10 10 10 10 8 8 Unit V V V V V V A A A A pF pF ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L ABSOLUTE MAXIMUM RATINGS ESD SENSITIVITY Stresses greater than those listed below may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameter Supply Voltage (VDD) Input Voltage1 Output Voltage Swing2 Operating Temperature Range Storage Temperature Range Rating -0.3 V to +4.6 V -0.5 V to VDD + 0.5 V -0.5 V to VDD +0.5 V -40C to +85C -65C to +150C Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. TIMING SPECIFICATIONS General Notes 1 Applies to bidirectional pins (D23-0, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A13-1, PF7-0) and input only pins (CLKIN, RESET, BR, DR0, DR1, PWD). 2 Applies to output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH). PACKAGE INFORMATION The information presented in Figure 15 provides details about the package branding for the ADSP-218xL processors. For a complete listing of product availability, see Ordering Guide on Page 47. a ADSP-218xL tppZ-cc Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, parameters cannot be added up meaningfully to derive longer times. Timing Notes Switching characteristics specify how the processor changes its signals. Designers have no control over this timing--circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics tell what the processor will do in a given circumstance. Switching characteristics can also be used to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices. vvvvvv.x n.n yyww country_of_origin Figure 15. Typical Package Brand Frequency Dependency For Timing Specifications Table 13. Package Brand Information Brand Key t pp Z cc vvvvvv.x n.n yyww ESD (electrostatic discharge) sensitive device. Field Description Temperature Range Package Type RoHs Compliant Option (optional) See Ordering Guide Assembly Lot Code Silicon Revision Date Code Rev. C | tCK is defined as 0.5 tCKI. The ADSP-218xL uses an input clock with a frequency equal to half the instruction rate. For example, a 26 MHz input clock (which is equivalent to 38 ns) yields a 19 ns processor cycle (equivalent to 52 MHz). tCK values within the range of 0.5 tCKI period should be substituted for all relevant timing parameters to obtain the specification value. Example: tCKH = 0.5 tCK - 7 ns = 0.5 (19) - 7 ns = 2.5 ns Page 22 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Clock Signals and Reset Table 14. Clock Signals and Reset Parameter Timing Requirements: tCKI CLKIN Period tCKIL CLKIN Width Low tCKIH CLKIN Width High Switching Characteristics: tCKL CLKOUT Width Low CLKOUT Width High tCKH tCKOH CLKIN High to CLKOUT High Control Signals Timing Requirements: tRSP RESET Width Low1 tMS Mode Setup Before RESET High tMH Mode Hold After RESET High 1 ADSP-2184L, ADSP-2186L Min Max ADSP-2185L, ADSP-2187L Min Max Unit 50 20 20 38 15 15 ns ns ns 150 0.5tCK - 7 0.5tCK - 7 0 20 5tCK 2 5 0.5tCK - 7 0.5tCK - 7 0 5tCK 2 5 100 20 ns ns ns ns ns ns Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles, assuming stable CLKIN (not including crystal oscillator start-up time). tCKI tCKIH CLKIN tCKIL tCKOH tCKH CLKOUT tCKL MODE A D tMS tMH RESET tRSP Figure 16. Clock Signals and Reset Rev. C | Page 23 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Interrupts and Flags Table 15. Interrupts and Flags Parameter Timing Requirements: IRQx, FI, or PFx Setup Before CLKOUT Low1, 2, 3, 4 tIFS tIFH IRQx, FI, or PFx Hold After CLKOUT High1, 2, 3, 4 Switching Characteristics: tFOH Flag Output Hold After CLKOUT Low5 tFOD Flag Output Delay From CLKOUT Low5 Min Max 0.25tCK + 15 0.25tCK ns ns 0.5tCK - 5 ns ns 0.5tCK + 4 1 Unit If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the following cycle. (Refer to "Interrupt Controller Operation" in the Program Control chapter of the ADSP-218x DSP Hardware Reference for further information on interrupt servicing.) 2 Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced. 3 IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE. 4 PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7. 5 Flag Outputs = PFx, FL0, FL1, FL2, FO. tFOD CLKOUT tFOH FLAG OUTPUTS tIFH IRQx FI PFx tIFS Figure 17. Interrupts and Flags Rev. C | Page 24 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Bus Request-Bus Grant Table 16. Bus Request--Bus Grant Parameter Timing Requirements: BR Hold After CLKOUT High1 tBH tBS BR Setup Before CLKOUT Low1 Switching Characteristics: tSD CLKOUT High to xMS, RD, WR Disable2 tSDB xMS, RD, WR Disable to BG Low tSE BG High to xMS, RD, WR Enable xMS, RD, WR Enable to CLKOUT High3 tSEC tSDBH xMS, RD, WR Disable to BGH Low4 tSEH BGH High to xMS, RD, WR Enable4 Min Max 0.25tCK + 2 0.25tCK + 17 ns ns 0.25tCK + 10 0 0 0.25tCK - 7 0 0 1 Unit ns ns ns ns ns ns BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User's Manual for BR/BG cycle relationships. xMS = PMS, DMS, CMS, IOMS, BMS. 3 For the ADSP-2187L, this specification is 0.25tCK - 4 ns min. 4 BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue. 2 tBH CLKOUT BR tBS CLKOUT PMS, DMS BMS, RD CMS, WR, IOMS tSD tSEC BG tSDB BGH tSE tSDBH tSEH Figure 18. Bus Request--Bus Grant Rev. C | Page 25 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Memory Read Table 17. Memory Read Parameter Timing Requirements: RD Low to Data Valid1 tRDD tAA A13-0, xMS to Data Valid2 tRDH Data Hold from RD High3 Switching Characteristics: tRP RD Pulse Width tCRD CLKOUT High to RD Low A13-0, xMS Setup Before RD Low tASR tRDA A13-0, xMS Hold After RD Deasserted tRWR RD High to RD or WR Low Min Unit 0.5tCK - 9 + w 0.75tCK - 12.5 + w ns ns ns 1 0.5tCK - 5 + w 0.25tCK - 5 0.25tCK - 6 0.25tCK - 3 0.5tCK - 5 w = wait states x tCK. xMS = PMS, DMS, CMS, IOMS, BMS. 3 For the ADSP-2187L, this specification is 0 ns min. 1 2 CLKOUT ADDRESS LINES1 DMS, PMS, BMS, IOMS, CMS tRDA RD tASR tRP tCRD tRWR DATA LINES2 tAA tRDD tRDH WR 1ADDRESS LINES FOR ACCESSES ARE: BDMA: A13-0 (14 LSBs), D23-16 (8 MSBs) I/O SPACE: A10-0 EXTERNAL PM AND DM: A13-0 2DATA LINES FOR ACCESSES ARE: BDMA: D15-8 I/O SPACE: D23-8 EXTERNAL DM: D23-8 EXTERNAL PM: D23-0 Figure 19. Memory Read Rev. C Max | Page 26 of 48 | January 2008 0.25tCK + 7 ns ns ns ns ns ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Memory Write Table 18. Memory Write Parameter Switching Characteristics: Data Setup Before WR High1 tDW tDH Data Hold After WR High tWP WR Pulse Width tWDE WR Low to Data Enabled tASW A13-0, xMS Setup Before WR Low2 tDDR Data Disable Before WR or RD Low CLKOUT High to WR Low tCWR tAW A13-0, xMS Setup Before WR Deasserted tWRA A13-0, xMS Hold After WR Deasserted tWWR WR High to RD or WR Low 1 2 Min Max 0.5tCK- 7 + w 0.25tCK - 2 0.5tCK - 5 + w 0 0.25tCK - 6 0.25tCK - 7 0.25tCK - 5 0.75tCK - 9 + w 0.25tCK - 3 0.5tCK - 5 w = wait states x tCK. xMS = PMS, DMS, CMS, IOMS, BMS. CLKOUT ADDRESS LINES1 DMS, PMS, BMS, CMS, IOMS tWRA WR tASW tWWR tWP tAW tDH tCWR DATA LINES2 tDW tWDE RD 1ADDRESS LINES FOR ACCESSES ARE: BDMA: A13-0 (14 LSBs), D23-16 (8 MSBs) I/O SPACE: A10-0 EXTERNAL PM AND DM: A13-0 2DATA LINES FOR ACCESSES ARE: BDMA: D15-8 I/O SPACE: D23-8 EXTERNAL DM: D23-8 EXTERNAL PM: D23-0 Figure 20. Memory Write Rev. C | Page 27 of 48 | January 2008 tDDR 0.25tCK + 7 Unit ns ns ns ns ns ns ns ns ns ns ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L Serial Ports Table 19. Serial Ports Parameter Timing Requirements: SCLK Period1 tSCK tSCS DR/TFS/RFS Setup Before SCLK Low tSCH DR/TFS/RFS Hold After SCLK Low2 tSCP SCLKIN Width3 Switching Characteristics: tCC CLKOUT High to SCLKOUT SCLK High to DT Enable tSCDE tSCDV SCLK High to DT Valid tRH TFS/RFSOUT Hold After SCLK High tRD TFS/RFSOUT Delay from SCLK High tSCDH DT Hold after SCLK High tTDE TFS (Alt) to DT Enable TFS (Alt) to DT Valid tTDV tSCDD SCLK High to DT Disable tRDV RFS (Multichannel, Frame Delay Zero) to DT Valid Min 50 4 8 20 0.25tCK 0 15 0 0 14 15 15 For the ADSP-2187L, this specification is 38 ns min. For the ADSP-2187L, this specification is 7 ns min. 3 For the ADSP-2185L, and the ADSP-2187L, this specification is 15 ns min. | Page 28 of 48 | 0.25tCK + 10 15 2 January 2008 Unit ns ns ns ns 0 1 Rev. C Max ns ns ns ns ns ns ns ns ns ns ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L CLKOUT t CC tCC tS C K SCLK tS CP t SC S DR TFSIN RFSIN tSC H tSC P tRD tR H RFSO UT TFSO UT tS C DD t SC D V tSC D H tS CD E DT tTD E t TD V TFSO UT A LTER N A TE FRA M E M OD E tR DV RFS OU T MU LTIC H A NN E L M ODE , FR A ME DE LA Y 0 ( MFD = 0 ) TFSIN tTD E tTD V ALTE R NA TE FR A ME MO DE tR DV RFSIN MU LTIC H A NN E L M ODE , FR A ME DE LA Y 0 ( MFD = 0 ) Figure 21. Serial Ports Rev. C | Page 29 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L IDMA Address Latch Table 20. IDMA Address Latch Parameter Timing Requirements: Duration of Address Latch1, 2 tIALP tIASU IAD15-0 Address Setup Before Address Latch End2 tIAH IAD15-0 Address Hold After Address Latch End2, 3 tIKA IACK Low Before Start of Address Latch2, 4 tIALS Start of Write or Read After Address Latch End2, 4 tIALD Address Latch Start After Address Latch End1, 2 Min 10 5 3 0 3 2 1 Start of Address Latch = IS Low and IAL High. End of Address Latch = IS High or IAL Low. 3 For the ADSP-2187L, this specification is 2 ns min. 4 Start of Write or Read = IS Low and IWR Low or IRD Low. 2 IACK tIKA tIALD IAL tIALP tIALP IS IAD15-0 tIASU tIASU tIAH IRD OR IWR Figure 22. IDMA Address Latch Rev. C | Page 30 of 48 | January 2008 tIAH tIALS Max Unit ns ns ns ns ns ns ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L IDMA Write, Short Write Cycle Table 21. IDMA Write, Short Write Cycle Parameter Timing Requirements: IACK Low Before Start of Write1 tIKW tIWP Duration of Write1, 2 tIDSU IAD15-0 Data Setup Before End of Write2, 3, 4 tIDH IAD15-0 Data Hold After End of Write2, 3, 4 Switching Characteristic: tIKHW Start of Write to IACK High5 Min 0 15 5 2 Start of Write = IS Low and IWR Low. End of Write = IS High or IWR High. 3 If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH. 4 If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH. 5 For the ADSP-2185L, and the ADSP-2187L, this specification is 4 ns min., and 15 ns max. 2 tIKW IACK tIKHW IS tIWP IWR tIDSU tIDH DATA Figure 23. IDMA Write, Short Write Cycle Rev. C | Page 31 of 48 | January 2008 Unit ns ns ns ns 17 1 IAD15-0 Max ns ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L IDMA Write, Long Write Cycle Table 22. IDMA Write, Long Write Cycle Parameter Timing Requirements: IACK Low Before Start of Write1 tIKW tIKSU IAD15-0 Data Setup Before End of Write2, 3, 4 tIKH IAD15-0 Data Hold After End of Write2, 3, 4 Switching Characteristics: tIKLW Start of Write to IACK Low4 tIKHW Start of Write to IACK High5 Min Max 0 0.5tCK + 10 2 ns ns ns 1.5tCK 17 1 Start of Write = IS Low and IWR Low. If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH. 3 If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH. 4 This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User's Manual. 5 For the ADSP-2185L, and the ADSP-2187L, this specification is 4 ns min., and 15 ns max. 2 tIK W IACK tIKH W tIK LW IS IWR tIKSU tIK H DATA IAD15-0 Figure 24. IDMA Write, Long Write Cycle Rev. C | Page 32 of 48 | January 2008 Unit ns ns ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L IDMA Read, Long Read Cycle Table 23. IDMA Read, Long Read Cycle Parameter Timing Requirements: IACK Low Before Start of Read1 tIKR tIRK End of Read After IACK Low2 Switching Characteristics: tIKHR IACK High After Start of Read1, 3 tIKDS IAD15-0 Data Setup Before IACK Low tIKDH IAD15 -0 Data Hold After End of Read2 IAD15-0 Data Disabled After End of Read2 tIKDD tIRDE IAD15-0 Previous Data Enabled After Start of Read tIRDV IAD15-0 Previous Data Valid After Start of Read4 tIRDH1 IAD15-0 Previous Data Hold After Start of Read (DM/PM1)5 tIRDH2 IAD15-0 Previous Data Hold After Start of Read (PM2)6 Min Max 0 2 ns ns 17 0.5tCK - 10 0 10 0 15 2tCK - 5 tCK - 5 1 Start of Read = IS Low and IRD Low. End of Read = IS High or IRD High. 3 For the ADSP-2185L, and the ADSP-2187L, this specification is 4 ns min., and 15 ns max. 4 For the ADSP-2187L, this specification is 10 ns max. 5 DM read or first half of PM read. 6 Second half of PM read. 2 IACK tIKHR tIKR IS tIRK IRD tIKDH tIKDS tIRDE PREVIOUS DATA IAD15-0 READ DATA tIRDV tIKDD tIRDH1 OR tIRDH2 Figure 25. IDMA Read, Long Read Cycle Rev. C | Page 33 of 48 | January 2008 Unit ns ns ns ns ns ns ns ns ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L IDMA Read, Short Read Cycle Table 24. IDMA Read, Short Read Cycle Parameter1, 2 Timing Requirements: IACK Low Before Start of Read3 tIKR tIRP1 Duration of Read (DM/PM1)4, 5 tIRP2 Duration of Read (PM2)6, 7 Switching Characteristics: tIKHR IACK High After Start of Read3 tIKDH IAD15-0 Data Hold After End of Read8 IAD15-0 Data Disabled After End of Read8 tIKDD tIRDE IAD15-0 Previous Data Enabled After Start of Read tIRDV IAD15-0 Previous Data Valid After Start of Read Min Max 0 15 15 ns ns ns 15 0 10 0 15 1 Unit ns ns ns ns ns Short Read Only must be disabled in the IDMA overlay memory mapped register. This mode is disabled by clearing (=0) Bit 14 of the IDMA overlay register, and is disabled by default upon reset. Consider using the Short Read Only mode, instead, because Short Read mode is not applicable at high clock frequencies. 3 Start of Read = IS Low and IRD Low. 4 DM Read or first half of PM Read. 5 For the ADSP-2186L, this specification also has a max value of 2tCK - 5. 6 Second half of PM Read. 7 For the ADSP-2186L, this specification also has a max value of tCK - 5 max. 8 End of Read = IS High or IRD High. 2 IACK tIKR tIKHR IS tIRPx IRD tIKDH tIRDE PREVIOUS DATA IAD15-0 tIRDV tIKDD Figure 26. IDMA Read, Short Read Cycle Rev. C | Page 34 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L IDMA Read, Short Read Cycle in Short Read Only Mode Table 25. IDMA Read, Short Read Cycle in Short Read Only Mode1 Parameter2 Timing Requirements: IACK Low Before Start of Read3 tIKR tIRP Duration of Read4 Switching Characteristics: tIKHR IACK High After Start of Read3 tIKDH IAD15-0 Previous Data Hold After End of Read4 tIKDD IAD15-0 Previous Data Disabled After End of Read4 IAD15-0 Previous Data Enabled After Start of Read tIRDE tIRDV IAD15-0 Previous Data Valid After Start of Read Min Max 0 10 ns ns 10 0 10 0 10 1 Unit ns ns ns ns ns Applies to the ADSP-2187L only. 2 Short Read Only is enabled by setting Bit 14 of the IDMA overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing to the register or by an external host writing to the register. Disabled by default. 3 Start of Read = IS Low and IRD Low. Previous data remains until end of read. 4 End of Read = IS High or IRD High. IA CK t IK R t IK H R IS tIR P IRD t IK D H t IR D E PR E V IO U S D A TA IA D 15-0 t IR D V tIK D D L EG EN D : IM PL IES TH A T IS A N D IR D C A N B E HE LD IN D E FIN ITE LY B Y H O S T Figure 27. IDMA Read, Short Read Cycle in Short Read Only Mode Rev. C | Page 35 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L POWER SUPPLY CURRENT Table 26. Power Supply Current1 Parameter ADSP-2184L IDD Supply Current (Idle)2 IDD Supply Current (Dynamic)3 ADSP-2185L IDD Supply Current (Idle)2 IDD Supply Current (Dynamic)3 ADSP-2186L IDD Supply Current (Idle)2 IDD Supply Current (Dynamic)3 ADSP-2187L IDD Supply Current (Idle)2 IDD Supply Current (Dynamic)3 Test Conditions Min @ VDD = 3.3 V4 @ VDD = 3.3, TAMB = 25C, tCK = 25 ns4 @ VDD = 3.3 V4 tCK = 19 ns tCK = 25 ns tCK = 30 ns @ VDD = 3.3 V, TAMB = 25C4 tCK = 19 ns tCK = 25 ns tCK = 30 ns @ VDD = 3.3 V4 @ VDD = 3.3 V, TAMB = 25C, tCK = 25 ns4 @ VDD = 3.3 V4 tCK = 19 ns tCK = 25 ns tCK = 30 ns @ VDD = 3.3 V, TAMB = 25C4 tCK = 19 ns tCK = 25 ns tCK = 30 ns 1 Typ Max Unit 8.6 42 mA mA 8.6 7.0 6.0 mA mA mA 49 38 31.5 mA mA mA 8.6 42 mA mA 10 8 7 mA mA mA 51 41 34 mA mA mA Specifications subject to change without notice. Idle refers to ADSP-218xL state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND. 3 IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2 and Type 6, and 20% are idle instructions. 4 VIN = 0 V and 3 V. 2 Rev. C | Page 36 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L POWER DISSIPATION Assumptions: * External data memory is accessed every cycle with 50% of the address pins switching. To determine total power dissipation in a specific application, the following equation should be applied for each output: C VDD2 f * External data memory writes occur every other cycle with 50% of the data pins switching. where: * Each address and data pin has a 10 pF total load at the pin. C is load capacitance. * Application operates at VDD = 3.3 V and tCK = 30 ns. f is the output switching frequency. Example: In an application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: Total Power Dissipation = PINT + (C VDD2 f) where: P INT is the internal power dissipation from Figure 28 through Figure 31 on Page 39. (C VDD2 f) is calculated for each output, as in the example in Table 27. Table 27. Example Power Dissipation Calculation1 Parameters Address, DMS Data Output, WR RD CLKOUT 1 No. of Pins 8 9 1 1 x C (pF) 10 10 10 10 x VDD2 (V) 3.32 3.32 3.32 3.32 Total power dissipation for this example is PINT + 50.7 mW. Rev. C | Page 37 of 48 | January 2008 x f (MHz) 33.3 16.67 16.67 33.3 PD (mW) 29.0 16.3 1.8 3.6 = 50.7 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L POWER, INTERNAL1, 2, 3 170 169mW V DDINT = 3.6V 150 140 1 26mW 130 139 mW V DDINT = 3.3V 120 110 10 2mW V DDIN T = 3.0V 11 3mW 100 90 19 7mW 210 POWER (P IN T) - mW POWER (P IN T) - mW 160 POWER, INTERNAL 1 , 2 , 3 230 190 VD D IN T = 3.6V 161m W 170 VD D INT = 3.3V 150 13 0mW 128m W 130 VD D INT = 3.0V 110 104m W 90 83mW 80 32 30 84m W 70 34 36 38 40 50 42 30 35 1/tCK - MHz 34 V DDINT = 3.6V 32 27mW 28 VDDINT = 3.3V 28mW 26 22mW V DDINT = 3.0V 22 20 22mW 17mW 18 3 5mW 30 28 32 34 36 38 40 28m W 24 VD D IN T = 3.3V 20m W 22 22m W 20 16 42 VD D INT = 3.6V 25m W 26 V DD IN T = 3. 0V 16m W 18 30 30 35 1/tCK - MHz 28mW VDD CORE = 1.9V VDD CORE = 1.8V 20 15 10mW 13mW IDLE(16) 12mW IDL E(128) 10 28mW 30 25 20mW 20 15 9mW 5 5 32 34 36 55 35 13mW 38 40 42 IDLE(16) 10m W IDLE(128) 10 30 50 40 POWER (PID LEn ) - mW POWER (PID LEn ) - mW 45 POWER, IDLE n MODES2 45 30 25 22mW 40 1/ tC K - MHz POWER, IDLE n MODES 2 35 55 32 35 mW POWER (PIDL E) - mW POWER (PIDL E) - mW 34 16 50 POWER, IDLE1 , 2 , 4 36 36 24 45 1/ tC K - MHz POWER, IDLE1, 2, 4 38 40 12mW 9mW 30 1/tCK - MHz 35 40 45 50 55 1/tC K - MHz NOTES VALID FOR ALLTEMPERATURE GRADES. 1. POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS. 2.TYPICAL POWER DISSIPATION AT 3.3V V DD AND 25C, EXCEPT WHERE SPECIFIED. 3. IDD MEASUREMENTTAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL MEMORY. 50% Of the INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS. 4. IDLE REFERSTO STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V DD OR GND. NOTES VALID FOR ALL TEMPERATURE G RADES. 1. POWER REFLECTS DE VICE O PERATING WI TH NO O UTPUT LOADS. 2. TYPICAL POWE R DISSI PATIO N AT 3. 3V V D D AND 25C, EX CEPT WHERE SPE CI FI ED. 3. IDD MEASUREMENT TAKEN WITH ALL INSTRUCTI ONS EXECUTING FROM INTERNAL MEMORY. 50% Of the INSTRUCTI ONS ARE MULTIFUNCTI ON (TY PES 1, 4, 5, 12, 13, 14), 30% ARE TYP E 2 AND TYPE 6, AND 20% ARE I DLE INSTRUCTIONS . 4. IDLE RE FERSTO STATE O F OPE RATI ON DURING EXECUTIO N OF IDLE I NSTRUCTION. DEASSERTE D PI NS ARE DRI VEN TO EITHER VD D OR G ND. Figure 28. Power vs. Frequency (ADSP-2184L) Rev. C Figure 29. Power vs. Frequency (ADSP-2185L) | Page 38 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L POWER, INTERNAL 1, 2, 3 170 210 169mW VDD INT = 3.6V 150 140 126mW 139 mW V DDINT = 3.3V 130 POWER (P IN T) - mW POWER (P IN T) - mW 160 120 110 10 2mW V DDINT = 3.0V 1 13mW 100 90 POWER, INTERNAL 1, 2, 3 230 170 VDDINT = 3.3V 150 130 110 70 50 30 VDDINT = 3.0V 13 2mW 112.2mW 32 34 36 38 40 42 87mW 35 30 40 POWER, IDLE1, 2, 4 38 45 50 55 1/ tCK - MHz 1/tCK - MHz POWER, IDLE1, 2, 4 36 V DDINT = 3.6V 34 36 35mW V DDINT = 3.6V 34 32 3 5mW 32 POWER (PIDL E) - mW POWER (P ID LE ) - mW 168.3mW 144 mW 90 83mW 80 2 7mW 28 VDDINT = 3.3V 28mW 26 24 22mW V DDINT = 3.0V 22 20 21 6mW V DDINT = 3.6V 190 22mW 19mW V DDINT = 3.3V 3 2mW VDDINT = 3.0V 30 28 25mW 26 23mW 30mW 24 22 21mW 20 18 18 16 16 30 32 34 36 38 40 42 30 35 POWER, IDLE n MODES 2 35 40 45 50 55 1/ tCK - MHz 1/tCK - MHz POWER, IDLE n MODES 2 45 28mW 40 25 22mW VDD CORE = 1.9V VDD CORE = 1.8V 20 13mW 15 10mW IDLE(16) 12mW IDLE(128) 10 POWER (PID LEn ) - mW POWER (PID LEn ) - mW 30 32mW 35 IDLE 30 25 23mW 20 15 13mW IDLE(128) 10 9mW 5 5 30 32 34 36 38 40 42 IDLE(16) 10mW 12mW 9mW 30 35 40 45 50 55 1/tCK - MHz 1/tCK - MHz NOTES VALID FOR ALL TEMPERATURE GRADES. 1. POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS. 2.TYPICAL POWER DISSIPATION AT 3.3V V DD AND 25C, EXCEPT WHERE SPECIFIED. 3. IDD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL MEMORY. 50% Of the INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS. 4. IDLE REFERSTO STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND. NOTES VALID FOR ALL TEMPERATURE GRADES. 1. POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS. 2.TYPICAL POWER DISSIPATION AT 3.3V VDD AND 25C, EXCEPT WHERE SPECIFIED. 3. IDD MEASUREMENT TAKEN WITH ALL INSTRUCT IONS EXECUTING FROM INTERNAL MEMORY. 50% Of the INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS. 4. IDLE REFERSTO STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V DD OR GND. Figure 30. Power vs. Frequency (ADSP-2186L) Rev. C | Figure 31. Power vs. Frequency (ADSP-2187L) Page 39 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L OUTPUT DRIVE CURRENTS Figure 32 through Figure 35 show typical I-V characteristics for the output drivers on the ADSP-218xL processors. The curves represent the current drive capability of the output drivers as a function of output voltage. 80 80 VDDEXT = 3.3V @ +25C VDDEXT = 3.3V @ +25C VDDEXT = 3.6V @ -40 C 60 VDDEXT = 3.6V @ -40 C 60 VOH SOURCE CURRENT - mA SOURCE CURRENT - mA VOH 40 20 VDDEXT = 3.0V @ +85C 0 VDDEXT = 3.0V @ +85C -20 VDDEXT = 3.3V @ +25C -40 40 20 VDDEXT = 3.0V @ +85C 0 VDDEXT = 3.0V @ +85C -20 VDDEXT = 3.3V @ +25C -40 VOL VOL -60 -60 VDDEXT = 3.6V @ -40C VDDEXT = 3.6V @ -40C -80 0 0.5 1.0 -80 1.5 2.0 2.5 3.0 3.5 0 0.5 1.5 1.0 2.0 2.5 3.5 Figure 34. Typical Output Driver Characteristics (ADSP-2186L) Figure 32. Typical Output Driver Characteristics (ADSP-2184L) 80 80 VDDEXT = 3.3V @ +25C VDDEXT = 3.3V @ +25C VDDEXT = 3.6V @ -40 C 60 VDDEXT = 3.6V @ -40 C 60 VOH VOH 40 SOURCE CURRENT - mA SOURCE CURRENT - mA 3.0 SOURCE VOLTAGE - V SOURCE VOLTAGE - V 20 VDDEXT = 3.0V @ +85C 0 VDDEXT = 3.0V @ +85C -20 VDDEXT = 3.3V @ +25C -40 40 20 VDDEXT = 3.0V @ +85C 0 VDDEXT = 3.0V @ +85C -20 VDDEXT = 3.3V @ +25C -40 VOL VOL -60 -60 VDDEXT = 3.6V @ -40C VDDEXT = 3.6V @ -40C -80 -80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 4.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 SOURCE VOLTAGE - V SOURCE VOLTAGE - V Figure 33. Typical Output Driver Characteristics (ADSP-2185L) Figure 35. Typical Output Driver Characteristics (ADSP-2187L) Rev. C | Page 40 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L POWER-DOWN CURRENT Figure 36 through Figure 39 show the typical power-down supply current. Note that these graphs reflect ADSP-218xL operation in lowest power mode. (See the "System Interface" chapter of the ADSP-218x DSP Hardware Reference for details). Current reflects device operating with no input loads. 10000 VDD = 3.6V 1000 VDD = 3.3V 100 10 CURRENT (LOG SCALE) - A CURRENT (LOG SCALE) - A 10000 VDD = 3.3V 100 10 0 0 0 25 55 TEMPERATURE - C 0 85 25 55 TEMPERATURE - C 85 Figure 38. Typical Power-Down Current (ADSP-2186L) Figure 36. Typical Power-Down Current (ADSP-2184L) 10000 1000 VDD = 3.6V VDD = 3.3V 100 10 CURRENT (LOG SCALE) - A 10000 CURRENT (LOG SCALE) - A VDD = 3.6V 1000 1000 VDD = 3.6V VDD = 3.3V VDD = 3.0V 100 10 0 0 0 25 55 TEMPERATURE - C 0 85 85 Figure 39. Typical Power-Down Current (ADSP-2187L) Figure 37. Typical Power-Down Current (ADSP-2185L) Rev. C | 25 55 TEMPERATURE - C Page 41 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L CAPACITIVE LOADING - ADSP-2184L, ADSP-2186L CAPACITIVE LOADING - ADSP-2185L, ADSP-2187L Figure 40 and Figure 41 show the capacitive loading characteristics of the ADSP-2184L and ADSP-2186L. Figure 42 and Figure 43 show the capacitive loading characteristics of the ADSP-2185L and ADSP-2187L. 18 25 T = 85C VDD = 3.0V T = 85C VDD = 3.0V 15 RISE TIME (0.4V-2.4V) - ns RISE TIME (0.4V-2.4V) - ns 20 15 10 5 12 9 6 0 0 0 40 80 120 160 180 200 0 50 100 CL - pF Figure 40. Typical Output Rise Time vs. Load Capacitance (at Maximum Ambient Operating Temperature) 250 12 VALID OUTPUT DELAY OR HOLD - ns 16 VALID OUTPUT DELAY OR HOLD - ns 200 Figure 42. Typical Output Rise Time vs. Load Capacitance (at Maximum Ambient Operating Temperature) 18 14 12 10 8 6 4 2 NOMINAL -2 -4 -6 150 CL - pF 0 50 100 150 200 250 10 8 6 4 2 NOMINAL -2 -4 -6 CL - pF Figure 41. Typical Output Valid Delay or Hold vs. Load Capacitance, CL (at Maximum Ambient Operating Temperature) Rev. C | Page 42 of 48 | 0 40 80 120 CL - pF 160 200 Figure 43. Typical Output Valid Delay or Hold vs. Load Capacitance, CL (at Maximum Ambient Operating Temperature) January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L TEST CONDITIONS REFERENCE SIGNAL Figure 44 shows voltage reference levels for all ac measurements (except output disable/enable). tMEASURED tENA tDIS VOH (MEASURED) INPUT OR OUTPUT 1.5V VOH (MEASURED) VOH (MEASURED) - 0.5V 2.0V VOL (MEASURED) + 0.5V 1.0V OUTPUT 1.5V VOL (MEASURED) Figure 44. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) OUTPUT STARTS DRIVING OUTPUT STOPS DRIVING HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V. Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The output disable time (tDIS) is the difference of tMEASURED and tDECAY, as shown in Figure 45. The time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 V from the measured output high or low voltage. Figure 45. Output Enable/Disable IOL TO OUTPUT PIN The decay time, tDECAY, is dependent on the capacitive load, CL, and the current load, iL, on the output pin. It can be approximated by the following equation: from which VOL (MEASURED) tDECAY 1.5V 50pF C L x 0.5V t DECAY = -----------------------iL IOH Figure 46. Equivalent Loading for AC Measurements (Including All Fixtures) t DIS = t MEASURED - t DECAY ENVIRONMENTAL CONDITIONS is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop driving. Table 28. Thermal Resistance Output Enable Time Output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. The output enable time (tENA) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in Figure 45. If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. Rev. C | Rating Description1 Thermal Resistance (Caseto-Ambient) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) 1 Page 43 of 48 | Symbol CA LQFP (C/W) 48 BGA (C/W) 63.3 JA 50 70.7 JC 2 7.4 Where the ambient temperature rating (TAMB) is: TAMB = TCASE - (PD x CA) TCASE = case temperature in C PD = power dissipation in W January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L LQFP PACKAGE PINOUT The LQFP package pinout is shown in Table 29. Pin names in bold text in the table replace the plain-text-named functions when Mode C equals 1. A plus sign (+) separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets are state bits latched from the value of the pin at the deassertion of RESET. The multiplexed pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode selectable by setting Bit 10 (SPORT1 configure) of the System Control Register. If Bit 10 = 1, these pins have serial port functionality. If Bit 10 = 0, these pins are the external interrupt and flag pins. This bit is set to 1 by default, upon reset. Table 29. LQFP Pin Assignments Lead No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 Lead Name A4/IAD3 A5/IAD4 GND A6/IAD5 A7/IAD6 A8/IAD7 A9/IAD8 A10/IAD9 A11/IAD10 A12/IAD11 A13/IAD12 GND CLKIN XTAL VDDEXT CLKOUT GND VDDINT WR RD BMS DMS PMS IOMS CMS Lead No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Lead Name IRQE + PF4 IRQL0 + PF5 GND IRQL1 + PF6 IRQ2 + PF7 DT0 TFS0 RFS0 DR0 SCLK0 VDDEXT DT1/FO TFS1/IRQ1 RFS1/IRQ0 DR1/FI GND SCLK1 ERESET RESET EMS EE ECLK ELOUT ELIN EINT Lead No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Lead Name EBR BR EBG BG D0/IAD13 D1/IAD14 D2/IAD15 D3/IACK VDDINT GND D4/IS D5/IAL D6/IRD D7/IWR D8 GND VDDEXT D9 D10 D11 GND D12 D13 D14 D15 Mode D function available on ADSP-2187L only. Rev. C | Page 44 of 48 | January 2008 Lead No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Lead Name D16 D17 D18 D19 GND D20 D21 D22 D23 FL2 FL1 FL0 PF3 [Mode D1] PF2 [Mode C] VDDEXT PWD GND PF1 [Mode B] PF0 [Mode A] BGH PWDACK A0 A1/IAD0 A2/IAD1 A3/IAD2 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L BGA PACKAGE PINOUT The BGA package pinout is shown in Table 30. Pin names in bold text in the table replace the plain text named functions when Mode C equals 1. A plus sign (+) separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets are state bits latched from the value of the pin at the deassertion of RESET. The multiplexed pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode selectable by setting Bit 10 (SPORT1 configure) of the System Control Register. If Bit 10 = 1, these pins have serial port functionality. If Bit 10 = 0, these pins are the external interrupt and flag pins. This bit is set to 1 by default upon reset. Table 30. BGA Pin Assignments Ball No. A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 1 Ball Name A2/IAD1 A1/IAD0 GND A0 NC GND NC NC NC D22 GND GND A4/IAD3 A3/IAD2 GND NC NC GND VDDEXT D23 D20 D18 D17 D16 PWDACK A6/IAD5 RD A5/IAD4 A7/IAD6 PWD VDDEXT D21 D19 D15 NC D14 Ball No. D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 E01 E02 E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 F01 F02 F03 F04 F05 F06 F07 F08 F09 F10 F11 F12 Ball Name NC WR NC BGH A9/IAD8 PF1 [MODE B] PF2 [MODE C] NC D13 D12 NC GND VDDEXT VDDEXT A8/IAD7 FL0 PF0 [MODE A] FL2 PF3 [MODE D1] GND GND VDDEXT GND D10 A13/IAD12 NC A12/IAD11 A11/IAD10 FL1 NC NC D7/IWR D11 D8 NC D9 Ball No. G01 G02 G03 G04 G05 G06 G07 G08 G09 G10 G11 G12 H01 H02 H03 H04 H05 H06 H07 H08 H09 H10 H11 H12 J01 J02 J03 J04 J05 J06 J07 J08 J09 J10 J11 J12 Ball Name XTAL NC GND A10/IAD9 NC NC NC D6/IRD D5/IAL NC NC D4/IS CLKIN GND GND GND VDDINT DT0 TFS0 D2/IAD15 D3/IACK GND NC GND CLKOUT VDDINT NC VDDEXT VDDEXT SCLK0 D0/IAD13 RFS1/IRQ0 BG D1/IAD14 VDDINT VDDINT Mode D function available on ADSP-2187L only. Rev. C | Page 45 of 48 | January 2008 Ball No. K01 K02 K03 K04 K05 K06 K07 K08 K09 K10 K11 K12 L01 L02 L03 L04 L05 L06 L07 L08 L09 L10 L11 L12 M01 M02 M03 M04 M05 M06 M07 M08 M09 M10 M11 M12 Ball Name NC NC NC BMS DMS RFS0 TFS1/IRQ1 SCLK1 ERESET EBR BR EBG IRQE + PF4 NC IRQL1 + PF6 IOMS GND PMS DR0 GND RESET ELIN ELOUT EINT IRQL0 + PF5 IRQL2 + PF7 NC CMS GND DT1/FO DR1/FI GND NC EMS EE ECLK ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L OUTLINE DIMENSIONS A1 BALL CORNER 10.10 10.00 SQ 9.90 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M BALL A1 PAD CORNER 8.80 BSC SQ 0.80 BSC TOP VIEW BOTTOM VIEW 0.60 REF DETAIL A 1.40 1.34 1.19 1.11 1.01 0.91 DETAIL A 0.33 NOM 0.28 MIN COPLANARITY 0.12 *0.50 0.45 0.40 BALL DIAMETER SEATING PLANE *COMPLIANT TO JEDEC STANDARDS MO-205-AC WITH THE EXCEPTION TO BALL DIAMETER. Figure 47. 144-Ball BGA [CSP_BGA] (BC-144-6) 16.00 BSC SQ 1.60 MAX 0.75 0.60 0.45 14.00 BSC SQ 12 TYP 100 1 76 75 SEATING PLANE 12.00 REF TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 0.20 0.09 7 3.5 0 0.08 MAX LEAD COPLANARITY SEATING PLANE VIEW A 51 50 25 26 0.50 BSC VIEW A 0.27 0.22 0.17 ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS-026-BED THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION. Figure 48. 100-Lead Low Profile Quad Flat Package [LQFP] (ST-100-1) Rev. C | Page 46 of 48 | January 2008 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L SURFACE MOUNT DESIGN Table 31 is provided as an aid to PCB design to accommodate BGA style surface mount packages. For industry-standard design recommendations, refer to IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard. Table 31. BGA Data for Use with Surface Mount Design Package 144-Ball BGA (BC-144-6) Ball Attach Type Solder Mask Defined Solder Mask Opening 0.40 mm diameter Ball Pad Size 0.50 mm diameter ORDERING GUIDE Model ADSP-2184LBST-160 ADSP-2184LBSTZ-1602 ADSP-2185LKST-115 ADSP-2185LKST-133 ADSP-2185LKST-160 ADSP-2185LKST-210 ADSP-2185LKSTZ-2102 ADSP-2185LBST-115 ADSP-2185LBST-133 ADSP-2185LBSTZ-1332 ADSP-2185LBST-160 ADSP-2185LBSTZ-1602 ADSP-2185LBST-210 ADSP-2185LBSTZ-2102 ADSP-2186LKST-115 ADSP-2186LKST-115R3 ADSP-2186LKST-133 ADSP-2186LKSTZ-1332 ADSP-2186LBST-115 ADSP-2186LBSTZ-1152 ADSP-2186LBST-1602 ADSP-2186LBCA-160R3 ADSP-2187LKST-160 ADSP-2187LKSTZ-1602 ADSP-2187LKST-210 ADSP-2187LKSTZ-2102 ADSP-2187LBST-160 ADSP-2187LBSTZ-1602 ADSP-2187LBST-210 ADSP-2187LBSTZ-2102 Temperature Range1 -40C to +85C -40C to +85C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C 0C to 70C 0C to 70C 0C to 70C 0C to 70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C 0C to 70C 0C to 70C 0C to 70C 0C to 70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Instruction Rate (MHz) 40 40 28.8 32.2 40 52.5 52.5 28.8 32.2 32.2 40 40 52.5 52.5 28.8 28.8 32.2 32.2 28.8 28.8 40 40 40 40 52.5 52.5 40 40 52.5 52.5 Package Description 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 144-Ball BGA 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 1 Ranges shown represent ambient temperature. Z = RoHS Compliant Part. 3 R = Tape and Reel. 2 Rev. C | Page 47 of 48 | January 2008 Package Option ST-100-1 ST-100-1 ST-100-1 ST-100-1 ST-100-1 ST-100-1 ST-100-1 ST-100-1 ST-100-1 ST-100-1 ST-100-1 ST-100-1 ST-100-1 ST-100-1 ST-100-1 ST-100-1 ST-100-1 ST-100-1 ST-100-1 ST-100-1 ST-100-1 BC-144-6 ST-100-1 ST-100-1 ST-100-1 ST-100-1 ST-100-1 ST-100-1 ST-100-1 ST-100-1 ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L (c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00192-0-1/08(C) Rev. C | Page 48 of 48 | January 2008