Serial Interface, 625 kSPS, 24-Bit ADC AD7763 Preliminary Technical Data FEATURES FUNCTIONAL BLOCK DIAGRAM High performance 24-bit Sigma-Delta ADC 118dB SNR at 78kHz output data rate 106dB SNR at 625 kHz output data rate 625 kHz maximum fully filtered output word rate Programmable over-sampling rate (32x to 256x) Flexible serial interface Fully differential modulator input On-chip differential amplifier for signal buffering Low pass FIR filter with default or user programmable coefficients Over-range alert bit Digital offset and gain correction registers Low power and power down modes Synchronization of multiple devices via SYNC pin VIN- VIN+ DIFF VREF+ REFGND + BUF - Multi-Bit Sigma-Delta Modulator Reconstruction AD7763 AVDD2 AVDD3 AVDD4 DECAP1 DECAP2 DECAP3 Programmable Decimation Control Logic, I/O and Registers RBIAS AGND VDRIVE FIR Filter Engine DVDD DGND I2S SCP SCR SDEN SDL DRDY SCO FSO SDO SDI FSI MCLK MCLKGND SYNC RESET SH2:0 ADR2:0 CLKDIV AVDD1 Figure 1. APPLICATIONS Data acquisition systems Vibration analysis Instrumentation PRODUCT OVERVIEW The AD7763 high performance, 24-bit, sigma delta analog to digital converter combines wide input bandwidth and high speed with the benefits of sigma delta conversion, as well as performance of 106dB SNR at 625 kSPS making it ideal for high speed data acquisition. A wide dynamic range combined with significantly reduced anti-aliasing requirements simplifies the design process. An integrated buffer to drive the reference, a differential amplifier for signal buffering and level shifting, an over-range flag, internal gain & offset registers and a low-pass digital FIR filter make the AD7763 a compact highly integrated data acquisition device requiring minimal peripheral component selection. In addition the device offers programmable decimation rates and the digital FIR filter can be adjusted if the default characteristics are not appropriate to the application. The AD7763 is ideal for applications demanding high SNR without necessitating design of complex front end signal processing. The differential input is sampled at up to 40MS/s by an analog modulator. The modulator output is processed by a series of low-pass filters, the final one having default or user programmable coefficients. The sample rate, filter corner frequencies and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7763. The reference voltage supplied to the AD7763 determines the analog input range. With a 4V reference, the analog input range is 3.2V differential biased around a common mode of 2V. This common mode biasing can be achieved using the on-chip differential amplifiers, further reducing the external signal conditioning requirements. The AD7763 is available in an exposed paddle 64-lead TQFP and 48-lead CSP packages and is specified over the industrial temperature range from -40C to +85C. Rev. PrD Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2005 Analog Devices, Inc. All rights reserved. Rev. PrD | Page 1 of 24 AD7763 Preliminary Technical Data TABLE OF CONTENTS TABLE OF CONTENTS.................................................................. 2 Clocking the AD7763 .................................................................... 16 AD7763--Specifications.................................................................. 3 Driving The AD7763 ..................................................................... 17 Timing Specifications....................................................................... 6 Using The AD7763..................................................................... 17 Timing Diagrams.............................................................................. 7 Bias Resistor Selection ............................................................... 18 Absolute Maximum Ratings............................................................ 8 Programmable FIR Filter............................................................... 19 ESD Caution.................................................................................. 8 Downloading a User-Defined Filter ............................................ 20 Pin Configuration and Functional Descriptions.......................... 9 Example Filter Download ......................................................... 20 Terminology .................................................................................... 11 AD7763 Registers ........................................................................... 22 Typical Performance Characteristics ........................................... 12 Non Bit-Mapped Registers........................................................ 23 Theory of Operation ...................................................................... 13 Outline Dimensions ....................................................................... 24 AD7763 Interface............................................................................ 14 Ordering Guide .......................................................................... 24 REVISION HISTORY Rev PrA: Preliminary Datasheet Rev PrB: Preliminary Datasheet Rev PrC: Preliminary Datasheet Rev. PrD | Page 2 of 24 Preliminary Technical Data AD7763 AD7763--SPECIFICATIONS Table 1. VDD1 = 2.5 V, VDD2 = 5 V, VREF = 4.096 V, TA = +25C, Full Power Mode using on-chip amplifierwith components as shown in Table 8 , unless otherwise noted Parameter DYNAMIC PERFORMANCE1 Decimate by 256 Dynamic Range 2 Signal to Noise Ratio (SNR)2 Spurious Free Dynamic Range (SFDR) 2 Total Harmonic Distortion (THD) 2 Decimate by 64 Dynamic Range2 Test Conditions/Comments Specifcation Unit TBD 120.8 117 120 129 -100 TBD -103 -66 dB min dB typ dB typ dBFS typ dBFS typ dB typ dB max dB typ dB typ TBD 114 TBD 109 109 -102 TBD -110 dB min dB typ dB max dB typ dBFS typ dB typ dB max dB typ 110 TBD 104 120 -102 TBD TBD dB typ dB min dB typ dBFS typ dB typ dB max dB typ 24 1 1 0.03 0.01 0.0006 1.4 Bits LSB typ LSB typ % typ % typ % /C typ ppm /C typ MCLK = 40MHz TBD S typ MCLK = 40MHz TBD S typ MCLK = 24.576MHz 480 S typ Vin(+) - Vin(-), VREF = 2.5V Vin(+) - Vin(-), VREF = 4.096V 2 3.25 2 V pk-pk V pk-pk A max MCLK = 40MHz, ODR = 78.125kHz, FIN = 1kHz Sine Wave Modulator inputs shorted Non-harmonic Input Amplitude = -60dB Input Amplitude = -0.5dB Input Amplitude = -6dB Input Amplitude = -60dB MCLK = 40MHz, ODR = 312.5kHz, FIN =100kHz Sine Wave Modulator inputs shorted Signal to Noise Ratio (SNR) 2 Modulator inputs shorted Spurious Free Dynamic Range (SFDR) 2 Total Harmonic Distortion (THD) 2 Non-harmonic Input Amplitude = -0.5dB Input Amplitude = -6dB Decimate by 32 Dynamic Range2 Signal to Noise Ratio (SNR) 2 Spurious Free Dynamic Range (SFDR) 2 Total Harmonic Distortion (THD) 2 DC ACCURACY Resolution Differential Nonlinearity2 Integral Nonlinearity2 Zero Error2 Gain Error2 Zero Error Drift Gain Error Drift DIGITAL FILTER RESPONSE Decimate by 32 Group Delay Decimate by 64 Group Delay Decimate by 128 Group Delay ANALOG INPUT Differential Input Voltage MCLK = 40MHz, ODR = 625kHz, FIN = 100kHz Sine Wave Modulator inputs shorted Non-harmonic Input Amplitude = -0.5dB Input Amplitude = -6dB Guaranteed monotonic to 24 bits At 16 bits DC Leakage Current Rev. PrD | Page 3 of 24 AD7763 Parameter Input Capacitance REFERENCE INPUT/OUTPUT VREF Input Voltage VREF Input DC Leakage Current VREF Input Capacitance POWER REQUIREMENTS AVDD1 (Modulator Supply) AVDD2 (General Supply) AVDD3 (Diff-Amp Supply) AVDD4 (Ref Buffer Supply) DVDD VDRIVE Full Power Mode AIDD1 (Modulator) AIDD2 (General) AIDD4 (Reference Buffer) Low Power Mode AVDD1 (Modulator) AIDD2 (General) AIDD4 (Reference Buffer) AIDD3 (Diff Amp) DIDD Standby Mode AVDD1 (Modulator) AIDD2 (General) AIDD3 (Diff Amp AIDD4 (Reference Buffer) DIDD POWER DISSIPATION Full Power Mode Modulator (P1) General (P2) Reference Buffer (P4) Low Power Mode Modulator (P1) General (P2) Reference Buffer (P4) Differential Amplifier (P3) Preliminary Technical Data Test Conditions/Comments At internal buffer inputs At modulator inputs Specifcation 5 55 Unit pF typ pF typ VDD3 = 3.3V VDD3 = 5V +2.5 +4.096 1 5 Volts Volts A max pF max 5% 5% +2.5 +5 +3.15/+5.25 +3.15/+5.25 +2.5 +1.65/+2.7 Volts Volts V min/max V min/max Volts V min/max AVDD4 = +5V 50 35 35 mA typ mA typ mA typ AVDD4 = +5V 26 20 10 mA typ mA typ mA typ AVDD3 = +5V, Both Modes Both Modes 42 45 mA typ mA typ AVDD3 = +5V AVDD4 = +5V Clock Stopped Clock Running 210 30 30 30 250 690 A typ nA typ nA typ nA typ A typ A typ AVDD4 = +3.3V AVDD4 = +5V 125 175 101 175 mW typ mW typ mW typ mW typ AVDD4 = +3.3V AVDD4 = +5V AVDD3 = +3.3V AVDD3 = +5V 65 100 27 50 116 210 mW typ mW typ mW typ mW typ mW typ mW typ 5% Rev. PrD | Page 4 of 24 Preliminary Technical Data Parameter Digital Power Total Power Dissipation Standby Mode AD7763 Test Conditions/Comments Full Power Mode Low Power Mode Clock Stopped Clock Running DIGITAL I/O Input Capacitance VINH VINL VOH VOL 1 2 Specifcation 112.5 TBD TBD 1.2 2.3 Unit mW typ mW max mW max mW typ mW typ TBD TBD TBD TBD TBD pF typ V min V max V min V max All specifications in dB's are referred to a full-scale input, FS. Tested with an input signal at 0.5dB below full-scale, unless otherwise specified. See Terminology Rev. PrD | Page 5 of 24 AD7763 Preliminary Technical Data TIMING SPECIFICATIONS Table 2. VDD1 = 2.5 V, VDD2 = 5 V, VREF = 4.096 V, VDRIVE = TBD V, TA = +25C, CLOAD = 25pF, Full Power Mode, unless otherwise noted Parameter fMCLK t13 t2 t3 Limit at TMIN, TMAX 1 40 500 20 1 x tICLK or 0.5 x tICLK4 1 x tICLK or 0.5 x tICLK TBD Unit MHz min MHz max kHz min MHz max typ typ typ SCO High Period SCO Low Period DRDY Low Period t4 32 x tSCO5 typ FSO Low Period t5 t6 t7 t8 TBD TBD6 TBD 8/16 x tSCO ns max ns max nS min typ Initial Data Access Time SCO Rising Edge to SDO Valid SDO Valid after SCO Falling Edge FSO Falling Edge to SDL Falling Edge t9 t10 TBD TBD typ ns max SDL Pulse Width FSO Rising Edge to SDO Three-state t11 TBD min FSI Low Period t12 t13 TBD TBD xS min xS min SDI Setup Time SDI Hold Time fICLK Description Applied Master Clock Frequency Internal Modulator Clock Derived from MCLK. 3 tICLK = 1/fICLK SCO frequency selected by SCR pin tSCO = t1+t2 6 All edges mentioned refer to SCP=0. Invert SCO edges for SCP=1 4 5 Rev. PrD | Page 6 of 24 Preliminary Technical Data AD7763 TIMING DIAGRAMS t1 SCO(O) t2 t3 DRDY (O) t4 FSO (O) t5 SDO (O) t6 t10 t7 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 t8 D8 D7 D6 D5 D4 D3 D2 D1 D0 ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0 t9 SDL (O) Figure 2. Serial Read Timing Diagram 32 SCLKs SCO (O) t1 t11 t2 FSI (I) t13 t 12 SDI (I) ALL AD2 AD1 AD0 RA11 RA10 RA1 RA0 D15 D14 D1 D0 Figure 3. AD7763 Register Write 32 CLKs SCO (O) DRDY (O) SDO (O) SERIAL DATA FROM ADC0 SERIAL DATA FROM ADC1 SERIAL DATA FROM ADC2 FSO 0 (O) FSO 1 (O) FSO 2 (O) FSO 3 (O) Figure 4. Serial Read Timing Using Multiple AD7763 Devices Rev. PrD | Page 7 of 24 SERIAL DATA FROM ADC3 AD7763 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 3. TA = 25C, unless otherwise noted. Parameters VDD to GND VIN+ to GND VIN- to GND Digital input voltage to GND Digital output voltage to GND VREF to GND Input current to any pin except supplies7 Operating temperature range Commercial (A, B version) Storage temperature range Junction temperature TQFP Exposed Paddle Package JA thermal impedance JC thermal impedance CSP Package JA thermal impedance JC thermal impedance Lead temperature, soldering Vapor phase (60 secs) Infrared (15 secs) ESD Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating TBD TBD TBD TBD TBD TBD TBD 7 -40C to +85C -65C to +150C 150C Transient currents of up to TBD mA do not cause SCR latch-up. 92.7 C/W 5.1 C/W 26.7 C/W 30 C/W 215C 220C TBD kV ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrD | Page 8 of 24 Preliminary Technical Data AD7763 43 SH2 11 38 DRDY 12 37 RESET 13 36 SYNC 14 35 DGND 15 34 AGND 16 33 AGND AVDD1 AGND AGND DECAP2 DECAP3 AVDD2 AGND VIN- AVDD3 VIN+ VOUTA1VOUTA1+ AGND AGND VINA1+ VINA1- 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RBIAS AD7763 TOP VIEW (Not to Scale) 31 DVDD 30 SH1 29 SH2 28 DRDY AVDD2 10 AVDD2 11 27 RESET 26 SYNC 25 AVDD1 RBIAS 12 VINA1+ 13 VINA1- 14 AGND AVDD4 AGND AVDD2 AVDD2 DECAP1 6 REFGND 7 VREF+ 8 AVDD4 9 AGND 24 39 AGND 23 40 9 10 33 SH0 32 VDRIVE DECAP3 22 TOP VIEW (Not to Scale) DVDD SH1 DECAP2 21 41 AVDD2 20 42 AD7763 35 ADR1 34 ADR2 MCLK 3 AVDD2 4 AVDD1 5 DGND DGND VIN+ 18 VIN- 19 7 8 36 ADR0 PIN 1 IDENTIFIER VOUTA1- 15 VOUTA1+ 16 AVDD3 17 AGND DECAP1 REFGND VREF+ 38 SDL 6 VDRIVE 1 MCLKGND 2 37 SCP 44 AGND AVDD1 39 FSI 5 ADR2 SH0 VDRIVE 41 SDO 45 40 SDI 4 42 SCO 46 PIN 1 IDENTIFIER 44 SDEN ADR1 3 2 43 FSO ADR0 47 MCLKGND MCLK AVDD2 45 DGND 48 1 47 SCR 48 I2S 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DGND 46 CDIV SCP FSI SDL SDI SDO DGND FSO SCO SDEN SCR CDIV DGND I2S DGND DGND VDRIVE PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS Figure 5. 48-PIN LFCSP Pin Configuration Figure 4. 64-Lead TQFP Pin Configuration Table 4. Pin Function Descriptions TQFP Pin Number 6, 33 CSP Pin Number 5, 25 Pin Mnemonic Description AVDD1 4, 14, 15, 27 24 4, 10, 11, 20 17 AVDD2 12 9 AVDD4 5, 7, 11, 13, 16, 18, 23, 28, 31, 32, 34 9 41 23, 24, Paddle AGND +2.5V power supply for modulator. These pins should be decoupled to AGND with 100nF and 10F capacitors on each pin. +5V power supply. These pins should be decoupled to AGND with TBD nF and TBD F capacitors on each pin. +3.3V to +5V power supply for differential amplifier. These pins should be decoupled to AGND with a 100nF capacitor. +3.3V to +5V power supply for reference buffer. This pin should be decoupled to AGND with a 10nF capacitor in series with a 10 resistor. Power supply ground for analog circuitry. In the Chip Scale package, most of the internal AGND pads are down-bonded to the exposed paddle. This paddle then become the main analog ground connection for the AD7763. 7 31 REFGND DVDD 44, 63 1, 32 VDRIVE 1, 35, 42, 43, 53, 58, 62, 64 45, Paddle DGND AVDD3 Reference Ground. Ground connection for the reference voltage. +2.5V power supply for digital circuitry and FIR filter. This pin should be decoupled to DGND with a 100nF capacitor. Logic power supply input, +1.8V to +2.5V. The voltage supplied at these pins will determine the operating voltage of the logic interface. Both these pins must be connected together and tied to the same supply. Each pin should also be decoupled to DGND with a 100nF capacitor. Ground Reference for digital circuitry. In the Chip Scale package, all the internal DGND pads are down-bonded to the exposed paddle. This paddle then becomes the single ground connection for the AD7763. Rev. PrD | Page 9 of 24 AD7763 Preliminary Technical Data TQFP Pin Number 19 20 21 22 25 26 10 CSP Pin Number 13 14 15 16 18 19 8 Pin Mnemonic Description VINA1+ VINA1VOUTA1VOUTA1+ VIN+ VINVREF+ 8 29 30 17 6 21 22 12 DECAP1 DECAP2 DECAP3 RBIAS 37 27 RESET 3 3 MCLK 2 36 2 26 MCLKGND SYNC 38 28 DRDY 39, 40, 45 29, 30, 33 SH2:0 46-48 34-36 ADR2:0 49 37 SCP 50 38 SDL 51 39 FSI 52 40 SDI 54 41 SDO 55 42 SCO 56 57 59 43 44 46 FSO SDEN CLKDIV 60 47 SCR 61 48 I2S Positive Input to Differential Amplifier. Negative Input to Differential Amplifier. Negative Output from Differential Amplifier. Positive Output from Differential Amplifier. Positive Input to the Modulator. Negative Input to the Modulator. Reference Input. The input range of this pin is determined by the reference buffer supply voltage (AVDD4). See Reference Section for more details. Decoupling Pin. A 100nF capacitor must be inserted between this pin and AGND. Decoupling Pin. A TBD F capacitor must be inserted between this pin and AGND. Decoupling Pin. A TBD F capacitor must be inserted between this pin and AGND. Bias Current setting pin. A resistor must be inserted between this pin and AGND. For more details on this, see the Bias Resistor Section. A falling edge on this pin resets all internal digital circuitry. Holding this pin low keeps the AD7763 in a reset state. Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate will depend on the frequency of this clock. See Clocking Section for more details. Master Clock ground sensing pin. Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to synchronize multiple devices in a system. Data Ready Output. Each time that new conversion data is available, an active low pulse, 1/2ICLK period wide, is produced on this pin. See AD7763 Interface Section for further details. Share Pins 2:0. For multiple AD7763 devices sharing a common serial bus, hardwiring these pins with the number of devices sharing the bus will ensure the correct number of DRDY pulses are generated. See Sharing the Serial Bus in the AD7763 Interface Section for further details. Address 2:0. To allow multiple AD7763 devices share a common serial bus, each device must be given an individual, hard-wired address. See Sharing the Serial Bus in the AD7763 Interface Section for further details. Serial Clock Polarity. Determines which edge of SCO that the data bits are clocked out and valid on. All timing diagrams are shown with SCP=0 and all SCO edges shown should be inverted for SCP=1. Serial Data Latch. A pulse is output on this pin after every 16 Data bits. The pulse is one SCO period wide and could be used in conjunction with FSO as an alternative framing method for serial transfers requiring a framing signal more frequently than every 32 bits. Frame Sync In. The status of this pin is checked on the falling edge of SCO. If this pin is low then the first data bit will be latched in on the next SCO falling edge. Serial Data In. The first data bit (MSB) must be valid on the next SCO falling edge after the FSI event has been latched. 32 bits are required for each write; the first 16-bit word contains the device and register address and the second word contains the data. Serial Data Out. Address, Status and Data bits are clocked out on this line during each serial transfer. If SCP=0, each bit is clocked out on an SCO rising edge and valid on the falling edge. Serial Clock Out. This clock signal is derived from the internal ICLK signal. The frequency of this clock is either equal to ICLK or ICLK/2 depending on the state of the SCR pin. See the Clocking the AD7763 and AD7763 Interface sections for further details. Frame Sync Out. This signal frames the serial data output and is 32 SCO periods wide. Serial Data Enable. When this pin is logic high, SDO will remain in three-state. Clock Divider. This pin is used to select the ratio of MCLK to ICLK. See the Clocking the AD7763 Section for further details. Serial Clock Rate. This pin as well as the state of the CLKDIV pin programs the SCO frequency.See Table 6 for details.. I2S Select. A logic 1 on this pin changes the serial data out mode from SPI to I2S compatible. Rev. PrD | Page 10 of 24 Preliminary Technical Data AD7763 TERMINOLOGY Signal to Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. Total Harmonic Distortion (THD) The ratio of the rms sum of harmonics to the fundamental. For the AD7763, it is defined as THD(dB ) = 20 log V22 + V32 + V42 + V52 + V62 V1 where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second to the sixth harmonics. Dynamic Range The dynamic range is the ratio of the rms value of the full scale to the rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels. Peak Harmonic or Spurious Noise The ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but, for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Non-Harmonic Spurious Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component excluding harmonics. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second-order terms include (fa + fb) and (fa - fb), while the third-order terms include (2fa + fb), (2fa - fb), (fa + 2fb) and (fa - 2fb). The AD7763 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dB. Integral Nonlinearity (INL) The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Differential Nonlinearity (DNL) The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Zero Error The zero error is the difference between the ideal midscale input voltage (0V) and the actual voltage producing the midscale output code, Gain Error The first transition (from 100...00 to 100...01) should occur for an analog voltage 1/2 LSB above the nominal negative full scale. The last transition (from 011...10 to 011...11) should occur for an analog voltage 1 1/2 LSB below the nominal full scale. The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Rev. PrD | Page 11 of 24 AD7763 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS 000 000 000 000 000 ALL CAPS ( Init ial cap) ALL CAPS ( Init ial cap) Default Conditions: TA = 25C, TBD, unless otherwise noted. TBD 000 000 000 000 000 TBD 000 000 000 000 000 ALL CAPS ( Init ial cap) 000 000 000 000 000 Figure 6. TBD 000 ALL CAPS ( Init ial cap) ALL CAPS ( Init ial cap) 000 000 000 000 000 TBD 000 000 TBD 000 000 000 000 000 000 ALL CAPS ( Init ial cap) 000 000 000 000 000 Figure 7. TBD 000 000 000 000 TBD 000 000 000 ALL CAPS ( Init ial cap) Figure 10. TBD 000 ALL CAPS ( Init ial cap) ALL CAPS ( Init ial cap) 000 Figure 9. TBD 000 000 000 000 000 000 000 000 000 000 000 ALL CAPS ( Init ial cap) 000 TBD 000 000 000 000 000 ALL CAPS ( Init ial cap) 000 000 Figure 8. TBD 000 000 000 000 000 ALL CAPS ( Init ial cap) Figure 11. TBD Rev. PrD | Page 12 of 24 Preliminary Technical Data AD7763 THEORY OF OPERATION The AD7763 employs a sigma-delta conversion technique to convert the analog input into an equivalent digital word. The modulator samples the input waveform and outputs an equivalent digital word to the digital filter at a rate equal to ICLK. Due to the high over-sampling rate, which spreads the quantization noise from 0 to fICLK, the noise energy contained in the band of interest is reduced (Figure 12a). To further reduce the quantization noise, a high order modulator is employed to shape the noise spectrum; so that most of the noise energy is shifted out of the band of interest (Figure 12b). The digital filtering which follows the modulator removes the large out-of-band quantization noise (Figure 12c) while also reducing the data rate from fICLK at the input of the filter to fICLK/8 or less at the output of the filter, depending on the decimation rate used. Digital filtering has certain advantages over analog filtering. It does not introduce significant noise or distortion and can be made perfectly linear phase. The AD7763 employs three Finite Impulse Response (FIR) filters in series. By using different combinations of decimation ratios and filter selection and bypassing, data can be obtained from the AD7763 at a large range of data rates. The first filter receives data from the modulator at ICLK MHz where it is decimated by four to output data at (ICLK/4) MHz. QUANTIZATION NOISE fICLK/2 BAND OF INTEREST a. NOISE SHAPING fICLK/2 BAND OF INTEREST b. DIGITAL FILTER CUTOFF FREQUENCY fICLK/2 BAND OF INTEREST c. Figure 12. Sigma-Delta ADC The second filter allows the decimation rate to be chosen from 4x to 32x or to be completely bypassed. The third filter has a fixed decimation rate of 2x and is user programmable as well as having a default configuration. It is described in detail in the Programmable FIR Filter Section. This filter can also be bypassed. Table 5 below shows some characteristics of the default filter. The group delay of the filter is defined to be the delay to the centre of the impulse response and is equal to the computation + filter delays. The delay until valid data is available (the DVALID status bit is set) is equal to 2x the filter delay + the computation delay. Table 5. Configuration With Default Filter ICLK Frequency 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 20 MHz 12.288MHz 12.288MHz 12.288MHz 12.288MHz Filter 1 Filter 2 Filter 3 Data State 4x 4x 4x 4x 4x 4x 4x 4x 4x 4x 4x 4x 8x 8x 16x 16x 32x 32x 8x 16x 32x 32x 2x Bypassed 2x Bypassed 2x Bypassed 2x 2x 2x Bypassed 2x Fully Filtered Partially Filtered Fully Filtered Partially Filtered Fully Filtered Partially Filtered Fully Filtered Fully Filtered Fully Filtered Partially Filtered Fully Filtered Computation Delay 1.775S 2.6S 2.25S 4.175S 3.1S 7.325S 4.65S 3.66S 5.05S 11.92S 7.57S Rev. PrD | Page 13 of 24 Filter Delay 44.4S 10.8S 87.6S 20.4S 174S 39.6S 346.8S 142.6S 283.2S 64.45S 564.5S Passband Bandwidth 250 kHz 140.625 kHz 125 kHz 70.3125 kHz 62.5 kHz 35.156 kHz 31.25 kHz 76.8 kHz 38.4 kHz 21.6 kHz 19.2 kHz Output Data Rate (ODR) 625 kHz 625 kHz 312.5 kHz 312.5 kHz 156.25 kHz 156.25 kHz 78.125 kHz 192 kHz 96 kHz 96 kHz 48 kHz AD7763 Preliminary Technical Data AD7763 INTERFACE Reading Data Sharing The Serial Bus The AD7763 uses an SPI compatible serial interface. The timing diagram in Figure 2 shows how the AD7763 transmits its conversion results. The AD7763 functionality allows up to eight devices to share the same serial bus, SDO. Devices sharing the serial output bus are assigned addresses from 000 to 111. The data being read from the AD7763 is clocked out using the serial clock output, SCO. The SCO frequency is dependant on the the state of the serial clock output rate, SCR, and the clock divider mode chosen by the state of the clock divider bit CDIV (see the Clocking the AD7763 section). Table 6 details the SCO frequency for the AD7763 as a result of the states of both the CDIV and SCR pins. For a part with an address of 0, the SDO line comes out of tristate on the first rising edge of SCO after the DRDY pulse and returns to tri-state after the 32nd SCO falling edge plus a TBD hold time. For the next device sharing the serial bus , address 1, the SDO line will come out of tri-state on the 32nd SCO rising edge for the next 32 SCO periods. This pattern will occur for the rest of the proceeding devices sharing the serial bus. Table 6. SCO Frequency Figure 4 shows an example lof four devices sharing the same serial bus. Each of the devices is hardwired with a different address form 0 to 3(ADR2:0). Device 0 outputs its serial word on the SDO line during the first 32 SCO cycles. Device 1 then outputs its serial word during the next 32 SCO cycles and so on for the remaining devices 2 and 3. Clock Divide Mode CDIV SCR SCO Frequency Divide by 1 1 0 MCLK 1 MCLK 0 MCLK/2 1 MCLK Divide by 2 0 An active low pulse of one SCO period on the data ready output, DRDY, indicates a new conversion result is available at the AD7763 serial data output,SDO. Each bit of the new conversion result is clocked onto the SDO line on the rising SCO edge and is valid on the falling SCO edge. The SDO line is tri-stated when the serial data enable pin, SDEN, is logic high.The 32-bit result consists of the 24 data bits which, are followed by 8 status bits. These status bits are shown in Table 7. The first three status bits. AD[2:0}, are the device address bits. Table 15 contains descriptions of the other status bits. Table 7. Status Bits During Data Read D7 AD2 D0 AD1 AD0 DValid Ovr LPwr FiltOk 0 The conversion result output on the SDO line is framed by the frame synchronization output, FSO, which is sent logic low for 32 SCO cycles following the rising edge of the DRDY signal. The AD7763 also features a serial data latch output, SDL, which outputs a pulse every sixteen data bits. The SDL output offers an alternative framing signal for serial transfers which require a framing signal more frequent than every 32 bits. To create the DRDY pulse as shown in Figure 4, (where four devices are sharing the same serial line) the share bits of this device, SH[2:0], should be set to 011, which, corresponds to 4 devices sharing the serial line. Each AD7763 device outputs its own FSO signal. The provision of two framing signals: DRDY and ,FSO ensures that the AD7763 offers flexible data output framing options, which, are further enhanced by the availability of the SDL output. The user can select the framing output which bests suits the application. Writing To The AD7763 Figure 3 shows the AD7763 write operation. The serial writing operation is synchronous to the SCO signal. The status of the frame sync input, FSI , is checked on the falling edge of the SCO signal. If the FSI line is low then the first data is latched in on the next SCO falling edge. The active edge of the FSI signal should be set to occur at a position when the SCO signal is high or low and which also allows set-up and hold time from the SCO falling edge to be met. The width of the FSI signal may be set to between 1 and 32 SCO periods wide. A second or subsequent FSI falling edge which occurs before 32 SCO periods have elapsed will be ignored. Figure 3 also shows the format for the serial data being written to the AD7763. 32 bits are required for a write operation. The first 16 bits are used to select the device and register address which the data being read is intended. The second 16 bits contain the data for the selected register. When using multiple Rev. PrD | Page 14 of 24 Preliminary Technical Data AD7763 devices which share the same serial bus, all FSI and SDI pins may be tied together and each device written to individually by setting the appropriate address bits in the serial 32-bit word. There is an exception to this in the case where all devices may be written to at the same time by setting the ALL bit logic high. Thus if this bit is set to logic high every device on the serial bus will accept the data written regardless of the address bits. This feature is particularly attractive, if, for example 4 devices were being configured with the same user defined filter. Instead of having to download the filter configuration four times, only one write would be required. Writing to AD7763 should be allowed at any time even while reading a conversion result. It should be noted that after writing to the devices, valid data will not be output until after the settling time for the filter has elapsed. The DVALID status bit is asserted at this point to indicate that the filter has settled and that valid data is available at the output. Reading Status and Other Registers The AD7763 features a number of programmable registers. To read back the contents of these registers or the status register, the user must first write to the control register of the device setting a bit corresponding to the register they wish to read. The next read operation will then output the contents of the selected register instead of a conversion result. More information on the relevant bits in the control register is given in the AD7763 Registers section. Rev. PrD | Page 15 of 24 AD7763 Preliminary Technical Data CLOCKING THE AD7763 The AD7763 requires an external low jitter clock source. This signal is applied to the MCLK and MCLKGND pins. An internal clock signal (ICLK) is derived from the MCLK input signal. This ICLK controls all the internal operation of the AD7763. The maximum ICLK frequency is 20MHz but due to an internal clock divider, a range of MCLK frequencies can be used. There are three possibilities available to generate the ICLK: 1. ICLK = MCLK (CDIV = 1) 2. ICLK = MCLK / 2 (CDIV = 0) for example, the input level was 3dB down from full-scale, the allowable jitter would be increased by a factor of 2 increasing the first example to 2.53ps RMS. This is due to the fact that the maximum slew rate is reduced by a reduction in amplitude. Figure 13 and Figure 14 illustrate this point showing the maximum slew rate of a sine wave of the same frequency but with different amplitudes. These options are pin selected (See Table 4 Pin Function Descriptions for further details). If the user wishes to get output data rates equal to those used in audio systems, a 12.288 MHz ICLK frequency can be used. As shown in Table 5, output data rates of 192, 96kHz and 48kHz are achievable with this ICLK frequency. As mentioned previously, this ICLK frequency can be derived from different MCLK frequencies. The MCLK jitter requirements depend on a number of factors and are given by the following equation: Figure 13. Maximum Slew Rate of Sine Wave with Amplitude of 2V Pk-Pk OSR t j ( RMS ) = 2 x x f IN x 10 SNR ( dB ) 20 OSR = Over-sampling ratio = f ICLK ODR fIN = Maximum Input Frequency SNR(dB) = Target SNR. Taking an example from Table 5: ODR = 625 kHz, fICLK = 20MHz, fIN (max) = 250 kHz, SNR = 108dB t j ( RMS ) = 32 = 3.6 ps 2 x x 250 x 10 3 x 10 6 This is the maximum allowable clock jitter for a full-scale 250kHz input tone with the given ICLK and Output Data Rate. Figure 14. Maximum Slew Rate of Same Frequency Sine Wave with Amplitude of 1V Pk-Pk Taking a second example from Table 5: ODR = 48kHz, fICLK = 12.288MHz, fIN (max) = 19.2kHz, SNR = 120dB t j ( RMS ) = 256 = 133 ps 2 x x 19.2 x 10 3 x 10 6 The input amplitude also has an effect on these jitter figures. If, Rev. PrD | Page 16 of 24 Preliminary Technical Data AD7763 DRIVING THE AD7763 The AD7763 has an on-chip differential amplifier. This amplifier will operate with a supply voltage (AVDD3) from 3V to 5.5V. For a 4.096V reference, the supply voltage must be 5V. To achieve the specified performance in full power mode, the differential amplifier should be configured as a first order antialias filter as shown in Figure 15. Any additional filtering should be carried out in previous stages using low noise, highperformance op-amps such as the AD8021. +2.5V +3.685V 0V +2.048V A 0.410V -2.5V +2.5V VIN+ +3.685V B 0V +2.048V -2.5V 0.410V VIN- Figure 16. Differential Amplifier Signal Conditioning Suitable component values for the first order filter are listed in Table 8. Using the first row as an example would yield a 10dB attenuation at the first alias point of 19MHz. CFB RFB RIN A VINA1 CS B VIN+ RIN To obtain maximum performance from the AD7763, it is advisable to drive the ADC with differential signals. However, it is possible to drive the AD7763 with a single ended signal once the common mode of the signal is within the range of +0.7V to +2.1V with VDD3 = 5V or +0.7 to +1.25V with VDD3 = 3.3V. In this case the on-chip differential amplifier can be used to convert the signal from single-ended to differential before being fed into the modulator inputs. Figure 17 shows how a bipolar single-ended signal biased around ground can be used to drive the AD7763 with the use of an external op-amp such as the AD8021. CFB RFB 2R VIN CFB Table 8. Full Power Component Values VREF RIN RFB RFB AD8021 R Figure 15. Differential Amplifier Configuration ODR 2R RIN CS VIN+ RIN CS VINA1 RFB CFB 625kHz 4.096v 1k 655 5.6pF 33pF 625kHz 2.5v TBD TBD TBD TBD pF 48kHz 4.096v TBD TBD TBD TBD pF 48kHz 2.5v TBD TBD TBD TBD pF CFB Figure 17. Single Ended to Differential Conversion If using a 4.096V reference, a supply must be provided to the reference buffer (AVDD4). If using a 2.5V reference, a 3.3V supply must be provided to AVDD4 . Figure 16 shows the signal conditioning that occurs using the circuit in Figure 15 with a 2.5V input signal biased around ground using the component values and conditions in the first row of Table 8. The differential amplifier will always bias the output signal to sit on the optimum common mode of VREF/2, in this case 2.048V. The signal is also scaled to give the maximum allowable voltage swing with this reference value. This is calculated as 80% of VREF, i.e. 0.8 x 4.096V 3.275V peak to peak on each input. Rev. PrD | Page 17 of 24 AD7763 Preliminary Technical Data USING THE AD7763 BIAS RESISTOR SELECTION The following is the recommended sequence for powering up and using the AD7763. The AD7763 requires a resistor to be connected between the RBIAS pin and AGND. The value for this resistor is dependant on the reference voltage being applied to the device. The resistor value should be selected to give a current of 25A through the resistor to ground. For a 2.5V reference voltage, the correct resistor value is 100k and for a 4.096V reference, 160k. 1. Apply Power 2. Start clock oscillator, applying MCLK 3. Take RESET low for a minimum of 1 MCLK cycle 4. Wait a minimum of 2 MCLK cycles after RESET has been released. 5. Write to Control Register 2 to power up the ADC and the differential amplifier as required. 6. Write to Control Register 1 to set up the Output Data Rate. 7. In circumstances where multiple parts are being synchronized, a SYNC pulse must be applied to the parts, otherwise no SYNC pulse is required. Conditions for applying the SYNC pulse: (a) The issue of a SYNC pulse to the part must not coincide with a write to the part. (b) The SYNC pulse should be applied a minimum of 2.5 ICLK cycles after the CS signal for the previous write to the part has returned logic high. (c) Ensure that the SYNC pulse is taken low for a minimum of 2.5 ICLK cycles. Data can now be read from the part using the default filter, offset, gain, and over range threshold values. The conversion data read will not be valid however until the settling time of the filter has passed. When this has occurred, the DVALID bit read will be set indicating that the data is indeed valid. The user can now download their own filter if required (see Downloading a User-Defined Filter). Values for gain, offset and over range threshold registers can be written or read at this stage. Rev. PrD | Page 18 of 24 Preliminary Technical Data AD7763 PROGRAMMABLE FIR FILTER As previously mentioned, the third FIR filter on the AD7763 is user programmable. The default coefficients that are loaded on reset are given in Table 9. This gives a frequency response shown in Figure 18. The frequencies quoted in Figure 18 scale directly with the Output Data Rate. * The filter must be even, symmetrical FIR. * The coefficients are in sign-and-magnitude format with 26 magnitude bits and sign coded as positive=0. * The filter length must be between 12 and 96 in steps of 12. * As the filter is symmetrical, the number of coefficients that must be downloaded will be half the filter length. The default filter coefficients are an example of this with only 48 coefficients listed for a 96-tap filter. * Coefficients are written from the center of impulse response (adjacent to the point of symmetry) outwards. * The coefficients are scaled so that the in-band gain of the filter is equal to 134217726 with the coefficients rounded to the nearest integer. For a low pass filter this is the equivalent of having the coefficients sum arithmetically (including sign) to +67108863 (0x3FF FFFF) positive value over the half-impulse-response coefficient set (max 48 coefficients). Any deviation from this will result in a gain error being introduced. Table 9. Default Filter Coefficients # Dec. Value Hex Value # 0 53656736 332BCA0 24 Dec. Value 700847 1 25142688 17FA5A0 25 -70922 2 -4497814 444A196 26 -583959 408E917 3 -11935847 4B62067 27 -175934 402AF3E 4 -1313841 4140C31 28 388667 5EE3B Hex Value AB1AF 401150A 5 6976334 6A734E 29 294000 47C70 6 3268059 31DDDB 30 -183250 402CBD2 7 -3794610 439E6B2 31 -302597 4049E05 8 -3747402 4392E4A 32 16034 3EA2 9 1509849 1709D9 33 238315 3A2EB 10 3428088 344EF8 34 88266 158CA 11 80255 1397F 35 -143205 4022F65 12 -2672124 428C5FC 36 -128919 401F797 13 -1056628 4101F74 37 51794 CA52 14 1741563 1A92FB 38 121875 1DC13 15 1502200 16EBF8 39 16426 402A 16 -835960 40CC178 40 -90524 401619C 17 -1528400 4175250 41 -63899 400F99B 18 93626 16DBA 42 45234 B0B2 19 1269502 135EFE 43 114720 1C020 20 411245 6466D 44 102357 18FD5 21 -864038 40D2F26 45 52669 CDBD 22 -664622 40A242E 46 15559 3CC7 23 434489 6A139 47 1963 7AB The default filter should be sufficient for almost all applications. It is a standard brick wall filter with a symmetrical impulse response. The default filter has a length of 96, is non-aliasing with 120dB of attenuation at Nyquist. This filter not only performs signal anti-aliasing but also suppresses out-of-band quantization noise produced by the A-D conversion process. Any significant relaxation in the stop-band attenuation or transition band width relative to the default filter may result in a failure to meet the SNR specifications. Figure 18. Default Filter Frequency Response (625kHz ODR) The procedure for downloading a user-defined filter is detailed in the Downloading a User-Defined Filter section. If a user does wish to create their own filter then the following should be noted: Rev. PrD | Page 19 of 24 AD7763 Preliminary Technical Data As previously mentioned, the filter coefficients are 27 bits in length; one sign and 26 magnitude bits. Since the AD7763 has a 16-bit parallel bus, the coefficients are padded with 5 MSB zeros to generate a 32-bit word and split into two 16-bit words for downloading. The first 16-bit word for each coefficient becomes (00000, Sign bit, Magnitude[25:16]), while the second word becomes (Magnitude [15:0]). To ensure that a filter is downloaded correctly, a checksum must also be generated and downloaded following the final coefficient. The checksum is a 16-bit word generated by splitting each 32-bit word mentioned above into 4 bytes and summing all bytes from all coefficients up to a maximum of 192 bytes (48 coefficients x 4 bytes). The same checksum is generated internally in the AD7763 and compared with the checksum downloaded. The DL_OK bit in the Status Register is set if these two checksums agree. The following is the procedure for downloading a user filter: 1. 2. Write to Control Register 1 setting the DL_Filt bit and also the correct filter length bits corresponding to the length of the filter about to be downloaded (See Table 10). Write the first half of the current coefficient data (00000, Sign bit, Magnitude[25:16]). The first coefficient to be written must be the one adjacent to the point of filter symmetry. 3. Write the second half of the current coefficient data (Magnitude [15:0]). 4. Repeat Steps 2 and 3 for each coefficient. 5. Write the 16-bit checksum. 6. There are two methods to verify that the filter coefficients have been downloaded correctly: a. b. It should be borne in mind that since the user coefficients are stored in RAM, they will be cleared after a RESET operation or a loss of power. EXAMPLE FILTER DOWNLOAD The following is an example of downloading a short user defined filter with 24-taps. The frequency response is shown in Figure 19. 10 0 -10 Amplitude (dB) DOWNLOADING A USER-DEFINED FILTER -20 -30 -40 -50 -60 -70 -80 0 300 400 500 600 Figure 19. 24-Tap FIR Frequency Response The coefficients for the filter are listed in Table 11. The coefficients are shown from the center of symmetry outwards. The raw coefficients were generated using a commercially available filter design tool and scaled appropriately so their sum equals +67108863 (0x3FF FFFF). Table 11. 24-Tap FIR Coefficients Read the Status Register checking the DL_OK bit. Coeff Start reading data and observe the status of the DL_OK bit. Num Coeffs Default 6 12 18 24 30 36 42 48 200 Frequency (kHz) Table 10. Filter Length Values FLEN[3:0] 0000 0001 0011 0101 0111 1001 1011 1101 1111 100 Filter Length Default 12 24 36 48 60 72 84 96 Rev. PrD | Page 20 of 24 1 Raw 0.365481974 Scaled 53188232 2 0.201339905 29300796 3 0.009636604 1402406 4 -0.075708848 -11017834 5 -0.042856209 -6236822 6 0.019944246 2902466 7 0.036437914 5302774 8 0.007592007 1104856 9 -0.021556583 -3137108 10 -0.024888355 -3621978 11 -0.012379538 -1801582 12 -0.001905756 -277343 Preliminary Technical Data AD7763 Table 12 shows the Hex values (in sign and magnitude format) that are downloaded to the AD7763 to realize this filter. The table is also split into the bytes which are all summed to produce the checksum. The checksum generated from these coefficients is 0x0E6B. 0x0001 Address of Control Register 1 Table 12. Filter Hex Values 0x9688 First Coefficient, Word 2 Coeff 0x8079 Control Reg Data; DL Filter, Set Filter Length = 24, Set Output Data Rate = 625kHz 0x032B First Coefficient, Word 1 Word 2 Word 1 0x01BF Second Coefficient, Word 1 Byte 1 Byte 2 Byte 3 1 03 2B 96 88 2 01 BF 18 3C 3 00 15 66 26 4 04 A8 1E 6A 0x0404 Twelfth (Final) Coefficient, Word 1 5 04 5F 2A 96 0x3B5F Final Coefficient, Word 2 6 00 2C 49 C2 7 00 50 E9 F6 8 00 10 DB D8 9 04 2F DE 54 Wait TBD xS for AD7763 to fill remaining unused coefficients with zeros. 10 04 37 44 5A 0x0001 Address of Control Register 11 04 1B 7D 6E 12 04 04 3B 5F Byte 4 What follows is a list of 16-bit words that the user would write to the AD7763 to set up the ADC and download this filter assuming an output data rate of 625kSPS has already been selected. 0x183C Second Coefficient, Word 2 ... ... 0x0E6B Checksum 0x0879 Control Reg Data; Set Read Status and maintain filter length and decimation settings. Read contents of Status Register. Check Bit 7 (DL_OK) to determine that the filter was downloaded correctly. Rev. PrD | Page 21 of 24 AD7763 Preliminary Technical Data AD7763 REGISTERS The AD7763 has a number of user-programmable registers. The control registers are used to set the decimation rate, the filter configuration, the clock divider etc. There are also digital gain, offset and over-range threshold registers. Writing to these registers involves writing the register address first, then a 16-bit data word. Register Addresses, details of individual bits and default values are given here. Table 13. Control Register 1 (Address 0x0001, Default Value 0x001A) MSB DL Filt LSB RD Ovr RD Gain Bit 15 Mnemonic DL Filt8 14 RD Ovr8,9 13 12 11 10 9 RD Gain8,9 RD Off8,9 RD Stat8,9 0 SYNC8 8-5 4 3 FLEN3:0 BYP F3 BYP F1 2-0 DEC2:0 8 9 RD Off RD Stat 0 SYNC FLEN3 FLEN2 FLEN1 FLEN0 BYP F3 BYP F1 DEC2 DEC1 DEC0 Comment Download Filter. Before downloading a user defined filter, this bit must be set. The Filter Length bits must also be set at this time. The write operations that follow will be interpreted as the user coefficients for the FIR filter until all the coefficients and the checksum have been written. Read Overrange. If this bit has been set, the next read operation will output the contents of the Overrange Threshold Register instead of a conversion result. Read Gain. If this bit has been set, the next read operation will output the contents of the digital Gain Register. Read Offset. If this bit has been set, the next read operation will output the contents of the digital Offset Register. Read Status. If this bit has been set, the next read operation will output the contents of the Status Register. Synchronize. Setting this bit will initiate in internal synchronisation routine. Setting this bit simultaneously on multiple devices will synchronize all filters. Filter Length Bits. These bits must be set when the DL Filt bit is set and before a user defined filter is downloaded. Bypass Filter 3. If this bit is a 0, Filter 3 (Programmable FIR) will be bypassed. Bypass Filter 1. If this bit is a 0, Filter 1 will be bypassed. This should only occur when the user requires unfiltered modulator data to be output. Decimation Rate. These bits set the decimation rate of Filter 2. All zeros implies that the filter is bypassed. A value of 1 corresponds to 2x decimation, a value of 2 corresponds to 4x and so on up to the maximum value of 5, corresponding to 32x decimation. Bits 15-9 are all self clearing bits. Only one of the bits may be set in any write operation as they all determine the contents of the next operation. Table 14. Control Register 2 (Address 0x0002, Default Value 0x009B) MSB 0 LSB 0 0 Bit 3 2 Mnemonic PD LPWR 1 0 D1PD 0 0 0 0 0 0 0 0 0 PD LPWR 1 D1PD Comment Power Down. Setting this bit powers down the AD7763 reducing the power consumption to TBD W. Low Power. If this bit is set, the AD7763 is operating in a low power mode. The power consumption is reduced for a 3dB reduction in noise performance. Write a `1' to this bit. Differential Amplifier Power Down. Setting this bit powers down the on-chip differential amplifier. Rev. PrD | Page 22 of 24 Preliminary Technical Data AD7763 Table 15. Status Register (Read Only) MSB LSB PART 1 PART 0 DIE 2 Bit 15,14 13-11 10 9 8 7 Mnemonic PART1:0 DIE2:0 DVALID LPWR OVR DL OK 6 Filter OK 5 4 3 2-0 U Filter BYP F3 BYP F1 DEC2:0 DIE 1 DIE 0 DVALID LPWR OVR DL OK Filter OK U Filter BYP F3 BYP F1 DEC2 DEC1 DEC0 Comment Part Number. These bits will be constant for the AD7763. Die Number. These bits will reflect the current AD7763 die number for identification purposes within a system. Data Valid. This bit corresponds to the DVALID bit in the status word output in the second 16-bit read operation. Low Power. If the AD7763 is operating in Low Power Mode, this bit is set to a 1. If the current analog input exceeds the current overrange threshold, this bit will be set. When downloading a user filter to the AD7763, a checksum is generated. This checksum is compared to the one downloaded following the coefficients. If these checksums agree, this bit is set. When a user-defined filter is in use, a checksum is generated when the filter coefficients pass through the filter. This generated checksum is compared to the one downloaded. If they match, this bit is set. If a user-defined filter is in use, this bit is set. Bypass Filter 3. If Filter 3 is bypassed by setting the relevant bit in Control Register 1, this bit is also set. Bypass Filter 1. If Filter 1 is bypassed by setting the relevant bit in Control Register 1, this bit is also set. Decimation Rate. These correspond to the bits set in Control Register 1. NON BIT-MAPPED REGISTERS Offset Register (Address 0x0003, Default Value 0x0000) The Offset Register uses 2's Complement notation and is scaled such that 0x7FFF (maximum positive value) and 0x8000 (maximum negative value) correspond to an offset of +0.78125% and -0.78125% respectively. Offset correction is applied after any gain correction. Using the default gain value of 1.25 and assuming a reference voltage of 4.096V, the offset correction range is approximately 25mV. Gain Register (Address 0x0004, Default Value 0xA000) The Gain Register is scaled such that 0x8000 corresponds to a gain of 1.0. The default value of this register is 1.25 (0xA000). This gives a full scale digital output when the input is at 80% of VREF. This ties in with the maximum analog input range of 80% of VREF Pk-Pk. Over Range Register (Address 0x0005, Default Value 0xCCCC) The Over Range register value is compared with the output of the first decimation filter to obtain an overload indication with minimum propagation delay. This is prior to any gain scaling or offset adjustment. The default value is 0xCCCC which corresponds to 80% of VREF (the maximum permitted analog input voltage) Assuming VREF = 4.096V, the bit will then be set when the input voltage exceeds approximately 6.55v pk-pk differential. Note that the over-range bit is also set immediately if the analog input voltage exceeds 100% of VREF for more than 4 consecutive samples at the modulator rate. Rev. PrD | Page 23 of 24 AD7763 Preliminary Technical Data OUTLINE DIMENSIONS 0.60 (0.024) 0.42 (0.017) 0.24 (0.009) 0.60 (0.024) 0.42 (0.017) 37 36 0.24 (0.009) 7.0 (0.276) BSC SQ PIN 1 INDICATOR 0.25 (0.010) MIN 48 1 6.75 (0.266) BSC SQ TOP VIEW 5.25 (0.207) 5.10 (0.201) SQ 4.95 (0.195) BOTTOM VIEW 25 24 0.50 (0.020) 0.40 (0.016) 0.30 (0.012) 12 13 5.5 (0.217) REF 0.70 (0.028) MAX 12MAX 0.65 (0.026) NOM 0.90 (0.035) MAX 0.05 (0.002) 0.85 (0.033) NOM 0.01 (0.0004) 0.0 (0.0) 0.30 (0.012) 0.50 (0.020) 0.20 (0.008) REF 0.23 (0.009) BSC 0.18 (0.007) Figure 20. 48-Lead Frame Chip Scale Package [LFCSP] (CP-48)--Dimensions shown in millimeters 1.60 (0.063) MAX 0.15(0.006) 0.05(0.002) 0.60 0.15 (0.024 0.006) 12o TYP 12.0(0.47) BSC 10.0(0.39) BSC 64 49 48 1 SEATING PLANE 6.0(0.235) BSC TOP VIEW 33 32 16 0o 3.5o 3.5o 17 0.50 (0.02) BSC 0.22 0.05 (0.0087 0.002) Figure 21. 64-Lead Thin Quad Flat Pack (Exposed Paddle) [TQFP] (SV-64)--Dimensions shown in millimeters ORDERING GUIDE Model AD7763BCP AD7763BSV Temperature Range -40C to +85C -40C to +85C Package Description Lead Frame Chip Scale Package Thin Quad Flat Pack, Exposed Paddle (c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Printed in the U.S.A. PR05476-0-4/05(PrD) Rev. PrD | Page 24 of 24 Package Option CP-48 SV-64