SN54ABTH162460, SN74ABTH162460 4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS241E - FEBRUARY 1993 - REVISED MAY 1997 D D D D D D D D D D SN54ABTH162460 . . . WD PACKAGE SN74ABTH162460 . . . DL PACKAGE (TOP VIEW) Members of the Texas Instruments Widebus Family B-Port Outputs Have Equivalent 25- Series Resistors, So No External Resistors Are Required State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Dissipation LEAB1 LEAB2 LEBA GND LEB1 LEB2 VCC CLKBA OEB CLKAB GND 1A 2A CE_SEL0 CE_SEL1 3A 4A GND CLKENAB CLKENB CLKENBA VCC LEB3 LEB4 GND OEA LEAB3 LEAB4 Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25C High-Impedance State During Power Up and Power Down Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Package and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings description The 'ABTH162460 are 4-bit to 1-bit multiplexed registered transceivers used in applications where four separate data paths must be multiplexed onto or demultiplexed from a single data path. Typical applications include multiplexing and/or demultiplexing of address and data information in microprocessor or bus-interface applications. This device also is useful in memory-interleaving applications. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 OEB1 OEB2 SEL0 GND 1B1 1B2 VCC 1B3 1B4 2B1 GND 2B2 2B3 2B4 3B1 3B2 3B3 GND 3B4 4B1 4B2 VCC 4B3 4B4 GND SEL1 OEB3 OEB4 Five 4-bit I/O ports (1A-4A, 1B1-4, 2B1-4, 3B1-4, and 4B1-4) are available for address and/or data transfer. The output-enable (OEB, OEB1-OEB4, and OEA) inputs control the bus-transceiver functions. These control signals also allow 4-bit or 16-bit control, depending on the OEB level. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and EPIC-B are trademarks of Texas Instruments Incorporated. Copyright 1997, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN54ABTH162460, SN74ABTH162460 4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS241E - FEBRUARY 1993 - REVISED MAY 1997 description (continued) Address and/or data information can be stored using the internal storage latches/flip-flops. The latch-enable (LEB1-LEB4, LEBA, and LEAB1-LEAB4) and clock/clock-enable (CLK/CLKEN) inputs are used to control data storage. When either one of the latch-enable inputs is high, the latch is transparent (clock is a don't care as long as the latch enable is high). When the latch-enable input goes low (providing that the clock does not transit from low to high), the data present at the inputs is latched and remains latched until the latch-enable input is returned high. When the clock enable is low and the corresponding latch enable is low, data can be clocked on the low-to-high transition of the clock. When either the clock enable or the corresponding latch enable is high, the clock is a don't care. Four select (SEL0, SEL1, CE_SEL0, and CE_SEL1) pins are provided to multiplex data (A port), or to select one of four clock enables (B port). This allows the user the flexibility of controlling one bit at a time. The B-port outputs, which are designed to sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABTH162460 is characterized for operation over the full military temperature range of -55C to 125C. The SN74ABTH162460 is characterized for operation from -40C to 85C. Function Tables A-TO-B OUTPUT ENABLE INPUTS OEB OEBn OUTPUT Bn H H Z H L Z L H Z L L n = 1, 2, 3, 4 Active A-TO-B STORAGE (assuming OEB = L, OEBn = L) INPUTS OUTPUTS CLKENAB CE_SEL1 CE_SEL0 CLKAB LEAB1 LEAB2 LEAB3 LEAB4 X X X H or L H L L X X X H or L H H H L X X L L L L L L L L L L L L L L H L L L L L H L L L L L L H H L L L L H X X L L L L This table does not cover all the latch-enable cases since they have similar results. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 B1 B2 B3 B4 L A L A A0 A A0 A A0 A0 A0 A A0 A0 A0 A0 A0 A0 A0 A0 A A0 A A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A SN54ABTH162460, SN74ABTH162460 4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS241E - FEBRUARY 1993 - REVISED MAY 1997 Function Tables (Continued) B-TO-A STORAGE (before point P) INPUTS P CLKENB CLKBA LEB1 LEB2 LEB3 LEB4 SEL1 SEL0 X X H L L L L L B1 X X L H L L L H B2 X X L L H L H L B3 X X L L L H H H B4 L L L L L L L L L L L L L B1 L H B2 H L B3 H H B4 L L L H B10 B20 H L B30 B40 H H Output level before the indicated steady-state input conditions were established B-TO-A STORAGE (after point P) INPUTS LEBA OEA B OUTPUT A X X H X Z X H L L L CLKENBA CLKBA X X X X H L H H H X L L X L L L L A0 L L L L H H A0 Output level before the indicated steady-state input conditions were established L L L POST OFFICE BOX 655303 L X * DALLAS, TEXAS 75265 3 SN54ABTH162460, SN74ABTH162460 4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS241E - FEBRUARY 1993 - REVISED MAY 1997 logic diagram (positive logic) LEB4 LEB3 LEB2 LEB1 24 28 23 27 6 2 5 1 56 55 CLKENB 30 20 29 9 SEL1 SEL0 LEBA CLKBA CLKENBA 14 54 15 1A 19 LEAB1 OEB1 OEB2 OEB3 OEB4 OEB CE_SEL0 CE_SEL1 CLKENAB 8 CLKENAB Selector 21 P M U X LE D CLK CE 52 LE D CLK CE 51 CLK CE D LE 49 CLK CE D LE 48 LE CLK CE D 10 LE CLK CE D 26 LE CLK CE D 12 LE CLK CE D 4 LEAB2 3 CE CLK D LE OEA LEAB3 31 One of Four Channels CLKAB LEAB4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1B1 1B2 1B3 1B4 SN54ABTH162460, SN74ABTH162460 4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS241E - FEBRUARY 1993 - REVISED MAY 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABTH162460 (A port) . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABTH162460 (A port) . . . . . . . . . . . . . . . . . . . . . . . . 128 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 2): DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51. recommended operating conditions (see Note 3) VCC VIH Supply voltage VIL VI Low-level input voltage SN54ABTH162460 SN74ABTH162460 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 High-level input voltage 2 2 0.8 Input voltage 0 0.8 V VCC -32 V A port B port -12 -12 A port 48 64 B port 12 12 High level output current High-level IOL Low level output current Low-level t/v Input transition rise or fall rate t/VCC TA Power-up ramp rate 200 Operating free-air temperature -55 Outputs enabled 10 10 -40 mA mA ns/V s/V 200 125 V V VCC -24 IOH 0 UNIT 85 C NOTE 3: Unused control pins must be held high or low to prevent them from floating. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN54ABTH162460, SN74ABTH162460 4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS241E - FEBRUARY 1993 - REVISED MAY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK A port VOH VCC = 4.5 V, VCC = 5 V, II = -18 mA IOH = -3 mA 5V VCC = 4 4.5 VCC = 5 V, B port A port VCC = 4.5 V -1.2 II(hold) I(h ld) IO ICEX Ioff 3 3.4 IOH = -3 mA IOH = -32 mA 2.5 3 IOH = -1 mA IOH = -1 mA 3.8 4.2 3.85 2 2.7 3.3 3.7 3.35 3 3.6 3.1 Control inputs VCC = 4 4.5 5V 0.25 0.55 VCC = 4 4.5 5V IOL = 8 mA IOL = 12 mA 0.4 0.8 VCC = 0 to 5.5 V, VCC = 2.1 V to 5.5 V, VI = VCC or GND VI = VCC or GND A or B ports VCC = 5.5 V, VCC = 4.5 V, VI = 0.8 V VI = 2 V A port VCC = 5.5 V, VO = 2.5 V VO = 2.5 V -50 -25 VO = 0 VO = 5.5 V -50 A or B ports B port VCC = 5 5.5 5V Outputs high VCC = 5.5 V, VCC = 0, 0.55 0.4 0.65 0.5 0.8 100 1 20 20 500 75 500 -75 -500 -75 -500 -110 -180 -50 -180 -55 -90 -25 -90 -110 -180 -50 -180 50 A 100 A 50 50 A VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X 50 50 A 1.5 6 10 32 18 32 1.5 0.7 1.5 VCC = 5 5.5 5V V, Outputs open VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND A or B ports mA 100 0.7 Control inputs A VI or VO 4.5 V VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X 10 Cio A 50 1.5 Ci V mV 1 75 Outputs disabled 1 VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 mA mA 3.5 3.5 pF 8 8 pF All typical values are at VCC = 5 V, TA = 25C. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This parameter is characterized but not production tested. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 6 0.3 A port low ICC V V Outputs high B port low UNIT 2.6 IOL = 24 mA IOL = 64 mA 100 IOZPU IOZPD ICC -1.2 3.4 Vhys II SN74ABTH162460 MIN TYP MAX 3 IOH = -3 mA IOH = -12 mA VOL B port SN54ABTH162460 MIN TYP MAX TEST CONDITIONS SN54ABTH162460, SN74ABTH162460 4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS241E - FEBRUARY 1993 - REVISED MAY 1997 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(see Figure 1) VCC = 5 V, TA = 25C fclock tw Clock frequency Pulse P l duration MIN MAX MIN MAX 0 160 0 160 0 160 3.8 3.8 4.5 4.5 4.5 LEAB1, 2, 3, or 4 high 2.8 2.8 2.8 LEBA high 2.8 2.8 2.8 3 3 3 A bus 2.5 2.5 2.5 CE_SEL0/1 3.2 3.2 3.2 CLKENAB 3.2 3.2 3.2 A bus 3.6 3.6 3.6 B bus 3.8 3.8 3.8 CLKENB 2.3 2.3 2.3 CLKENBA 2.5 2.5 2.5 LEB1, 2, 3, or 4 4.3 4.3 4.3 SEL0/1 4.5 4.5 4.5 B bus 3.2 3.2 3.2 B bus 4 4 4 LEB1, 2, 3, or 4 4.4 4.4 4.4 SEL0/1 4.3 4.3 4.3 A bus 0.5 0.5 0.5 CE_SEL0/1 1.1 1.1 1.1 CLKENAB 0.5 0.5 0.5 A bus 1.2 1.2 1.2 B bus 1.3 1.3 1.3 CLKENB 1 1 1 CLKENBA 1 1 1 Before CLKBA Before LEB1, 2, 3, or 4 Before LEBA After CLKAB After LEAB1, 2, 3, or 4 Hold time MAX 3.8 Before LEAB1, 2, 3, or 4 th MIN CLKBA high or low Before CLKAB Setup time SN74ABTH162460 CLKAB high or low LEB1, 2, 3, or 4 high tsu SN54ABTH162460 After CLKBA SEL0/1 After LEB1, 2, 3, or 4 After LEBA 0 0 0 B bus 1.5 1.5 1.5 B bus 0.4 0.4 0.4 SEL0/1 0.1 0.1 0.1 UNIT MHz ns ns ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SN54ABTH162460, SN74ABTH162460 4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS241E - FEBRUARY 1993 - REVISED MAY 1997 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25C MIN TYP SN54ABTH162460 MAX 160 B A OEA A OEA A A B OEB B OEB B OEB1 2, OEB1, 2 3, 3 4 B OEB1 2, 2 3, 3 4 OEB1, B CLKBA A CLKAB B LEBA A LEAB1 2 LEAB1, 2, 3 3, 4 B LEBA1 2 LEBA1, 2, 3 3, 4 A SEL A MAX 160 MIN 160 MHz 3.6 5.9 2 7.1 2 6.5 2 3.5 5.8 2 6.8 2 6.5 1.5 2.8 4.8 1.5 5.9 1.5 5.6 1.5 2.6 4.8 1.5 5.7 1.5 5.5 2 3.8 5.3 2 6 2 5.9 1.5 4 6.1 1.5 7 1.5 6.5 2 3.3 5.5 2 6.5 2 6.2 2 3.7 5.8 2 6.8 2 6.5 2 3.9 5.8 2 7.1 2 6.8 2 3.7 5.6 2 6.6 1.5 6.3 2 4 5.6 2 6.4 2 6.2 2 3.7 5.2 2 6.1 2 5.8 2 3.7 5.8 2 6.8 2 6.6 2 3.5 5.4 2 6.4 2 6.2 1.5 3.3 4.8 1.5 5.4 1.5 5.3 1.5 3.1 4.4 1.5 5.1 1.5 4.9 1.5 4.2 6.7 1.5 8.1 1.5 7.4 1.5 4.4 6.9 1.5 8.4 1.5 7.7 2 3.5 5.8 2 6.9 2 6.5 2 3.7 6 2 7 2 6.5 1.5 3 5.2 1.5 6.3 1.5 5.8 1.5 3 5 1.5 6.3 1.5 5.8 2 3.4 5.4 2 6.5 2 6.2 2 3.6 5.7 2 6.3 2 6.2 2 4 6.5 2 7.8 2 7.2 2 4 6.1 2 7.5 2 6.8 2 4.1 6.7 2 8.1 2 7.5 2 3.8 6.2 2 7.3 2 6.9 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 UNIT MAX 2 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 8 MIN SN74ABTH162460 ns ns ns ns ns ns ns ns ns ns ns ns ns ns SN54ABTH162460, SN74ABTH162460 4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS241E - FEBRUARY 1993 - REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION 500 From Output Under Test S1 7V Open GND CL = 50 pF (see Note A) 500 TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 3V th 3V 1.5 V Input 1.5 V Data Input 0V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 3V 3V 1.5 V Input Output Control 1.5 V 0V 1.5 V 1.5 V VOL tPLH tPHL VOH Output 1.5 V 1.5 V VOL 1.5 V 0V tPLZ Output Waveform 1 S1 at 7 V (see Note B) VOH Output 1.5 V tPZL tPHL tPLH 1.5 V Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 3.5 V VOL + 0.3 V VOL tPHZ tPZH 1.5 V VOH - 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 PACKAGE OPTION ADDENDUM www.ti.com 26-Aug-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 74ABTH162460DGGRE4 ACTIVE TSSOP DGG 56 TBD Call TI Call TI 74ABTH162460DGGRG4 ACTIVE TSSOP DGG 56 TBD Call TI Call TI 74ABTH162460DLG4 ACTIVE SSOP DL 56 TBD Call TI Call TI 74ABTH162460DLRG4 ACTIVE SSOP DL 56 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTSS003D - JANUARY 1995 - REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MSSO001C - JANUARY 1995 - REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0-8 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). 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