SN54ABTH162460, SN74ABTH162460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS241E – FEBRUAR Y 1993 – REVISED MAY 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
Family
D
B-Port Outputs Have Equivalent 25-Ω
Series Resistors, So No External Resistors
Are Required
D
State-of-the-Art
EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
D
High-Impedance State During Power Up
and Power Down
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center
Spacings
description
The ’ABTH162460 are 4-bit to 1-bit multiplexed
registered transceivers used in applications
where four separate data paths must be
multiplexed onto or demultiplexed from a single
data path. Typical applications include
multiplexing and/or demultiplexing of address and
data information in microprocessor or
bus-interface applications. This device also is
useful in memory-interleaving applications.
Five 4-bit I/O ports (1A–4A, 1B1–4, 2B1–4, 3B1–4, and 4B1–4) are available for address and/or data transfer .
The output-enable (OEB, OEB1–OEB4, and OEA) inputs control the bus-transceiver functions. These control
signals also allow 4-bit or 16-bit control, depending on the OEB level.
SN54ABTH162460 ...WD PACKAGE
SN74ABTH162460 . . . DL PACKAGE
(TOP VIEW)
1
2
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LEAB1
LEAB2
LEBA
GND
LEB1
LEB2
VCC
CLKBA
OEB
CLKAB
GND
1A
2A
CE_SEL0
CE_SEL1
3A
4A
GND
CLKENAB
CLKENB
CLKENBA
VCC
LEB3
LEB4
GND
OEA
LEAB3
LEAB4
OEB1
OEB2
SEL0
GND
1B1
1B2
VCC
1B3
1B4
2B1
GND
2B2
2B3
2B4
3B1
3B2
3B3
GND
3B4
4B1
4B2
VCC
4B3
4B4
GND
SEL1
OEB3
OEB4
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54ABTH162460, SN74ABTH162460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS241E – FEBRUAR Y 1993 – REVISED MAY 1997
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Address and/or data information can be stored using the internal storage latches/flip-flops. The latch-enable
(LEB1–LEB4, LEBA, and LEAB1–LEAB4) and clock/clock-enable (CLK/CLKEN) inputs are used to control data
storage. When either one of the latch-enable inputs is high, the latch is transparent (clock is a don’t care as long
as the latch enable is high). When the latch-enable input goes low (providing that the clock does not transit from
low to high), the data present at the inputs is latched and remains latched until the latch-enable input is returned
high. When the clock enable is low and the corresponding latch enable is low, data can be clocked on the
low-to-high transition of the clock. When either the clock enable or the corresponding latch enable is high, the
clock is a don’t care.
Four select (SEL0, SEL1, CE_SEL0, and CE_SEL1) pins are provided to multiplex data (A port), or to select
one of four clock enables (B port). This allows the user the flexibility of controlling one bit at a time.
The B-port outputs, which are designed to sink up to 12 mA, include equivalent 25-Ω series resistors to reduce
overshoot and undershoot.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However , to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABTH162460 is characterized for operation over the full military temperature range of –55°C to
125°C. The SN74ABTH162460 is characterized for operation from –40°C to 85°C.
Function Tables
A-TO-B OUTPUT ENABLE†
INPUTS OUTPUT
OEB OEBn Bn
H H Z
HLZ
LHZ
L L Active
†n = 1, 2, 3, 4
A-TO-B STORAGE
(assuming OEB = L, OEBn = L)‡
INPUTS OUTPUTS
CLKENAB CE_SEL1 CE_SEL0 CLKAB LEAB1 LEAB2 LEAB3 LEAB4 B1 B2 B3 B4
X X X H or L H L L L A A0A0A0
XX X H or L H H H L A AAA
0
LX X L LLLLA
0A0A0A0
LLL↑LLLLAA0A0A0
LLH↑LLLLA
0AA
0A0
LHL↑LLLLA
0A0AA
0
LHH↑LLLLA
0A0A0A
H X X ↑L L L L A0A0A0A0
‡This table does not cover all the latch-enable cases since they have similar results.
SN54ABTH162460, SN74ABTH162460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS241E – FEBRUAR Y 1993 – REVISED MAY 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables (Continued)
B-TO-A STORAGE
(before point P)
INPUTS
P
CLKENB CLKBA LEB1 LEB2 LEB3 LEB4 SEL1 SEL0
P
X X H L L L L L B1
XXLHLLLHB2
XX LLHLHLB3
XXLLLHHHB4
↑
L L B1
L
↑
L
L
L
L
LHB2
L
↑
L
L
L
L
HLB3
HHB4
L L B10†
L
L
L
L
L
L
LHB2
0†
L
L
L
L
L
L
HLB3
0†
H H B40†
†Output level before the indicated steady-state input conditions were established
B-TO-A STORAGE
(after point P)
INPUTS OUTPUT
CLKENBA CLKBA LEBA OEA BA
X X X H X Z
XXHLL L
XXHLH H
HXLLXA
0†
L↑LLL L
L↑LLH H
L L L L X A0†
†Output level before the indicated steady-state input conditions
were established
SN54ABTH162460, SN74ABTH162460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS241E – FEBRUAR Y 1993 – REVISED MAY 1997
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
LE
D
CLK
CE
LE
D
CLK
CE
CLK
CE
D
LE
CLK
CE
D
LE LE
CLK
CE
D
LE
CLK
CE
D
LE
CLK
CE
D
LE
CLK
CE
D
M
U
X
CE
CLK
D
LE
P
CE_SEL0
CE_SEL1
CLKENAB
1B1
1B2
1B3
1B4
CLKENAB Selector
One of Four
Channels
CLKAB
OEA
1A
OEB
OEB4
OEB3
OEB2
OEB1
CLKENBA
CLKBA
LEBA
SEL0
SEL1
CLKENB
LEB1
LEB2
LEB3
LEB4 LEAB4
LEAB3
LEAB2
LEAB1
24
23
6
5
31
54
3
8
21
10
26
12
48
49
51
52
19
15
14
9
29
30
55
56
1
2
27
28
20
SN54ABTH162460, SN74ABTH162460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS241E – FEBRUAR Y 1993 – REVISED MAY 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABTH162460 (A port) 96 mA. . . . . . . . . . . . . . . . . . . . . . . .
SN74ABTH162460 (A port) 128 mA. . . . . . . . . . . . . . . . . . . . . . . .
B port 30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DL package 74 °C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABTH162460 SN74ABTH162460
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 0 VCC 0 VCC V
IOH
High level out
p
ut current
A port –24 –32
mA
I
OH
High
-
le
v
el
o
u
tp
u
t
c
u
rrent
B port –12 –12
mA
IOL
Low level out
p
ut current
A port 48 64
mA
I
OL
Lo
w-
le
v
el
o
u
tp
u
t
c
u
rrent
B port 12 12
mA
∆t/∆vInput transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆VCC Power-up ramp rate 200 200 µs/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 3: Unused control pins must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABTH162460, SN74ABTH162460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS241E – FEBRUAR Y 1993 – REVISED MAY 1997
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ABTH162460 SN74ABTH162460
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 5 V, IOH = –3 mA 3 3.4 3 3.4
A port
VCC =45V
IOH = –3 mA 2.5 3
V
CC =
4
.
5
V
IOH = –32 mA 2 2.7
VOH VCC = 5 V, IOH = –1 mA 3.8 4.2 3.85 V
B
p
ort
IOH = –1 mA 3.3 3.7 3.35
B
port
VCC = 4.5 V IOH = –3 mA 3 3.6 3.1
IOH = –12 mA 2.6
A
p
ort
VCC =45V
IOL = 24 mA 0.25 0.55
A
port
V
CC =
4
.
5
V
IOL = 64 mA 0.3 0.55
OL
B
p
ort
VCC =45V
IOL = 8 mA 0.4 0.8 0.4 0.65
B
port
V
CC =
4
.
5
V
IOL = 12 mA 0.5 0.8
Vhys 100 100 mV
Control inputs VCC = 0 to 5.5 V, VI = VCC or GND ±1±1
IA or B ports VCC = 2.1 V to 5.5 V, VI = VCC or GND ±20 ±20 µ
AorB
p
orts
VCC = 5.5 V, VI = 0.8 V 75 500 75 500
I(hold)
A
or
B
ports
VCC = 4.5 V, VI = 2 V –75 –500 –75 –500 µ
A port VCC = 5.5 V, VO = 2.5 V –50 –110 –180 –50 –180
IO
B
p
ort
VCC =55V
VO = 2.5 V –25 –55 –90 –25 –90 mA
B
port
V
CC =
5
.
5
V
VO = 0 –50 –110 –180 –50 –180
ICEX Outputs high VCC = 5.5 V, VO = 5.5 V 50 50 µA
Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
IOZPU§VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 µA
IOZPD§VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 µA
Outputs high 1.5 0.7 1.5
A port low
VCC =55VOut
p
uts o
p
en
10 6 10
CC B port low
V
CC =
5
.
5
V
,
O
u
tp
u
ts
open
32 18 32
Outputs disabled 1.5 0.7 1.5
∆ICCVCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND 1 1 mA
CiControl inputs VI = 2.5 V or 0.5 V 3.5 3.5 pF
Cio A or B ports VO = 2.5 V or 0.5 V 8 8 pF
†All typical values are at VCC = 5 V, TA = 25°C.
‡Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
§This parameter is characterized but not production tested.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABTH162460, SN74ABTH162460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS241E – FEBRUAR Y 1993 – REVISED MAY 1997
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)(see Figure 1)
VCC = 5 V,
TA = 25°CSN54ABTH162460 SN74ABTH162460 UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency 0 160 0 160 0 160 MHz
CLKAB high or low 3.8 3.8 3.8
Pl
CLKBA high or low 4.5 4.5 4.5
twPulse
duration
LEAB1, 2, 3, or 4 high 2.8 2.8 2.8 ns
duration
LEBA high 2.8 2.8 2.8
LEB1, 2, 3, or 4 high 3 3 3
↑
A bus 2.5 2.5 2.5
Before CLKAB
↑
CE_SEL0/1 3.2 3.2 3.2
CLKENAB 3.2 3.2 3.2
Before LEAB1, 2, 3, or 4↓A bus 3.6 3.6 3.6
↑
B bus 3.8 3.8 3.8
↑
CLKENB 2.3 2.3 2.3
tsu Setup time Before CLKBA
↑
CLKENBA 2.5 2.5 2.5 ns
LEB1, 2, 3, or 4 4.3 4.3 4.3
SEL0/1 4.5 4.5 4.5
Before LEB1, 2, 3, or 4↓B bus 3.2 3.2 3.2
↓
B bus 4 4 4
Before LEBA
↓
LEB1, 2, 3, or 4 4.4 4.4 4.4
SEL0/1 4.3 4.3 4.3
↑
A bus 0.5 0.5 0.5
After CLKAB
↑
CE_SEL0/1 1.1 1.1 1.1
CLKENAB 0.5 0.5 0.5
After LEAB1, 2, 3, or 4↓A bus 1.2 1.2 1.2
↑
B bus 1.3 1.3 1.3
thHold time
After CLKBA↑
CLKENB 1 1 1 ns
After
CLKBA↑
CLKENBA 1 1 1
SEL0/1 0 0 0
After LEB1, 2, 3, or 4↓B bus 1.5 1.5 1.5
After LEBA↓
B bus 0.4 0.4 0.4
After
LEBA↓
SEL0/1 0.1 0.1 0.1
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABTH162460, SN74ABTH162460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS241E – FEBRUAR Y 1993 – REVISED MAY 1997
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°CSN54ABTH162460 SN74ABTH162460 UNIT
(INPUT)
(OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
fmax 160 160 160 MHz
tPLH
B
A
2 3.6 5.9 2 7.1 2 6.5
tPHL
B
A
2 3.5 5.8 2 6.8 2 6.5
tPZH
OEA
A
1.5 2.8 4.8 1.5 5.9 1.5 5.6
tPZL
OEA
A
1.5 2.6 4.8 1.5 5.7 1.5 5.5
tPHZ
OEA
A
2 3.8 5.3 2 6 2 5.9
tPLZ
OEA
A
1.5 4 6.1 1.5 7 1.5 6.5
tPLH
A
B
2 3.3 5.5 2 6.5 2 6.2
tPHL
A
B
2 3.7 5.8 2 6.8 2 6.5
tPZH
OEB
B
2 3.9 5.8 2 7.1 2 6.8
tPZL
OEB
B
2 3.7 5.6 2 6.6 1.5 6.3
tPHZ
OEB
B
2 4 5.6 2 6.4 2 6.2
tPLZ
OEB
B
2 3.7 5.2 2 6.1 2 5.8
tPZH
OEB1 2 3 4
B
2 3.7 5.8 2 6.8 2 6.6
tPZL
OEB1
,
2
,
3
,
4
B
2 3.5 5.4 2 6.4 2 6.2
tPHZ
OEB1 2 3 4
B
1.5 3.3 4.8 1.5 5.4 1.5 5.3
tPLZ
OEB1
,
2
,
3
,
4
B
1.5 3.1 4.4 1.5 5.1 1.5 4.9
tPLH
CLKBA
A
1.5 4.2 6.7 1.5 8.1 1.5 7.4
tPHL
CLKBA
A
1.5 4.4 6.9 1.5 8.4 1.5 7.7
tPLH
CLKAB
B
2 3.5 5.8 2 6.9 2 6.5
tPHL
CLKAB
B
2 3.7 6 2 7 2 6.5
tPLH
LEBA
A
1.5 3 5.2 1.5 6.3 1.5 5.8
tPHL
LEBA
A
1.5 3 5 1.5 6.3 1.5 5.8
tPLH
LEAB1234
B
2 3.4 5.4 2 6.5 2 6.2
tPHL
LEAB1
,
2
,
3
,
4
B
2 3.6 5.7 2 6.3 2 6.2
tPLH
LEBA1234
A
2 4 6.5 2 7.8 2 7.2
tPHL
LEBA1
,
2
,
3
,
4
A
2 4 6.1 2 7.5 2 6.8
tPLH
SEL
A
2 4.1 6.7 2 8.1 2 7.5
tPHL
SEL
A
2 3.8 6.2 2 7.3 2 6.9
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABTH162460, SN74ABTH162460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS241E – FEBRUAR Y 1993 – REVISED MAY 1997
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input 1.5 V 3 V
0 V
1.5 V 1.5 V
3 V
0 V
3 V
0 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V 1.5 V 3 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
W aveform 1
S1 at 7 V
(see Note B)
Output
W aveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
3.5 V
0 V
1.5 V VOL + 0.3 V
1.5 V VOH – 0.3 V
≈ 0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
74ABTH162460DGGRE4 ACTIVE TSSOP DGG 56 TBD Call TI Call TI
74ABTH162460DGGRG4 ACTIVE TSSOP DGG 56 TBD Call TI Call TI
74ABTH162460DLG4 ACTIVE SSOP DL 56 TBD Call TI Call TI
74ABTH162460DLRG4 ACTIVE SSOP DL 56 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 26-Aug-2009
Addendum-Page 1
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040048/E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
4828
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0°–ā8°
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
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