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FEATURES DESCRIPTION
APPLICATIONS
1
2
3
4
8
7
6
5
DIN
SCLK
CS
OUTA
VDD
OUTB
REF
AGND
D PACKAGE
(TOP VIEW)
TLV5637
SLAS224C – JUNE 1999 – REVISED JUNE 2007
2.7V TO 5.5V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTER WITHINTERNAL REFERENCE AND POWER DOWN
•Dual 10-Bit Voltage Output DAC
The TLV5637 is a dual 10-bit voltage output DACwith a flexible 3-wire serial interface. The serial•Programmable Internal Reference
interface allows glueless interface to TMS320 and•Programmable Settling Time:
SPI™, QSPI™, and Microwire™ serial ports. It is– 0.8 µs in Fast Mode
programmed with a 16-bit serial string containing 2– 2.8 µs in Slow Mode control and 10 data bits.•Compatible With TMS320 and SPI™ Serial
The resistor string output voltage is buffered by a x2Ports
gain rail-to-rail output buffer. The buffer features aClass AB output stage to improve stability and•Differential Nonlinearity <0.1LSB Typ
reduce settling time. The programmable settling time•Monotonic Over Temperature
of the DAC allows the designer to optimize speedversus power dissipation. With its on-chipprogrammable precision voltage reference, the•Digital Servo Control Loops
TLV5637 simplifies overall system design.•Digital Offset and Gain Adjustment
Because of its ability to source up to 1mA, the•Industrial Process Control
reference can also be used as a system reference.•Machine and Motion Control Devices
Implemented with a CMOS process, the device isdesigned for single supply operation from 2.7V to•Mass Storage Devices
5.5V. It is available in an 8-pin SOIC package toreduce board space in standard commercial andindustrial temperature ranges.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.SPI, QSPI are trademarks of Motorola, Inc.Microwire is a trademark of National Semiconductor Corporation.All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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Serial
Interface
and
Control
10-Bit
DAC B
Latch
SCLK
DIN
CS
OUTA
Power-On
Reset
x2
10
2-Bit
Control
Latch
Power
and Speed
Control
2
Voltage
Bandgap
PGA With
Output Enable
10-Bit
DAC A
Latch
10
REF AGND VDD
2
10 10
OUTB
x2
Buffer
10
TLV5637
SLAS224C – JUNE 1999 – REVISED JUNE 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
Terminal Functions
TERMINAL
I/O/P DESCRIPTIONNAME NO.
AGND 5 P GroundCS 3 I Chip select. Digital input active low, used to enable/disable inputsDIN 1 I Digital serial data inputOUTA 4 I DAC A analog voltage outputOUTB 7 O DAC B analog voltage outputREF 6 I/O Analog reference voltage input/outputSCLK 2 I Digital serial clock inputV
DD
8 P Positive power supply
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ABSOLUTE MAXIMUM RATINGS
(1)
PACKAGE/ORDERING INFORMATION
RECOMMENDED OPERATING CONDITIONS
TLV5637
SLAS224C – JUNE 1999 – REVISED JUNE 2007
Over operating free-air temperature range (unless otherwise noted).
UNIT
Supply voltage (V
DD
to AGND) 7VReference input voltage range –0.3 V to V
DD
+ 0.3VDigital input voltage range –0.3 V to V
DD
+ 0.3VOperating free-air temperature range, T
A
TLV5637C 0°C to +70°CTLV5637I –40°C to +85°CStorage temperature range, T
stg
–65°C to +150°CLead temperature 1,6mm (1/16 inch) from case for 10 seconds +260°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For the most current package and ordering information, see the Package Option Addendum at the end of thisdocument, or see the TI website at www.ti.com .
MIN NOM MAX UNIT
V
DD
= 5 V 4.5 5 5.5 VSupply voltage, V
DD
V
DD
= 3 V 2.7 3 3.3 VPower on threshold voltage, POR 0.55 2 VDV
DD
= 2.7 V 2High-level digital input voltage, V
IH
VDV
DD
= 5.5 V 2.4DV
DD
= 2.7 V 0.6Low-level digital input voltage, V
IL
VDV
DD
= 5.5 V 1Reference voltage, V
ref
to REF terminal V
DD
= 5 V (see
(1)
) AGND 2.048 V
DD
–1.5 VReference voltage, V
ref
to REF terminal V
DD
= 3 V (see
(1)
) AGND 1.024 V
DD
–1.5 VLoad resistance, R
L
2 k ΩLoad capacitance, C
L
100 pFClock frequency, f
CLK
20 MHzTLV5637C 0 +70Operating free-air temperature, T
A
°CTLV5637I –40 +85
(1) Due to the x2 output buffer, a reference input voltage ≥(V
DD
- 0.4V)/2 causes clipping of the transfer function. The output buffer of theinternal reference must be disabled, if an external reference is used.
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ELECTRICAL CHARACTERISTICS
TLV5637
SLAS224C – JUNE 1999 – REVISED JUNE 2007
Over recommended operating conditions (unless otherwise noted).
POWER SUPPLY
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Fast 4.2 7 mAV
DD
= 5V, Int. ref.
Slow 2 3.6 mAFast 3.7 6.3 mAV
DD
= 3V, Int. ref.
Slow 1.7 3.0 mANo load, All inputs = AGND orI
DD
Power supply current
V
DD
, DAC latch = 0x800
Fast 3.8 6.3 mAV
DD
= 5V, Ext. ref.
Slow 1.7 3.0 mAFast 3.4 5.7 mAV
DD
= 3V, Ext. ref.
Slow 1.4 2.6 mAPower-down supply current 0.01 10 µAZero scale, See
(1)
65PSRR Power supply rejection ratio dBFull scale, See
(2)
65
(1) Power supply rejection ratio at zero scale is measured by varying V
DD
and is given by: PSRR = 20 log [(E
ZS
(V
DD
max) –E
ZS
(V
DD
min))/V
DD
max](2) Power supply rejection ratio at full scale is measured by varying V
DD
and is given by: PSRR = 20 log [(E
G
(V
DD
max) –E
G
(V
DD
min))/V
DD
max]
STATIC DAC SPECIFICATIONS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 10 bitsINL Integral nonlinearity, end point adjusted See
(1)
±0.4 ±1 LSBDNL Differential nonlinearity See
(2)
±0.1 ±0.5 LSBE
ZS
Zero-scale error (offset error at zero scale) See
(3)
±24 mVE
ZS
TC Zero-scale-error temperature coefficient See
(4)
10 ppm/°C
% fullE
G
Gain error See
(5)
±0.6
scale VE
G
T
C
Gain error temperature coefficient See
(6)
10 ppm/°C
OUTPUT SPECIFICATIONS
V
O
Output voltage R
L
= 10k Ω0 V
DD
–0.4 V% fullOutput load regulation accuracy V
O
= 4.096V, 2.048V, R
L
= 2 k Ω±0.25
scale V
(1) The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output fromthe line between zero and full scale excluding the effects of zero code and full-scale errors. Tested from code 32 to 4095.(2) The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSBamplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant)as a change in the digital input code.(3) Zero-scale error is the deviation from zero voltage output when the digital input code is zero.(4) Zero-scale-error temperature coefficient is given by: E
ZS
TC = [E
ZS
(T
max
) – E
ZS
(T
min
)]/V
ref
×10
6
/(T
max
– T
min
).(5) Gain error is the deviation from the ideal output (2V
ref
– 1LSB) with an output load of 10 k excluding the effects of the zero-error.(6) Gain temperature coefficient is given by: E
G
TC = [E
G
(T
max
) – E
G
(T
min
)]/V
ref
×10
6
/(T
max
– T
min
).
4
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ELECTRICAL CHARACTERISTICS (Continued)
TLV5637
SLAS224C – JUNE 1999 – REVISED JUNE 2007
over recommended operating conditions (unless otherwise noted)
REFERENCE PIN CONFIGURED AS OUTPUT (REF)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
ref(OUTL)
Low reference voltage 1.003 1.024 1.045 VV
ref(OUTH)
High reference voltage V
DD
> 4.75V 2.027 2.048 2.069 VI
ref(source)
Output source current 1 mAI
ref(sink)
Output sink current 1 mALoad capacitance 100 pFPSRR Power supply rejection ratio 65 dB
REFERENCE PIN CONFIGURED AS INPUT (REF)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
DD
–1.V
I
Input voltage 0 V5R
I
Input resistance 10 M ΩC
I
Input capacitance 5 pFFast 1.3 MHzReference input bandwidth REF = 0.2V
PP
+ 1.024V dc
Slow 525 kHzReference feedthrough REF = 1V
PP
at 1 kHz + 1.024V dc, See
(1)
80 dB
(1) Reference feedthrough is measured at the DAC output with an input code = 0x000.
DIGITAL INPUTS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
IH
High-level digital input current V
I
= V
DD
1 µAI
IL
Low-level digital input current V
I
= 0V 1 µAC
i
Input capacitance 8 pF
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ELECTRICAL CHARACTAERISTICS (CONTINUED)
DIGITAL INPUT TIMING REQUIREMENTS
PARAMETER MEASUREMENT INFORMATION
twL
SCLK
CS
DIN D15 D14 D13 D12 D1 D0 XX
1
X2 3 4 5 15 16 X
twH
tsu(D) th(D)
tsu(CS-CK)
tsu(C16-CS)
TLV5637
SLAS224C – JUNE 1999 – REVISED JUNE 2007
over recommended operating conditions (unless otherwise noted)
ANALOG OUTPUT DYNAMIC PERFORMANCE
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Fast 0.8 2.4t
s(FS)
Output settling time, full scale R
L
= 10k Ω, C
L
= 100pF, See
(1)
µsSlow 2.8 5.5Fast 0.4 1.2t
s(CC)
Output settling time, code to code R
L
= 10k Ω, C
L
= 100pF, See
(2)
µsSlow 0.8 1.6Fast 12SR Slew rate R
L
= 10k Ω, C
L
= 100pF, See
(3)
V/µsSlow 1.8Glitch energy DIN = 0 to 1, f
CLK
= 100kHz, CS = V
DD
5 nV-SSNR Signal-to-noise ratio 53 56S/(N+D) Signal-to-noise + distortion 50 54f
s
= 480kSPS, f
out
= 1kHz, R
L
= 10k Ω, C
L
= 100pF dBTHD Total harmonic distortion 61 50SFDR Spurious free dynamic range 51 62
(1) Settling time is the time for the output signal to remain within ±0.5LSB of the final measured value for a digital input code change of0x020 to 0xFDF or 0xFDF to 0x020 respectively. Not tested, assured by design.(2) Settling time is the time for the output signal to remain within ± 0.5LSB of the final measured value for a digital input code change of onecount. Not tested, assured by design.(3) Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
MIN NOM MAX UNIT
t
su(CS-CK)
Setup time, CS low before first negative SCLK edge 10 nst
su(C16-CS)
Setup time, 16
th
negative SCLK edge (when D0 is sampled) before CS rising edge 10 nst
wH
SCLK pulse width high 25 nst
wL
SCLK pulse width low 25 nst
su(D)
Setup time, data ready before SCLK falling edge 10 nst
h(D)
Hold time, data held valid after SCLK falling edge 5 ns
Figure 1. Timing Diagram
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TYPICAL CHARACTERISTICS
Fast Mode
Slow Mode
VDD = 5 V
Vref = Int. 2 V
Input Code = 1023 (Both DACs)
2.5
2
1
0.5
–40–30 –20–10 0 10 20
– Supply Current – mA
3
4
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
4.5
30 40 50 90
3.5
1.5
60 70 80
IDD
TA – Free-Air Temperature – °C
Fast Mode
Slow Mode
VDD = 3 V
Vref = Int. 1 V
Input Code = 1023 (Both DACs)
2.5
2
1
0.5
–40–30 –20–10 0 10 20
– Supply Current – mA
3
4
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
4.5
30 40 50 90
3.5
1.5
60 70 80
IDD
TA – Free-Air Temperature – °C
1.4
1
0.4
00 10 20 30 40
– Power Down Supply Current – mA
2.2
2.4
POWER DOWN SUPPLY CURRENT
vs
TIME
2.6
50 60 70 80
2
1.8
1.6
1.2
0.8
0.6
0.2
t – T ime – µs
IDD
2.058
2.054
2.052
2.05 0 0.5 1 1.5 2 2.5 3
– Output Voltage – V
2.06
2.062
Source Current – mA
OUTPUT VOLTAGE
vs
LOAD CURRENT
2.064
3.5 4
2.056
VO
Fast Mode
Slow Mode
VDD = 3 V
Vref = Int. 1 V
Input Code = 4095
TLV5637
SLAS224C – JUNE 1999 – REVISED JUNE 2007
Figure 2. Figure 3.
Figure 4. Figure 5.
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1.5
1
0.5
00 0.5 1 1.5 2 2.5 3
2
2.5
3
3.5 4
– Output Voltage – V
Sink Current – mA
OUTPUT VOLTAGE
vs
LOAD CURRENT
VO
Fast Mode
Slow Mode
VDD = 3 V
Vref = Int. 1 V
Input Code = 0
3.5
2
1
00 0.5 1 1.5 2 2.5 3
4
4.5
5
3.5 4
3
2.5
1.5
0.5
– Output Voltage – V
Sink Current – mA
OUTPUT VOLTAGE
vs
LOAD CURRENT
VO
Fast Mode
Slow Mode
VDD = 5 V
Vref = Int. 2 V
Input Code = 0
–40
–50
–80
–100
100 1000
THD+N – Total Harmonic Distortion and Noise – dB
–20
–10
f – Frequency – Hz
TOTAL HARMONIC DISTORTION AND NOISE
vs
FREQUENCY
0
10000 100000
–30
–60
–70
–90
Fast Mode
Slow Mode
VDD = 5 V
Vref = 1 V dc + 1 V p/p Sinewave
Output Full Scale
TLV5637
SLAS224C – JUNE 1999 – REVISED JUNE 2007
TYPICAL CHARACTERISTICS (continued)
Figure 6. Figure 7.
Figure 8. Figure 9.
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–40
–50
–80
–100
100 1000
THD – Total Harmonic Distortion – dB
–20
–10
f – Frequency – Hz
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0
10000 100000
–30
–60
–70
–90 Fast Mode
Slow Mode
VDD = 5 V
Vref = 1 V dc + 1 V p/p Sinewave
Output Full Scale
–0.4
–1 0 256 512
INL – Integral Nonlinearity Error – LSB
0
0.6
Digital Code
INTEGRAL NONLINEARITY ERROR
1
768 1024
0.8
0.4
0.2
–0.2
–0.6
–0.8
–0.1
–0.2 0 256 512
DNL – Differential Nonlinearity Error – LSB
0
0.15
Digital Code
DIFFERENTIAL NONLINEARITY ERROR
0.2
768 1024
0.1
0.05
–0.05
–0.15
TLV5637
SLAS224C – JUNE 1999 – REVISED JUNE 2007
TYPICAL CHARACTERISTICS (continued)
Figure 10.
Figure 11.
Figure 12.
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APPLICATION INFORMATION
GENERAL FUNCTION
2 REF CODE
0x1000 [V]
SERIAL INTERFACE
TMS320
DSP FSX
CLKX
DX
TLV5637
SCLK
DIN
CS SPI I/O
SCK
MOSI
TLV5637
SCLK
DIN
CS Microwire
I/O
SK
SO
TLV5637
SCLK
DIN
CS
SERIAL CLOCK FREQUENCY AND UPDATE RATE
fsclkmax =1
(t +t )
whmin wlmin
=20MHz
f=
updatemax
1
16(t +t )
whmin wlmin
=1.25MHz
TLV5637
SLAS224C – JUNE 1999 – REVISED JUNE 2007
The TLV5637 is a dual 10-bit, single supply DAC, based on a resistor string architecture. It consists of a serialinterface, a speed and power-down control logic, a programmable internal reference, a resistor string, and arail-to-rail output buffer.
The output voltage (full scale determined by reference) is given by:
Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFFF. Becauseit is a 10-bit DAC, only D11 to D2 are used. D0 and D1 are ignored. A power-on reset initially puts the internallatches to a defined state (all bits zero).
A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the fallingedges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to thetarget latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.
Figure 13 shows examples of how to connect the TLV5637 to TMS320, SPI, and Microwire.
Figure 13. Three-Wire Interface
Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a fallingedge on the I/O pin connected to CS. If the word width is 8 bits (SPI and Microwire), two write operations mustbe performed to program the TLV5637. After the write operation(s), the holding registers or the control registerare updated automatically on the 16th positive clock edge.
The maximum serial clock frequency is given by:
The maximum update rate is:
Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of theTLV5637 has to be considered as well.
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DATA FORMAT
Register Select Bits
Data Bits: DAC A, DAC B and BUFFER
Data Bits: CONTROL
TLV5637
SLAS224C – JUNE 1999 – REVISED JUNE 2007
APPLICATION INFORMATION (continued)
The 16-bit data word for the TLV5637 consists of two parts:•Program bits (D15..D12)•New data (D11..D0)D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R1 SPD PWR R0 12 Data bits
SPD: Speed control bit 1 →fast mode 0 →slow modePWR: Power control bit 1 →power down 0 →normal operation
The following table lists the possible combination of the register select bits:
R1 R0 REGISTER
0 0 Write data to DAC B and BUFFER0 1 Write data to BUFFER1 0 Write data to DAC A and update DAC B with BUFFER content1 1 Write data to control register
The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected,then the 12 data bits determine the new DAC value:
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
New DAC Value 0 0
If control is selected, then D1, D0 of the 12 data bits are used to program the reference voltage:
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X X X X X X X X X X REF1 REF0X: don't care
REF1 and REF0 determine the reference source and, if internal reference is selected, the reference voltage.
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APPLICATION INFORMATION
REFERENCE BITS
EXAMPLES OF OPERATION:
TLV5637
SLAS224C – JUNE 1999 – REVISED JUNE 2007
REF1 REF0 REFERENCE
0 0 External0 1 1.024V1 0 2.048V1 1 External
CAUTION:
If external refeence voltage is applied to the REF pin, external reference MUSTbe selected.
1. Set DAC A output, select fast mode, select internal reference at 2.048V:a. Set reference voltage to 2.048V (CONTROL register)D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D01101000000000010
b. Write new DAC A value and update DAC A output:D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D01 1 0 0 New DAC A output value 0 0
The DAC A output is updated on the rising clock edge after D0 is sampled.
To output data consecutively using the same DAC configuration, it is not necessary to program theCONTROL register again.2. Set DAC B output, select fast mode, select external reference:a. Select external reference (CONTROL register):D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D01101000000000000
b. Write new DAC B value to BUFFER and update DAC B output:D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 0 New BUFFER content and DAC B output value 0 0
The DAC A output is updated on the rising clock edge after D0 is sampled.
To output data consecutively using the same DAC configuration, it is not necessary to program theCONTROL register again.1. Set DAC A value, set DAC B value, update both simultaneously, select slow mode, select internalreference at 1.024V:a. Set reference voltage to 1.024V (CONTROL register):D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D01001000000000001
b. Write data for DAC B to BUFFER:D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D00 0 0 1 New DAC B value 0 0
c. Write new DAC A value and update DAC A and B simultaneously:D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D01 0 0 0 New DAC A value 0 0
Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled.2. Set power down mode:D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0XX1XXXXXXXXXXXXXX = Don't care
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LINEARITY, OFFSET, AND GAIN ERROR USING SINGLE ENDED SUPPLIES
DAC Code
Output
Voltage
0 V
Negative
Offset
TLV5637
SLAS224C – JUNE 1999 – REVISED JUNE 2007
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative.With a positive offset, the output voltage changes on the first code change. With a negative offset, the outputvoltage may not change with the first code, depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negativesupply rail is ground, the output cannot drive below ground and clamps the output at 0V.
The output voltage then remains at zero until the input code value produces a sufficiently positive output voltageto overcome the negative offset voltage, resulting in the transfer function shown in Figure 14 .
Figure 14. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed thedotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) afteroffset and full scale are adjusted out or accounted for in some way. However, single supply operation does notallow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity ismeasured between full-scale code and the lowest code that produces a positive output voltage.
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DEFINITIONS OF SPECIFICATIONS AND TERMINOLOGY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Zero-Scale Error (E
ZS
)
GAIN ERROR (E
G
)
SIGNAL-TO-NOISE RATIO + DISTORTION (S/N+D)
SPURIOUS FREE DYNAMIC RANGE (SFDR)
TLV5637
SLAS224C – JUNE 1999 – REVISED JUNE 2007
The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximumdeviation of the output from the line between zero and full scale excluding the effects of zero code and full-scaleerrors.
The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between themeasured and ideal 1LSB amplitude change of any two adjacent codes. Monotonic means the output voltagechanges in the same direction (or remains constant) as a change in the digital input code.
Zero-scale error is defined as the deviation of the output from 0V at a digital input value of 0.
Gain error is the error in slope of the DAC transfer function.
S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral componentsbelow the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed indecibels.
Spurious free dynamic range is the difference between the rms value of the output signal and the rms value ofthe spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels.
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TLV5637
SLAS224C – JUNE 1999 – REVISED JUNE 2007
Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from B Revision (January 2004) to C Revision .............................................................................................. Page
•Changed —moved package option table from front page. ................................................................................................... 3
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PACKAGE OPTION ADDENDUM
www.ti.com 1-Oct-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV5637CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5637CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5637CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5637ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5637IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5637IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5637IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 1-Oct-2011
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV5637IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV5637IDR SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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