®
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
Rev. 03 — 2 July 2012 Product data sheet
1. General description
The ADC1006S055/070 are a family of Bipolar CMOS (BiCMOS) 10-bit Analog-to-Digital
Converters (ADC) optimized for a wide range of applications such as cellular
infrastructures, professional telecommunications, imaging, and digital radio. It converts
the analog input signal into 10-bit binary coded digital words at a maximum sampling rate
of 70 MHz. All static digital inputs (SH, CE and OTC) are Transistor-Transistor Logic (TTL)
and CMOS compatible and all outputs are CMOS compatible. A sine wave clock input
signal can also be used.
2. Features
10-bit resolution
Sampling rate up to 70 MHz
3 dB bandwidth of 245 MHz
5 V power supplies and 3.3 V output power supply
Binary or two’s complement CMOS outputs
In-range CMOS compatible output
TTL and CMOS compatible static digital inputs
TTL and CMOS compatible digital outputs
Differential AC or Positive Emitter-Coupled Logic (PECL) clock input; TTL compatible
Power dissipation 550 mW (typical)
Low analog input capacitance (typical 2 pF), no buffer amplifier required
Integrated sample-and-hold amplifier
Differential analog input
External amplitude range control
Voltage controlled regulator included
40 C to +85 C ambient temperature
3. Applications
High-speed analog-to-digital conversion for:
Cellular infrastructure
Professional telecommunication
Digital radio
Radar
Medical imaging
Fixed network
Cable modem
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 2 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
Barcode scanner
Cable Modem Termination System (CMTS)/Data Over Cable Service Interface
Specification (DOCSIS)
4. Quick reference data
Table 1. Quick reference data
VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and
V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted
together; Tamb =
40
C to +85
C; VI(IN)(p-p)
VI(INN)(p-p) = 1.9 V; VVREF = VCCA3
1.75 V;
VI(cm) = VCCA3
1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V,
Tamb = 25
C and CL = 10 pF; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VCCA analog supply voltage 4.75 5.0 5.25 V
VCCD digital supply voltage 4.75 5.0 5.25 V
VCCO output supply voltage 3.0 3.3 3.6 V
ICCA analog supply current -78 87 mA
ICCD digital supply current -27 30 mA
ICCO output supply current fclk = 20 MHz;
fi = 400 kHz
- 34mA
INL integral non-linearity fclk = 20 MHz;
fi = 400 kHz
-0.65 1.12 LSB
DNL differential non-linearity fclk = 20 MHz;
fi = 400 kHz
(no missing code
guaranteed)
-0.12 0.27 LSB
fclk(max) maximum clock
frequency
ADC1006S055H 55 --MHz
ADC1006S070H 70 --MHz
Ptot total power dissipation fclk = 55 MHz;
fi = 20 MHz
-550 660 mW
5. Ordering information
Table 2. Ordering information
Type number Package Sampling
frequency
(MHz)
Name Description Version
ADC1006S055H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10 10 1.75 mm
SOT307-2 55
ADC1006S070H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10 10 1.75 mm
SOT307-2 70
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 3 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
6. Block diagram
014aaa464
MSB
data
outputs
19
D9
D8
D7
D6
D5
D4
D3
43
42
39
1
5
11
12
VREF
FSREF
SH
DEC
CMADC
6 to 10, 13,
14, 16, 31, 32
n.c.
D2
21
22
23
24
25
26
27
28
29
30
D1
D0 LSB
V
CCO
33
IR
34
20
18
CMOS
OUTPUTS
LATCHES
ANALOG-TO-DIGITAL
CONVERTER
CLOCK DRIVER
15
V
CCD2
37
V
CCD1
41
V
CCA4
3
V
CCA3
2
V
CCA1
36
CLK
35
CLKN
CMOS
OUTPUT
OGND
OVERFLOW/
UNDERFLOW
LATCH
VREF
REFERENCE
CMADC
REFERENCE
CE
OTC
ADC1006S055/070
17
DGND2
38
DGND1
40
AGND4
4
AGND3
44
AGND1
INN
IN
AMP
s
sample -
and - hold
Fig 1. Block diagram
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 4 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
7. Pinning information
7.1 Pinning
ADC1006S055/070
CMADC VCCO
VCCA1 n.c.
VCCA3 n.c.
AGND3 D0
DEC D1
n.c. D2
n.c. D3
n.c. D4
n.c. D5
n.c. D6
VREF D7
FSREF AGND1
n.c. INN
n.c. IN
VCCD2 VCCA4
n.c. AGND4
DGND2 SH
OTC DGND1
CE VCCD1
IR CLK
D9 CLKN
D8 OGND
014aaa442
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
Fig 2. Pin configuration
7.2 Pin description
Table 3. Pin description
Symbol Pin Description
CMADC 1regulator output common mode ADC input
VCCA1 2analog supply voltage 1 (5 V)
VCCA3 3analog supply voltage 3 (5 V)
AGND3 4analog ground 3
DEC 5decoupling node
n.c. 6not connected
n.c. 7not connected
n.c. 8not connected
n.c. 9not connected
n.c. 10 not connected
VREF 11 reference voltage input
FSREF 12 full-scale reference output
n.c. 13 not connected
n.c. 14 not connected
VCCD2 15 digital supply voltage 2 (5 V)
n.c. 16 not connected
DGND2 17 digital ground 2
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 5 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
8. Limiting values
OTC 18 control input two’s complement output; active HIGH
CE 19 chip enable input (CMOS level; active LOW)
IR 20 in-range output
D9 21 data output; bit 9 (Most Significant Bit (MSB))
D8 22 data output; bit 8
D7 23 data output; bit 7
D6 24 data output; bit 6
D5 25 data output; bit 5
D4 26 data output; bit 4
D3 27 data output; bit 3
D2 28 data output; bit 2
D1 29 data output; bit 1
D0 30 data output; bit 0 (Least Significant Bit (LSB))
n.c. 31 not connected
n.c. 32 not connected
VCCO 33 output supply voltage (3.3 V)
OGND 34 output ground
CLKN 35 complementary clock input
CLK 36 clock input
VCCD1 37 digital supply voltage 1 (5 V)
DGND1 38 digital ground 1
SH 39 sample-and-hold enable input (CMOS level; active HIGH)
AGND4 40 analog ground 4
VCCA4 41 analog supply voltage 4 (5 V)
IN 42 analog input voltage
INN 43 complementary analog input voltage
AGND1 44 analog ground 1
Table 3. Pin description …continued
Symbol Pin Description
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VCCA analog supply voltage [1] 0.3 +7.0 V
VCCD digital supply voltage [1] 0.3 +7.0 V
VCCO output supply voltage [1] 0.3 +7.0 V
VCC supply voltage difference VCCA VCCD 1.0 +1.0 V
VCCD VCCO 1.0 +4.0 V
VCCA VCCO 1.0 +4.0 V
Vi(IN) input voltage on pin IN referenced to
AGND
0.3 VCCA V
Vi(INN) input voltage on pin INN 0.3 VCCA V
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 6 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
[1] The supply voltages VCCA, VCCD and VCCO may have any value between 0.3 V and +7.0 V provided that
the supply voltage differences VCC are respected.
9. Thermal characteristics
Table 5. Thermal characteristics
Symbol Parameter Condition Value Unit
Rth(j-a) thermal resistance from junction to
ambient
in free air 75 K/W
10. Characteristics
Vi(clk)(p-p) peak-to-peak clock input
voltage
differential clock
drive at pins
35 and 36
- VCCD V
IOoutput current -10 mA
Tstg storage temperature 55 +150 C
Tamb ambient temperature 40 +85 C
Tjjunction temperature -150 C
Table 4. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Table 6. Characteristics
VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V;
VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb =
40
C to +85
C;
VI(IN)(p-p)
VI(INN)(p-p) = 1.9 V; VVREF = VCCA3
1.75 V; VI(cm) = VCCA3
1.6 V; typical values measured at VCCA = VCCD = 5 V
and VCCO = 3.3 V, Tamb = 25
C and CL = 10 pF; unless otherwise specified.
Symbol Parameter Conditions Test[1] Min Typ Max Unit
Supplies
VCCA analog supply
voltage
4.75 5.0 5.25 V
VCCD digital supply
voltage
4.75 5.0 5.25 V
VCCO output supply
voltage
3.0 3.3 3.6 V
ICCA analog supply
current
I - 78 87 mA
ICCD digital supply
current
I - 27 30 mA
ICCO output supply
current
fclk = 20 MHz; fi = 400 kHz I - 3 4 mA
fclk = 55 MHz; fi = 20 MHz I - 9.5 12 mA
Ptot total power
dissipation
fclk = 55 MHz; fi = 20 MHz -550 660 mW
Inputs
CLK and CLKN (referenced to DGND)[2]
VIL LOW-level input
voltage
PECL mode; VCCD = 5 V I 3.19 -3.52 V
TTL mode C 0 - 0.8 V
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 7 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
VIH HIGH-level input
voltage
PECL mode; VCCD = 5 V I 3.83 -4.12 V
TTL mode C2.0 - VCCD V
IIL LOW-level input
current
VCLK or VCLKN = 3.19 V C 10 - - A
IIH HIGH-level input
current
VCLK or VCLKN = 3.83 V C - - 10 A
Vi(dif)(p-p) peak-to-peak
differential input
voltage
AC driving mode;
DC voltage level = 2.5 V
C 1 1.5 2.0 V
Riinput resistance fclk = 55 MHz D 2 - - k
Ciinput capacitance fclk = 55 MHz D - - 2 pF
OTC, SH and CE (referenced to DGND); see Table 7 and 8
VIL LOW-level input
voltage
I 0 - 0.8 V
VIH HIGH-level input
voltage
I2.0 - VCCD V
IIL LOW-level input
current
VIL = 0.8 V I 20 - - A
IIH HIGH-level input
current
VIH = 2.0 V I - - 20 A
IN and INN (referenced to AGND); see Table 7, VVREF = VCCA3 1.75 V
IIL LOW-level input
current
SH = HIGH C - 10 -A
IIH HIGH-level input
current
SH = HIGH C - 10 -A
Riinput resistance fi = 20 MHz D - 14 - M
Ciinput capacitance fi = 20 MHz D - 450 -fF
VI(cm) common-mode
input voltage
VI(IN) = VI(INN)
output code 512
C VCCA3 1.7 VCCA3 1.6 VCCA3 1.2 V
Voltage controlled regulator output CMADC
VO(cm) common-mode
output voltage
I - VCCA3 1.6 - V
Iload load current I - 1 2 mA
Voltage input Vref[3]
Vref reference voltage full-scale fixed voltage;
fi = 20 MHz; fclk = 55 MHz
C - VCCA3 1.75 - V
Iref reference current C - 0.3 10 A
Vi(dif)(p-p) peak-to-peak
differential input
voltage
VI(IN)(p-p) VI(INN)(p-p);
Vref = VCCA3 1.75 V;
VI(cm) = VCCA3 1.6 V
C - 1.9 - V
Table 6. Characteristics …continued
VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V;
VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb =
40
C to +85
C;
VI(IN)(p-p)
VI(INN)(p-p) = 1.9 V; VVREF = VCCA3
1.75 V; VI(cm) = VCCA3
1.6 V; typical values measured at VCCA = VCCD = 5 V
and VCCO = 3.3 V, Tamb = 25
C and CL = 10 pF; unless otherwise specified.
Symbol Parameter Conditions Test[1] Min Typ Max Unit
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 8 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
Voltage controlled regulator output FSREF
VO(ref) reference output
voltage
VI(IN)(p-p) VI(INN)(p-p) = 1.9 V I - VCCA3 1.75 - V
Digital outputs D9 to D0 and IR (referenced to OGND)
VOL LOW-level output
voltage
IOL = 2 mA I 0 - 0.5 V
VOH HIGH-level output
voltage
IOH = 0.4 mA I VCCO 0.5 - VCCO V
Iooutput current 3-state output level between
0.5 V and VCCO
I20 -+20 A
Switching characteristics; Clock frequency fclk; see Figure 3
fclk(min) minimum clock
frequency
SH = HIGH C - - 7 MHz
fclk(max) maximum clock
frequency
ADC1006S055H I55 - - MHz
ADC1006S070H C70 - - MHz
tw(clk)H HIGH clock pulse
width
fi = 20 MHz C6.8 - - ns
tw(clk)L LOW clock pulse
width
fi = 20 MHz C6.8 - - ns
Analog signal processing; 50 % clock duty factor; VI(IN)(p-p) VI(INN)(p-p) = 1.9 V; VVREF = VCCA3 1.75 V; see Table 7
Linearity
INL integral
non-linearity
fclk = 20 MHz; fi = 400 kHz I - 0.65 1.12 LSB
DNL differential
non-linearity
fclk = 20 MHz; fi = 400 kHz
(no missing code
guaranteed)
I - 0.12 0.27 LSB
Eoffset offset error VCCA = VCCD = 5 V;
VCCO = 3.3 V; Tamb = 25 C;
output code = 512
C25 +5 +25 mV
EGgain error spread from
device to device;
VCCA = VCCD = 5 V;
VCCO = 3.3 V; Tamb = 25 C
C7 - +7 %FS
Bandwidth (fclk = 55 MHz)[4]
Bbandwidth 3 dB; full-scale input C220 245 -MHz
Table 6. Characteristics …continued
VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V;
VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb =
40
C to +85
C;
VI(IN)(p-p)
VI(INN)(p-p) = 1.9 V; VVREF = VCCA3
1.75 V; VI(cm) = VCCA3
1.6 V; typical values measured at VCCA = VCCD = 5 V
and VCCO = 3.3 V, Tamb = 25
C and CL = 10 pF; unless otherwise specified.
Symbol Parameter Conditions Test[1] Min Typ Max Unit
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 9 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
Harmonics
2H second harmonic
level
ADC1006S055H (fclk = 55 MHz)
fi = 4.43 MHz C - 77 -dBFS
fi = 10 MHz C - 76 -dBFS
fi = 15 MHz C - 75 -dBFS
fi = 20 MHz I - 73 -dBFS
ADC1006S070H (fclk = 70 MHz)
fi = 4.43 MHz C - 75 -dBFS
fi = 10 MHz C - 74 -dBFS
fi = 15 MHz C - 70 -dBFS
3H third harmonic level ADC1006S055H (fclk = 55 MHz)
fi = 4.43 MHz C - 73 -dBFS
fi = 10 MHz C - 73 -dBFS
fi = 15 MHz C - 73 -dBFS
fi = 20 MHz I - 72 -dBFS
ADC1006S070H (fclk = 70 MHz)
fi = 4.43 MHz C - 73 -dBFS
fi = 10 MHz C - 73 -dBFS
fi = 15 MHz C - 72 -dBFS
Total harmonic distortion[5]
THD total harmonic
distortion
ADC1006S055H (fclk = 55 MHz)
fi = 4.43 MHz C - 68 -dBFS
fi = 10 MHz C - 68 -dBFS
fi = 15 MHz C - 68 -dBFS
fi = 20 MHz I - 68 -dBFS
ADC1006S070H (fclk = 70 MHz)
fi = 4.43 MHz C - 67 -dBFS
fi = 10 MHz C - 67 -dBFS
fi = 15 MHz C - 66 -dBFS
Thermal noise
Nth(RMS) RMS thermal noise shorted input; SH = HIGH;
fclk = 55 MHz
C - 0.12 -LSB
Table 6. Characteristics …continued
VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V;
VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb =
40
C to +85
C;
VI(IN)(p-p)
VI(INN)(p-p) = 1.9 V; VVREF = VCCA3
1.75 V; VI(cm) = VCCA3
1.6 V; typical values measured at VCCA = VCCD = 5 V
and VCCO = 3.3 V, Tamb = 25
C and CL = 10 pF; unless otherwise specified.
Symbol Parameter Conditions Test[1] Min Typ Max Unit
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 10 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
Signal-to-noise ratio[6]
S/N signal-to-noise ratio ADC1006S055H (fclk = 55 MHz)
fi = 4.43 MHz C - 60 -dBFS
fi = 10 MHz C - 60 -dBFS
fi = 15 MHz C - 60 -dBFS
fi = 20 MHz I - 59.5 -dBFS
ADC1006S070H (fclk = 70 MHz)
fi = 4.43 MHz C - 60 -dBFS
fi = 10 MHz C - 60 -dBFS
fi = 15 MHz C - 59 -dBFS
Spurious free dynamic range; see Figure 7, 13 and 14
SFDR spurious free
dynamic range
ADC1006S055H (fclk = 55 MHz)
fi = 4.43 MHz C - 71 -dBFS
fi = 10 MHz C - 70 -dBFS
fi = 15 MHz C - 70 -dBFS
fi = 20 MHz I - 70 -dBFS
ADC1006S070H (fclk = 70 MHz)
fi = 4.43 MHz C - 70 -dBFS
fi = 10 MHz C - 69 -dBFS
fi = 15 MHz C - 68 -dBFS
Effective number of bits[7]
ENOB effective number of
bits
ADC1006S055H (fclk = 55 MHz)
fi = 4.43 MHz C - 9.5 -bit
fi = 10 MHz C - 9.5 -bit
fi = 15 MHz C - 9.5 -bit
fi = 20 MHz I - 9.5 -bit
ADC1006S070H (fclk = 70 MHz)
fi = 4.43 MHz C - 9.5 -bit
fi = 10 MHz C - 9.5 -bit
fi = 15 MHz C - 9.4 -bit
Intermodulation; (fclk = 55 MHz; fi = 20 MHz)[8]
IM intermodulation
suppression
C - 69 -dBFS
IMD3 third-order
intermodulation
distortion
C - 79 -dBFS
Bit error rate (fclk = 55 MHz)
BER bit error rate fi = 20 MHz; VI = 16 LSB at
code 512
C - 1014 -times/
sample
Table 6. Characteristics …continued
VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V;
VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb =
40
C to +85
C;
VI(IN)(p-p)
VI(INN)(p-p) = 1.9 V; VVREF = VCCA3
1.75 V; VI(cm) = VCCA3
1.6 V; typical values measured at VCCA = VCCD = 5 V
and VCCO = 3.3 V, Tamb = 25
C and CL = 10 pF; unless otherwise specified.
Symbol Parameter Conditions Test[1] Min Typ Max Unit
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 11 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
[1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.
[2] The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation:
a) PECL mode 1: (DC level vary 1 : 1 with VCCD) CLK and CLKN inputs are at differential PECL levels.
b) PECL mode 2: (DC level vary 1 : 1 with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor.
c) PECL mode 3: (DC level vary 1 : 1 with VCCD) CLKN input is at PECL level and sampling is taken on the rising edge of the clock
input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.
d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level
of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLKN input with the same signal, sampling
takes place at the rising edge of the clock signal. It is recommended to decouple the CLKN or CLK input to DGND via a 100 nF
capacitor.
e) TTL mode 1: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that case CLKN pin has
to be connected to the ground.
[3] The ADC input range can be adjusted with an external reference connected to VREF pin. This voltage has to be referenced to VCCA;
see Figure 12.
[4] The 3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave.
[5] Total Harmonic Distortion (THD) is obtained with the addition of the first five harmonics:
THD 20 log
2H

23H

24H

2
26H

2
++++
a1H

2
--------------------------------------------------------------------------------------------------------------------------------------
=
where 1H is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input; see Figure 6.
[6] Signal-to-noise ratio (S/N) takes into account all harmonics above five and noise up to Nyquist frequency; see Figure 8.
[7] Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all harmonics and noise up
to half of the clock frequency (Nyquist frequency). Conversion to SIgnal-to_Noise_Distortion ratio (SINAD) is given by
SINAD = ENOB 6.02 + 1.76 dB; see Figure 5.
[8] Intermodulation measured relative to either tone with analog input frequencies of 20 MHz and 20.1 MHz. The two input signals have the
same amplitude and the total amplitude of both signals provides full-scale to the converter (6 dB below full scale for each input signal).
IMD3 is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product.
[9] Output data acquisition: the output data is available after the maximum delay of td(o); see Figure 3.
Timing (CL = 10 pF)[9]
td(s) sampling delay time C - 0.25 1ns
th(o) output hold time C 4 6.4 -ns
td(o) output delay time C - 9.0 13 ns
3-state output delay times; see Figure 4
tdZH float to active HIGH
delay time
C - 5.1 9.0 ns
tdZL float to active LOW
delay time
C - 7.0 11 ns
tdHZ active HIGH to float
delay time
C - 9.7 14 ns
tdLZ active LOW to float
delay time
C - 9.5 13 ns
Table 6. Characteristics …continued
VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V;
VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb =
40
C to +85
C;
VI(IN)(p-p)
VI(INN)(p-p) = 1.9 V; VVREF = VCCA3
1.75 V; VI(cm) = VCCA3
1.6 V; typical values measured at VCCA = VCCD = 5 V
and VCCO = 3.3 V, Tamb = 25
C and CL = 10 pF; unless otherwise specified.
Symbol Parameter Conditions Test[1] Min Typ Max Unit
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 12 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
11. Additional information relating to Table 6
Table 7. Output coding with differential inputs (typical values to AGND);
Vi(IN)(p-p) Vi(INN)(p-p) = 1.9 V, VVREF = VCCA3 1.75 V
Code Vi(a)(p-p)
(V)
Vi(a)(p-p)
(V)
IR Binary outputs
D9 to D0
Two’s complement
outputs[1] D9 to D0
Underflow < 3.125 > 4.075 000 0000 0000 10 0000 0000
03.125 4.075 100 0000 0000 10 0000 0000
1 - - 1 00 0000 0001 10 0000 0001
- -
511 3.6 3.6 101 1111 1111 11 1111 1111
- -
1022 - - 1 11 1111 1110 01 1111 1110
1023 4.075 3.125 111 1111 1111 01 1111 1111
Overflow > 4.075 < 3.125 011 1111 1111 01 1111 1111
[1] Two’s complement reference is inverted MSB.
Table 8. Mode selection
OTC CE D0 to D9 and IR
0 0 binary; active
1 0 two’s complement; active
X[1] 1high-impedance
[1] X = don’t care.
Table 9. Sample-and-hold selection
SH Sample-and-hold
1active
0inactive; tracking mode
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 13 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
sample N + 1sample N
CLK
014aaa465
sample N + 2
sample N + 1sample N sample N + 2
tw(clk)L
tw(clk)H
DATA
D0 T O D9 HIGH
50 %
LOW
HIGH
50 %
LOW
IN
td(s) th(o)
td(o)
DATA
N − 2 DATA
N − 1 DATA
NDATA
N + 1
Fig 3. Timing diagram
014aaa443
50 %
50 %
HIGH
LOW
tdZH
tdHZ
50 %
HIGH
LOW
tdZL
tdLZ
10 %
90 %
output
data
VCCD
output
data
3.3 kΩ
15 pF
S1
VCCO
ADC1006S
070
CE
TEST
tdLZ
tdZL
tdHZ
S1
VCCO
VCCO
OGND
OGND
tdZH
0 V
CE
(1) frequency on pin CE = 100 kHz.
Fig 4. Timing diagram and test conditions of 3-state output delay time
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 14 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
fi (MHz)
0252010 155
014aaa444
9.50
9.40
9.60
9.70
ENOB
(bit)
9.30
(1)
(2)
fi (MHz)
0252010 155
014aaa445
−67
−69
−65
−63
THD
(dB)
−71
(1)
(2)
(1) 55 MHz.
(2) 70 MHz.
(1) 55 MHz.
(2) 70 MHz.
Fig 5. Effective Number Of Bits (ENOB) as a function
of input frequency (sample device)
Fig 6. Total Harmonic Distortion (THD) as a function
of input frequency (sample device)
fi (MHz)
0252010 155
014aaa446
70
71
69
72
73
SFDR
(dB)
68
(1)
(2)
fi (MHz)
0252010 155
014aaa447
59.4
59.6
59.2
59.8
60.0
S/N
(dB)
59.0
(1)
(2)
(1) 55 MHz.
(2) 70 MHz.
(1) 55 MHz.
(2) 70 MHz.
Fig 7. Spurious Free Dynamic Range (SFDR) as a
function of input frequency (sample device)
Fig 8. Signal-to-Noise Ratio (S/N) as a function of
input frequency (sample device)
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 15 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
014aaa448
−80
−120
−40
0
power
spectrum
(dB)
−160
fi (MHz)
0 3020105 2515
Fig 9. Single-tone; fi = 20 MHz; fclk = 55 MHz
014aaa449
−80
−120
−40
0
power
spectrum
(dB)
−160
fi (MHz)
0 3020105 2515
Fig 10. Two-tone; fi 1 = 20 MHz; fi 2 = 20.1 MHz; fclk = 55 MHz
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 16 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
output code
0 1024768512256
014aaa450
−0.60
0.60
0.20
−0.20
1.00
output
range
(INL)
Fig 11. Integral Non-Linearity (INL)
output code
0 1024768512256
014aaa451
0
0.10
−0.10
0.20
0.30
DNL
(LSB)
−0.20
Fig 12. Differential Non-Linearity (DNL)
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 17 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
Input amplitude (dBFS)
−60 0−20 −10−30−50 −40
014aaa452
40
60
80
SFDR
(dBFS)
20
(1)
(2)
(3)
(1) fi = 4.43 MHz.
(2) fi = 20 MHz.
(3) SFDR = 80 dB.
Fig 13. SFDR as a function of input amplitude; Vi(IN)(p-p) Vi(INN)(p-p) = 1.9 V; fclk = 40 MHz
Input amplitude (dBFS)
−60 0−20 −10−30−50 −40
014aaa453
40
60
80
SFDR
(dBFS)
20
(1)
(2)
(3)
(1) fi = 4.43 MHz.
(2) fi = 20 MHz.
(3) SFDR = 80 dB.
Fig 14. SFDR as a function of input amplitude; Vi(IN)(p-p) Vi(INN)(p-p) = 1.9 V; fclk = 55 MHz
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 18 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
VCCA − VVREF (V)
1.3 2.22.0 2.11.81.7 1.91.5 1.61.4 014aaa455
55
45
65
75
50
40
60
70
(dB)
35
8.0
7.0
9.0
10.0
7.5
6.5
8.5
9.5
(bit)
6.0
(1)
(2)
(3)
(1) SFDR.
(2) ENOB.
(3) S/N.
Fig 15. SFDR, ENOB and S/N as a function of
VCCA VVREF; fclk = 55 MHz; fi = 20 MHz
Fig 16. ADC full-scale; VI(IN)(p-p) VI(INN)(p-p) as a
function of VCCA VVREF
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 19 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
12. Application information
12.1 Application diagrams
014aaa457
100 Ω100 Ω
100 nF100 nF 5 V
100 nF
100 nF
100 nF
220 nF
10 nF
5 V
IN
1 : 1
INN
5 V
100 nF
5 V
5 V SH
mode
CLK
n.c.
n.c.
D0 (LSB)
ADC1006S055/070
D1
D2
D3
D4
D5
D6
n.c.
n.c.
n.c.
n.c.
n.c.
D7
D8
chip select input
IRn.c.n.c.
n.c.
output format select
D9
(MSB)
VREF
343536 33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
3738394041424344
2221201918171615141312
The analog, digital and output supplies should be separated and decoupled.
Fig 17. Application diagram
014aaa458
270 Ω270 Ω
ADC1006S
055/070
CLKN
CLK
TTL
input
MC100
ELT20
PECL
D
Fig 18. Application diagram for differential clock input PECL compatible using a TTL to
PECL translator
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 20 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
014aaa459
ADC1006S
055/070
CLKN
CLK
TTL
input
Fig 19. Application diagram for TTL single-ended clock
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 21 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
12.2 Demonstration board
IC2
ADC1006S055/070
014aaa460
34
35
36
37
38
39
40
41
42
43
44
OGND
CLKN
CLK
VCCD1
DGND1
SH
AGND4
VCCA4
IN
INN
AGND1
VCCA
VCCD
VCCA
VCC
VCCO
VCC
22
21
20
19
18
17
16
15
14
13
12
CMADC
VCCA1
VCC
VCCA
VCC
VCCA
VCC
VCCO
VCCO
VCCA3
AGDN3
DEC
n.c.
n.c.
n.c.
n.c.
n.c.
VREF
33 32 31 30 29 28 27 26 25 24 23
1234567891011
VCCO
n.c
n.c
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
IR
CE
OTC
DGND2
n.c.
VCCD2
n.c.
n.c.
FSREF
MC78MO5CDT
IN OUT
ICI
GND
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
24 B8
23
B11
R4
50 Ω
R3
100 Ω
FL3
FL1
FL2
C13
100 nF
C6
330 nF
C15
10 nF
R1
100 Ω
5 kΩ
FL4
C8
10 nF
C17
10 nF
C19
C1
22 μF
(20 V)
C2
4.7 μF
(16 V)
C3
1 μF
T1
TP2
TM3
R5
4.7 kΩ
C4
1 μF
R2
62 Ω
R6
2.4 KΩ
1 kΩ
S2
S4
S3
B7
B5
1.2 kΩ
C11
100 nF
C18
10 nF C5
330 nF
C12
100 nF
C16
10 nF C10
100 nF
PMBT
2222A
D2
BZV55C3V6
C14
100 nF C7
330 nF
S1
S5
R9
100 Ω
J2
J3
J1
J4
J4
1
2
BYD17G
D3
CLK2
CLK1 CLK1
IN
C9
220 nF
P1
MCLT1_6T_KK81
TR1 CMADC
12 V13
GND
R8
750 Ω
D1
LGT679
330 nF
P2 R7
C8 is close to TR1 pin.
Fig 20. Demonstration board schematic
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 22 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
014aaa466
J4
C4 C5
D2
TP2
P2
C3
D3
R2 R5
R7 R4
R6
C11
C10 C14
P1
R1
R3
J3
J2
J1
1
1
1
1
1
112 23
34
C12
S2
S5
S1
S3 S4
B7
B4
B5 B8
B11
C7
C9
R9
FL4
FL2
T1
TM3
TM2
TM1
C2
C1
IC1
IC2
TR1
R8
D1
12
Fig 21. Component placement (top side)
014aaa467
C6
FL1
FL3
C8
C13
C17
C15
C19 C16
C18
Fig 22. Component placement (underside)
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 23 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
014aaa461
1
Fig 23. Printed-circuit board layout (top layer)
014aaa462
2
Fig 24. Printed-circuit board layout (ground layer)
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 24 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
014aaa463
3
Fig 25. Printed-circuit board layout (power plane)
12.3 Alternative parts
The following alternative parts are also available:
Table 10. Alternative parts
Type number Description Sampling frequency
ADC1206S040 Single 12 bits ADC [1] 40 MHz
ADC1206S055 Single 12 bits ADC [1] 55 MHz
ADC1206S070 Single 12 bits ADC [1] 70 MHz
[1] Pin to pin compatible
12.4 Recommended companion chip
The recommended companion chip is the TDA9901 wideband differential digital controlled
variable gain amplifier.
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 25 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
13. Support information
13.1 Definitions
13.1.1 Non-linearities
13.1.1.1 Integral Non-Linearity (INL)
It is defined as the deviation of the transfer function from a best fit straight line (linear
regression computation). The INL of the code i is obtained from the equation:
INL i VIi VIideal–
S
------------------------------------------
=
(1)
where
i02
n1–=
and
S = slope of the ideal straight line = code width; i = code value.
13.1.1.2 Differential Non-Linearity (DNL)
It is the deviation in code width from the value of 1 LSB.
DNL i VIi1+VIi–
S
--------------------------------------- 1–=
(2)
where
i02
n2–=
13.1.2 Dynamic parameters (single tone)
Figure 26 shows the spectrum of a full-scale input sine wave with frequency ft, conforming
to coherent sampling (ft / fs = M / N, where M is the number of cycles and N is number of
samples, M and N being relatively prime), and digitized by the ADC under test.
a
2
a
3
a
k
a
1
SFDR
014aaa440
f
s
/2
measured output range (MHz)
magnitude
Fig 26. Spectrum of full-scale input sine wave with frequency ft
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 26 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
Remark: In the following equations, Pnoise is the power of the terms which include the
effects of random noise, non-linearities, sampling time errors, and ‘quantization noise’.
13.1.2.1 Signal-to-Noise And Distortion (SINAD)
The ratio of the output signal power to the noise and distortion power for a given sample
rate and input frequency, excluding the DC component:
SINAD dB 10 Psignal
Pnoise distortion+
------------------------------------------
log=
(3)
13.1.2.2 Effective Number Of Bits (ENOB)
It is derived from SINAD and gives the theoretical resolution an ideal ADC would require
to obtain the same SINAD measured on the real ADC. A good approximation gives:
ENOB SINAD dB1.76–6.02=
13.1.2.3 Total Harmonic Distortion (THD)
The ratio of the power of the harmonics to the power of the fundamental. For k-1
harmonics the THD is:
THD dB10 = Pharmonics
Psignal
---------------------------
log
(4)
where
Pharmonics 2
23
2k
2
++=
and
Psignal 1
2
=
The value of k is usually 6 (i.e. calculation of THD is done on the first 5 harmonics).
13.1.2.4 Signal-to-Noise ratio (S/N)
The ratio of the output signal power to the noise power, excluding the harmonics and the
DC component.
S/N dB 10 Psignal
Pnoise
-----------------
log=
(5)
13.1.2.5 Spurious Free Dynamic Range (SFDR)
The number SFDR specifies available signal range as the spectral distance between the
amplitude of the fundamental and the amplitude of the largest spurious (harmonic and
non-harmonic), excluding DC component.
SFDR dB 20 1
max s
------------------
log=
(6)
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 27 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
13.1.3 Intermodulation distortion
13.1.3.1 Spectral analysis (dual-tone)
IMD3
014aaa441
fs/2
measured output range (MHz)
magnitude
Fig 27. Spectral analysis (dual-tone)
From a dual-tone input sinusoid (ft1 and ft2, these frequencies being chosen according to
the coherence criterion), the intermodulation distortion products IMD2 and IMD3
(respectively, 2nd and 3rd-order components) are defined, as follows.
13.1.3.2 IMD2 (IMD3)
The ratio of the RMS value of either tone to the RMS value of the worst second (third)
order intermodulation product.
The total IMD is given by:
IMD dB 10 Pintermod
Psignal
-----------------------
log=
where,
Pintermod aim
2ft1 ft2
–aim
2ft1 ft2
+aim
2ft1 2ft2
–aim
2ft1 2ft2
+
aim
22ft1 ft2
–aim
22ft1 ft2
+++
++–=
Psignal a2ft1
a2ft2
+=
and
aim
2ft

is the power in the intermodulation component at frequency ft.
13.1.4 Noise Power Ratio (NPR)
When using a notch-filtered broadband white-noise generator as the input to the ADC
under test, the NPR is defined as the ratio of the average out-of-notch to the in-notch
power spectral density magnitudes for the FFT spectrum of the ADC output sample set.
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 28 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
14. Package outline
UNIT A1A2A3bpcE
(1) eH
ELL
pZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.25
0.05 1.85
1.65 0.25 0.4
0.2 0.25
0.14 10.1
9.9 0.8 1.3
12.9
12.3 1.2
0.8 10
0
o
o
0.15 0.10.15
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.95
0.55
SOT307-2 97-08-01
03-02-25
D(1) (1)(1)
10.1
9.9
HD
12.9
12.3
E
Z
1.2
0.8
D
e
E
B
11
c
E
H
D
ZD
A
ZE
e
vMA
X
1
44
34 33 23 22
12
y
θ
A1
A
Lp
detail X
L
(A )
3
A2
pin 1 index
D
HvMB
bp
bp
wM
wM
0 2.5 5 mm
scale
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2
A
max.
2.1
Fig 28. Package outline SOT307-2 (QFP44)
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 29 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
15. Revision history
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
ADC1006S055_070_3 20120702 Product data sheet -ADC1006S055_070_2
ADC1006S055_070_2 20080812 Product data sheet -ADC1006S055_070_1
Modifications: •Corrections made to titles in Figure 13 and 14.
•Corrections made to note in Figure 4.
ADC1006S055_070_1 20080611 Product data sheet - -
16. Contact information
For more information or sales office addresses, please visit: http://www.idt.com
ADC1006S055_070_3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 30 of 30
Integrated Device Technology
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
5 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Thermal characteristics . . . . . . . . . . . . . . . . . . 6
10 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 6
11 Additional information relating to Table 6 . . . 12
12 Application information. . . . . . . . . . . . . . . . . . 19
12.1 Application diagrams . . . . . . . . . . . . . . . . . . . 19
12.2 Demonstration board . . . . . . . . . . . . . . . . . . . 21
12.3 Alternative parts . . . . . . . . . . . . . . . . . . . . . . . 24
12.4 Recommended companion chip . . . . . . . . . . . 24
13 Support information . . . . . . . . . . . . . . . . . . . . 25
13.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
13.1.1 Non-linearities . . . . . . . . . . . . . . . . . . . . . . . . 25
13.1.1.1 Integral Non-Linearity (INL) . . . . . . . . . . . . . . 25
13.1.1.2 Differential Non-Linearity (DNL). . . . . . . . . . . 25
13.1.2 Dynamic parameters (single tone) . . . . . . . . . 25
13.1.2.1 Signal-to-Noise And Distortion (SINAD) . . . . 26
13.1.2.2 Effective Number Of Bits (ENOB) . . . . . . . . . 26
13.1.2.3 Total Harmonic Distortion (THD) . . . . . . . . . . 26
13.1.2.4 Signal-to-Noise ratio (S/N) . . . . . . . . . . . . . . . 26
13.1.2.5 Spurious Free Dynamic Range (SFDR). . . . . 26
13.1.3 Intermodulation distortion. . . . . . . . . . . . . . . . 27
13.1.3.1 Spectral analysis (dual-tone) . . . . . . . . . . . . . 27
13.1.3.2 IMD2 (IMD3) . . . . . . . . . . . . . . . . . . . . . . . . . 27
13.1.4 Noise Power Ratio (NPR) . . . . . . . . . . . . . . . 27
14 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 28
15 Revision history . . . . . . . . . . . . . . . . . . . . . . . 29
16 Contact information . . . . . . . . . . . . . . . . . . . . 29
17 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30