ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz Rev. 03 -- 2 July 2012 Product data sheet 1. General description The ADC1006S055/070 are a family of Bipolar CMOS (BiCMOS) 10-bit Analog-to-Digital Converters (ADC) optimized for a wide range of applications such as cellular infrastructures, professional telecommunications, imaging, and digital radio. It converts the analog input signal into 10-bit binary coded digital words at a maximum sampling rate of 70 MHz. All static digital inputs (SH, CE and OTC) are Transistor-Transistor Logic (TTL) and CMOS compatible and all outputs are CMOS compatible. A sine wave clock input signal can also be used. 2. Features 10-bit resolution Sampling rate up to 70 MHz 3 dB bandwidth of 245 MHz 5 V power supplies and 3.3 V output power supply Binary or two's complement CMOS outputs In-range CMOS compatible output TTL and CMOS compatible static digital inputs TTL and CMOS compatible digital outputs Differential AC or Positive Emitter-Coupled Logic (PECL) clock input; TTL compatible Power dissipation 550 mW (typical) Low analog input capacitance (typical 2 pF), no buffer amplifier required Integrated sample-and-hold amplifier Differential analog input External amplitude range control Voltage controlled regulator included 40 C to +85 C ambient temperature 3. Applications High-speed analog-to-digital conversion for: Cellular infrastructure Professional telecommunication Digital radio Radar Medical imaging Fixed network Cable modem (R) ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz Barcode scanner Cable Modem Termination System (CMTS)/Data Over Cable Service Interface Specification (DOCSIS) 4. Quick reference data Table 1. Quick reference data VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = 40 C to +85 C; VI(IN)(p-p) VI(INN)(p-p) = 1.9 V; VVREF = VCCA3 1.75 V; VI(cm) = VCCA3 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Parameter Min Typ Max Unit VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output supply voltage 3.0 3.3 3.6 V ICCA analog supply current - 78 87 mA ICCD digital supply current - 27 30 mA ICCO output supply current fclk = 20 MHz; fi = 400 kHz - 3 4 mA INL integral non-linearity fclk = 20 MHz; fi = 400 kHz - 0.65 1.12 LSB DNL differential non-linearity fclk = 20 MHz; fi = 400 kHz (no missing code guaranteed) - 0.12 0.27 LSB fclk(max) maximum clock frequency ADC1006S055H 55 - - MHz ADC1006S070H 70 - - MHz total power dissipation fclk = 55 MHz; fi = 20 MHz - 550 660 mW Ptot Conditions 5. Ordering information Table 2. Ordering information Type number Package Sampling frequency (MHz) Name Description Version ADC1006S055H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm SOT307-2 55 ADC1006S070H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm SOT307-2 70 ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 2 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz 6. Block diagram VCCA1 VCCA3 VCCA4 2 3 CLKN CLK 35 41 VCCD1 VCCD2 37 15 36 CE OTC 19 18 6 to 10, 13, 14, 16, 31, 32 n.c. 21 D9 CLOCK DRIVER FSREF VREF 12 VREF REFERENCE 23 D7 24 D6 11 25 D5 AMP CMOS OUTPUTS sample and - hold INN SH CMADC DEC LATCHES 28 D2 42 29 D1 s 39 30 D0 33 1 CMADC REFERENCE OVERFLOW/ UNDERFLOW LATCH 5 ADC1006S055/070 44 AGND1 4 AGND3 AGND4 CMOS OUTPUT 20 17 34 DGND1 DGND2 OGND 40 data outputs 26 D4 27 D3 ANALOG-TO-DIGITAL CONVERTER 43 IN MSB 22 D8 38 LSB VCCO IR 014aaa464 Fig 1. Block diagram ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 3 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz 7. Pinning information 34 OGND 35 CLKN 36 CLK 37 VCCD1 38 DGND1 39 SH 40 AGND4 41 VCCA4 42 IN 43 INN 44 AGND1 7.1 Pinning CMADC 1 33 VCCO VCCA1 2 32 n.c. VCCA3 3 31 n.c. AGND3 4 30 D0 DEC 5 n.c. 6 n.c. 7 27 D3 n.c. 8 26 D4 n.c. 9 25 D5 n.c. 10 24 D6 VREF 11 23 D7 29 D1 D8 22 28 D2 D9 21 IR 20 CE 19 OTC 18 DGND2 17 n.c. 16 VCCD2 15 n.c. 14 n.c. 13 FSREF 12 ADC1006S055/070 014aaa442 Fig 2. Pin configuration 7.2 Pin description Table 3. Pin description Symbol Pin Description CMADC 1 regulator output common mode ADC input VCCA1 2 analog supply voltage 1 (5 V) VCCA3 3 analog supply voltage 3 (5 V) AGND3 4 analog ground 3 DEC 5 decoupling node n.c. 6 not connected n.c. 7 not connected n.c. 8 not connected n.c. 9 not connected n.c. 10 not connected VREF 11 reference voltage input FSREF 12 full-scale reference output n.c. 13 not connected n.c. 14 not connected VCCD2 15 digital supply voltage 2 (5 V) n.c. 16 not connected DGND2 17 digital ground 2 ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 4 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz Table 3. Pin description ...continued Symbol Pin Description OTC 18 control input two's complement output; active HIGH CE 19 chip enable input (CMOS level; active LOW) IR 20 in-range output D9 21 data output; bit 9 (Most Significant Bit (MSB)) D8 22 data output; bit 8 D7 23 data output; bit 7 D6 24 data output; bit 6 D5 25 data output; bit 5 D4 26 data output; bit 4 D3 27 data output; bit 3 D2 28 data output; bit 2 D1 29 data output; bit 1 D0 30 data output; bit 0 (Least Significant Bit (LSB)) n.c. 31 not connected n.c. 32 not connected VCCO 33 output supply voltage (3.3 V) OGND 34 output ground CLKN 35 complementary clock input CLK 36 clock input VCCD1 37 digital supply voltage 1 (5 V) DGND1 38 digital ground 1 SH 39 sample-and-hold enable input (CMOS level; active HIGH) AGND4 40 analog ground 4 VCCA4 41 analog supply voltage 4 (5 V) IN 42 analog input voltage INN 43 complementary analog input voltage AGND1 44 analog ground 1 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Min Max Unit analog supply voltage [1] 0.3 +7.0 V VCCD digital supply voltage [1] 0.3 +7.0 V VCCO output supply voltage [1] 0.3 +7.0 V VCC supply voltage difference VCCA VCCD 1.0 +1.0 V VCCD VCCO 1.0 +4.0 V VCCA VCCO 1.0 +4.0 V 0.3 VCCA V 0.3 VCCA V VCCA Parameter Conditions Vi(IN) input voltage on pin IN Vi(INN) input voltage on pin INN referenced to AGND ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 5 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz Table 4. Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Vi(clk)(p-p) peak-to-peak clock input voltage differential clock drive at pins 35 and 36 - VCCD V IO output current - 10 mA Tstg storage temperature 55 +150 C Tamb ambient temperature 40 +85 C Tj junction temperature - 150 C [1] The supply voltages VCCA, VCCD and VCCO may have any value between 0.3 V and +7.0 V provided that the supply voltage differences VCC are respected. 9. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Condition Value Unit Rth(j-a) thermal resistance from junction to ambient in free air 75 K/W 10. Characteristics Table 6. Characteristics VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = 40 C to +85 C; VI(IN)(p-p) VI(INN)(p-p) = 1.9 V; VVREF = VCCA3 1.75 V; VI(cm) = VCCA3 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Parameter Test[1] Min Conditions Typ Max Unit Supplies VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output supply voltage 3.0 3.3 3.6 V ICCA analog supply current I - 78 87 mA ICCD digital supply current I - 27 30 mA ICCO output supply current fclk = 20 MHz; fi = 400 kHz I - 3 4 mA fclk = 55 MHz; fi = 20 MHz I - 9.5 12 mA total power dissipation fclk = 55 MHz; fi = 20 MHz - 550 660 mW Ptot Inputs CLK and CLKN (referenced to DGND)[2] VIL LOW-level input voltage PECL mode; VCCD = 5 V I 3.19 - 3.52 V TTL mode C 0 - 0.8 V ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 6 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz Table 6. Characteristics ...continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = 40 C to +85 C; VI(IN)(p-p) VI(INN)(p-p) = 1.9 V; VVREF = VCCA3 1.75 V; VI(cm) = VCCA3 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Test[1] Min Typ Max Unit VIH HIGH-level input voltage PECL mode; VCCD = 5 V I 3.83 - 4.12 V TTL mode C 2.0 - VCCD V IIL LOW-level input current VCLK or VCLKN = 3.19 V C 10 - - A IIH HIGH-level input current VCLK or VCLKN = 3.83 V C - - 10 A Vi(dif)(p-p) peak-to-peak differential input voltage AC driving mode; DC voltage level = 2.5 V C 1 1.5 2.0 V Ri input resistance fclk = 55 MHz D 2 - - k Ci input capacitance fclk = 55 MHz D - - 2 pF OTC, SH and CE (referenced to DGND); see Table 7 and 8 VIL LOW-level input voltage I 0 - 0.8 V VIH HIGH-level input voltage I 2.0 - VCCD V IIL LOW-level input current VIL = 0.8 V I 20 - - A IIH HIGH-level input current VIH = 2.0 V I - - 20 A IN and INN (referenced to AGND); see Table 7, VVREF = VCCA3 1.75 V IIL LOW-level input current SH = HIGH C - 10 - A IIH HIGH-level input current SH = HIGH C - 10 - A Ri input resistance fi = 20 MHz D - 14 - M Ci input capacitance fi = 20 MHz D - 450 - fF VI(cm) common-mode input voltage VI(IN) = VI(INN) output code 512 C VCCA3 1.7 VCCA3 1.6 VCCA3 1.2 V Voltage controlled regulator output CMADC VO(cm) common-mode output voltage I - VCCA3 1.6 - V Iload load current I - 1 2 mA C - VCCA3 1.75 - V C - 0.3 10 A C - 1.9 - V Voltage input Vref[3] Vref reference voltage Iref reference current Vi(dif)(p-p) peak-to-peak differential input voltage full-scale fixed voltage; fi = 20 MHz; fclk = 55 MHz VI(IN)(p-p) VI(INN)(p-p); Vref = VCCA3 1.75 V; VI(cm) = VCCA3 1.6 V ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 7 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz Table 6. Characteristics ...continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = 40 C to +85 C; VI(IN)(p-p) VI(INN)(p-p) = 1.9 V; VVREF = VCCA3 1.75 V; VI(cm) = VCCA3 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Parameter Test[1] Min Conditions Typ Max Unit Voltage controlled regulator output FSREF VO(ref) reference output voltage VI(IN)(p-p) VI(INN)(p-p) = 1.9 V I - VCCA3 1.75 - V Digital outputs D9 to D0 and IR (referenced to OGND) VOL LOW-level output voltage IOL = 2 mA I 0 - 0.5 V VOH HIGH-level output voltage IOH = 0.4 mA I VCCO 0.5 - VCCO V Io output current 3-state output level between I 0.5 V and VCCO 20 - +20 A Switching characteristics; Clock frequency fclk; see Figure 3 fclk(min) minimum clock frequency SH = HIGH C - - 7 MHz fclk(max) maximum clock frequency ADC1006S055H I 55 - - MHz ADC1006S070H C 70 - - MHz tw(clk)H HIGH clock pulse width fi = 20 MHz C 6.8 - - ns tw(clk)L LOW clock pulse width fi = 20 MHz C 6.8 - - ns Analog signal processing; 50 % clock duty factor; VI(IN)(p-p) VI(INN)(p-p) = 1.9 V; VVREF = VCCA3 1.75 V; see Table 7 Linearity INL integral non-linearity fclk = 20 MHz; fi = 400 kHz I - 0.65 1.12 LSB DNL differential non-linearity fclk = 20 MHz; fi = 400 kHz (no missing code guaranteed) I - 0.12 0.27 LSB Eoffset offset error VCCA = VCCD = 5 V; VCCO = 3.3 V; Tamb = 25 C; output code = 512 C 25 +5 +25 mV EG gain error spread from device to device; VCCA = VCCD = 5 V; VCCO = 3.3 V; Tamb = 25 C C 7 - +7 %FS 3 dB; full-scale input C 220 245 - MHz Bandwidth (fclk = 55 MHz)[4] B bandwidth ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 8 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz Table 6. Characteristics ...continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = 40 C to +85 C; VI(IN)(p-p) VI(INN)(p-p) = 1.9 V; VVREF = VCCA3 1.75 V; VI(cm) = VCCA3 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Test[1] Min Parameter Conditions second harmonic level ADC1006S055H (fclk = 55 MHz) Typ Max Unit Harmonics 2H fi = 4.43 MHz C - 77 - dBFS fi = 10 MHz C - 76 - dBFS fi = 15 MHz C - 75 - dBFS fi = 20 MHz I - 73 - dBFS ADC1006S070H (fclk = 70 MHz) 3H fi = 4.43 MHz C - 75 - dBFS fi = 10 MHz C - 74 - dBFS fi = 15 MHz C - 70 - dBFS third harmonic level ADC1006S055H (fclk = 55 MHz) fi = 4.43 MHz C - 73 - dBFS fi = 10 MHz C - 73 - dBFS fi = 15 MHz C - 73 - dBFS fi = 20 MHz I - 72 - dBFS ADC1006S070H (fclk = 70 MHz) fi = 4.43 MHz C - 73 - dBFS fi = 10 MHz C - 73 - dBFS fi = 15 MHz C - 72 - dBFS Total harmonic distortion[5] THD total harmonic distortion ADC1006S055H (fclk = 55 MHz) fi = 4.43 MHz C - 68 - dBFS fi = 10 MHz C - 68 - dBFS fi = 15 MHz C - 68 - dBFS fi = 20 MHz I - 68 - dBFS ADC1006S070H (fclk = 70 MHz) fi = 4.43 MHz C - 67 - dBFS fi = 10 MHz C - 67 - dBFS fi = 15 MHz C - 66 - dBFS shorted input; SH = HIGH; fclk = 55 MHz C - 0.12 - LSB Thermal noise Nth(RMS) RMS thermal noise ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 9 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz Table 6. Characteristics ...continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = 40 C to +85 C; VI(IN)(p-p) VI(INN)(p-p) = 1.9 V; VVREF = VCCA3 1.75 V; VI(cm) = VCCA3 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Parameter Test[1] Min Conditions Typ Max Unit Signal-to-noise ratio[6] S/N signal-to-noise ratio ADC1006S055H (fclk = 55 MHz) fi = 4.43 MHz C - 60 - dBFS fi = 10 MHz C - 60 - dBFS fi = 15 MHz C - 60 - dBFS fi = 20 MHz I - 59.5 - dBFS ADC1006S070H (fclk = 70 MHz) fi = 4.43 MHz C - 60 - dBFS fi = 10 MHz C - 60 - dBFS fi = 15 MHz C - 59 - dBFS Spurious free dynamic range; see Figure 7, 13 and 14 SFDR spurious free dynamic range ADC1006S055H (fclk = 55 MHz) fi = 4.43 MHz C - 71 - dBFS fi = 10 MHz C - 70 - dBFS fi = 15 MHz C - 70 - dBFS fi = 20 MHz I - 70 - dBFS ADC1006S070H (fclk = 70 MHz) fi = 4.43 MHz C - 70 - dBFS fi = 10 MHz C - 69 - dBFS fi = 15 MHz C - 68 - dBFS Effective number of bits[7] ENOB effective number of bits ADC1006S055H (fclk = 55 MHz) fi = 4.43 MHz C - 9.5 - bit fi = 10 MHz C - 9.5 - bit fi = 15 MHz C - 9.5 - bit fi = 20 MHz I - 9.5 - bit ADC1006S070H (fclk = 70 MHz) fi = 4.43 MHz C - 9.5 - bit fi = 10 MHz C - 9.5 - bit fi = 15 MHz C - 9.4 - bit Intermodulation; (fclk = 55 MHz; fi = 20 MHz)[8] IM intermodulation suppression C - 69 - dBFS IMD3 third-order intermodulation distortion C - 79 - dBFS fi = 20 MHz; VI = 16 LSB at C code 512 - 1014 - times/ sample Bit error rate (fclk = 55 MHz) BER bit error rate ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 10 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz Table 6. Characteristics ...continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = 40 C to +85 C; VI(IN)(p-p) VI(INN)(p-p) = 1.9 V; VVREF = VCCA3 1.75 V; VI(cm) = VCCA3 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. Symbol Parameter Conditions Test[1] Min Typ Max Unit Timing (CL = 10 pF)[9] td(s) sampling delay time C - 0.25 1 ns th(o) output hold time C 4 6.4 - ns td(o) output delay time C - 9.0 13 ns 3-state output delay times; see Figure 4 tdZH float to active HIGH delay time C - 5.1 9.0 ns tdZL float to active LOW delay time C - 7.0 11 ns tdHZ active HIGH to float delay time C - 9.7 14 ns tdLZ active LOW to float delay time C - 9.5 13 ns [1] [2] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested. The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation: a) PECL mode 1: (DC level vary 1 : 1 with VCCD) CLK and CLKN inputs are at differential PECL levels. b) PECL mode 2: (DC level vary 1 : 1 with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor. c) PECL mode 3: (DC level vary 1 : 1 with VCCD) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLKN input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to decouple the CLKN or CLK input to DGND via a 100 nF capacitor. e) TTL mode 1: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that case CLKN pin has to be connected to the ground. [3] The ADC input range can be adjusted with an external reference connected to VREF pin. This voltage has to be referenced to VCCA; see Figure 12. [4] The 3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave. [5] Total Harmonic Distortion (THD) is obtained with the addition of the first five harmonics: 2 2 2 2 2 2H + 3H + 4H + + 6H THD = 20 log -------------------------------------------------------------------------------------------------------------------------------------2 a 1H where 1H is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input; see Figure 6. [6] Signal-to-noise ratio (S/N) takes into account all harmonics above five and noise up to Nyquist frequency; see Figure 8. [7] Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to SIgnal-to_Noise_Distortion ratio (SINAD) is given by SINAD = ENOB 6.02 + 1.76 dB; see Figure 5. [8] Intermodulation measured relative to either tone with analog input frequencies of 20 MHz and 20.1 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (6 dB below full scale for each input signal). IMD3 is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product. [9] Output data acquisition: the output data is available after the maximum delay of td(o); see Figure 3. ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 11 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz 11. Additional information relating to Table 6 Table 7. Output coding with differential inputs (typical values to AGND); Vi(IN)(p-p) Vi(INN)(p-p) = 1.9 V, VVREF = VCCA3 1.75 V Code Vi(a)(p-p) (V) Underflow < 3.125 0 1 Vi(a)(p-p) (V) IR Binary outputs D9 to D0 Two's complement outputs[1] D9 to D0 > 4.075 0 00 0000 0000 10 0000 0000 3.125 4.075 1 00 0000 0000 10 0000 0000 - - 1 00 0000 0001 10 0000 0001 - - 511 3.6 3.6 1 01 1111 1111 11 1111 1111 - - 1022 - - 1 11 1111 1110 01 1111 1110 1023 4.075 3.125 1 11 1111 1111 01 1111 1111 Overflow > 4.075 < 3.125 0 11 1111 1111 01 1111 1111 [1] Two's complement reference is inverted MSB. Table 8. Mode selection OTC CE 0 0 binary; active 1 0 two's complement; active X[1] 1 high-impedance [1] X = don't care. Table 9. Sample-and-hold selection SH Sample-and-hold 1 active 0 inactive; tracking mode ADC1006S055_070_3 Product data sheet D0 to D9 and IR (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 12 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz sample N sample N + 1 sample N + 2 tw(clk)H tw(clk)L HIGH 50 % LOW CLK sample N sample N + 1 sample N + 2 IN th(o) td(s) DATA D0 TO D9 DATA N-2 DATA N-1 HIGH 50 % LOW DATA N+1 DATA N td(o) 014aaa465 Fig 3. Timing diagram VCCD 50 % CE 0V tdHZ tdZH HIGH 90 % output data 50 % tdLZ LOW tdZL HIGH output data 50 % LOW 10 % VCCO ADC1006S 070 3.3 k S1 15 pF TEST S1 tdLZ VCCO tdZL VCCO tdHZ OGND tdZH CE OGND 014aaa443 (1) frequency on pin CE = 100 kHz. Fig 4. Timing diagram and test conditions of 3-state output delay time ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 13 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz 014aaa444 9.70 014aaa445 -63 ENOB (bit) THD (dB) -65 9.60 (1) -67 9.50 (1) (2) -69 9.40 9.30 0 5 10 15 20 25 fi (MHz) (1) 55 MHz. -71 (2) 0 5 10 15 20 25 fi (MHz) (1) 55 MHz. (2) 70 MHz. (2) 70 MHz. Fig 5. Effective Number Of Bits (ENOB) as a function of input frequency (sample device) 014aaa446 73 Fig 6. Total Harmonic Distortion (THD) as a function of input frequency (sample device) 014aaa447 60.0 SFDR (dB) S/N (dB) 72 (1) 59.8 (1) 71 59.6 70 59.4 (2) 69 (2) 59.2 68 59.0 0 5 10 15 20 25 fi (MHz) 0 (1) 55 MHz. (1) 55 MHz. (2) 70 MHz. (2) 70 MHz. Fig 7. Spurious Free Dynamic Range (SFDR) as a function of input frequency (sample device) 10 15 20 25 fi (MHz) Fig 8. Signal-to-Noise Ratio (S/N) as a function of input frequency (sample device) ADC1006S055_070_3 Product data sheet 5 (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 14 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz 014aaa448 0 power spectrum (dB) -40 -80 -120 -160 0 5 10 15 20 25 30 fi (MHz) Fig 9. Single-tone; fi = 20 MHz; fclk = 55 MHz 014aaa449 0 power spectrum (dB) -40 -80 -120 -160 0 5 10 15 20 25 30 fi (MHz) Fig 10. Two-tone; fi 1 = 20 MHz; fi 2 = 20.1 MHz; fclk = 55 MHz ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 15 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz 014aaa450 1.00 output range (INL) 0.60 0.20 -0.20 -0.60 0 256 512 768 1024 output code Fig 11. Integral Non-Linearity (INL) 014aaa451 0.30 DNL (LSB) 0.20 0.10 0 -0.10 -0.20 0 256 512 768 1024 output code Fig 12. Differential Non-Linearity (DNL) ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 16 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz 014aaa452 80 SFDR (dBFS) 60 (1) (2) 40 (3) 20 -60 -50 -40 -30 -20 -10 0 Input amplitude (dBFS) (1) fi = 4.43 MHz. (2) fi = 20 MHz. (3) SFDR = 80 dB. Fig 13. SFDR as a function of input amplitude; Vi(IN)(p-p) Vi(INN)(p-p) = 1.9 V; fclk = 40 MHz 014aaa453 80 SFDR (dBFS) 60 (1) 40 (2) (3) 20 -60 -50 -40 -30 -20 -10 0 Input amplitude (dBFS) (1) fi = 4.43 MHz. (2) fi = 20 MHz. (3) SFDR = 80 dB. Fig 14. SFDR as a function of input amplitude; Vi(IN)(p-p) Vi(INN)(p-p) = 1.9 V; fclk = 55 MHz ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 17 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz 75 (dB) 10.0 (bit) (1) 70 9.5 (2) 9.0 65 60 8.5 (3) 55 8.0 50 7.5 45 7.0 40 6.5 35 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 VCCA - VVREF (V) 2.6 VI(IN)(p-p) - VI(INN)(p-p) (V) 2.2 2.1 1.8 1.4 6.0 2.2 1.0 1.3 014aaa455 1.4 1.5 1.6 1.7 1.8 1.9 VCCA - VVREF (V) 2.0 2.1 2.2 014aaa456 (1) SFDR. (2) ENOB. (3) S/N. Fig 15. SFDR, ENOB and S/N as a function of VCCA VVREF; fclk = 55 MHz; fi = 20 MHz Fig 16. ADC full-scale; VI(IN)(p-p) VI(INN)(p-p) as a function of VCCA VVREF ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 18 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz 12. Application information 12.1 Application diagrams 100 nF 220 nF SH mode 5V 5V 100 nF IN 1:1 100 CLK 100 INN 44 5V 10 nF 100 nF 43 42 41 40 39 38 37 36 35 5V 34 100 nF 1 33 2 32 n.c. 3 31 n.c. 4 30 D0 (LSB) 5 29 D1 28 D2 100 nF ADC1006S055/070 n.c. 6 n.c. 7 27 D3 n.c. 8 26 D4 n.c. 9 25 D5 n.c. 10 24 D6 23 D7 VREF 11 12 13 14 15 16 n.c. n.c. 17 18 19 n.c. 20 21 IR 22 D8 D9 (MSB) 5V 100 nF chip select input output format select 014aaa457 The analog, digital and output supplies should be separated and decoupled. Fig 17. Application diagram MC100 ELT20 TTL input D CLKN PECL CLK 270 ADC1006S 055/070 270 014aaa458 Fig 18. Application diagram for differential clock input PECL compatible using a TTL to PECL translator ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 19 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz CLKN TTL input CLK ADC1006S 055/070 014aaa459 Fig 19. Application diagram for TTL single-ended clock ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 20 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz 1 3 5 7 9 11 13 15 17 19 21 23 2 4 6 8 10 12 14 16 18 20 22 24 D3 B11 D2 12.2 Demonstration board VCC J2 C6 330 nF CLK2 R4 50 33 AGND4 C17 10 nF VCCA4 IN C9 TR1 CMADC INN IN AGND1 R9 100 41 15 42 14 43 13 44 12 1 2 3 4 5 6 7 8 9 C16 10 nF S3 VCC n.c. FL2 VCCD2 n.c. C12 100 nF n.c. C5 330 nF C18 10 nF FSREF FL1 B7 VCC P2 VCCA C7 330 nF 1 IN 1 k R7 VCCA 1.2 k R6 2.4 K VCC VCC ICI C1 22 F (20 V) DGND2 FL4 C14 100 nF GND OTC C11 100 nF C10 100 nF 5 k J4 2 S4 CE S2 P1 BYD17G D3 D9 IR 10 11 S1 VCCA J4 1 D7 16 330 nF 12 V D6 D5 D4 D1 D0 40 MCLT1_6T_KK81 C8 17 ADC1006S055/070 CMADC R1 100 39 D8 VREF S5 18 IC2 n.c. SH 19 38 n.c. VCCA DGND1 20 37 n.c. VCCD 10 nF 36 n.c. VCCD1 21 n.c. C19 35 DEC CLK1 CLK 22 AGDN3 CLK1 34 VCCA3 CLKN B5 31 30 29 28 27 26 25 24 23 VCCA1 J3 OGND C13 100 nF R3 100 32 n.c VCCO n.c VCCO C15 10 nF FL3 J1 220 nF B8 TM3 OUT 3 MC78MO5CDT GND C2 4.7 F (16 V) R2 62 PMBT 2222A VCCO T1 R8 750 D1 LGT679 C3 1 F D2 BZV55C3V6 R5 4.7 k C4 1 F TP2 VCCO 014aaa460 C8 is close to TR1 pin. Fig 20. Demonstration board schematic ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 21 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz TM2 R1 J1 J3 C9 B4 1 1 S5 TR1 S1 R3 34 P1 1 R9 C7 FL4 IC1 R8 R2 T1 R5 1 C12 D1 C3 D2 2 1 R6 B5 P2 C4 J4 23 112 TP2 C2 D3 IC2 C14 B7 C11 TM3 C1 C10 S2 R7 C5 S3 S4 FL2 J2 B8 R4 B11 TM1 1 014aaa466 Fig 21. Component placement (top side) C6 FL3 C19 C15 C8 C13 C16 FL1 C17 C18 014aaa467 Fig 22. Component placement (underside) ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 22 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz 1 014aaa461 Fig 23. Printed-circuit board layout (top layer) 2 014aaa462 Fig 24. Printed-circuit board layout (ground layer) ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 23 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz 3 014aaa463 Fig 25. Printed-circuit board layout (power plane) 12.3 Alternative parts The following alternative parts are also available: Table 10. Alternative parts Type number Description Sampling frequency ADC1206S040 Single 12 bits ADC [1] ADC1206S055 Single 12 bits ADC [1] 55 MHz Single 12 bits ADC [1] 70 MHz ADC1206S070 [1] 40 MHz Pin to pin compatible 12.4 Recommended companion chip The recommended companion chip is the TDA9901 wideband differential digital controlled variable gain amplifier. ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 24 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz 13. Support information 13.1 Definitions 13.1.1 Non-linearities 13.1.1.1 Integral Non-Linearity (INL) It is defined as the deviation of the transfer function from a best fit straight line (linear regression computation). The INL of the code i is obtained from the equation: V I i - V I ideal INL i = -----------------------------------------S (1) n where i = 0 2 - 1 and S = slope of the ideal straight line = code width; i = code value. 13.1.1.2 Differential Non-Linearity (DNL) It is the deviation in code width from the value of 1 LSB. VI i + 1 - VI i DNL i = --------------------------------------- - 1 S (2) n where i = 0 2 - 2 13.1.2 Dynamic parameters (single tone) Figure 26 shows the spectrum of a full-scale input sine wave with frequency ft, conforming to coherent sampling (ft / fs = M / N, where M is the number of cycles and N is number of samples, M and N being relatively prime), and digitized by the ADC under test. magnitude a1 SFDR a3 ak a2 measured output range (MHz) fs/2 014aaa440 Fig 26. Spectrum of full-scale input sine wave with frequency ft ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 25 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz Remark: In the following equations, Pnoise is the power of the terms which include the effects of random noise, non-linearities, sampling time errors, and `quantization noise'. 13.1.2.1 Signal-to-Noise And Distortion (SINAD) The ratio of the output signal power to the noise and distortion power for a given sample rate and input frequency, excluding the DC component: P signal SINAD dB = 10 log -----------------------------------------P noise + distortion 13.1.2.2 (3) Effective Number Of Bits (ENOB) It is derived from SINAD and gives the theoretical resolution an ideal ADC would require to obtain the same SINAD measured on the real ADC. A good approximation gives: ENOB = SINAD dB - 1.76 6.02 13.1.2.3 Total Harmonic Distortion (THD) The ratio of the power of the harmonics to the power of the fundamental. For k-1 harmonics the THD is: P harmonics THD dB = 10 log --------------------------P signal 2 2 (4) 2 2 where P harmonics = 2 + 3 + k and P signal = 1 The value of k is usually 6 (i.e. calculation of THD is done on the first 5 harmonics). 13.1.2.4 Signal-to-Noise ratio (S/N) The ratio of the output signal power to the noise power, excluding the harmonics and the DC component. P signal S/N dB = 10 log ----------------P noise 13.1.2.5 (5) Spurious Free Dynamic Range (SFDR) The number SFDR specifies available signal range as the spectral distance between the amplitude of the fundamental and the amplitude of the largest spurious (harmonic and non-harmonic), excluding DC component. 1 SFDR dB = 20 log ----------------max s ADC1006S055_070_3 Product data sheet (6) (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 26 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz 13.1.3 Intermodulation distortion 13.1.3.1 Spectral analysis (dual-tone) magnitude IMD3 measured output range (MHz) fs/2 014aaa441 Fig 27. Spectral analysis (dual-tone) From a dual-tone input sinusoid (ft1 and ft2, these frequencies being chosen according to the coherence criterion), the intermodulation distortion products IMD2 and IMD3 (respectively, 2nd and 3rd-order components) are defined, as follows. 13.1.3.2 IMD2 (IMD3) The ratio of the RMS value of either tone to the RMS value of the worst second (third) order intermodulation product. The total IMD is given by: P intermod IMD dB = 10 log ----------------------P signal where, P intermod = a +a 2 2f t1 im 2 2 f im t1 - f t2 + a - f t2 - a 2 2f t1 im 2 f im t1 + f t2 + a 2 f im t1 - 2f t2 + a 2 f im t1 + 2f t2 + f t2 2 P signal = a f t1 + a f t2 and 2 a im f t is the power in the intermodulation component at frequency ft. 13.1.4 Noise Power Ratio (NPR) When using a notch-filtered broadband white-noise generator as the input to the ADC under test, the NPR is defined as the ratio of the average out-of-notch to the in-notch power spectral density magnitudes for the FFT spectrum of the ADC output sample set. ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 27 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz 14. Package outline QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 c y X A 33 23 34 22 ZE e E HE A A2 wM (A 3) A1 bp Lp pin 1 index L 12 44 1 detail X 11 wM bp e ZD v M A D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 2.1 0.25 0.05 1.85 1.65 0.25 0.4 0.2 0.25 0.14 10.1 9.9 10.1 9.9 0.8 12.9 12.3 12.9 12.3 1.3 0.95 0.55 0.15 0.15 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 97-08-01 03-02-25 SOT307-2 Fig 28. Package outline SOT307-2 (QFP44) ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 28 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes ADC1006S055_070_3 20120702 Product data sheet - ADC1006S055_070_2 ADC1006S055_070_2 20080812 Product data sheet - ADC1006S055_070_1 Modifications: ADC1006S055_070_1 * * Corrections made to titles in Figure 13 and 14. Corrections made to note in Figure 4. 20080611 Product data sheet - - 16. Contact information For more information or sales office addresses, please visit: http://www.idt.com ADC1006S055_070_3 Product data sheet (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 29 of 30 ADC1006S055/070 Integrated Device Technology Single 10 bits ADC, up to 55 MHz or 70 MHz 17. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 12 12.1 12.2 12.3 12.4 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal characteristics . . . . . . . . . . . . . . . . . . 6 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Additional information relating to Table 6 . . . 12 Application information. . . . . . . . . . . . . . . . . . 19 Application diagrams . . . . . . . . . . . . . . . . . . . 19 Demonstration board . . . . . . . . . . . . . . . . . . . 21 Alternative parts . . . . . . . . . . . . . . . . . . . . . . . 24 Recommended companion chip . . . . . . . . . . . 24 13 Support information . . . . . . . . . . . . . . . . . . . . 13.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.1 Non-linearities . . . . . . . . . . . . . . . . . . . . . . . . 13.1.1.1 Integral Non-Linearity (INL) . . . . . . . . . . . . . . 13.1.1.2 Differential Non-Linearity (DNL) . . . . . . . . . . . 13.1.2 Dynamic parameters (single tone) . . . . . . . . . 13.1.2.1 Signal-to-Noise And Distortion (SINAD) . . . . 13.1.2.2 Effective Number Of Bits (ENOB) . . . . . . . . . 13.1.2.3 Total Harmonic Distortion (THD) . . . . . . . . . . 13.1.2.4 Signal-to-Noise ratio (S/N) . . . . . . . . . . . . . . . 13.1.2.5 Spurious Free Dynamic Range (SFDR). . . . . 13.1.3 Intermodulation distortion. . . . . . . . . . . . . . . . 13.1.3.1 Spectral analysis (dual-tone) . . . . . . . . . . . . . 13.1.3.2 IMD2 (IMD3) . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.4 Noise Power Ratio (NPR) . . . . . . . . . . . . . . . 14 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information . . . . . . . . . . . . . . . . . . . . 17 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC1006S055_070_3 Product data sheet 25 25 25 25 25 25 26 26 26 26 26 27 27 27 27 28 29 29 30 (c) IDT 2012. All rights reserved. Rev. 03 -- 2 July 2012 30 of 30