HD3-6409-9Z - Intersil Corporation

®HD-6409

CMOS Manchester Encoder-Decoder

The HD-6409 Manchester Encoder-Decoder (MED) is a high

speed, low power device ma nufactured using self-aligned

silicon gate technology. The device is intended for use in

serial data communication, and can be operated in either of

two modes. In the converter mode, the MED converts Non

return-to-Zero code (NRZ) into Manchester code and

decodes Manchester code into N onreturn-to-Zero code. For

serial data communication, Manchester code does not have

some of the deficiencies inherent in Nonreturn-to-Zero code.

For instance, use of the MED on a serial line eliminates DC

components, provides clock recovery, and gives a relatively

high degree of noise immunity. Because the MED converts

the most commonly used code (NRZ) to Ma nchester code,

the advantages of using Manchester code are easily realized

in a serial data link.

In the Repeater mode, the MED accepts Manchester code

input and reconstructs it with a recovered clock. This

minimizes the effects of noise on a serial data link. A digital

phase lock loop generates the recovered clock. A maximum

data rate of 1MHz requires only 50mW of power.

Manchester code is used in magnetic tape recording and in

fiber optic communication, and generally is used where data

accuracy is imperative. Because it frames blocks of data, the

HD-6409 easily interfaces to protocol controllers.

Features

• Converter or Repeater Mode

• Independent Manchester Encoder and Decoder

Operation

• Static to One Megabit/sec Data Rate Guaranteed

• Low Bit Error Rate

• Digital PLL Clock Recovery

• On Chip Oscillator

• Low Operating Power: 50mW Typical at +5V

• Pb-Free Available (RoHS Compliant)

Pinout

HD-6409

(20 LD PDIP, SOIC)

TOP VIEW

BZI

BOI

UDI

SD/CDS

SDO

SRST

DCLK

NVM

RST

GND

VCC

BZO

ECLK

BOO

CTS

Ordering Information

PART NUMBER

(1 MEGABIT/SEC) PART MARKING TEMP. RANGE

(°C) PACKAGE PKG. DWG. #

HD3-6409-9 HD3-6409-9 -40 to +85 20 Ld PDIP E20.3

HD3-6409-9Z (Notes 2, 3) HD3-6409-9Z -40 to +85 20 Ld PDIP (Pb-free) E20.3

HD9P6409-9 HD9P6409-9 -40 to +85 20 Ld SOIC M20.3

HD9P6409-9Z (Notes 2, 3) HD9P6409-9Z -40 to +85 20 Ld SOIC (Pb-free) M20.3

HD9P6409-9Z96 (Notes 1, 2, 3) HD9P6409-9Z -40 to +85 20 Ld SOIC Tape & Reel

(Pb-free) M20.3

NOTES:

1. “96” suffix is for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets , molding compounds/die attach materials, and 100%

matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).

Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC

J STD-020.

3. Pb-free PDIPs can be used for through hole wave solder processing only . They are not intended for use in Reflow solder processing applications.

FN2951.3Data Sheet October 15, 2008

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

2FN2951.3

October 15, 2008

Block Diagram

Logic Symbol

EDGE

DETECTOR

COMMAND

SYNC

GENERATOR

OUTPUT

SELECT

LOGIC

BOI

BZI

UDI

RST

SD/CDS

RESET

5-BIT SHIFT

AND DECODER

DATA

INPUT

LOGIC

INPUT/

OUTPUT

SELECT

OSCILLATOR COUNTER

CIRCUITS

MANCHESTER

ENCODER

SDO

NVM

BOO

BZO

CTS

SRST

ECLK

DCLK

CLOCK

GENERATOR

ENCODER

CONTROL

DECODER

SD/CDS

ECLK

RST

SDO

DCLK

NVM

SRST

BOO

BZO

CTS

BOI

BZI

UDI

HD-6409HD-6409

3FN2951.3

October 15, 2008

Pin Descriptions

NUMBER TYPE SYMBOL NAME DESCRIPTION

1 I BZl Bipolar Zero Input Used in conjunction with pin 2, Bipolar One Input (BOl), to input Manchester II encoded

data to the decoder, BZI and BOl are logical complements. When using pin 3, Unipolar

Data Input (UDI) for data input, BZI must be held high.

2 I BOl Bipolar One Input Used in conjunction with pin 1, Bipolar Zero Input (BZI), to input Manchester II encoded

data to the decoder, BOI and BZI are logical complements. When using pin 3, Unipolar

Data Input (UDI) for data input, BOl must be held low.

3 I UDI Unipolar Data Input An alternate to bipolar input (BZl, BOl), Unipolar Data Input (UDl) is used to input

Manchester II encoded data to the decoder. When using pin 1 (BZl) and pin 2 (BOl) for

data input, UDI must be held low.

4 I/O SD/CDS Serial Data/Command

Data Sync In the converter mode, SD/CDS is an input used to receive serial NRZ data. NRZ data is

accepted synchronously on the falling edge of encoder clock output (ECLK). In the

repeater mode, SD/CDS is an output indicating the status of last valid sync pattern

received. A high indicates a command sync and a low indicates a data sync pattern.

5 O SDO Serial Data Out The decoded serial NRZ data is transmitted out synchronously with the decoder clock

(DCLK). SDO is forced low when RST is low.

6 O SRST Serial Reset In the converter mode, SRST follows RST. In the repeater mode, when RST goes low,

SRST goes low and remains low after RST goes high. SRST goes high only when RST

is high, the reset bit is zero, and a valid synchronization sequence is received.

7ONVM

Nonvalid Manchester A low on NVM indicates that the decoder has received invalid Manchester data and

present data on Serial Data Out (SDO) is invalid. A high indicates that the sync pulse and

data were valid and SDO is valid. NVM is set low by a low on RST, and remains low after

RST goes high until valid sync pulse followed by two valid Manchester bits is received.

8 O DCLK Decoder Clock The decoder clock is a 1X clock recovered from BZl and BOl, or UDI to synchronously

output received NRZ data (SDO).

9IRST

Reset In the converter mode, a low on RST forces SDO, DCLK, NVM, and SRST low. A high on

RST enables SDO and DCLK, and forces SRST high. NVM remains low after RST goes

high until a valid sync pulse followed by two Manchester bits is received, after which it

goes high. In the repeater mode, RST has the same effect on SDO, DCLK and NVM as

in the converter mode. When RST goes low, SRST goes low and remains low after RST

goes high. SRST goes high only when RST is high, the reset bit is zero and a valid

synchronization sequence is received.

10 I GND Ground Ground

11 O COClock Output Buffered output of clock input IX. May be used as clock signal for other peripherals.

12 I IXClock Input IX is the input for an external clock or, if the internal oscillator is used, IX and OX are used

for the connection of the crystal.

13 O OXClock Drive If the internal oscillator is used, OX and IX are used for the connection of the crystal.

14 I MS Mode Select MS must be held low for operation in the converter mode, and high for operation in the

repeater mode.

15 I CTS Clear to Send In the converter mode, a high d isables the e ncoder, fo rcing out puts BOO, BZO high and

ECLK low . A high to low transition of CTS initiates transmission of a Command sync pulse.

A low on CTS enables BOO, BZO, an d E CLK. In the repea ter m ode , th e fu nction o f CTS

is identical to that of the converter mod e with the exception that a transition o f CTS do es

not initiate a synchronization sequence.

16 O ECLK Encoder Clock In the converter mode, ECLK is a 1X clock output used to receive serial NRZ data to

SD/CDS. In the repeater mode, ECLK is a 2X clock which is recovered from BZl and BOl

data by the digital phase locked loop.

17 I SS Speed Select A logic high on SS sets the data rate at 1/32 times the clock frequency while a low sets

the data rate at 1/16 times the clock frequency.

18 O BZO Bipolar Zero Output BZO and its logical complement BOO are the Manchester data outputs of the encoder.

The inactive state for these outputs is in the high state.

19 O BOO Bipolar One Out See pin 18.

20 I VCC VCC VCC is the +5V power supply pin. A 0.1µF decoupling capacitor from VCC (pin 20) to GND

(pin 10) is recommended.

NOTE: (I) Input (O) Output

HD-6409HD-6409

4FN2951.3

October 15, 2008

Encoder Operation

The encoder uses free running clocks at 1X and 2X the data

rate derived from the system clock lX for internal timing. CTS

is used to control the encoder outputs, ECLK, BOO and

BZO. A free running 1X ECLK is transmitted out of the

encoder to drive the external circuits which supply the NRZ

data to the MED at pin SD/CDS.

A low on CTS enables encoder outputs ECLK, BOO and

BZO, while a high on CTS forces BZO, BOO high and holds

ECLK low. When CTS goes from high to low , a

synchronization sequence is transmitted out on BOO and

BZO. A synchronization sequence consists of eight

Manchester “0” bits followed by a command sync pulse.

A command sync pulse is a 3-bit wide pulse with the first 1

1/2 bits high followed by 1 1/2 bits low . Serial NRZ data is

clocked into the encoder at SD/CDS on the high to low

transition of ECLK during the command sync pulse. The

NRZ data received is encoded into Manchester II data and

transmitte d ou t on BOO and BZO following the command

sync pulse. Following the synchronization sequence,

input data is encoded and transmitted out continuously

without parity check or word framing. The length of the data

block encoded is defined by CTS. Manchester data out is

inverted.

Decoder Operation

The decoder requires a single clock with a frequency 16X or

32X the desired data rate. The rate is selected on the speed

select with SS low producing a 16X clock and high a 32 X

clock. For long data links the 32X mode should be used as

this permits a wider timing jitter margin. The internal

operation of the decoder utilizes a free running clock

synchronized with incoming data for its clocking.

The Manchester II encoded data can be presented to the

decoder in either of two ways. The Bipolar One and Bipolar

Zero inputs will accept data from differential inputs such as a

comparator sensed transformer coupled bus. The Unipolar

Data input can only accept noninverted Manchester II

encoded data i.e. Bipolar One Out through an inverter to

Unipolar Data Input. The decoder continuously monitors this

data input for valid sync pattern. Note that while the MED

encoder section can generate only a command sync pattern,

the decoder can recognize either a command or data sync

pattern. A data sync is a logically inverted command sync.

There is a three bit delay between UDI, BOl, or BZI input and

the decoded NRZ data transmitted out of SDO.

Control of the decoder outputs is provided by the RST pin.

When RST is low, SDO, DCLK and NVM are forced low.

When RST is high, SDO is transmitted out synchronously

with the recovered clock DCLK. The NVM output remains

low after a low to high transition on RST until a valid sync

pattern is received.

The decoded data at SDO is in NRZ format. DCLK is

provided so that the decoded bits can be shifted into an

external register on every high to low transition of this clock.

Three bit periods after an invalid Manchester bit is received

on UDI, or BOl, NVM goes low synchronously with the

questionable data output on SDO. FURTHER, THE

DECODER DOES NOT RE-ESTABLISH PROPER DATA

DECODING UNTIL ANOTHER SYNC PATTERN IS

RECOGNIZED.

234

CTS

ECLK

SD/CDS

BZO

BOO

tCE6

0000 0000

tCE5

SYNCHRONIZATION SEQUENCE

EIGHT “0’s” COMMAND

SYNC

DON’T CARE

‘1’ ‘0’ ‘1’

FIGURE 1. ENCODER OPERATION

HD-6409HD-6409

5FN2951.3

October 15, 2008

Repeater Operation

Manchester Il data can be presented to the repeater in either

of two ways. The inputs Bipolar One In and Bipolar Zero In

will accept data from differential inputs such as a comparator

or sensed transformer coupled bus. The input Unipolar Data

In accepts only noninverted Manchester II coded data. The

decoder requires a single clock with a frequency 16X or 32X

the desired data rate. This clock is selected to 16X w ith

Speed Select low and 32X with Speed Select high. For long

data links the 32X mode should be used as this permits a

wider timing ji tt er margin.

The inputs UDl, or BOl, BZl are delayed approximately 1/2

bit period and repeated as outputs BOO and BZO. The 2X

ECLK is transmitted out of the repeater synchronously with

BOO and BZO.

A low on CTS enables ECLK, BOO, and BZO. In contrast to

the converter mode, a transition on CTS does not initiate a

synchronization sequence of eight 0’s and a command sync.

The repeater mode does recognize a command or data sync

pulse. SD/CDS is an output which reflects the state of the

most recent sync pulse received, with high indicating a

command sync and low indicating a data sync.

When RST is low, the outputs SDO, DCLK, and NVM are

low , and SRST is set low . SRST remains low af ter RST goes

high and is not reset until a sync pulse and two valid

manchester bits are received with the reset bit low . The reset

bit is the first data bit after the sync pulse. With RST high,

NRZ Data is transmitted out of Serial Data Out

synchronously with the 1X DCLK.

FIGURE 2. DECODER OPERATION

DCLK

UDI

SDO

RST

NVM

COMMAND

SYNC 1001010101010

FIGURE 3. REPEATER OPERATION

INPUT

COUNT

ECLK

UDI

BZO

BOO

RST

SRST

SYNC PUL SE

1234567

HD-6409HD-6409

6FN2951.3

October 15, 2008

Manchester Code

Nonreturn-to-Zero (NRZ) code represents the binary values

logic-O and Iogic-1 with a static level maintained throughout

the data cell. In contrast, Manchester code represents data

with a level transition in the middle of the data cell.

Manchester has bandwidth, error detection, an d

synchronization advantages over NRZ code.

The Manchester II code Bipolar One and Bipolar Zero shown

below are logical complements. The direction of the

transition indicates the binary value of data. A logic-0 in

Bipolar One is defined as a Low to high transition in the

middle of the data cell, and a logic-1 as a high to low mid bit

transition, Manchester Il is also known as Biphase-L code.

The bandwid th of NRZ is from DC to the clock frequency fc/2,

while that of Manchester is from fc/2 to Thus, Manchester

can be AC or transformer coupled, which has considerable

advantages over D C couplin g. Also, the ratio of maximum to

minimum frequency of Manchester exten ds one oct ave, while

the ratio for NRZ is the range of 5 to 10 octave s. It is much

easier to design a narro w band than a wi deban d amp.

Secondly, the mid bit transition in each data cell provides the

code with an effective error detection scheme. If noise

produces a logic inversion in the data cell such that there is

no transition, an error indiction is given, and synchronization

must be re-established. This places relatively stringent

requirements on the incoming data.

The synchronization advantages of using the HD-6409 and

Manchester code are several fold. One is that Manchester is

a self clocking code. The clock in serial data communication

defines the position of each data cell. Non self clocking

codes, as NRZ, often require an extra clock wire or clock

track (in magnetic recording). Further, there can be a phase

variation between the clock and data track. Crosstalk

between the two may be a problem. In Manchester, the

serial data stream contains both the clock and the data, with

the position of the mid bit transition representing the clock,

and the direction of the transition representing data. There is

no phase variation between the clock and the data.

A second synchronization advantage is a result of the

number of transitions in the data. The decoder

resynchronizes on each transition, or at leas t once every

data cell. In contrast, receivers using NRZ, which does not

necessarily have transitions, must resynchronize on frame

bit transitions, which occur far less often, usually on a

character basis. This more frequent resynchronization

eliminates the cumulative effect of errors over successive

data cells. A final synchronization advantage concerns the

HD-6409’s sync pulse used to initiate synchronization. This

three bit wide pattern is sufficiently distinct from Manchester

data that a false start by the receiver is unlikely.

FIGURE 4. MANCHESTER CODE

BIT PERIOD

BINARY CODE

NONRETURN

TO ZERO

BIPOLAR ONE

BIPOLAR ZERO

123 45

011 00

Crystal Oscillator Mode

FIGURE 5. CRYSTAL OSCILLATOR MODE

LC Oscillator Mode

FIGURE 6. LC OSCILLATOR MODE

X1R1C0 16MHz

C1 = 32pF

C0 = CRYSTAL + STRAY

X1 = AT CUT PARALLEL

RESONANCE

FUNDAMENTAL

MODE

RS (TYP) = 30Ω

R1 = 15MΩ

LCE

C1 2C0–

--------------------------

≈

2πLCe

-----------------------

≈

C1 = 20pF

C0 = 5pF

HD-6409HD-6409

7FN2951.3

October 15, 2008

Using the 6409 as a Manchester Encoded UART

VCC

BOO

BZO

ECLK

CTS

BZI

BOI

UDI

SD/CDS

SDO

SRST

NVM

DCLK

RST

GND

BIPOLAR OUT

CTS

LOAD

LOAD QHCKSI

‘165

LOAD QHCK

‘165

BQHA

‘164

BCKA

‘164

DATA IN

‘273

DATA IN

‘273

RESET

BIPOLAR IN

FIGURE 7. MANCHESTER ENCODER UART

PARALLEL DATA OUT

PARALLEL DATA IN

HD-6409HD-6409

8FN2951.3

October 15, 2008

Common Electrical Specifications Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.

Temperature limits established by characterization and are not production tested.

Absolute Maximum Ratings Thermal Information

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V

Input, Output or I/O Voltage. . . . . . . . . . . .GND -0.5V to VCC +0.5V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1

Operating Conditions

Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C

Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . .+4.5V to +5.5V

Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . 50ns Max

Sync. Transition Span (t2) . . . . . . . . . .1.5 DBP Typical, (Notes 1, 2)

Short Data Transition Span (t4) . . . . . . 0.5DBP Typical, (Notes 1, 2)

Long Data Transition Span (t5) . . . . . . 1.0DBP Typical, (Notes 1, 2)

Zero Crossing Tolerance (tCD5) . . . . . . . . . . . . . . . . . . . . . (Note 3)

Thermal Resistance (Typical, Note 4) θJA (°C/W) θJC (°C/W)

PDIP Package . . . . . . . . . . . . . . . . . . . 75 N/A

SOIC Package . . . . . . . . . . . . . . . . . . . 100 N/A

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

Maximum Junction Temperature

Ceramic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175°C

Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

*Pb-free PDIPs can be used for through hole wave solder

processing only. They are not intended for use in Reflow solder

processing applications.

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 Gates

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

1. D BP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles.

2. The input conditions specified are nominal values, the actual input waveforms transition spans may vary by ±2 IX clock cycles (16X mode) or ±6

IX clock cycles (32X mode).

3. The maximum zero crossing tolerance is ±2 IX clock cycles (16X mode) or ±6 IX clock cycles (32 mode ) from the nominal.

4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

DC Electrical Specifications VCC = 5.0V ± 10%, TA = -40°C to +85°C (HD-6409-9).

SYMBOL PARAMETER TEST CONDITIONS

(Note 5) MIN MAX UNITS

VIH Logical “1” Input Voltage VCC = 4.5V 70% VCC -V

VIL Logical “0” Input Voltage VCC = 4.5V - 20% VCC V

VIHR Logic “1” Input Voltage (Reset)V

CC = 5.5V VCC -0.5 - V

VILR Logic “0” Input Voltage (Reset)V

CC = 4.5V - GND +0.5 V

VIHC Logical “1” Input Voltage (Clock) VCC = 5.5V VCC -0.5 - V

VILC Logical “0” Input Voltage (Clock) VCC = 4.5V - GND +0.5 V

IIInput Leakage Current (Except IX)V

IN = VCC or GND, VCC = 5.5V -1.0 +1.0 μA

IIInput Leakage Current (IX)V

IN = VCC or GND, VCC = 5.5V -20 +20 μA

IOI/O Leakage Current VOUT = VCC or GND, VCC = 5.5V -10 +10 μA

VOH Output HIGH Voltage (All Except OX)I

OH = -2.0mA, VCC = 4.5V (Note 6) VCC -0.4 - V

VOL Output LOW Voltage (All Except OX)I

OL = +2.0mA, VCC = 4.5V (Note 6) - 0.4 V

ICCSB Standby Power Supply Current VIN = VCC or GND, VCC = 5.5V,

Outputs Open - 100 μA

ICCOP Operating Power Supply Current f = 16.0MHz, VIN = VCC or GND

VCC = 5.5V, CL = 50pF - 18.0 mA

FTFunctional Test (Note 5) - - -

NOTES:

5. Tested as follows: f = 16MHz, VIH = 70% VCC, VIL = 20% VCC, VOH ≥ VCC/2, and VOL ≤ VCC/2, VCC = 4.5V and 5.5V.

6. Interchanging of force and sense conditions is permitted

HD-6409HD-6409

9FN2951.3

October 15, 2008

Capacitance TA = +25°C, Frequency = 1MHz.

SYMBOL PARAMETER TEST CONDITIONS TYP UNITS

CIN Input Capacitance All measurements are referenced to device GND 10 pF

COUT Output Capacitance 12 pF

AC Electrical Specifications V

CC = 5.0V ±10%, TA = -40°C to +85°C (HD-6409-9).

SYMBOL PARAMETER TEST CONDITIONS

(Note 7) MIN MAX UNITS

fCClock Frequency - - 16 MHz

tCClock Period - 1/fC-sec

t1Bipolar Pulse Width - tC+10 - ns

t3One-Zero Overlap - - tC-10 ns

tCH Clock High Time f = 16.0MHz 20 - ns

tCL Clock Low Time f = 16.0MHz 20 - ns

tCE1 Serial Data Setup Time - 120 - ns

tCE2 Serial Data Hold Time - 0 - ns

tCD2 DCLK to SDO, NVM - - 40 ns

tR2 ECLK to BZO - - 40 ns

trOutput Rise Time ( All except Clock) From 1.0V to 3.5V, CL = 50pF, Note 8 - 50 ns

tfOutput Fall Time (All except Clock) From 3.5V to 1.0V, CL = 50pF, Note 8 - 50 ns

trClock Output Rise Time From 1.0V to 3.5V, CL = 20pF, Note 8 - 11 ns

tfClock Output Fall Time From 3.5V to 1.0V, CL = 20pF, Note 8 - 11 ns

tCE3 ECLK to BZO, BOO Notes 8, 9 0.5 1.0 DBP

tCE4 CTS Low to BZO, BOO Enabled Notes 8, 9 0.5 1.5 DBP

tCE5 CTS Low to ECLK Enabled Notes 8, 9 10.5 11.5 DBP

tCE6 CTS High to ECLK Disabled Notes 8, 9 - 1.0 DBP

tCE7 CTS High to BZO, BOO Disabled Notes 8, 9 1.5 2.5 DBP

tCD1 UDI to SDO, NVM N o tes 8, 9 2.5 3.0 DBP

tCD3 RST Low to CDLK, SDO, NVM Low Notes 8, 9 0.5 1.5 DBP

tCD4 RST High to DCLK, Enabled Notes 8, 9 0.5 1.5 DBP

tR1 UDI to BZO, BOO Notes 8, 9 0.5 1.0 DBP

tR3 UDI to SDO, NVM Notes 8, 9 2.5 3.0 DBP

NOTES:

7. AC testing as follows: f = 4.0MHz, VIH = 70% VCC, VIL = 20% VCC, S peed Select = 16X, VOH ≥ VCC/2, VOL ≤ VCC/2, VCC = 4.5V and 5.5V.

Input rise and fall times driven at 1ns/V, Output load = 50pF.

8. Limits established by characterization and are not production tested.

9. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles.

HD-6409HD-6409

10 FN2951.3

October 15, 2008

Timing Waveforms

FIGURE 8.

FIGURE 9. CLOCK TIMING FIGURE 10. OUTPUT WAVEFORM

DATA SYNC

BIT PERIOD BIT PERIOD BIT PERIOD

COMMAND SYNC t2

t3t3

ONEONE ZERO

t3t3

t3t3t3t3

t4t5

COMMAND SYNC

t2t2

t4t5t5t4t4

ZERO ONE ONEONE

DATA SYNC

BOI

BZI

BOI

BZI

BOI

BZI

UDI

NOTE: UDI = 0, FOR NEXT DIAGRAMS

NOTE: BOI = 0, BZI = 1 FOR NEXT DIAGRAMS

tCH

trtCL

10% 90%

trtf

1.0V 3.5V

HD-6409HD-6409

11 FN2951.3

October 15, 2008

FIGURE 11. ENCODER TIMING

FIGURE 12. ENCODER TIMING FIGURE 13. ENCODER TIMING

NOTE: Manchester Data-In is not synchronous with Decoder Clock.

Decoder Clock is synchronous with decoded NRZ out of SDO.

FIGURE 14. DECODER TIMING

FIGURE 15. DECODER TIMING FIGURE 16. DECODER TIMING

Timing Waveforms (Continued)

ECLK

SD/CDS

BZO

BOO

tCE1

tCE2

tCE3

tCE5

tCE4

CTS

BZO

BOO

ECLK

tCE6

CTS

BZO

BOO

ECLK

tCE7

DCLK

UDI

SDO

NVM

MANCHESTER

LOGIC-1 MANCHESTER

LOGIC-0 MANCHESTER

LOGIC-1

tCD2

tCD5

tCD2

tCD1

NRZ

LOGIC-1

RST

DCLK, SDO,

NVM

50%

tCD3

RST

DCLK

50%

tCD4

HD-6409HD-6409

12 FN2951.3

October 15, 2008

Test Load Circuit

FIGURE 17. REPEATER TIMING

Timing Waveforms (Continued)

UDI

ECLK

BZO

SDO

NVM

MANCHESTER ‘1’

tR2

tR3

tR2

tR1

MANCHESTER ‘0’ MANCHESTER ‘0’ MANCHESTER ‘1’

MANCHESTER ‘1’ MANCHESTER ‘0’ MANCHESTER ‘0’

FIGURE 18. TEST LOAD CIRCUIT

DUT

(NOTE)

NOTE: INCLUDES STRAY AND JIG

CAPACITANCE

HD-6409HD-6409

13 FN2951.3

October 15, 2008

HD-6409

Dual-In-Line Plastic Packages (PDIP)

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English

and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2

of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in

JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.

Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be perpen-

dicular to datum .

7. eB and eC are measured at the lead tips with the leads uncon-

strained. eC must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions. Dam-

bar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,

E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

-C-

-B-

INDEX 12 3 N/2

AREA

SEATING

BASE

PLANE

-C-

-A-

0.010 (0.25) C AMBS

E20.3 (JEDEC MS-001-AD ISSUE D)

20 LEAD DUAL-IN-LINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.210 - 5.33 4

A1 0.015 - 0.39 - 4

A2 0.115 0.195 2.93 4.95 -

B 0.014 0.022 0.356 0.558 -

B1 0.045 0.070 1.55 1.77 8

C 0.008 0.014 0.204 0.355 -

D 0.980 1.060 24.89 26.9 5

D1 0.005 - 0.13 - 5

E 0.300 0.325 7.62 8.25 6

E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC -

eA0.300 BSC 7.62 BSC 6

eB- 0.430 - 10.92 7

L 0.115 0.150 2.93 3.81 4

N20 209

Rev. 0 12/93

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Inter sil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN2951.3

October 15, 2008

HD-6409

Small Outline Plastic Packages (SOIC)

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions.

Interlead flash and protrusions shall not exceed 0.25mm (0.010

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. T e rminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch

dimensions are not necessarily exact.

INDEX

AREA E

123

-B-

0.25(0.010) C A

MBS

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45°

H0.25(0.010) B

M20.3 (JEDEC MS-013-AC ISSUE C)

20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.014 0.019 0.35 0.49 9

C 0.0091 0.0125 0.23 0.32 -

D 0.4961 0.5118 12.60 13.00 3

E 0.2914 0.2992 7.40 7.60 4

e 0.050 BSC 1.27 BSC -

H 0.394 0.419 10.00 10.65 -

h 0.010 0.029 0.25 0.75 5

L 0.016 0.050 0.40 1.27 6

N20 207

α0° 8° 0° 8° -

Rev. 2 6/05