HYS 72D128520GR-7-A - Infineon Technologies

INFINEON Technologies 1 2002-05-08 (0.9)

HYS 72Dxx5xxGR-7/8-A

Low Profile Registered DDR-I SDRAM-Modules

2.5 V Low Profile 184-pin Registered DDR-I SDRAM Modules

256MB, 512MB & 1GByte

PC1600 & PC2100

Preliminary Datasheet Revision 0.9

The HYS72Dxx5x0GR are low profile versions of the standard Registered DIMM modules with 1.2”

inch (30,40 mm) height for 1U Server Applications. The Low Profile DIMM versions are available as

32M x 72 (256MB), 64M x 72 (512MB) and 128M x 72 (1 GB).

The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications.

All control and address signals are re-driven on the DIMM using register devices and a PLL for the

clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the

SDRAM timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs

feature serial presence detect based on a serial E2PROM device using the 2-pin I2Cprotocol.The

first 128 bytes are programmed with configuration data and the second 128 bytes are available to

the customer.

• 184-pin Registered 8-Byte Dual-In-Line

DDR-I SDRAM Module for “1U” PC,

Workstation and Server main memory

applications

• One bank 32M ×72, 64M x 72 and two bank

128M ×72 organization

• JEDEC standard Double Data Rate

Synchronous DRAMs (DDR-I SDRAM) with a

single + 2.5 V (±0.2 V) power supply

• Built with DDR-I SDRAMs in 66-Lead TSOPII

package

• Programmable CAS Latency, Burst Length,

and Wrap Sequence (Sequential &

Interleave)

• Auto Refresh (CBR) and Self Refresh

• All inputs and outputs SSTL_2 compatible

• Re-drive for all input signals using register

and PLL devices.

• Serial Presence Detect with E2PROM

• Low Profile Modules form factor:

133.35 mm x 30,40 mm (1.2”) x 4.00 mm

(6,80 mm with stacked components)

• Based on Jedec standard reference card

layouts RawCard “L”, “M”, “N”

• Gold plated contacts

• Performance:

-7 -8 Unit

Component Speed Grade DDR266A DDR200

Module Speed Grade PC2100 PC1600

fCK Clock Frequency (max.) @ CL = 2.5 143 125 MHz

fCK Clock Frequency (max.) @ CL = 2 133 100 MHz

HYS 72Dxx5xxGR-7/8-A

Registered DDR-I SDRAM-Modules

INFINEON Technologies 2 2002-05-08 (0.9)

Ordering Information

Type Compliance Code Description SDRAM

Technology

Module

height

PC2100 (CL=2):

HYS 72D32500GR-7-A PC2100R-20330-L one bank 256 MB Reg. DIMM 256 MBit (x8) 1.2”

HYS 72D64500GR-7-A PC2100R-20330-M one bank 512 MB Reg. DIMM 256 Mbit (x4) 1.2”

HYS 72D128520GR-7-A PC2100R-20330-N two banks 1 GByte Reg. DIMM 256 MBit (x4)

(stacked)

1.2”

PC1600 (CL=2):

HYS 72D32500GR-8-A PC1600R-20220-L one bank 256 MB Reg. DIMM 256 MBit (x8) 1.2”

HYS 72D64500GR-8-A PC1600R-20220-M one bank 512 MB Reg. DIMM 256 Mbit (x4) 1.2”

HYS 72D128520GR-8-A PC1600R-20220-N two banks 1 GByte Reg. DIMM 256 MBit (x4)

(stacked)

1.2”

Notes:

1. All part numbers end with a place code (not shown), designating the silicon-die revision. Reference information available

on request. Example: HYS 72D32500GR-8-A, indicating Rev.A die are used for SDRAM components.

2. The Compliance Code is printed on the module labels and describes the speed sort fe. “PC2100R”, the latencies (f.e.

“20330” means CAS latency = 2.5, trcd latency = 3 and trp latency =3 ) and the Raw Card used for this module

HYS 72Dxx5xxGR-7/8-A

Registered DDR-I SDRAM-Modules

INFINEON Technologies 3 2002-05-08 (0.9)

Pin Definitions and Functions

A0 - A11,A12 Address Inputs

(A12 for 256Mb & 512Mb based modules)

VDD Power (+ 2.5 V)

BA0, BA1 Bank Selects VSS Ground

DQ0 - DQ63 Data Input/Output VDDQ I/O Driver power supply

CB0 - CB7 Check Bits (x72 organization only) VDDID VDD Indentification flag

RAS Row Address Strobe VDDSPD EEPROM power supply

CAS Column Address Strobe VREF I/O reference supply

WE Read/Write Input SCL Serial bus clock

CKE0, CKE1 Clock Enable SDA Serial bus data line

DQS0 - DQS8 SDRAM low data strobes SA0 - SA2 slave address select

CK0, CK0 Differential Clock Input NC no connect

DM0 - DM8

DQS9 - DQS17

SDRAM low data mask/

high data strobes

DU don’t use

CS0 -CS1 Chip Selects RESET Reset pin (forces register

inputs low) *)

*) for detailed description of the Power Up and Power Management on DDR Registered DIMMs see the

Application Note at the end of this datasheet

Address Format

Density Organization Memory

Banks

SDRAMs # of

SDRAMs

# of row/bank/

columns bits

Refresh Period Interval

256 MB 32M x 72 1 (256Mb)

32M x 8

9 13/2/10 8k 64 ms 7.8 µs

512 MB 64M ×72 1 (256Mb)

64M ×4

18 13/2/11 8k 64 ms 7.8 µs

1 GB 128M ×72 2 (256Mb)

64M ×4

(stacked)

13/2/11 8k 64 ms 7.8 µs

HYS 72Dxx5xxGR-7/8-A

Registered DDR-I SDRAM-Modules

INFINEON Technologies 4 2002-05-08 (0.9)

Pin Configuration

PIN# Symbol PIN# Symbol PIN# Symbol Symbol

1 VREF 48 A0 93 VSS 140 DM8/DQS17

2 DQ0 49 CB2 94 DQ4 141 A10

3 VSS 50 VSS 95 DQ5 142 CB6

4 DQ1 51 CB3 96 VDDQ 143 VDDQ

5 DQS0 52 BA1 97 DM0/DQS9 144 CB7

6DQ2 KEY 98 DQ6 KEY

7 VDD 53 DQ32 99 DQ7 145 VSS

8 DQ3 54 VDDQ 100 VSS 146 DQ36

9 NC 55 DQ33 101 NC 147 DQ37

10 RESET 56 DQS4 102 NC 148 VDD

11 VSS 57 DQ34 103 NC 149 DM4/DQS13

12 DQ8 58 VSS 104 VDDQ 150 DQ38

13 DQ9 59 BA0 105 DQ12 151 DQ39

14 DQS1 60 DQ35 106 DQ13 152 VSS

15 VDDQ 61 DQ40 107 DM1/DQS10 153 DQ44

16 DU 62 VDDQ 108 VDD 154 RAS

17 DU 63 WE 109 DQ14 155 DQ45

18 VSS 64 DQ41 110 DQ15 156 VDDQ

19 DQ10 65 CAS 111 CKE1 157 CS0

20 DQ11 66 VSS 112 VDDQ 158 CS1

21 CKE0 67 DQS5 113 NC 159 DM5/DQS14

22 VDDQ 68 DQ42 114 DQ20 160 VSS

23 DQ16 69 DQ43 115 NC / A12 161 DQ46

24 DQ17 70 VDD 116 VSS 162 DQ47

25 DQS2 71 NC 117 DQ21 163 NC

26 VSS 72 DQ48 118 A11 164 VDDQ

27 A9 73 DQ49 119 DM2/DQS11 165 DQ52

28 DQ18 74 VSS 120 VDD 166 DQ53

29 A7 75 DU 121 DQ22 167 NC

30 VDDQ 76 DU 122 A8 168 VDD

31 DQ19 77 VDDQ 123 DQ23 169 DM6/DQS15

32 A5 78 DQS6 124 VSS 170 DQ54

33 DQ24 79 DQ50 125 A6 171 DQ55

34 VSS 80 DQ51 126 DQ28 172 VDDQ

35 DQ25 81 VSS 127 DQ29 173 NC

36 DQS3 82 VDDID 128 VDDQ 174 DQ60

37 A4 83 DQ56 129 DM3/DQS12 175 DQ61

38 VDD 84 DQ57 130 A3 176 VSS

39 DQ26 85 VDD 131 DQ30 177 DM7/DQS16

40 DQ27 86 DQS7 132 VSS 178 DQ62

41 A2 87 DQ58 133 DQ31 179 DQ63

42 VSS 88 DQ59 134 CB4 180 VDDQ

43 A1 89 VSS 135 CB5 181 SA0

44 CB0 90 NC 136 VDDQ 182 SA1

45 CB1 91 SDA 137 CK0 183 SA2

46 VDD 92 SCL 138 CK0 184 VDDSPD

47 DQS8 139 VSS

Note: A12 is used for 256Mbit and 512Mbit based modules only

HYS 72Dxx5xxGR-7/8-A

Registered DDR-I SDRAM-Modules

INFINEON Technologies 5 2002-05-08 (0.9)

Block Diagram: One Bank 32M x 72 DDR-I SDRAM DIMM Module (x8 components)

HYS72D32500GR on Raw Card L

PCK

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DM0/DQS9

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

DM1/DQS10

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

DM2/DQS11

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

DM3/DQS12

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

DM4/DQS13

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

DM5/DQS14

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

DM7/DQS16

RS0

CS CS

DQS0

DQS

DQS4

DQS1 DQS5

DQS

DQS2

DQS

DQS3

DQS

DM6/DQS15

DQS6

DQS7

DQ15

CB4

CB5

CB6

CB7

CB0

CB1

CB2

CB3

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS8

DM8/DQS17

DQS

CK0, CK 0 --------- PLL*

* Wire per Clock Loading Table/Wiring Diagrams

CS0 RS0 -> CS : SDRAMs D0-D8

BA0-BA1 RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D8

A0-A12 RA0-RA12 -> A0-A12: SDRAMs D0 - D8

RAS RRAS -> RAS : SDRAMs D0 - D8

CAS RCAS -> CAS : SDRAMs D0 - D8

CKE0 RCKE0 -> CKE: SDRAMs D0 - D8

WE RWE -> WE : SDRAMs D0 - D8

RESET

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

Notes:

1. DQ-to-I/O wiring may be changed within a byte.

2. DQ/DQS/DM/CKE/S relationships must be

maintained as shown.

3. DQ, DQS, Adress and control resistors: 22 Ohms.

4. VDDID strap connections

STRAP OUT (OPEN): VDD = VDDQ

5. SDRAM placement alternates between the back

and front of the DIMM.

VDD,

VSS

D0 - D8

VDDQ

D0 - D8

VREF

VDDID Strap:seeNote4

VDDSPD EEPROM

Serial PD

A1 A2

SA0 SA1 SA2

SCL

SDA

HYS 72Dxx5xxGR-7/8-A

Registered DDR-I SDRAM-Modules

INFINEON Technologies 6 2002-05-08 (0.9)

Block Diagram: One Bank 64M x 72 DDR-I SDRAM DIMM Modules (x4 comp.)

HYS72D64500GR on Raw Card M

RS0A

DQS4

DQS6

DQS2

DQ0

DQ1

DQ2

DQ3

DQ8

DQ9

DQ10

DQ11

DQ16

DQ17

DQ18

DQ19

DQ24

DQ25

DQ26

DQ27

DQ32

DQ33

DQ34

DQ35

DQ40

DQ41

DQ42

DQ43

DQ56

DQ57

DQ58

DQ59

DQS

DQS0

DQ48

DQ49

DQ50

DQ51

DQS

DQ4

DQ5

DQ6

DQ7

DQ12

DQ13

DQ14

DQ15

DQ20

DQ21

DQ22

DQ23

DQ28

DQ29

DQ30

DQ31

DQ36

DQ37

DQ38

DQ39

DQ44

DQ45

DQ46

DQ47

DQ60

DQ61

DQ62

DQ63

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DM0/DQS9

D10

D11

D12

D13

D14

D16

DQ52

DQ53

DQ54

DQ55

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D15

CB0

CB1

CB2

CB3

DQS

CB4

CB5

CB6

CB7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D17

CS CS

VSS

DQS1

DQS3

DQS8

DQS5

DQS7

DM6/DQS15

DM5/DQS14

DM4/DQS13

DM1/DQS10

DM2/DQS11

DM3/DQS12

DM7/DQS16

DM8/DQS17

RS0B

CK0, CK 0 --------- PLL*

* Wire per Clock Loading Table/Wiring Diagrams

BA0-BA1 RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D17

A0-A11,A12 RA0-RA11,RA12 -> A0-A11,A12: SDRAMs D0 - D17

RAS RRAS -> RAS : SDRAMs D0 - D17

CS0

CAS RCAS -> CAS : SDRAMs D0 - D17

CKE0 RCKE0A -> CKE: SDRAMs D0 - D8

WE RWE -> W E : SDRAMs D0 - D17

RCKEB -> CKE: SDRAMs D9 - D17

PCK

PCK RESET

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

Serial PD

A1 A2

SA0 SA1 SA2

SCL

SDA

Notes:

1. DQ-to-I/O wiring may be changed within a byte.

2. DQ/DQS/DM/CKE/S relationships must be

maintained as shown.

3. DQ, DQS, Adress and control resistors: 22 Ohms.

4. VDDID strap connections

STRAP OUT (OPEN): VDD = VDDQ

5. SDRAM placement alternates between the back

and front of the DIMM.

VDD,

VSS

DDQ

VREF

VDDID Strap: see Note 4

VDDSPD EEPROM

D0 - D17

RS 0 -> CS : SDRAMs D0-D17

HYS 72Dxx5xxGR-7/8-A

Registered DDR-I SDRAM-Modules

INFINEON Technologies 7 2002-05-08 (0.9)

Block Diagram: Two Bank 128M x 72 DDR-I SDRAM DIMM Modules (x4 comp.)

HYS72D128520GR on Raw Card N

RS0

DQS4

DQS6

DQS2

DQ0

DQ1

DQ2

DQ3

DQ8

DQ9

DQ10

DQ11

DQ16

DQ17

DQ18

DQ19

DQ24

DQ25

DQ26

DQ27

DQ32

DQ33

DQ34

DQ35

DQ40

DQ41

DQ42

DQ43

DQ56

DQ57

DQ58

DQ59

DQS

DQS0

DQ48

DQ49

DQ50

DQ51

DQS

DQ4

DQ5

DQ6

DQ7

DQ12

DQ13

DQ14

DQ15

DQ20

DQ21

DQ22

DQ23

DQ28

DQ29

DQ30

DQ31

DQ36

DQ37

DQ38

DQ39

DQ44

DQ45

DQ46

DQ47

DQ60

DQ61

DQ62

DQ63

DQS

DM0/DQS9

D10

D11

D12

D13

D14

D16

DQ52

DQ53

DQ54

DQ55

DQS

D15

CK0, CK 0 --------- PLL*

CS CS

CS S

CS CS

CS1 RS1 -> CS : SDRAMs D18 -D35

BA0-BA1 RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D35

A0-A12 RA0-RA12 -> A0-A12: SDRAMs D0 - D35

RAS RRAS -> RAS :SDRAMsD0-D35

CS0 RS0 -> CS : SDRAMs D0-D17

VSS

DQS1

DQS3

DQS5

DQS7

DM6/DQS15

DM5/DQS14

DM4/DQS13

DM1/DQS10

DM2/DQS11

DM3/DQS12

DM7/DQS16

* Wire per Clock Loading Table/Wiring Diagrams

RS1

CAS RCAS -> CAS :SDRAMsD0-D35

CKE0 RCKE0 -> CKE: SDRAMs D0 - D17

WE RWE -> W E : SDRAMs D0 - D35

R RCKE1 -> CKE: SDRAMs D18 - D35

DQS

D18

DQS

D19

D20

D21

D22

D23

D25

DQS

D24

DQS

D27

DQS

I/O 0

I/O 1

I/O 2

I/O 3

D28

D29

D30

D31

D32

D34

DQS

D33

CB0

CB1

CB2

CB3

DQS

CS DM

DQS8

DQS

D26

CS DM

CB4

CB5

CB6

CB7

DQS

D17

CS DM

DM8/DQS17

DQS

D35

CS DM

CKE1

RESET

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

Notes:

1. DQ-to-I/O wiring may be changed within a byte.

2. DQ/DQS/DM/CKE/S relationships must be

maintained as shown.

3. DQ, DQS, Adress and control resistors: 22 Ohms.

4. VDDID strap connections

STRAP OUT (OPEN): VDD = VDDQ

5. SDRAM placement alternates between the back

and front of the DIMM.

Serial PD

A1 A2

SA0 SA1 SA2

SCL

SDA

VDD,

VSS

VDDQ

VREF

VDDID Strap: see Note 4

VDDSPD EEPROM

D0 - D35

HYS 72Dxx5xxGR-7/8-A

Registered DDR-I SDRAM-Modules

INFINEON Technologies 8 2002-05-08 (0.9)

Absolute Maximum Ratings

Parameter Symbol Limit Values Unit

min. max.

Input / Output voltage relative to VSS VIN, VOUT –0.5 3.6 V

Power supply voltage on VDD/VDDQ to VSS VDD, VDDQ –0.5 3.6 V

Storage temperature range TSTG -55 +150 oC

Power dissipation (per SDRAM component) PD–1W

Data out current (short circuit) IOS –50mA

Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.

Functional operation should be restricted to recommended operation conditions.

Exposure to higher than recommended voltage for extended periods of time affect device reliability

Supply Voltage Levels

Parameter Symbol Limit Values Unit Notes

min. nom. max.

Device Supply Voltage VDD 2.3 2.5 2.7 V -

Output Supply Voltage VDDQ 2.3 2.5 2.7 V 1)

Input Reference Voltage VREF 0.49 x VDDQ 0.5 x VDDQ 0.51 x VDDQ V2)

Termination Voltage VTT VREF –0.04 VREF VREF +0.04 V 3)

EEPROM supply voltage VDDSPD 2.3 2.5 3.6 V

1 Under all conditions, VDDQ must be less than or equal to VDD

2 Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).

VREF is also expected to track noise variations in VDDQ.

3VTT of the transmitting device must track VREF of the receiving device.

DC Operating Conditions (SSTL_2 Inputs)

(VDDQ = 2.5 V, TA=70°C, Voltage Referenced to VSS)

Parameter Symbol Limit Values Unit Notes

min. max.

DC Input Logic High VIH (DC) VREF +0.15 VDDQ +0.3 V 1)

DC Input Logic Low VIL (DC) –0.30 VREF –0.15 V –

Input Leakage Current IIL –5 5 µA1)

Output Leakage Current IOL –5 5 µA2)

1) The relationship between the VDDQ of the driving device and the VREF of the receiving device is what

determines noise margins. However, in the case of VIH (max) (input overdrive), it is the VDDQ of the receiving

device that is referenced. In the case where a device is implemented such that it supports SSTL_2 inputs but

has no SSTL_2 outputs (such as a translator), and therefore no VDDQ supply voltage connection, inputs must

tolerate input overdrive to 3.0 V (High corner VDDQ + 300 mV).

2) For any pin under test input of 0 V ≤VIN ≤VDDQ + 0.3 V. Values are shown per DDR-SDRAM component.

HYS 72Dxx5xxGR-7/8-A

Registered DDR-I SDRAM-Modules

INFINEON Technologies 9 2002-05-08 (0.9)

Operating, Standby and Refresh Currents (PC2100)

Notes

IDD2P mA 2, 4

IDD2F mA 2, 4

IDD2Q mA 2, 4

IDD3P mA 2, 4

IDD5 mA 1, 4

4590

108

5580

1. The module IDD values are calculated from the component IDD datasheet values as:

n * IDDx[component] for single bank modules (n: number of components per module bank)

n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank)

2. The module IDD values are calculated from the component IDD datasheet values as:

n * IDDx[component] for single bank modules (n: number of components per module bank)

2 * n * IDDx[component] for two bank modules (n: number of components per module bank)

3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions

4. DRAM component currents only: module IDD will be measured differently depending upon register and PLL operation currents

5. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C

2205 4410

1710 34204230

720

2340

4590

4230

1GB

x72

2bank

-7

MAX

2970

3330

720

1440

1530 3060

585 1170

1710 3420

360 720

180 360

360 720

900 1800

1080 2160

256MB

x72

1bank

-7

512MB

x72

1bank

-7

MAXMAX

135

315

135

495

1350

1170

IDD7

IDD6

Operating Curr ent: four bank;four bank interleaving with BL=4;

Refer to the following page for detailed test conditions. 2025

Self-Refresh Current:CKE<=0.2V;external clock on;tCK = tCK MIN

Auto-Refresh Current: tRC = tRFC MIN, distributed refresh 1620

1, 3, 450404050

54 108 mA

Symbol UnitParameter/Condition

IDD4W

IDD4R

IDD3N

IDD1

315

270

1800

3330

3690

2, 4

540

1260

540

2790

2610 1, 4

Prechar ge Quiet Standby Current: /CS >= VIH MIN, all banks idle;

CKE >= VIH MIN;tCK = tCK MIN ,address and other control inputs

stable at >= VIH MIN or <=VILMAX; VIN = VREF for DQ, DQS and DM.

IDD0

Operating Current: one bank;active/read/precharge;Burst = 4;

Refer to the following page for detailed test conditions.

Operating Current: one bank;active / precharge;tRC = tRC MIN;tCK =

tCK MIN;DQ, DM, and DQS inputs changing once per clock cycle;

address and control inputs changing once every two clock cycles

Pr echarge Floating Standby Current: /CS >= VIH MIN, all banks idle;

CKE >= VIH MIN;tCK = tCK MIN ,address and other control inputs

changing once per clock cycle, VIN = VREF for DQ, DQS and DM.

Active Power-Down Sta ndby Current: one bank active;power-down

mode;CKE <=VILMAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and

DM.

Active Standby Current: one bank active;active / precharge;CS >= VIH

MIN;CKE >= VIH MIN;tRC = tR AS MAX; tCK = tC K MIN ;DQ, DM, and

DQS inputs changing twice per clock cycle;address and control inputs

changing once per clock cycle

Operating Current: one bank active;Burst = 2;reads;continuous burst;

address and control inputs changing once per clock cycle;50% of data

outputs changing on every clock edge;CL = 2 for DDR200, and

DDR266A, CL=3 for DDR333;tC K = tCK MIN;IOUT = 0mA

Operating Current: one bank active;Burst = 2;writes;continuous burst;

address and control inputs changing once per clock cycle;50% of data

outputs changing on every clock edge;CL = 2 for DDR200, and

DDR266A, CL=3 for DDR333;tCK = tCK MIN

3240

2340

2700

990

mA 1, 3, 4

2, 4

1260

630

mA 1, 4

270

mA 1, 3, 4

1980 mA

630

256MB

x72

1bank

-8

512MB

x72

1bank

-8

1GB

x72

2bank

-8

Prec harge Power -Down Standby Current: all banks idle;power-down

mode;CKE <=VILMAX; tCK = tCK MIN

1620

MAXMAXMAX

810

900

HYS 72Dxx5xxGR-7/8-A
Registered DDR-I SDRAM-Modules
INFINEON Technologies 10 2002-05-08 (0.9)
Electrical Characteristics & AC Timing for DDR-I components
(for reference only)
(0 °C≤ TA≤ 70 °C; VDDQ =2.5V± 0.2V;VDD =2.5V± 0.2V)
Symbol Parameter
DDR266A
-7
DDR200
-8 Unit Notes
Min Max Min Max
tAC DQ output access time from CK/CK −0.75 +0.75 −0.8 +0.8 ns 1-4
tDQSCK DQS output access time from CK/CK −0.75 +0.75 −0.8 +0.8 ns 1-4
tCH CK high-level width 0.45 0.55 0.45 0.55 tCK 1-4
tCL CK low-level width 0.45 0.55 0.45 0.55 tCK 1-4
tHP Clock Half Period min (tCL, tCH) min (tCL, tCH) ns 1-4
tCK Clock cycle time
CL = 2.5 7 12 8 12 ns 1-4
tCK CL = 2.0 7.5 12 10 12 ns 1-4
tDH DQ and DM input hold time 0.5 0.6 ns 1-4
tDS DQ and DM input setup time 0.5 0.6 ns 1-4
tIPW Control and Addr. input pulse width (each input) 2.2 2.5 ns 1, 10
tDIPW DQ and DM input pulse width (each input) 1.75 2 ns 1-4,11
tHZData-out high-impedence time from CK/CK −0.75 +0.75 −0.8 +0.8 ns 1-4, 5
tLZData-out low-impedence time from CK/CK −0.75 +0.75 −0.8 +0.8 ns 1-4, 5
tDQSS Write command to 1st DQS latching transition 0.75 1.25 0.75 1.25 tCK 1-4
tDQSQ
DQS-DQ skew
(for DQS & associated DQ signals) +0.5 +0.6 ns 1-4
tQHS Data hold skew factor + 0.75 + 1.0 ns 1-4
tQH Data Output hold time from DQS tHP-tQHS tHP-tQHS ns 1-4
tDQSL,H DQS input low (high) pulse width (write cycle) 0.35 0.35 tCK 1-4
tDSS DQS falling edge to CK setup time (write cycle) 0.2 0.2 tCK 1-4
tDSH DQS falling edge hold time from CK (write cycle) 0.2 0.2 tCK 1-4
tMRD Mode register set command cycle time 14 16 ns 1-4
tWPRES Write preamble setup time 0 0 ns 1-4, 7
tWPST Write postamble 0.40 0.60 0.40 0.60 tCK 1-4, 6
tWPRE Write preamble 0.25 0.25 tCK 1-4
tIS Address and control input setup time fast slew rate 0.9 1.1 ns
2-4,
10,11
slow slew rate 1.0 1.1 ns
tIH Address and control input hold time
fast slew rate 0.9 1.1 ns
slow slew rate 1.0 1.1 ns
tRPRE Read preamble 0.9 1.1 0.9 1.1 tCK 1-4
tRPST Read postamble 0.40 0.60 0.40 0.60 tCK 1-4
tRAS Active to Precharge command 45 120,000 50 120,000 ns 1-4
tRC Active to Active/Auto-refresh command period 65 70 ns 1-4
tRFC
Auto-refresh to Active/Auto-refresh
command period 75 80 ns 1-4
tRCD Active to Read or Write delay 20 20 ns 1-4

HYS 72Dxx5xxGR-7/8-A
Registered DDR-I SDRAM-Modules
INFINEON Technologies 11 2002-05-08 (0.9)
tRP Precharge command period 20 20 ns 1-4
tRRD Active bank A to Active bank B command 15 15 ns 1-4
tWR Write recovery time 15 15 ns 1-4
tDAL
Auto precharge write recovery
+ precharge time (twr/tck) + (trp/tck) tCK 1-4,9
tWTR Internal write to read command delay 1 1 tCK 1-4
tXSNR Exit self-refresh to non-read command 75 80 ns 1-4
tXSRD Exit self-refresh to read command 200 200 tCK 1-4
tREFI Average Periodic Refresh Interval 256Mb based 7.8 7.8 µs1-4,8
1. Input slew rate >=1V/ns for DDR266 and = 1V/ns for DDR200.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK,isV
REF. CK/CK slew rate are >= 1.0 V/ns.
3. Inputs are not recognized as valid until VREF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT.
5. tHZand tLZtransitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Zto logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
10. These parameters guarantee device timing, but they are not necessarily tested on each device
11. Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and <1V/ns for command/address and CK & CK slew rate >1.0 V/
ns, measured between VOH(ac) and VOL(ac)
Electrical Characteristics & AC Timing for DDR-I components
(for reference only)
(0 °C≤ TA≤ 70 °C; VDDQ =2.5V± 0.2V;VDD =2.5V± 0.2V)
Symbol Parameter
DDR266A
-7
DDR200
-8 Unit Notes
Min Max Min Max

HYS 72Dxx5xxGR-7/8-A

Registered DDR-I SDRAM-Modules

INFINEON Technologies 12 2002-05-08 (0.9)

SPD Codes

256MB

x72

1bank

-7

256MB

x72

1bank

-8

512MB

x72

1bank

-7

512MB

x72

1bank

-8

1GB

x72

2bank

-7

1GB

x72

2bank

-8

HEXHEXHEXHEXHEXHEX

0 Number of SPD Bytes 128 80 80 80 80 80 80

1 Total Bytes in Serial PD 256 08 08 08 08 08 08

2 MemoryType DDR-SDRAM 070707070707

3 Number of Row Addresses 13 0D 0D 0D 0D 0D 0D

4 Number of Column Addresses 10 / 11 0A 0A 0B 0B 0B 0B

5 Number of DIMM Banks 1 / 2 01 01 01 01 02 02

6 Module Data Width x72 48 48 48 48 48 48

7 Module Data Width (cont’d) 0 00 00 00 00 00 00

8 Module Interface Levels SSTL_2.5 04 04 04 04 04 04

9 SDRAM Cycle Time at CL = 2.5 7ns / 8ns 70 80 70 80 70 80

10 Access Time from Clock at CL = 2.5 0.75ns / 0.8ns 75 80 75 80 75 80

11 DIMMConfig ECC 020202020202

12 Refresh Rate/Type Self-Refresh, 7.8ms 82 82 82 82 82 82

13 SDRAMWidth,Primary x8/x4 080804040404

14 Error Checking SDRAM Data Width na 08 08 04 04 04 04

15 Minimum Clock Delay for Back-to-Back

Random Column Address tccd=1CLK 010101010101

16 Burst Length Supported 2, 4 & 8 0E 0E 0E 0E 0E 0E

17 Number of SDRAM Banks 4 04 04 04 04 04 04

18 Supported CAS Latencies CAS latency = 2 & 2.5 0C 0C 0C 0C 0C 0C

19 CS Latencies CS latency = 0 01 01 01 01 01 01

20 WE Latencies Write latency = 1 02 02 02 02 02 02

21 SDRAM DIMM Module Attributes registered 26 26 26 26 26 26

22 SDRAM Device Attributes: General Concurrent Auto

Precharge C0 C0 C0 C0 C0 C0

23 Min. Clock Cycle Time at CAS Latency = 2 7.5ns / 10ns 75 A0 75 A0 75 A0

24 Access Time from Clock for CL = 2 0.75ns / 0.8ns 75 80 75 80 75 80

25 Minimum Clock Cycle Time at CL = 1.5 not supported 00 00 00 00 00 00

26 Access Time from Clock at CL = 1.5 not supported 00 00 00 00 00 00

27 Minimum Row Precharge Time 20ns 50 50 50 50 50 50

28 Minimum Row Act. to Row Act. Delay tRRD 15ns 3C 3C 3C 3C 3C 3C

29 Minimum RAS to CAS Delay tRCD 20ns 50 50 50 50 50 50

30 Minimum RAS Pulse Width tRAS 45ns / 50ns 2D 32 2D 32 2D 32

31 Module Bank Density (per bank) 256MByte / 512MByte 40 40 80 80 80 80

32 Addr. and Command Setup Time 0.9ns / 1.1ns 90 B0 90 B0 90 B0

33 Addr. and Command Hold Time 0.9ns / 1.1ns 90 B0 90 B0 90 B0

34 Data Input Setup Time 0.5ns / 0.6ns 50 60 50 60 50 60

35 Data Input Hold Time 0.5ns / 0.6ns 50 60 50 60 50 60

36-40 Superset Information – 00 00 00 00 00 00

41 Minimum Core Cycle Time tRC 65ns / 70ns 41 46 41 46 41 46

42 Min. Auto Refresh Cmd Cycle Time tRFC 75ns / 80ns 4B 50 4B 50 4B 50

43 Maximum Clock Cycle Time tck 12ns 30 30 30 30 30 30

44 Max. DQS-DQ Skew tDQSQ 0.5ns / 0.6ns 32 3C 32 3C 32 3C

45 X-Factor tQHS 0.75ns / 1.0ns 75 A0 75 A0 75 A0

46-61 Superset Information – 00 00 00 00 00 00

62 SPDRevision Revision0.0 000000000000

63 Checksum for Bytes 0 - 62 – CA BF 03 F8 04 F9

64 Manufacturers JEDEC ID Code – C1 C1 C1 C1 C1 C1

65-71 Manufacturer – INFI-

NEON

INFI-

NEON

INFI-

NEON

INFI-

NEON

INFI-

NEON

INFI-

NEON

72 Module Assembly Location –

73-90 Module Part Number –

91-92 Module Revision Code –

93-94 Module Manufacturing Date –

95-98 Module Serial Number –

99-127 – –

Byte# Description

HYS 72Dxx5xxGR-7/8-A

Registered DDR-I SDRAM-Modules

INFINEON Technologies 13 2002-05-08 (0.9)

Package Outlines Raw Card L

Module Package

DDR-I Registered DIMM Modules 1.2” Low Profile Raw Card L

256MB (one physical bank, 9 components)

note: all outline dimensions and tolerances are in accordance with the JEDEC standard

L-DIM-184-13 Raw Card L Reg.

*) on ECC modules only

Detail of Contacts A

2.5

1.27

0.20

+0.05

+0.20

+0.15

1.27

4.0 max.

+0.1

Detail of Contacts B

3.8 typ.

2.175

6.35

1.8

0.9R

PLL

133.35

2.3 typ.

64.77

2.3 typ.

1.2"/ 30.4 max.

pin 1

+0.15

6.62

49.53

4.0

Front View

144 145 184

17.80

10.0

pin 93

2.5D

Backside View

HYS 72Dxx5xxGR-7/8-A

Registered DDR-I SDRAM-Modules

INFINEON Technologies 14 2002-05-08 (0.9)

Package Outlines Raw Card M

L-DIM-184-12 Raw Card M Reg.

*) on ECC modules only

Detail of Contacts A

2.5

1.27

0.20

+0.05

+0.20

+0.15

1.27

4.0 max.

+0.1

Detail of Contacts B

3.8 typ.

2.175

6.35

1.8

0.9R

PLL

133.35

2.3 typ.

64.77

2.3 typ.

1.2"/ 30.4 max.

pin 1

+0.15

6.62

49.53

4.0

Front View

144 145 184

17.80

10.0

pin 93

2.5D

Backside View

Module Package

DDR-I Registered DIMM Modules 1.2” Low Profile Raw Card M

512 MB (one physical bank, 18 components)

note: all outline dimensions and tolerances are in accordance with the JEDEC standard

HYS 72Dxx5xxGR-7/8-A

Registered DDR-I SDRAM-Modules

INFINEON Technologies 15 2002-05-08 (0.9)

Package Outlines Raw Card with stacked components

Module Package

DDR-I Registered DIMM Modules 1.2” Low Profile Raw Card N

1GB (two physical banks, 36 components)

note: all outline dimensions and tolerances are in accordance with the JEDEC standard

L-DIM-184-14 Raw Card Reg.

*) on ECC modules only

Detail of Contacts A

2.5

1.27

0.20

+0.05

+0.20

+0.15

1.27

6.8 max.

+0.1

Detail of Contacts B

3.8 typ.

2.175

6.35

1.8

0.9R

PLL

133.35

2.3 typ.

64.77

2.3 typ.

1.2"/30.4max.

pin 1

+0.15

6.62

49.53

4.0

Front View

144 145 184

17.80

10.0

pin 93

2.5D

Backside View

HYS 72Dxx5xxGR-7/8-A

Registered DDR-I SDRAM-Modules

INFINEON Technologies 16 2002-05-08 (0.9)

APPLICATION NOTE:

Power Up and Power Management on DDR Registered DIMMs

(according to JEDEC ballot JC-42.5 Item 1173)

184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up

and to minimize power consumption during low power mode. One feature is externally controlled via a system-

generated RESET signal;the second is based on module detection of the input clocks. These enhancements

permit the modules to power up with SDRAM outputs in a High-Zstate (eliminating risk of high current dissipa-

tions and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-

Locked Loop) when the memory is in Self-Refresh mode.

The new RESET pin controls power dissipation on the module’s registers and ensures that CKE and other

SDRAM inputs are maintained at a valid ‘low’ level during power-up and self refresh. When RESET is at a low

level, all the register outputs are forced to a low level, and all differential register input receivers are powered

down, resulting in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven

from the system as an asynchronous signal according to the attached details. Using this function also permits the

system and DIMM clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs

stay in Self Refresh mode.

ThefunctionforRESETisasfollows:

As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are

maintained low at the SDRAM pins (CKE being one of the 'Q'signals at the register output). Holding CKE low

maintains a high impedance state on the SDRAM DQ, DQS and DM outputs — where they will remain until acti-

vated by a valid ‘read’ cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable.

The DDR PLL devices automatically detect clock activity above 20MHz. When an input clock frequency of

20MHz or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operat-

ing frequency at which all specifications will be met is 95MHz). If the clock input frequency drops below 20MHz

(actual detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are

Outputs

RESET CK CK Data in (D) Data out (Q)

H Rising Falling H H

H Rising Falling L L

H L or H L or H XQo

HHighZHigh ZX

Illegal input

conditions

LXor Hi-ZXor Hi-ZXor Hi-ZL

X:Don’tcare,Hi-Z: High Impedance, Qo: Data latched at the previous of CK

risning and CK falling

HYS 72Dxx5xxGR-7/8-A

Registered DDR-I SDRAM-Modules

INFINEON Technologies 17 2002-05-08 (0.9)

made High-Z, and the differential inputs are powered down — resulting in a total PLL current consumption of less

than 1mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it is

tied inactive on the DIMM.

This application note describes the required and optional system sequences associated with the DDR Regis-

tered DIMM 'RESET'function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for

a 2-bank DIMM. Because RESET applies to all DIMM register devices, it is therefore not possible to uniquely

control CKE to one physical DIMM bank through the use of the RESET pin.

Power-Up Sequence with RESET —Required

1. The system sets RESET at a valid low level.

This is the preferred default state during power-up. This input condition forces all register outputs to a low

state independent of the condition on the register inputs (data and clock), ensuring that CKE is at a stable

low-level at the DDR SDRAMs.

2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR

SDRAMs.

3. Stabilization of Clocks to the SDRAM

The system must drive clocks to the application frequency (PLL operation is not assured until the input clock

reaches 20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,

and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM

PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. When

a stable clock is present at the SDRAM input (driven from the PLL), the DDR SDRAM requires 200 µsec prior

to SDRAM operation.

4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM con-

nector).

CKE must be maintained low and all other inputs should be driven to a known state. In general these com-

mands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command (with

CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally this would be a

‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be consistent

with the state of the register outputs.

5. The system switches RESET toalogic‘high’level.

The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,

setting the RESET timing in relation to a specific clock edge is not required (during this period, register inputs

must remain stable).

6. The system must maintain stable register inputs until normal register operation is attained.

The registers have an activation time that allows their clock receivers, data input receivers, and output drivers

sufficient time to be turned on and become stable. During this time the system must maintain the valid logic

levels described in step 5. It is also a functional requirement that the registers maintain a low state at the CKE

outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time

(t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to

accept an input signal, is specified in the register and DIMM do-umentation.

7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDEC-

pproved initialization sequence).

Self Refresh Entry (RESET low, clocks powered off) — Optional

Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down

and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking.

Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption

(RESET low deactivates register CK and CK, data input receivers, and data output drivers).

HYS 72Dxx5xxGR-7/8-A

Registered DDR-I SDRAM-Modules

INFINEON Technologies 18 2002-05-08 (0.9)

1. The system applies Self Refresh entry command.

(CKE→Low, CS→Low, RAS → Low, CAS→Low, WE→High)

Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a

Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input

conditions to the SDRAM are Don’t Cares— with the exception of CKE.

2. The system sets RESET at a valid low level.

This input condition forces all register outputs to a low state, independent of the condition on the registerm

inputs (data and clock), and ensures that CKE, and all other control and address signals, are a stable low-

level at the DDR SDRAMs. Since the RESET signal is asynchronous, setting the RESET timing in relation to

a specific clock edge is not required.

3. The system turns off clock inputs to the DIMM. (Optional)

a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Zclock

inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the reg-

ister (t (INACT) ). The deactivate time defines the time in which the clocks and the control and address sig-

nals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM

documentation.

b. The system may release DIMM address and control inputs to High-Z.

This can be done after the RESET deactivate time of the register. The deactivate time defines the time in

which the clocks and the control and the address signals must maintain valid levels after RESET low has

been applied. It is highly recommended that CKE continue to remain low during this operation.

4. The DIMM is in lowest power Self Refresh mode.

Self Refresh Exit (RESET low, clocks powered off) — Optional

1. Stabilization of Clocks to the SDRAM.

The system must drive clocks to the application frequency (PLL operation is not assured until the input clock

reaches ~20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices,

and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM

PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds.

2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM con-

nector).

CKE must be maintained low and all other inputs should be driven to a known state. In general these com-

mands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command (with

CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence (ideally this would

be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs, to be con-

sistent with the state of the register outputs.

3. The system switches RESET toalogic‘high’level.

The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,

RESET timing relationship to a specific clock edge is not required (during this period, register inputs must

remain stable).

4. The system must maintain stable register inputs until normal register operation is attained.

The registers have an activation time that allows the clock receivers, input receivers, and output drivers suffi-

cient time to be turned on and become stable. During this time the system must maintain the valid logic levels

described in Step 2. It is also a functional requirement that the registers maintain a low state at the CKE out-

puts to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t

(ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to

accept an input signal, is specified in the register and DIMM do-umentation.

5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure.

Self Refresh Entry (RESET low, clocks running) — Optional

HYS 72Dxx5xxGR-7/8-A

Registered DDR-I SDRAM-Modules

INFINEON Technologies 19 2002-05-08 (0.9)

Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh,

this is an alternate operating mode for these DIMMs.

1. System enters Self Refresh entry command.

(CKE→Low, CS→Low, RAS→Low, CAS→Low, WE→High)

Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a

Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input

conditions to the SDRAM are Don’t Cares — with the exception of CKE.

2. The system sets RESET at a valid low level.

This input condition forces all register outputs to a low state, independent of the condition on the data and

clock register inputs, and ensures that CKE is a stable low-level at the DDR SDRAMs.

3. The system may release DIMM address and control inputs to High-Z.

This can be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time describes

the time in which the clocks and the control and the address signals must maintain valid levels after RESET

low has been applied. It is highly recommended that CKE continue to remain low during the operation.

4. The DIMM is in a low power, Self Refresh mode.

Self Refresh Exit (RESET low, clocks running) — Optional

1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM con-

nector).

CKE must be maintained low and all other inputs should be driven to a known state. In general these com-

mands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’ command (with

CKE low), as this is the first command defined by the Self Refresh Exit sequence (ideally this would be a

‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be consistent

with the state of the register outputs.

2. The system switches RESET to a logic 'high' level.

The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,

it does not need to be tied to a particular clock edge (during this period, register inputs must continue to

remain stable).

3. The system must maintain stable register inputs until normal register operation is attained.

The registers have an activation time that allows the clock receivers, input receivers, and output drivers suffi-

cient time to be turned on and become stable. During this time the system must maintain the valid logic levels

described in Step 1. It is also a functional requirement that the registers maintain a low state at the CKE out-

puts in order to guarantee that the DDR SDRAMs continue to receive a low level on CKE. This activation

time, from asynchronous switching of RESET from low to high, until the registers are stable and ready to

accept an input signal, is t (ACT ) as specified in the register and DIMM documentation.

4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure.

Self Refresh Entry/Exit (RESET high, clocks running) — Optional

As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification

explains in detail the method for entering and exiting Self Refresh for this case.

Self Refresh Entry (RESET high, clocks powered off) — Not Permissible

In order to maintain a valid low level on the register output, it is required that either the clocks be running and the

system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the

HYS 72Dxx5xxGR-7/8-A

Registered DDR-I SDRAM-Modules

INFINEON Technologies 20 2002-05-08 (0.9)

sequence defined in this application note. In the case where RESET remains high and the clocks are powered

off, the PLL drives a High-Zclock input into the register clock input. Without the low level on RESET an unknown

DIMM state will result.