CMOS Low Cost, 10-Bit Multiplying DAC AD7533 FEATURES GENERAL DESCRIPTION Low cost 10-bit DAC Low cost AD7520 replacement Linearity: 1/2 LSB, 1 LSB, or 2 LSB Low power dissipation Full 4-quadrant multiplying DAC CMOS/TTL direct interface Latch free (protection Schottky not required) Endpoint linearity The AD7533 is a low cost, 10-bit, 4-quadrant multiplying DAC manufactured using an advanced thin-film-on-monolithicCMOS wafer fabrication process. Pin and function equivalent to the AD7520 industry standard, the AD7533 is recommended as a lower cost alternative for old AD7520 sockets or new 10-bit DAC designs. AD7533 application flexibility is demonstrated by its ability to interface to TTL or CMOS, operate on 5 V to 15 V power, and provide proper binary scaling for reference inputs of either positive or negative polarity. APPLICATIONS Digitally controlled attenuators Programmable gain amplifiers Function generation Linear automatic gain controls FUNCTIONAL BLOCK DIAGRAM 10k VREF 10k 10k 20k 20k 20k 20k S1 S2 S3 SN 20k IOUT2 IOUT1 BIT 1 (MSB) BIT 2 BIT 3 BIT 10 (LSB) DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE) RFB 01134-001 10k Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved. AD7533 TABLE OF CONTENTS Features .............................................................................................. 1 Circuit Description............................................................................7 Applications....................................................................................... 1 General Circuit Information........................................................7 General Description ......................................................................... 1 Equivalent Circuit Analysis .........................................................7 Functional Block Diagram .............................................................. 1 Operation............................................................................................8 Revision History ............................................................................... 2 Unipolar Binary Code ..................................................................8 Specifications..................................................................................... 3 Bipolar (Offset Binary) Code.......................................................8 Absolute Maximum Ratings............................................................ 4 Applications........................................................................................9 ESD Caution.................................................................................. 4 Outline Dimensions ....................................................................... 10 Terminology ...................................................................................... 5 Ordering Guide .......................................................................... 12 Pin Configurations and Function Descriptions ........................... 6 REVISION HISTORY 3/07--Rev. B to Rev. C Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 4 Changes to Figure 13, Figure 14, and Figure 17 ........................... 9 Updated Outline Dimensions ....................................................... 10 Changes to Ordering Guide .......................................................... 12 3/04--Rev. 0 to Rev. A Changes to Specifications.................................................................2 Changes to Absolute Maximum Ratings........................................3 Changes to Ordering Guide .............................................................3 Updated Outline Dimensions..........................................................7 1/06--Rev. A to Rev. B Updated Format..................................................................Universal Changes to Absolute Maximum Ratings ....................................... 4 Added Pin Configurations and Function Descriptions Section................................................ 6 Updated Outline Dimensions ....................................................... 10 Changes to Ordering Guide .......................................................... 12 Rev. C | Page 2 of 12 AD7533 SPECIFICATIONS VDD = 15 V, VOUT1 = VOUT2 = 0 V, VREF = 10 V, unless otherwise noted. Table 1. Parameter STATIC ACCURACY Resolution Relative Accuracy 1 AD7533JN, AD7533AQ, AD7533SQ, AD7533JP AD7533KN, AD7533BQ, AD7533KP, AD7533TE AD7533LN, AD7533CQ, AD7533UQ DNL Gain Error 2, 3 Supply Rejection 4 Gain/VDD Output Leakage Current IOUT1 IOUT2 DYNAMIC ACCURACY Output Current Settling Time Feedthrough Error Propagation Delay Glitch Impulse REFERENCE INPUT Input Resistance (VREF) ANALOG OUTPUTS Output Capacitance CIOUT1 CIOUT2 CIOUT1 CIOUT2 DIGITAL INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Leakage Current (IIN) Input Capacitance (CIN) POWER REQUIREMENTS VDD VDD Ranges5 IDD TA = 25C TA = Operating Range 10 Bits 10 Bits 0.2% FSR maximum 0.2% FSR maximum 0.1% FSR maximum 0.1% FSR maximum 0.05% FSR maximum 1 LSB maximum 1% FS maximum 0.05% FSR maximum 1 LSB maximum 1% FS maximum Digital input = VINH 0.001%/% maximum 0.001%/% maximum Digital inputs = VINH, VDD = 14 V to 17 V 5 nA maximum 5 nA maximum 200 nA maximum 200 nA maximum Digital inputs = VINL, VREF = 10 V Digital inputs = VINH, VREF = 10 V 600 ns maximum4 800 ns 5 0.05% FSR maximum5 0.1% FSR maximum5 To 0.05% FSR; RLOAD = 100 , digital inputs = VINH to VINL or VINL to VINH Digital inputs = VINL, VREF = 10 V, 100 kHz sine wave 100 ns typical 100 nV-s typical 100 ns typical 100 nV-s typical 5 k min, 20 k maximum 5 k min, 20 k maximum 6 11 k nominal 50 pF maximum5 20 pF maximum5 30 pF maximum5 50 pF maximum5 100 pF maximum5 35 pF maximum5 35 pF maximum5 100 pF maximum5 Digital inputs = VINH 2.4 V minimum 0.8 V maximum 1 A maximum 8 pF maximum5 2.4 V minimum 0.8 V maximum 1 A maximum 8 pF maximum5 15 V 10% 5 V to 16 V 2 mA maximum 25 A maximum 15 V 10% 5 V to 16 V 2 mA maximum 50 A maximum 1 FSR = full-scale range. Full scale (FS) = VREF. 3 Maximum gain change from TA = 25C to TMIN or TMAX is 0.1% FSR. 4 AC parameter, sample tested to ensure specification compliance. 5 Guaranteed, not tested. 6 Absolute temperature coefficient is approximately -300 ppm/C. 2 Rev. C | Page 3 of 12 Test Conditions Digital inputs = VINL VIN = 0 V and VDD Rated accuracy Functionality with degraded performance Digital inputs = VINL or VINH D Digital inputs over VIN AD7533 ABSOLUTE MAXIMUM RATINGS TA = 25 C unless otherwise noted. Table 2. Parameter VDD to GND RFB to GND VREF to GND Digital Input Voltage Range IOUT1, IOUT2 to GND Power Dissipation (Any Package) To 75C Derates above 75C by Operating Temperature Range Plastic (JN, JP, KN, KP, LN Versions) Hermetic (AQ, BQ, CQ Versions) Hermetic (SQ, TE, UQ Versions) Storage Temperature Range Lead Temperature (Soldering, 10 sec) Rating -0.3 V, +17 V 25 V 25 V -0.3 V to VDD + 0.3 V -0.3 V to VDD 450 mW 6 mW/C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION -40C to +85C -40C to +85C -55C to +125C -65C to +150C 300C Rev. C | Page 4 of 12 AD7533 TERMINOLOGY Relative Accuracy Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for ideal zero and full scale and is expressed in % of full-scale range or (sub) multiples of 1 LSB. Resolution Value of the LSB. For example, a unipolar converter with n bits has a resolution of (2-n) (VREF). A bipolar converter of n bits has a resolution of [2-(n-1)] (VREF). Resolution in no way implies linearity. Settling Time Time required for the output function of the DAC to settle to within 1/2 LSB for a given digital input stimulus, that is, 0 to full scale. Gain Error Gain error is a measure of the output error between an ideal DAC and the actual device output. It is measured with all 1s in the DAC after offset error is adjusted out and is expressed in LSBs. Gain error is adjustable to zero with an external potentiometer. Feedthrough Error Error caused by capacitive coupling from VREF to output with all switches off. Output Capacitance Capacity from IOUT1 and IOUT2 terminals to ground. Output Leakage Current Current that appears on IOUT1 terminal with all digital inputs low or on IOUT2 terminal when all inputs are high. Rev. C | Page 5 of 12 AD7533 VREF 14 VDD GND 3 AD7533 TOP VIEW 13 BIT 10 (LSB) BIT 2 5 (Not to Scale) 12 BIT 9 BIT 3 6 11 BIT 8 BIT 4 7 10 BIT 7 BIT 5 8 9 BIT 6 Figure 3. 16-Lead SOIC Pin Configuration IOUT1 1 16 RFB IOUT2 2 15 VREF GND 3 AD7533 14 VDD TOP VIEW 13 BIT 10 (LSB) BIT 2 5 (Not to Scale) 12 BIT 9 BIT 4 7 10 BIT 7 BIT 5 8 9 BIT 6 RFB NC VREF BIT 9 14 BIT 8 10 11 12 13 GND 4 BIT 1 (MSB) 5 NC 6 BIT 2 7 BIT 3 8 3 2 1 20 19 PIN 1 INDENTFIER AD7533 18 VDD 17 BIT 10 (LSB) 16 NC TOP VIEW (Not to scale) 15 BIT 9 14 BIT 8 9 10 11 12 13 Figure 6. 20-Lead PLCC Pin Configuration 01134-004 11 BIT 8 NC 15 NC = NO CONNECT BIT 1 (MSB) 4 BIT 3 6 BIT 10 (LSB) 16 Figure 5. 20-Terminal LCC Pin Configuration 01134-003 BIT 1 (MSB) 4 VDD 01134-006 RFB 15 9 VREF 16 IOUT2 2 NC = NO CONNECT 18 17 BIT 7 Figure 2. 16-Lead PDIP Pin Configuration IOUT1 1 IOUT1 BIT 3 8 BIT 7 BIT 6 BIT 6 9 RFB BIT 5 8 TOP VIEW (Not to Scale) BIT 2 7 BIT 6 BIT 7 NC 10 NC 6 NC BIT 4 7 AD7533 NC BIT 8 20 19 GND 4 BIT 5 11 1 BIT 1 (MSB) 5 01134-002 BIT 3 6 2 01134-005 TOP VIEW 13 BIT 10 (LSB) BIT 2 5 (Not to Scale) 12 BIT 9 BIT 1 (MSB) 4 3 BIT 4 VDD AD7533 IOUT2 VREF 14 GND 3 IOUT1 RFB 15 BIT 5 16 IOUT2 2 BIT 4 IOUT1 1 IOUT2 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. 16-Lead CERDIP Pin Configuration Table 3. Pin Function Descriptions Pin Number 16-Lead PDIP, SOIC, CERDIP 20-Lead LCC, PLCC 1 2 2 3 Mnemonic IOUT1 IOUT2 3 4 to 13 14 4 5, 7 to 10, 12 to 15, 17 18 GND BIT 1 to BIT 10 VDD 15 16 19 20 VREF RFB NA 1, 6, 11, 16 NC Description DAC Current Output. DAC Analog Ground. This pin should normally be tied to the analog ground of the system. Ground. MSB to LSB. Positive Power Supply Input. These parts can be operated from a supply of 5 V to 16 V. DAC Reference Voltage Input Terminal. DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting RFB to external amplifier output. No Connect. Rev. C | Page 6 of 12 AD7533 CIRCUIT DESCRIPTION V+ 1 The AD7533 is a 10-bit multiplying DAC that consists of a highly stable thin-film R-2R ladder and ten CMOS current switches on a monolithic chip. Most applications require the addition of only an output operational amplifier and a voltage or current reference. DTL/TTL/ CMOS INPUT 10k 10k 20k 20k 20k S1 S2 S3 SN IOUT1 BIT 3 BIT 10 (LSB) DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE) RFB 01134-001 BIT 2 7 8 9 IOUT1 EQUIVALENT CIRCUIT ANALYSIS IOUT2 BIT 1 (MSB) 5 TO LADDER Figure 8. CMOS Switch 20k 10k 6 IOUT2 10k 20k 4 250 2 The simplified D/A circuit is shown in Figure 7. An inverted R- 2R ladder structure is used, that is, the binarily weighted currents are switched between the IOUT1 and IOUT2 bus lines, thus maintaining a constant current in each ladder leg independent of the switch state. VREF 3 01134-007 GENERAL CIRCUIT INFORMATION The equivalent circuits for all digital inputs high and digital inputs low are shown in Figure 9 and Figure 10. In Figure 9 with all digital inputs low, the reference current is switched to IOUT2. The current source ILEAKAGE is composed of surface and junction leakages to the substrate, while the I/1024 current source represents a constant 1-bit current drain through the termination resistor on the R-2R ladder. The on capacitance of the output N channel switch is 100 pF, as shown on the IOUT2 terminal. The off switch capacitance is 35 pF, as shown on the IOUT1 terminal. Analysis of the circuit for all digital inputs high, as shown in Figure 10, is similar to Figure 9; however, the on switches are now on Terminal IOUT1. Therefore, there is the 100 pF at that terminal. Figure 7. Functional Diagram RFB R IOUT1 R 10k ILEAKAGE 35pF ILEAKAGE 100pF IREF VREF R IOUT2 I/1024 01134-008 One of the CMOS current switches is shown in Figure 8. The geometries of Device 1, Device 2, and Device 3 are optimized to make the digital control inputs DTL/TTL/CMOS compatible over the full military temperature range. The input stage drives two inverters (Device 4, Device 5, Device 6, and Device 7), which in turn drive the two output N channels. The on resistances of the switches are binarily sealed so that the voltage drop across each switch is the same. For example, Switch 1 in Figure 8 is designed for an on resistance of 20 , Switch 2 for 40 , and so on. For a 10 V reference input, the current through Switch 1 is 0.5 mA, the current through Switch 2 is 0.25 mA, and so on, thus maintaining a constant 10 mV drop across each switch. It is essential that each switch voltage drop be equal if the binarily weighted current division property of the ladder is to be maintained. Figure 9. Equivalent Circuit--All Digital Inputs Low RFB R IREF VREF R 10k R IOUT1 I/1024 ILEAKAGE 100pF ILEAKAGE 35pF Figure 10. Equivalent Circuit--All Digital Inputs High Rev. C | Page 7 of 12 01134-009 IOUT2 AD7533 OPERATION UNIPOLAR BINARY CODE BIPOLAR (OFFSET BINARY) CODE Table 4. Unipolar Binary Operation (2-Quadrant Multiplication) Table 5. Unipolar Binary Operation (4-Quadrant Multiplication) Digital Input MSB LSB 1111111111 Digital Input MSB LSB 1111111111 Analog Output (VOUT as shown in Figure 11) 1023 - VREF 1024 Analog Output (VOUT as shown in Figure 12) 511 + VREF 512 1000000001 513 - VREF 1024 1000000001 1000000000 512 VREF - VREF = 1024 2 1000000000 0111111111 511 - VREF 1024 0000000001 1 - VREF 1024 511 - VREF 512 0000000000 512 - VREF 512 0111111111 0000000001 0000000000 1 + VREF 512 0 1 - VREF 512 0 - VREF =0 1024 Nominal LSB magnitude for the circuit of Figure 12 is given by 1 LSB = V REF 512 Nominal LSB magnitude for the circuit of Figure 11 is given by 1 LSB = V REF 1024 BIPOLAR ANALOG INPUT VDD 10V BIPOLAR ANALOG INPUT VDD 10V 15 MSB 15 UNIPOLAR DIGITAL INPUT LSB VREF 14 4 AD7533 16 RFB 1 IOUT1 BIPOLAR DIGITAL INPUT C1 LSB 14 4 16 1 IOUT1 AD7533 C1 A1 2 13 R4 20k R2 330 3 IOUT2 A2 VOUT R6 5k GND 3 NOTES 1. R3, R4, AND R5 SELECTED FOR MATCHING AND TRACKING. 2. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 3. C1 PHASE COMPENSATION (5pF TO 15pF) MAY BE REQUIRED WHEN USING HIGH SPEED AMPLIFIERS. 01134-010 GND NOTES 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2. C1 PHASE COMPENSATION (5pF TO 15pF) MAY BE REQUIRED WHEN USING HIGH SPEED AMPLIFIER. R5 20k R3 10k IOUT2 VOUT 2 13 R2 330 VREF Figure 11. Unipolar Binary Operation (2-Quadrant Multiplication) Rev. C | Page 8 of 12 Figure 12. Bipolar Operation (4-Quadrant Multiplication) 01134-011 R1 1k MSB R1 1k AD7533 APPLICATIONS BIPOLAR ANALOG INPUT VDD 10V VREF 15 MSB 16 4 1 AD7533 LSB RFB 2 13 DIGITAL INPUT 3 10k IOUT1 10k 1/2 AD7512DIJN VOUT 5k OP97 IOUT2 OP97 GND 01134-012 MAGNITUDE BITS 14 SIGN BIT Figure 13. 10-Bit and Sign Multiplying DAC 4.7k CALIBRATE 10V 1k +15V VDD DIGITAL FREQUENCY CONTROL WORD LSB NC 10k 1% 10k 1% Ct 14 16 4 1 AD7533 2 13 IOUT1 IOUT2 TRIANGULAR WAVE OP97 1 ) 8RtCt Rt = 10k 0 < N (1 210) 3 f=N( GND 01134-013 15 MSB VREF SQUARE WAVE OP97 6.8V (2) Figure 14. Programmable Function Generator +15V IOUT1 MSB AD7533 1 LSB 13 3 15 VREF BIT 1 DIGITAL INPUT "D" BIT 10 VOUT = GND VOUT MSB DIGITAL INPUT (TEST LIMIT) -VIN where: BIT 10 BIT 1 BIT 2 D= + + ... 10 2 21 22 1023 0<D 1024 AD7533 R1 16 2 13 IOUT1 IOUT2 3 VOUT = VREF = GND VOUT RFB 1 AD7533 16 1 2 13 IOUT1 AD790 COMPARATOR FAIL/PASS TEST IOUT2 GND R2 -VREFD R1D R2 - R1 + R2 R1 + R2 where: BIT 10 BIT 1 BIT 2 + ... 10 D= + 2 21 22 1023 0<D 1024 01134-015 LSB 14 4 LSB 4 Figure 17. Digitally Programmable Limit Detector . +15V 15 14 3 VREF MSB 15 TEST INPUT (0 TO - VREF ) D Figure 15. Divider (Digitally Controlled Gain) BIT 1 DIGITAL INPUT "D" BIT 10 +15V 14 4 2 VREF Figure 16. Modified Scale Factor and Offset Rev. C | Page 9 of 12 01134-016 16 IOUT2 RFB 01134-014 VIN AD7533 OUTLINE DIMENSIONS 0.800 (20.32) 0.790 (20.07) 0.780 (19.81) 16 9 1 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 8 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.100 (2.54) BSC 0.060 (1.52) MAX 0.210 (5.33) MAX 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.430 (10.92) MAX 0.005 (0.13) MIN 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 073106-B COMPLIANT TO JEDEC STANDARDS MS-001-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 18. 16-Lead Plastic Dual In-Line Package [PDIP] (N-16) Dimensions shown in inches and (millimeters) 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 45 8 0 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 19. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) Rev. C | Page 10 of 12 1.27 (0.0500) 0.40 (0.0157) 112906-B 1 AD7533 0.005 (0.13) MIN 0.098 (2.49) MAX 16 9 1 PIN 1 8 0.310 (7.87) 0.220 (5.59) 0.100 (2.54) BSC 0.320 (8.13) 0.290 (7.37) 0.840 (21.34) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING 0.070 (1.78) PLANE 0.030 (0.76) 0.015 (0.38) 0.008 (0.20) 15 0 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 20. 16-Lead Ceramic Dual In-Line Package [CERDIP] (Q-16) Dimensions shown in inches and (millimeters) 0.095 (2.41) 0.075 (1.90) 0.358 (9.09) MAX SQ 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 0.088 (2.24) 0.054 (1.37) 19 18 3 20 4 0.028 (0.71) 0.022 (0.56) 1 BOTTOM VIEW 0.055 (1.40) 0.045 (1.14) 0.050 (1.27) BSC 8 14 13 9 45 TYP 0.150 (3.81) BSC CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 022106-A 0.358 (9.09) 0.342 (8.69) SQ 0.200 (5.08) REF 0.100 (2.54) REF 0.015 (0.38) MIN 0.075 (1.91) REF 0.100 (2.54) 0.064 (1.63) Figure 21. 20-Terminal Ceramic Leadless Chip Carrier [LCC] (E-20-1) Dimensions shown in inches and (millimeters) 0.180 (4.57) 0.165 (4.19) 0.048 (1.22 ) 0.042 (1.07) 3 0.048 (1.22) 0.042 (1.07) 4 0.056 (1.42) 0.042 (1.07) PIN 1 IDENTIFIER 18 TOP VIEW (PINS DOWN) 8 0.020 (0.51) R 9 0.20 (0.51) MIN 19 0.021 (0.53) 0.013 (0.33) 0.050 (1.27) BSC 0.330 (8.38) 0.032 (0.81) 0.290 (7.37) 0.026 (0.66) 14 13 0.356 (9.04) SQ 0.350 (8.89) 0.395 (10.03) SQ 0.385 (9.78) 0.020 (0.50) R 0.045 (1.14) R 0.025 (0.64) 0.120 (3.04) 0.090 (2.29) COMPLIANT TO JEDEC STANDARDS MO-047-AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 22. 20-Lead Plastic Leaded Chip Carrier [PLCC] (P-20) Dimensions shown in inches and (millimeters) Rev. C | Page 11 of 12 BOTTOM VIEW (PINS UP) AD7533 ORDERING GUIDE Model AD7533ACHIPS AD7533JN AD7533JNZ 1 AD7533KN AD7533KNZ1 AD7533LN AD7533LNZ1 AD7533JP AD7533JP-REEL AD7533JPZ1 AD7533JPZ-REEL1 AD7533KP AD7533KP-REEL AD7533KPZ1 AD7533KPZ-REEL1 AD7533KR AD7533KR-REEL AD7533KRZ1 AD7533KRZ-REEL1 AD7533AQ AD7533BQ AD7533CQ AD7533SQ AD7533UQ AD7533UQ/883B AD7533TE/883B Temperature Range Package Description -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C -55C to +125C -55C to +125C 16-Lead Plastic Dual In-Line Package [PDIP] 16-Lead Plastic Dual In-Line Package [PDIP] 16-Lead Plastic Dual In-Line Package [PDIP] 16-Lead Plastic Dual In-Line Package [PDIP] 16-Lead Plastic Dual In-Line Package [PDIP] 16-Lead Plastic Dual In-Line Package [PDIP] 20-Lead Plastic Leaded Chip Carrier [PLCC] 20-Lead Plastic Leaded Chip Carrier [PLCC] 20-Lead Plastic Leaded Chip Carrier [PLCC] 20-Lead Plastic Leaded Chip Carrier [PLCC] 20-Lead Plastic Leaded Chip Carrier [PLCC] 20-Lead Plastic Leaded Chip Carrier [PLCC] 20-Lead Plastic Leaded Chip Carrier [PLCC] 20-Lead Plastic Leaded Chip Carrier [PLCC] 16-Lead Standard Small Outline Package [SOIC_W] 16-Lead Standard Small Outline Package [SOIC_W] 16-Lead Standard Small Outline Package [SOIC_W] 16-Lead Standard Small Outline Package [SOIC_W] 16-Lead Ceramic Dual In-Line Package [CERDIP] 16-Lead Ceramic Dual In-Line Package [CERDIP] 16-Lead Ceramic Dual In-Line Package [CERDIP] 16-Lead Ceramic Dual In-Line Package [CERDIP] 16-Lead Ceramic Dual In-Line Package [CERDIP] 16-Lead Ceramic Dual In-Line Package [CERDIP] 20-Terminal Ceramic Leadless Chip Carrier [LCC] Package Option DIE N-16 N-16 N-16 N-16 N-16 N-16 P-20 P-20 P-20 P-20 P-20 P-20 P-20 P-20 RW-16 RW-16 RW-16 RW-16 Q-16 Q-16 Q-16 Q-16 Q-16 Q-16 E-20-1 Nonlinearity (% FSR max) 0.2 0.2 0.1 0.1 0.05 0.05 0.2 0.2 0.2 0.2 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.2 0.1 0.05 0.2 0.05 0.05 0.1 1 Z = RoHS compliant part. (c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01134-0-3/07(C) T T Rev. C | Page 12 of 12