LTC3622EMSE-2#TRPBF - LINEAR TECHNOLOGY

LTC3622/

LTC3622-2/LTC3622-23/5

3622fa

For more information www.linear.com/LTC3622

Typical applicaTion

FeaTures DescripTion

17V, Dual 1A

Synchronous Step-Down Regulator

with Ultralow Quiescent Current

The LT C

3622 is a dual 1A output, high efficiency synchro-

nous monolithic step-down regulator capable of operating

from input supplies up to 17V. The switching frequency is

fixed to 1MHz or 2.25MHz with a ±50% synchronization

range to an external clock. The regulator features ultralow

quiescent current and high efficiency over a wide output

voltage range.

The step-down regulators operate from an input voltage

range of 2.7V to 17V and provide an adjustable output

from 0.6V to VIN while delivering up to 1A of output cur-

rent. A user-selectable mode input is provided to allow

the user to trade off ripple noise for light load efficiency.

Burst Mode

operation provides the highest efficiency at

light loads, while pulse-skipping mode provides the lowest

ripple noise. The switching regulators can be synchronized

to an external clock. Furthermore, fixed VOUT options are

available to eliminate the external feedback resistors.

2.5V/5V VOUT Application, fSW = 1MHz Efficiency vs Load Current

applicaTions

n Dual Step-Down Outputs: 1A Per Channel

n Wide VIN Range: 2.7V to 17V

n Wide VOUT Range: 0.6V to VIN

n Up to 95% Efficiency

n No-Load IQ = 5µA with Both Channels Enabled;

IQ < 4µA with Only One Channel Enabled

n High Efficiency, Low Dropout Operation

(100% Duty Cycle)

n Constant Frequency (1MHz/2.25MHz) with External

Frequency Synchronization

n ±1% Output Voltage Accuracy

n Current Mode Operation for Excellent Line and Load

Transient Response

n Phase Shift Programmable with External Clock

n Selectable Current Limit

n Internal Compensation and Soft-Start

n Compact 14-Pin DFN (3mm × 4mm) and 16-Lead

MSOP Packages

n Battery Powered Systems

n Point-of-Load Supplies

n Portable – Handheld Scanners L, LT , LT C , LT M , Burst Mode, Linear Technology and the Linear logo are registered trademarks

and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners. Protected by U.S. Patents, including 5481178, 6580258,

6498466, 6611131, 5705919.

List of LTC3622 Options

PART NAME FREQUENCY VOUT

LTC3622 1.00MHz Adjustable

LTC3622-2 2.25MHz Adjustable

LTC3622-23/5 2.25MHZ 5V/3.3V

LOAD CURRENT (A)

EFFICIENCY (%)

POWER LOSS (W)

3622 TA01b

100

0.5

0.4

0.6

0.3

0.2

0.1

0.0001 0.001 0.01 0.1 1

VOUT2 = 5V

VOUT1 = 2.5V

VIN = 12V

fSW = 1MHz

BURST MODE OPERATION

22pF

619k

84.5k

6.8µH4.7µH

3622 TA01

RUN1

RUN2

GND

FB1

SW1

VIN1

VIN

5.5V TO 17V

VOUT2

COUT2

22µF

CIN

10µF

1µF

VIN2

PHASE

ILIM

INTVCC

MODE/SYNC

SW2

FB2

LTC3622

22pF 619k

196k

VOUT1

2.5V

COUT1

22µF

LTC3622/

LTC3622-2/LTC3622-23/5

3622fa

For more information www.linear.com/LTC3622

pin conFiguraTion

absoluTe MaxiMuM raTings

VIN1, VIN2, SVIN (MSOP Only) (Note 2) ....... –0.3V to 17V

RUN1, RUN2 .............................................. –0.3V to 17V

MODE/SYNC, FB1, FB2 ................................ –0.3V to 6V

PGOOD1, PGOOD2, ILIM, PHASE .................. –0.3V to 6V

(Note 1)

SW1

RUN1

FB1

INTVCC

FB2

RUN2

SW2

VIN1

PGOOD1

MODE/SYNC

PHASE

PGOOD2

ILIM

VIN2

TOP VIEW

DE PACKAGE

14-LEAD (4mm × 3mm) PLASTIC DFN

GND

TJMAX = 150°C, θJA = 40°C/W, θJC = 4.4°C/W

EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PCB

VIN1

SVIN

PGOOD1

MODE/SYNC

PHASE

PGOOD2

ILIM

VIN2

SW1

RUN1

FB1

INTVCC

FB2

RUN2

SW2

TOP VIEW

MSE PACKAGE

16-LEAD PLASTIC MSE

GND

TJMAX = 150°C, θJA = 40°C/W, θJC = 10°C/W

EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3622EDE#PBF LTC3622EDE#TRPBF 3622 14-Lead (3mm x 4mm) Plastic DFN –40°C to 125°C

LTC3622IDE#PBF LTC3622IDE#TRPBF 3622 14-Lead (3mm x 4mm) Plastic DFN –40°C to 125°C

LTC3622HDE#PBF LTC3622HDE#TRPBF 3622 14-Lead (3mm x 4mm) Plastic DFN –40°C to 150°C

LTC3622EMSE#PBF LTC3622EMSE#TRPBF 3622 16-Lead Plastic MSOP –40°C to 125°C

LTC3622IMSE#PBF LTC3622IMSE#TRPBF 3622 16-Lead Plastic MSOP –40°C to 125°C

LTC3622HMSE#PBF LTC3622HMSE#TRPBF 3622 16-Lead Plastic MSOP –40°C to 150°C

LTC3622EDE-2#PBF LTC3622EDE-2#TRPBF 36222 14-Lead (3mm x 4mm) Plastic DFN –40°C to 125°C

LTC3622IDE-2#PBF LTC3622IDE-2#TRPBF 36222 14-Lead (3mm x 4mm) Plastic DFN –40°C to 125°C

LTC3622HDE-2#PBF LTC3622HDE-2#TRPBF 36222 14-Lead (3mm x 4mm) Plastic DFN –40°C to 150°C

LTC3622EMSE-2#PBF LTC3622EMSE-2#TRPBF 36222 16-Lead Plastic MSOP –40°C to 125°C

LTC3622IMSE-2#PBF LTC3622IMSE-2#TRPBF 36222 16-Lead Plastic MSOP –40°C to 125°C

LTC3622HMSE-2#PBF LTC3622HMSE-2#TRPBF 36222 16-Lead Plastic MSOP –40°C to 150°C

LTC3622EDE-23/5#PBF LTC3622EDE-23/5#TRPBF 223/5 14-Lead (3mm x 4mm) Plastic DFN –40°C to 125°C

LTC3622IDE-23/5#PBF LTC3622IDE-23/5#TRPBF 223/5 14-Lead (3mm x 4mm) Plastic DFN –40°C to 125°C

LTC3622HDE-23/5#PBF LTC3622HDE-23/5#TRPBF 223/5 14-Lead (3mm x 4mm) Plastic DFN –40°C to 150°C

Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

Operating Junction Temperature Range (Note 3)

LTC3622E .......................................... –40°C to 125°C

LTC3622I ........................................... –40°C to 125°C

LTC3622H .......................................... –40°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

LTC3622/

LTC3622-2/LTC3622-23/5

3622fa

For more information www.linear.com/LTC3622

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN1, VIN2 Operating Voltage 2.7 17 V

SVIN Operating Voltage MSOP Package 2.7 17 V

VOUT Operating Voltage 0.6 VIN V

IQInput Quiescent Current Active Mode, VRUN1 = VRUN2 = 2V (Note 4)

Burst Mode Operation, VRUN1 = VRUN2 = 2V,

MODE/SYNC = 3V, No Load

Shutdown Mode; VRUN1 = VRUN2 = 0V

0.1

±1

µA

VFB Regulated Feedback Voltage LTC3622/LTC3622-2

0.594

0.591

0.6

0.606

0.609

IFB FB Input Current LTC3622/LTC3622-2 10 nA

VOUT1 Regulated Fixed Output Voltage

(Channel 1)

LTC3622-23/5

4.950

4.925

5.0

5.050

5.075

VOUT2 Regulated Fixed Output Voltage

(Channel 2)

LTC3622-23/5

3.267

3.250

3.3

3.333

3.350

IFB(VOUT) Feedback Input Leakage Current LTC3622-23/5 1 5 µA

Reference Voltage Line Regulation VIN = 2.7V to 17V (Note 5) 0.01 0.015 %/V

Output Voltage Load Regulation (Note 5) 0.1 %

NMOS Switch Leakage

PMOS Switch Leakage

0.1

µA

RDS(ON) NMOS On-Resistance

PMOS On-Resistance

VIN = 5V 0.15

0.37

Maximum Duty Cycle VFB = 0V l100 %

tON(MIN) Minimum On-Time VFB = 0.7V, VIN1 = VIN2 = 5 75 ns

VRUN RUN Input High

RUN Input Low

0.35

1.0 V

RUN Input Current VRUN = 12V 0.1 ±20 nA

VMODE Pulse-Skipping Mode

Burst Mode Operation

VINTVCC–0.4

0.15 V

PHASE Input Threshold Input Low

Input High

2.0

0.4 V

ILIM Input Threshold Input Low

Input High

VINTVCC–0.1

0.1

INTVCC

tSS Soft Start Time 0.5 ms

ILIM Peak Current Limit VIN > 5V

VILIM = 0.1V (Both Channels)

VILIM = INTVCC – 0.1V (Both Channels)

VILIM = Floating, Channel 1

VILIM = Floating, Channel 2

1.6

0.8

1.6

0.8

1.8

1.0

1.8

1.0

2.0

1.2

2.0

1.2

VINTVCC Undervoltage Lockout VIN Ramping Up 2.3 2.5 2.65 V

VINTVCC Undervoltage Lockout Hysteresis 160 mV

VIN Overvoltage Lockout Rising l18 19 20 V

VIN Overvoltage Lockout Hysteresis 300 mV

elecTrical characTerisTics

The l denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at TA = 25°C. VIN1 = VIN2 = 12V, unless otherwise noted. (Notes 3, 6)

LTC3622/

LTC3622-2/LTC3622-23/5

3622fa

For more information www.linear.com/LTC3622

The l denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at TA = 25°C. VIN1 = VIN2 = 12V, unless otherwise noted. (Notes 3, 6)

elecTrical characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fOSC Oscillator Frequency LTC3622-2/LTC3622-23/5 –40°C ≤ TA ≤ 150°C

LTC3622 –40°C ≤ TA ≤ 125°C

LTC3622 –40°C ≤ TA ≤ 150°C

1.8

0.82

0.75

2.25

1.00

2.6

1.16

MHz

External CLK Amplitude 0.4 VINTVCC–0.3 V

SYNC Capture Range % of Programmed Frequency 50 150 %

VINTVCC INTVCC Voltage 3.3 3.6 3.9 V

Power Good Range VIN > 4V –7.5 –11 %

RPGOOD Power Good Resistance PGOOD RDS(ON) at 2mA 275 350 Ω

tPGOOD PGOOD Delay PGOOD Low to High

PGOOD High to Low

Cycles

Phase Shift Between Channel 1 and Channel

VPHASE = 0V

VPHASE = INTVCC, VMODE/SYNC = 0V

180

Deg

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2. Transient Absolute Maximum Voltages should not be applied for

more than 4% of the switching duty cycle.

Note 3. The LTC3622 is tested under pulsed load conditions such that

TJ ≈ TA. The LTC3622E is guaranteed to meet specified performance from

0°C to 85°C. Specifications over the –40°C to 125°C operating junction

temperature range are assured by design, characterization and correlation

with statistical process controls. The LTC3622I is guaranteed over the

–40°C to 125°C operating junction temperature range and the LTC3622H

is guaranteed over the -40°C to 150°C operating junction temperature

range. High junction temperatures degrade operating lifetimes; operating

lifetime is derated for junction temperatures greater than 125°C. Note that

the maximum ambient temperature consistent with these specifications

is determined by specific operating conditions in conjunction with board

layout, the rated package thermal impedance and other environment

factors.

Note 4. The quiescent current in active mode does not include switching

loss of the power FETs.

Note 5. The LTC3622 is tested in a proprietary test mode that connects

VFB to the output of error amplifier.

Note 6. TJ is calculated from the ambient TA and power dissipation PD

according to the following formula: TJ = TA + (PD • θJA)

LTC3622/

LTC3622-2/LTC3622-23/5

3622fa

For more information www.linear.com/LTC3622

Burst Mode Operation Pulse-Skipping Mode Operation

Efficiency vs Input Voltage

Efficiency vs Load Current

Efficiency vs Load Current at

Dropout Operation

IQ vs VIN

Typical perForMance characTerisTics

VIN1 = VIN2 = 12V, TA = 25°C, unless otherwise noted.

Efficiency vs Load Current

VOUT Efficiency vs Input Voltage

Above and Below Dropout Efficiency vs Load Current

INPUT VOLTAGE (V)

EFFICIENCY (%)

3622 G04

02.5 4.5 6.5 8.5 18.510.5 12.5 14.5 16.5

ILOAD = 1mA

ILOAD = 100µA

ILOAD = 10mA

VOUT = 4.25V

fSW = 1MHz

Burst Mode OPERATION

LOAD CURRENT (A)

EFFICIENCY (%)

3622 G05

0.001 0.01 0.1 1

VIN = 12V

VOUT = 1.8V

fSW = 1MHz

Burst Mode OPERATION

INPUT VOLTAGE (V)

IQ (µA)

3622 G07

00 2 4 6 8 10 12 14 16 18

IQ SHUT DOWN

IQ BURST MODE

10V/DIV

200mA/DIV

VOUT

AC-COUPLED

50mV/DIV

3622 G08

VIN = 12V

VOUT = 2.5V

BURST MODE OPERATION

IOUT = 75mA

4µs/DIV

10V/DIV

100mA/DIV

VOUT

AC-COUPLED

20mV/DIV

3622 G09

VIN = 12V

VOUT = 2.5V

PULSE-SKIPPING MODE

IOUT = 10mA

4µs/DIV

INPUT VOLTAGE (V)

EFFICIENCY (%)

3622 G06

70 0 42 6 108 1412 1816

1A LOAD

10mA LOAD

VOUT = 2.5V

fSW = 1MHz

Burst Mode OPERATION

LOAD CURRENT (A)

EFFICIENCY (%)

3622 G01

100

0.0001 0.001 0.01 0.1 1

VOUT = 5V

VOUT = 2.5V

fSW = 1MHz

BURST MODE OPERATION

VIN = 12V

LOAD CURRENT (A)

EFFICIENCY (%)

3622 G02

100

0.0001 0.001 0.01 0.1 1

PULSE SKIP

BURST MODE

100% Duty Cycle

fSW = 2.25MHz

VIN = 5V

LOAD CURRENT (A)

EFFICIENCY (%)

3622 G03

100

0.0001 0.001 0.01 0.1 1

VOUT = 3.3V

VOUT = 2.5V

VIN = 12V

fSW = 2.25MHz

Burst Mode OPERATION

LTC3622/

LTC3622-2/LTC3622-23/5

3622fa

For more information www.linear.com/LTC3622

Typical perForMance characTerisTics

Load Step Start-Up Operation

Oscillator Frequency

vs Temperature

VIN1 = VIN2 = 12V, TA = 25°C, unless otherwise noted.

Oscillator Frequency

vs Supply Voltage

Reference Voltage

vs Temperature RDS(ON) vs Input Voltage

RDS(ON) vs Temperature Load Regulation Line Regulation

500mA/DIV

VOUT

AC-COUPLED

200mV/DIV

3622 G10

VIN = 12V

VOUT = 3.3V

BURST MODE OPERATION

LOAD STEP FROM 100mA TO 1A

40µs/DIV

200mA/DIV

RUN

5V/DIV

PGOOD

2V/DIV

VOUT

1V/DIV

3622 G11

50µs/DIV

TEMPERATURE (°C)

OSCILLATOR FREQUENCY (kHz)

3622 G12

1400

1300

1200

1500

1100

1000

900

800

700

600

500

–100 –50 0 10050 150 200

fSW = 1MHz

VIN = 12V

INPUT VOLTAGE (V)

OSCILLATOR FREQUENCY (MHz)

3622 G13

2.45

2.40

2.35

2.50

2.30

2.25

2.20

2.15

2.10

2.05

2.00 0 2 4 86 10 12 14 16 18

TEMPERATURE (°C)

REFERENCE VOLTAGE (mV)

3622 G14

600.0

599.5

600.5

599.0

598.5

598.0

597.0

597.5

–50 503010–10–30 1109070 130 150

INPUT VOLTAGE (V)

RDS(ON) (mΩ)

3622 G15

600

500

400

300

200

100 0 2 4 6 8 10 12 14 16 18

NMOS CH2 RDS(ON)

NMOS CH1 RDS(ON)

PMOS CH2 RDS(ON)

PMOS CH1 RDS(ON)

INPUT VOLTAGE (V)

RDS(ON) (mΩ)

3622 G16

700

600

500

400

300

200

100 –50 50250–25 15012510075

NMOS CHANNEL 2

NMOS CHANNEL 1

PMOS CHANNEL 2

PMOS CHANNEL 1

LOAD CURRENT (A)

∆VOUT (%)

3622 G17

–1

–2

–3

–4

–5 0 0.40.2 0.80.6 1.21.0

BURST MODE

PULSE SKIP

VIN = 12V

VOUT = 3.3V

PULSE SKIPPING OPERATION

fSW = 1MHz

INPUT VOLTAGE (V)

∆VOUT (%)

3622 G18

0.3

0.2

0.5

0.4

0.1

–0.1

–0.2

–0.3

–0.4

–0.5 0 63 129 1815

VOUT = 2.5V

ILOAD = 500mA

fSW = 1MHz

PULSE-SKIPPING OPERATION

LTC3622/

LTC3622-2/LTC3622-23/5

3622fa

For more information www.linear.com/LTC3622

Typical perForMance characTerisTics

VOUT vs Load Current

Sync Mode Out-Of-Phase

OperationOut-Of-Phase Operation

VIN1 = VIN2 = 12V, TA = 25°C, unless otherwise noted.

ILIM vs Input Voltage

IQ vs Temperature Switch Leakage vs Temperature

TEMPERATURE (°C)

QUIESCENT CURRENT (µA)

3622 G19

–100 0–50 10050 150 200

SHUTDOWN

SLEEP

TEMPERATURE (°C)

SW LEAKAGE (nA)

3622 G20

50000

30000

35000

40000

45000

25000

20000

15000

10000

5000

–5000

–50 –25 0 25 50 75 100 125 150

PMOS2

PMOS1

NMOS2

NMOS1

LOAD CURRENT (A)

VOUT (V)

3622 G21

00 0.5 1 1.5 2

ILIM = INTVCC

ILIM = GND

SW1

10V/DIV

SW2

10V/DIV

3622 G22

VIN = 12V

VOUT = 2.5V, VOUT = 3.3V

L1 = 4.7µH, L2 = 3.3µH

OUT-OF-PHASE OPERATION

200ns/DIV

EXTERNAL

CLOCK

2V/DIV

SW1

10V/DIV

SW2

10V/DIV

3622 G23

SYNC MODE OPERATION

EXTERNAL CLOCK PULSE WIDTH

CONTROLS PHASE SHIFT

200ns/DIV

INPUT VOLTAGE (V)

ILIM (A)

3622 G24

1.0

2.0

0.8

0.6

0.2

0.4

1.6

1.8

1.4

1.2

00 3 15 1896 12

TA = 150°C

TA = 25°C

TA = –45°C

LTC3622/

LTC3622-2/LTC3622-23/5

3622fa

For more information www.linear.com/LTC3622

pin FuncTions

VIN1 (Pin 1/Pin 1): Input Voltage of Channel 1 Step-Down

Regulator. This input also powers the INTVCC LDO.

PGOOD1 (Pin 2/Pin 3): Open Drain Power Good Indicator

for Channel 1.

MODE/SYNC (Pin 3/Pin 4): Burst Mode Select and External

Clock Synchronization of the Step-Down Regulator. Tie

MODE/SYNC to INTVCC for Burst Mode operation with a

400mA peak current clamp. Tie MODE/SYNC to GND for

pulse-skipping operation. Furthermore, connecting this pin

to an external clock will synchronize the switch clock to

the external clock and put the part in pulse-skipping mode.

PHASE (Pin 4/Pin 5): Phase Select Pin. Tie this pin to

ground to run the regulators in phase (0° phase shift)

between SW rising edge of channel 1 and channel 2. Tie

this pin to INTVCC to set 180° phase shift between chan-

nels. When this pin is high, the phase shift may also be

set by modulating the duty cycle of external clock on the

MODE/SYNC pin (channel 1 edge synced to rising edge

of external clock, channel 2 edge synced to falling edge of

external clock). See Applications Section for more details.

PGOOD2 (Pin 5/Pin 6): Open Drain Power Good Indicator

for Channel 2.

ILIM (Pin 6/Pin 7): Current Limit Select Pin. Tying this pin

to ground sets the full current limit for both channels. Tying

this pin to INTVCC drops the current limit by a factor of 2

for both channels. Biasing this pin to 1V sets the current

on channel 1 to be the full amount, and the current on

channel 2 to be dropped by a factor of 2.

VIN2 (Pin 7/Pin 8): Input Voltage of Channel 2 Step-Down

Regulator. May be a different voltage than VIN1.

SW2 (Pin 8/Pin 9): Switch Node Connection to the Induc-

tor of Channel 2 Step-Down Regulator.

RUN2 (Pin 9/Pin 10): Logic Controlled RUN Input to Chan-

nel 2. Do not leave this pin floating. Logic high activates

the step-down regulator.

FB2 (Pin 10/Pin 11): Feedback Input to the Error Amplifier

of Channel 2 Step-Down Regulator. Connect resistor divider

tap to this pin. The output voltage can be adjusted from

0.6V to VIN by: VOUT = 0.6V • [1 + (R2/R1)]. (Figure 2) For

fixed VOUT options, connect the FB pin directly to VOUT.

INTVCC (Pin 11/Pin 12): Low Dropout Regulator. Bypass

with a low ESR capacitor of at least 1µF to ground.

FB1 (Pin 12/Pin 13): Feedback Input to the Error Amplifier

of Channel 1 Step-Down Regulator. Connect resistor divider

tap to this pin. The output voltage can be adjusted from

0.6V to VIN by: VOUT = 0.6V • [1 + (R2/R1)]. (Figure 2) For

fixed VOUT options, connect the FB pin directly to VOUT.

RUN1 (Pin 13/Pin 14): Logic Controlled RUN Input to

Channel 1. Do not leave this pin floating. Logic high acti-

vates the step-down regulator.

SW1 (Pin 14/Pin 16): Switch Node Connection to the

Inductor of Channel 1 Step-Down Regulator.

GND (Pin 15/Pin 17): Ground for Power and Signal Ground.

The exposed pad must be connected to PCB ground for

rated electrical and rated thermal performance.

SVIN (NA/Pin 2): Signal VIN Pin. This input powers the

INTVCC. May be a different voltage than either VIN1 or

VIN2. Connect SVIN to either VIN1 or VIN2 , whichever one

is higher. For applications where it is not known which

VIN is higher, connect external diode between SVIN to both

VIN1 and VIN2 to ensure that SVIN is less than a diode drop

from the higher of VIN1 or VIN2.

(DFN/MSOP)

LTC3622/

LTC3622-2/LTC3622-23/5

3622fa

For more information www.linear.com/LTC3622

block DiagraM

–

0.5ms

SOFT-START

SLOPE

COMPENSATION

BUCK

LOGIC

AND

GATE DRIVE

0.6V

FB1

RUN1

PGOOD1

MODE/SYNC

PHASE

INTVCC

ERROR

AMPLIFIER BURST

COMPARATOR

MAIN

I-COMPARATOR

OVERCURRENT

COMPARATOR

REVERSE

CURRENT

COMPARATOR

LDO

OSCILLATOR CURRENT LIMIT

SELECT

VIN1

SW1

GND

ILIM

CHANNEL 1

CHANNEL 2

SAME AS CHANNEL 1

3622 BD

VIN–5V

INTVCC

SW2

SVIN (MSOP ONLY)

CLK1

CLK2

FB2

RUN2

PGOOD2

VIN2

FIXED VOUT

LTC3622/

LTC3622-2/LTC3622-23/5

3622fa

For more information www.linear.com/LTC3622

operaTion

The LTC3622 is a dual high efficiency monolithic step-

down regulator, which uses a constant frequency, peak

current mode architecture. It operates through a wide VIN

range and regulates with ultralow quiescent current. The

operation frequency is set at either 2.25MHz or 1MHz and

can be synchronized to an external oscillator ±50% of the

inherent frequency. To suit a variety of applications, the

selectable MODE/SYNC pin allows the user to trade off

output ripple for efficiency.

For each channel, the output voltage is set by an external

divider returned to the FB pin. An error amplifier compares

the divided output voltage with a reference voltage of

0.6V and adjusts the peak inductor current accordingly.

Overvoltage and undervoltage comparators will pull the

PGOOD output low if the output voltage is not within 7.5%

of the programmed value. The PGOOD output will go high

immediately after achieving regulation and will go low 32

clock cycles after falling out of regulation.

Main Control Loop

During normal operation, the top power switch (P-channel

MOSFET) is turned on at the beginning of a clock cycle.

The inductor current is allowed to ramp up to a peak level.

Once the level is reached, the top power switch is turned

off and the bottom switch (N-channel MOSFET) is turned

on until the next clock cycle. The peak current level is con-

trolled by the internally compensated ITH voltage, which is

the output of the error amplifier. This amplifier compares

the FB voltage to the 0.6V internal reference. When the

load current increases, the FB voltage decreases slightly

below the reference, which causes the error amplifier to

increase the ITH voltage until the average inductor current

matches the new load current.

The main control loop is shut down by pulling the RUN

pin to ground.

Low Current Operation

Tw o discontinuous conduction modes (DCM) are available

to control the operation of the LTC3622 at low currents.

Both modes, Burst Mode operation and pulse-skipping

mode, automatically switch from continuous operation to

the selected mode when the load current is low.

To optimize efficiency, Burst Mode operation can be se-

lected by tying the MODE/SYNC pin to INTVCC. In Burst

Mode operation, the peak inductor current is set to be at

least 400mA, even if the output of the error amplifier de-

mands less. Thus, when the switcher is on at relatively

light output loads, FB voltage will rise and cause the ITH

voltage to drop. Once the ITH voltage drops low enough,the

switcher goes into sleep mode with both power switches off.

The switchers remain in this sleep state until the external

load pulls the output voltage below its regulation point.

When both channels are in sleep mode, the part draws an

ultralow 5µA of quiescent current from VIN.

To minimize VOUT ripple, pulse-skipping mode can be

selected by grounding the MODE/SYNC pin. In LTC3622,

pulse-skipping mode is implemented similarly to Burst

Mode operation with the peak inductor current set to be

at above 66mA. This results in lower ripple than in Burst

Mode operation with the trade-off being slightly lower

efficiency.

High Duty Cycle/Dropout Operation

When the input supply voltage decreases towards the output

voltage, the duty cycle increases and slope compensation

is required to maintain the fixed switching frequency. The

LTC3622 has internal circuitry to accurately maintain the

peak current limit (ILIM) of 1.8A even at high duty cycles.

As the duty cycle approaches 100%, the LTC3622 enters

dropout operation. During dropout, the part will transition

in and out of sleep mode depending on the output load

current. This significantly reduces the quiescent current,

thus prolonging the use of the input supply.

LTC3622/

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Figure 1. 90° Phase Shift Set by External Clock

operaTion

VIN Overvoltage Protection

In order to protect the internal power MOSFET devices

against transient voltage events, the LTC3622 constantly

monitors the VIN1 and VIN2 pins for an overvoltage condi-

tion. When VIN1 or VIN2 rise above 18.5V, both regulators

suspend operation by shutting off both power MOSFETs.

Once VIN drops below 18.2V, the regulator immediately

resumes normal operation. The regulators execute soft-

start when exiting an overvoltage condition.

Low Supply Operation

The LTC3622 incorporates undervoltage lockout circuits

which shut down the part when the input voltages drop

below 2.5V. As the input voltages rise slightly above the

undervoltage threshold, the switchers will begin basic op-

eration. However,

the RDS(ON) of the top and bottom switch

of each channel will be slightly higher than that specified

in the electrical characteristics due to lack of gate drive.

Refer to graph of RDS(ON) versus VIN for more details.

Phase Selection

The two channels of LTC3622 can operate in phase, 180°

out-of-phase (anti-phase) depending on the state of PHASE

pin- low, or high, respectively. Anti-phase generally re-

duces input voltage and current ripple. Crosstalk between

switch nodes SW1, SW2 and components or sensitive

lines connected to FBx, can sometimes cause unstable

switching waveforms and unexpectedly large input and

output voltage ripple.

The situation improves if rising and falling edges of the

switch nodes are timed carefully not to coincide. Depending

on the duty cycle of the two channels, choose the phase

difference between the channels to keep edges as far away

from each other as possible.

Crosstalk can generally be avoided by carefully choosing

the phase shift such that the SW edges do not coincide.

However, there are often situations where this is unavoid-

able, such as when both channels are operating at near

50% duty cycle. In such cases, the optimized phase shift

can be set by modulating the duty cycle of external clock

on the MODE/SYNC pin (channel 1 edge synced to rising

edge of external clock, channel 2 edge synced to falling

edge of external clock), while keeping the PHASE pin volt-

age high. Figure 1 shows a 90° phase shifting between

two channels. Table 1 shows the phase selection by the

PHASE pin.

Table 1. Phase Selection

NO EXTERNAL CLK EXTERNAL CLK

PHASE = 0 0° Phase Shift 0° Phase Shift

PHASE = INTVCC 180° Phase Shift Phase Shift Determined by

Clock Edges

Soft-Start

The LTC3622 has a 500µs soft-start ramp for each channel

when enabled. During soft-start operation, the switchers

operate in pulse-skipping mode.

EXTERNAL

CLOCK

SW1

SW2

3622 F01

500ns/DIV

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Output Voltage Programming

For non-fixed output voltage parts, the output voltage is

set by external resistive dividers according to the follow-

ing equation:

VOUT =0.6V •1+R2













The resistive divider allows the FB pin to sense a fraction

of the output voltage as shown in Figure 2.

For fixed VOUT parts, tie FB directly to VOUT, as R2 and R1

are matched internal resistors.

applicaTions inForMaTion

Figure 2. Setting the Output Voltage

Note that ripple current ratings from capacitor manufac-

turers are often based on only 2000 hours of life which

makes it advisable to further derate the capacitor, or choose

a capacitor rated at a higher temperature than required.

Several capacitors may also be paralleled to meet size or

height requirements in the design. For low input voltage

applications, sufficient bulk input capacitance may be

needed to minimize transient effects during output load

changes.

Output Capacitor (COUT) Selection

The selection of COUT is determined by the effective series

resistance (ESR) that is required to minimize voltage ripple

and load step transients as well as the amount of bulk

capacitance that is necessary to ensure that the control

loop is stable. Loop stability can be checked by viewing

the load transient response. The output ripple, ΔVOUT, is

determined by:

ΔVOUT < ΔIL

8•ƒ•COUT

+ESR













The output ripple is highest at maximum input voltage since

ΔIL increases with input voltage. Multiple capacitors placed

in parallel may be needed to meet the ESR and RMS current

handling requirements. Dry tantalum, special polymer and

hybrid conductive polymer capacitors are very low ESR but

have lower capacitance density than other types. Tantalum

capacitors have the highest capacitance density but it is

importance to only use types that have been surge tested

for use in switching power supplies. Aluminum electrolytic

capacitors have significantly higher ESR, but can be used

in cost-sensitive applications provided that consideration

is given to ripple current ratings and long-term reliability.

Ceramic capacitors have excellent low ESR characteristics

and small footprints.

Using Ceramic Input and Output Capacitors

Higher capacitance value, lower cost ceramic capacitors

are now becoming available in smaller case sizes. Their

high ripple current, high voltage rating and low ESR make

them ideal for switching regulator applications. However,

care must be taken when these capacitors are used at

the input and output. When a ceramic capacitor is used

VOUT

CFF

3622 F02

GND

LTC3622

Input Capacitor (CIN) Selection

The input capacitance, CIN, is needed to filter the square

wave current at the drain of the top power MOSFET. To

prevent large voltage transients from occurring, a low

ESR input capacitor sized for the maximum RMS current

should be used. The RMS current calculation is different

if the part is used in in-phase or out-of-phase.

For "in phase", when VOUT1 = VOUT2

VOUT(V

IN – VOUT )

This formula has a maximum at VIN = 2VOUT. This simple

worst case is commonly used to determine the highest IRMS.

For out-of-phase case, the ripple current can be lower than

the "in phase" current. The maximum current typically oc-

curs when VOUT1 – VIN/2 = VOUT2 or when VOUT2 – VIN/2

= VOUT1. As a good rule of thumb, the amount of worst

case ripple is about 75% of the worst case ripple in the

in-phase mode. Also note that when VOUT1 = VOUT2 = VIN/2

and I1 = I2, the input current ripple is at its minimum.

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applicaTions inForMaTion

at the input and the power is supplied by a wall adapter

through long wires, a load step at the output can induce

ringing at the VIN input. At best, this ringing can couple to

the output and be mistaken as loop instability. At worst,

a sudden inrush of current through the long wires can

potentially cause a voltage spike at VIN large enough to

damage the part.

When choosing the input and output ceramic capacitors,

choose the X5R and X7R dielectric formulations. These

dielectrics have the best temperature and voltage char-

acteristics of all the ceramics for a given value and size.

Since the ESR of a ceramic capacitor is so low, the input

and output capacitor must instead fulfill a charge storage

requirement. During a load step, the output capacitor must

instantaneously supply the current to support the load

until the feedback loop raises the switch current enough

to support the load. Typically, five cycles are required to

respond to a load step, but only in the first cycle does the

output voltage drop linearly. The output droop, VDROOP, is

usually about three times the linear drop of the first cycle.

Thus, a good place to start with the output capacitor value

is approximately:

COUT =3

ΔI

OUT

ƒO•V

DROOP

More capacitance may be required depending on the duty

cycle and load step requirements. In most applications,

the input capacitor is merely required to supply high

frequency bypassing, since the impedance to the supply

is very low. A 10µF ceramic capacitor is usually enough

for these conditions. Place this input capacitor as close

to the VIN1 and VIN2 pins as possible.

Output Power Good

When the LTC3622’s output voltages are within the ±7.5%

window of the regulation point, the output voltages are good

and the PGOOD pins are pulled high with external resistors.

Otherwise, internal open-drain pull-down devices (275Ω)

will pull the PGOOD pins low. To prevent unwanted PGOOD

glitches during transients or dynamic VOUT changes, the

LTC3622’s PGOOD falling edge includes a blanking delay

of approximately 32 switching cycles.

Frequency Synchronization Capability

The LTC3622 has the capability to synchronize to a ±50%

range of the internal programmed frequency. It takes

several cycles of external clock to engage the sync mode,

and roughly 2μs for the part to detect the absence of the

external clock signal. Once engaged in sync, the LTC3622

immediately runs at the external clock frequency.

Inductor Selection

Given the desired input and output voltages, the inductor

value and operating frequency determine the ripple current:

ΔIL=VOUT

ƒ•L1– VOUT

IN(MAX)













Lower ripple current reduces power losses in the inductor,

ESR losses in the output capacitors and output voltage

ripple. Highest efficiency operation is obtained at low

frequency with small ripple current. However, achieving

this requires a large inductor. There is a trade-off between

component size, efficiency and operating frequency.

A reasonable starting point is to choose a ripple current

that is about 50% of IOUT(MAX). To guarantee that ripple

current does not exceed a specified maximum, the induc-

tance should be chosen according to:

L=VOUT

ƒ•ΔIL(MAX)

1– VOUT

IN(MAX)













Once the value for L is known, the type of inductor must

be selected. Actual core loss is independent of core size

for a fixed inductor value, but is very dependent on the

inductance selected. As the inductance or frequency in-

creases, core loss decreases. Unfortunately, increased

inductance requires more turns of wire and therefore

copper losses increase.

Ferrite designs have very low core losses and are pre-

ferred at high switching frequencies, so design goals can

concentrate on copper loss and preventing saturation.

Ferrite core material saturates “hard,” which means that

inductance collapses abruptly when the peak design current

is exceeded. This results in an abrupt increase in inductor

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applicaTions inForMaTion

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

Different core materials and shapes change the size/cur-

rent and price/current relationship of an inductor. Toroid

or shielded pot cores in ferrite or permalloy materials are

small and don’t radiate much energy, but generally cost

more than powdered iron core inductors with similar

characteristics. The choice of which style inductor to use

mainly depends on the price versus size requirements

and any radiated field/EMI requirements. New designs for

Table 2. Inductor Selection Table

INDUCTOR INDUCTANCE

(μH)

DCR

(mΩ)

MAX CURRENT

(A)

DIMENSIONS

(mm)

HEIGHT

(mm)

MANUFACTURER

IHLP-1616BZ-11 Series 1.0

2.2

4.7

4.5

3.25

1.7

4.3 × 4.7

Vishay

www.vishay.com

IHLP-2020BZ-01 Series 1

2.2

3.3

4.7

5.6

6.8

18.9

45.6

79.2

108

113

139

4.2

3.3

2.8

2.5

2.4

5.4 × 5.7

FDV0620 Series 1

2.2

3.3

4.7

5.7

3.2

2.8

6.7 × 7.4

Toko

www.toko.com

MPLC0525L Series 1

1.5

2.2

6.4

5.2

4.1

6.2 × 5.4

2.5

NEC/Tokin

www.nec-tokin.com

HCM0703 Series 1

1.5

2.2

3.3

4.7

5.5

7 × 7.4

Cooper Bussmann

www.cooperbussmann.com

RLF7030 Series 1

1.5

2.2

3.3

4.7

6.8

8.8

9.6

6.4

6.1

5.4

4.1

3.4

2.8

6.9 × 7.3

3.2

TDK

www.tdk.com

WE-TPC 4828 Series 1.2

1.8

2.2

2.7

3.3

3.9

4.7

3.1

2.7

2.5

2.35

2.15

1.72

1.55

4.8 × 4.8

2.8

Würth Elektronik

www.we-online.com

XFL4020 Series 1.0

1.5

2.2

3.3

4.7

10.8

14.4

21.35

34.8

52.2

6.7

6.0

3.9

3.6

4 × 4

Coilcraft

www.coilcraft.com

surface mount inductors are available from Toko, Vishay,

NEC/Tokin, Cooper, TDK and Würth Elektronik. Refer to

Table 2 for more details.

Checking Transient Response

The regulator loop response can be checked by looking

at the load transient response. Switching regulators take

several cycles to respond to a step in load current. When

a load step occurs, VOUT immediately shifts by an amount

equal to the ΔILOAD • ESR, where ESR is the effective series

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resistance of COUT. ΔILOAD also begins to charge or dis-

charge COUT generating a feedback error signal used by the

regulator to return VOUT to its steady state value. During

this recovery time, VOUT can be monitored for overshoot

or ringing that indicates a stability problem.

The initial output voltage step may not be within the band-

width of the feedback loop, so the standard second order

overshoot/DC ratio cannot be used to determine phase

margin. In addition, a feedforward capacitor can be added

to improve the high frequency response, shown in Figure 2.

Capacitor CFF provides phase lead by creating a high fre-

quency zero with R2, which improves the phase margin.

The output voltage settling behavior is related to the stabil-

ity of the closed-loop system and demonstrates the actual

overall supply performance. For a detailed explanation of

optimizing the compensation components, including a

review of control loop theory, refer to Application Note 76.

In some applications, a more severe transient can be caused

by switching in loads with large (>1µF) input capacitors.

The discharge input capacitors are effectively put in paral-

lel with COUT, causing a rapid drop in VOUT. No regulator

can deliver enough current to prevent this problem if the

switch connecting to load has low resistance and is driven

quickly. The solution is to limit the turn-on speed of the

load switch driver. A Hot Swap™ controller is designed

specifically for this purpose and usually incorporates

current limiting, short-circuit protection and soft-starting.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can

be expressed as:

% Efficiency = 100% – (L1 + L2 + L3 + …)

where L1, L2 etc. are the individual losses as a percentage

of input power. Although all dissipative elements in the

circuit produce losses, three main sources usually account

for most of the losses in LTC3622 circuit: 1) I2R losses,

2) switching and biasing losses, 3) other losses.

applicaTions inForMaTion

1. I2R losses are calculated from the DC resistances of

the internal switches, RSW, and external inductor, RL.

In continuous mode, the average output current flows

through inductor L but is “chopped” between the

internal top and bottom power MOSFETs. Thus, the

series resistance looking into the SW pin is a function

of both top and bottom MOSFET RDS(ON) and the duty

cycle (DC) as follows:

RSW =(RDS(ON)TOP)(DC)+(RDS(ON)BOT)(1 – DC)

The RDS(ON) for both the top and bottom MOSFETs can be

obtained from the Typical Performance Characteristics

curves. Thus to obtain I2R losses:

I2R Losses = IOUT2(RSW + RL)

2. The switching current is the sum of the MOSFET driver

and control currents. The power MOSFET driver current

results from switching the gate capacitance of the power

MOSFETs. Each time a power MOSFET gate is switched

from low to high to low again, a packet of charge dQ

moves from VIN to ground. The resulting dQ/dt is a

current out of VIN that is typically much larger than the

DC control bias current. In continuous mode, IGATECHG

= fOSC(QT + QB), where QT and QB are the gate charges

of the internal top and bottom power MOSFETs and

fOSC is the switching frequency. The power loss is thus:

Switching Loss = IGATECHG • VIN

The gate charge loss is proportional to VIN and fOSC and

thus their effects will be more pronounced at higher

supply voltages and higher frequencies.

3. Other “hidden” losses such as transition loss and cop-

per trace and internal load resistances can account for

additional efficiency degradations in the overall power

system. It is very important to include these “system”

level losses in the design of a system. Transition loss

arises from the brief amount of time the top power

MOSFET spends in the saturated region during switch

node transitions. The LTC3622 internal power devices

switch quickly enough that these loses are not significant

compared to other sources. These losses plus other

losses, including diode conduction losses during dead

time and inductor core losses, generally account for

less than 2% total additional loss.

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applicaTions inForMaTion

Thermal Conditions

In a majority of applications, the LTC3622 does not dis-

sipate much heat due to its high efficiency. However, in

applications where the LTC3622 is running at high ambi-

ent temperature, high VIN, high switching frequency, and

maximum output current load, the heat dissipated may

exceed the maximum junction temperature of the part. If

the junction temperature reaches approximately 160°C,

all power switches will be turned off until the temperature

drops about 15°C cooler.

To prevent the LTC3622 from exceeding the maximum

junction temperature, the user needs to do some thermal

analysis. The goal of the thermal analysis is to determine

whether the power dissipated exceeds the maximum

junction temperature of the part. The temperature rise is

given by:

TRISE = PD • θJA

As an example, consider the case when the LTC3622 is

used in applications where VIN = 12V, IOUT = IOUT1 = IOUT2

= 1A, ƒ = 2.25MHz, VOUT = VOUT1 = VOUT2 = 1.8V. The

equivalent power MOSFET resistance RSW is:

RSW =RDS(ON)TOP •VOUT

+RDS(ON)BOT •1– VOUT













=370mΩ•1.8V

12V

+150mΩ•1– 1.8V

12V









=183mΩ

The active current through VIN at 2.25MHz without load

is about 10mA, which includes switching and internal

biasing current loss, and transition loss. Therefore, the

total power dissipated by the part is:

PD = 2 • IOUT2 • RSW + VIN • IIN(Q)

= 2 • 1A2 • 183mΩ + 12V • 10mA

= 486mW

For the DFN package, the θJA is 40°C/W. Therefore, the

junction temperature of the regulator operating at 25°C

ambient temperature is approximately:

TJ = 486mW • 40°C/W + 25°C = 44.4°C

Remembering that the above junction temperature is

obtained from an RDS(ON) at 25°C, we might recalculate

the junction temperature based on a higher RDS(ON) since

it increases with temperature. Redoing the calculation

assuming that RSW increased 5% at 44.4°C yields a new

junction temperature of 45.4°C. If the application calls

for a higher ambient temperature and/or higher switching

frequency, care should be taken to reduce the temperature

rise of the part by using a heat sink or air flow.

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VIN

SW1

SW2

GND

CIN

COUT2

VIAS TO

GROUND

PLANE

VIAS TO

GROUND

PLANE

VIAS TO

GROUND

PLANE

COUT1

36222 F03

Figure 3. Layout Diagram

Board Layout Considerations

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the LTC3622 (refer to Figure 3). Check the following in

the layout:

1. Do the capacitors CIN connect to the VIN and GND as

close as possible? These capacitors provide the AC

current to the internal power MOSFETs and their driv-

ers. Does CVCC connect to INTVCC as close as possible?

2. Are COUT and L closely connected? The (–) plate of

COUT returns current to GND and the (–) plate of CIN.

3. The resistive divider, R1 and R2, must be connected

between the (+) plate of COUT and a ground line ter-

minated near GND. The feedback signal VFB should be

routed away from noisy components and traces, such

as the SW line, and its trace should be minimized. Keep

R1 and R2 close to the IC.

4. Solder the exposed pad (Pin 15 for DFN, Pin 17 for

MSOP) on the bottom of the package to the GND plane.

Connect this GND plane to other layers with thermal

vias to help dissipate heat from the LTC3622.

5. Keep sensitive components away from the SW pin. The

input capacitor, CIN, feedback resistors, and INTVCC

bypass capacitors should be routed away from the SW

trace and the inductor.

6. A ground plane is highly recommended.

7. Flood all unused areas on all layers with copper, which

reduces the temperature rise of power components.

These copper areas should be connected to GND.

LTC3622/

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applicaTions inForMaTion

619k 619k

137k

3622 F04

84.5k

22pF 22pF

VIN

17V MAX

VOUT1

VOUT2

3.3V

COUT1

22µF

COUT2

22µF

VIN1 INTVCC

MODE/SYNC

PHASE

ILIM

VIN2

RUN1

RUN2

SW2 SW2

FB2

3.3µH 2.7µH

FB2

GND

PGOOD1 PGOOD2

LTC3622-2

CIN

10µF

1µF

Figure 4. 5V/3.3V VOUT Burst Mode Operation Application

Design Example

As a design example, consider using the LTC3622 in an

application with the following specifications:

VIN1 = VIN1 = 10.8V to 13.2V

VOUT1 = 5V

VOUT2 = 3.3V

IOUT1(MAX) = 1A

IOUT2(MAX) = 1A

IOUT(MIN) = 0

fSW = 2.25MHz

Because efficiency is important at both high and low load

current, Burst Mode operation will be utilized.

Given the internal oscillator of 2.25MHz, we can calculate

the inductors value for about 40% ripple current at maxi-

mum VIN:

L1=

2.25MHz •0.4A











1–

13.2V











=3.4µH

L2 =3.3V

2.25MHz •0.4A









1– 3.3V

13.2V









=2.75µH

Using standard value of 3.3µH and 2.7µH for inductors

results in maximum ripple currents of:

ΔIL1 =

2.25MHz •3.3µH 1–

13.2V











=0.42A

ΔIL2 =3.3V

2.25MHz •2.7µH 1– 3.3V

13.2V









=0.41A

COUT will be selected based on the ESR that is required to

satisfy the output voltage ripple requirement and the bulk

capacitance needed for loop stability. For this design, a

22µF ceramic capacitor will be used.

CIN should be sized for a maximum current rating of:

IRMS1=1A 5

13.2









13.2

5– 1=0.49A

IRMS2 =1A 3.3

13.2









13.2

3.3 – 1=0.43A

Decoupling the VIN1 and VIN2 pins with 10µF ceramic

capacitors is adequate for most applications.

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LTC3622-2/LTC3622-23/5

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Typical applicaTions

5V/3.3V VOUT, Burst Mode Operation, In-Phase Switching

Efficiency vs Load Load Step Waveform

619k 619k

137k

3622 TA02

84.5k

22pF 22pF

VIN

17V MAX

VOUT1

VOUT2

3.3V

COUT1

22µF

COUT2

22µF

VIN1 INTVCC

MODE/SYNC

PHASE

ILIM

VIN2

RUN1

RUN2

SW1 SW2

FB1

6.8µH 3.3µH

FB2

GND

PGOOD1 PGOOD2

LTC3622-2

CIN

10µF

1µF

LOAD CURRENT (A)

EFFICIENCY (%)

3622 TA02a

100

0.0001 0.001 0.01 0.1 1

VOUT = 3.3V

VOUT = 5V

VIN = 12V

fSW = 2.25MHz

Burst Mode OPERATION

500mA/DIV

VOUT

AC-COUPLED

200mV/DIV

3622 TA02b

VIN = 12V

VOUT1 = 5V

ILOAD = 5mA → 500mA

BURST MODE OPERATION

fSW = 2.25MHz

40µs/DIV

LTC3622/

LTC3622-2/LTC3622-23/5

3622fa

For more information www.linear.com/LTC3622

Typical applicaTions

Dual Output Regulators from Multiple Input Sources

604k 604k

134k

3622 TA06

82.5k

22pF 22pF

VIN1

12V

VOUT1

VOUT2

3.3V

COUT1

22µF

COUT2

22µF

VIN1

INTVCC

MODE/SYNC

PHASE

ILIM

VIN2

RUN1 RUN2

SW1 SW2

FB1

3.3µH 1µH

FB2

SVIN

GND

PGOOD1 PGOOD2

LTC3622

CIN1

10µF

VIN2

CIN2

10µF

1µF

LTC3622/

LTC3622-2/LTC3622-23/5

3622fa

For more information www.linear.com/LTC3622

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

3.00 ±0.10

(2 SIDES)

4.00 ±0.10

(2 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC

PACKAGE OUTLINE MO-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40 ±0.10

BOTTOM VIEW—EXPOSED PAD

1.70 ±0.10

0.75 ±0.05

R = 0.115

TYP

R = 0.05

TYP

3.00 REF

1.70 ±0.05

148

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DE14) DFN 0806 REV B

PIN 1 NOTCH

R = 0.20 OR

0.35 × 45°

CHAMFER

3.00 REF

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

2.20 ±0.05

0.70 ±0.05

3.60 ±0.05

PACKAGE

OUTLINE

0.25 ±0.05

0.50 BSC

3.30 ±0.05

3.30 ±0.10

0.50 BSC

DE Package

14-Lead Plastic DFN (4mm × 3mm)

(Reference LTC DWG # 05-08-1708 Rev B)

LTC3622/

LTC3622-2/LTC3622-23/5

3622fa

For more information www.linear.com/LTC3622

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

MSOP (MS16) 0213 REV A

0.53 ±0.152

(.021 ±.006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 –0.27

(.007 – .011)

TYP

0.86

(.034)

REF

0.50

(.0197)

BSC

16151413121110

12345678

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.254

(.010) 0° – 6° TYP

DETAIL “A”

GAUGE PLANE

5.10

(.201)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ±0.127

(.035 ±.005)

RECOMMENDED SOLDER PAD LAYOUT

0.305 ±0.038

(.0120 ±.0015)

TYP

0.50

(.0197)

BSC

4.039 ±0.102

(.159 ±.004)

(NOTE 3)

0.1016 ±0.0508

(.004 ±.002)

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

0.280 ±0.076

(.011 ±.003)

REF

4.90 ±0.152

(.193 ±.006)

MS Package

16-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1669 Rev A)

LTC3622/

LTC3622-2/LTC3622-23/5

3622fa

For more information www.linear.com/LTC3622

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER

A 03/15 Added LTC3622-23/5 Options in Header

Added LTC3622-23/5 to Options Table

Added LTC3622-23/5 to Electrical Characteristics

Added MSOP-16E Package Options

Added H-Grade Options

Clarified Pin Functions

Clarified Table 2

Added MSOP-16E in #4

All

1, 2, 3, 22

2, 3, 4

LTC3622/

LTC3622-2/LTC3622-23/5

3622fa

For more information www.linear.com/LTC3622

 LINEAR TECHNOLOGY CORPORATION 2014

LT 0315 REV A • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3622

relaTeD parTs

Typical applicaTion

5V/3.3V Series Output, Burst Mode Operation

PART NUMBER DESCRIPTION COMMENTS

LTC3621/

LTC3621-2

1A, 17V, 1/2.25MHz, Synchronous Step-Down Regulator 95% Efficiency, VIN: 2.7V to 17V, VOUT(MIN) = 0.6V, IQ = 3.5µA, ISD < 1µA,

2mm × 3mm DFN-6, MSOP-8E

LTC3600 1.5A, 15V, 4MHz Synchronous Rail-to-Rail Single

Resistor Step-Down Regulator

95% Efficiency, VIN: 4V to 15V, VOUT(MIN) = 0V, IQ = 700µA, ISD < 1µA,

3mm × 3mm DFN-12, MSOP-12E Packages

LTC3601 15V, 1.5A (IOUT) 4MHz Synchronous Step-Down

DC/DC Converter

95% Efficiency, VIN: 4.5V to 15V, VOUT(MIN) = 0.6V, IQ = 300µA, ISD < 1µA,

4mm × 4mm QFN-20, MSOP-16E Packages

LTC3603 15V, 2.5A (IOUT) 3MHz Synchronous Step-Down

DC/DC Converter

95% Efficiency, VIN: 4.5V to 15V, VOUT(MIN) = 0.6V, IQ = 75µA, ISD < 1µA,

4mm × 4mm QFN-20, MSOP-16E Packages

LTC3633A 20V, Dual 3A (IOUT) 4MHz Synchronous Step-Down

DC/DC Converter

95% Efficiency, VIN: 3.6V to 20V, VOUT(MIN) = 0.6V, IQ = 500µA, ISD < 15µA,

4mm × 5mm QFN-28, TSSOP-28E Packages. A Version Up to 20VIN

LTC3605A 20V, 5A (IOUT) 4MHz Synchronous Step-Down

DC/DC Converter

95% Efficiency, VIN: 4V to 20V, VOUT(MIN) = 0.6V, IQ = 2mA, ISD < 15µA,

4mm × 4mm QFN-24 Package. A Version Up to 20VIN

LTC3604 15V, 2.5A (IOUT) 4MHz Synchronous Step-Down

DC/DC Converter

95% Efficiency, VIN: 3.6V to 15V, VOUT(MIN) = 0.6V, IQ = 300µA, ISD < 14µA,

3mm × 3mm QFN-16, MSOP-16E Packages

LTC3624/

LTC3624-2

2A, 17V, 1MHz/2.25MHz Synchronous Step-Down

Regulator

95% Efficiency, VIN: 2.7V to 17V, VOUT(MIN) = 0.6V, IQ = 3.5µA, ISD < 1µA,

3mm × 3mm DFN-8 Package

604k 604k

134k

3622 TA03

82.5k

22pF 22pF

VIN

5V TO 17V

VOUT1

VOUT2

3.3V

COUT1

22µF

COUT2

22µF

VIN1 INTVCC

MODE/SYNC

PHASE

ILIM

VIN2

RUN1

RUN2

SW1 SW2

FB1

3.3µH

10k

1µH

FB2

GND

PGOOD1 PGOOD2

LTC3622-2

CIN

10µF C1

1µF

INTVCC