RT9218
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DS9218-09 April 2011 www.richtek.com
Features
zz
zz
zOperating with 5V or 12V Supply Voltage
zz
zz
zDrives All Low Cost N-MOSFET s
zz
zz
zVoltage Mode PWM Control
zz
zz
z300kHz Fixed Frequency Oscillator
zz
zz
zFa st Transient Response :
``
``
`High-Speed GM Amplifier
``
``
`Full 0 to 100% Duty Ration
zz
zz
zInternal Soft-Start
zz
zz
zPower Good Indicator
zz
zz
zAdaptive Non-Overla pping Gate Driver
zz
zz
zOver Current Fault Monitor on MOSFET, No Current
Sense Resistor Required
zz
zz
zSpecific Power Good Indicator for Intel®
Grantsdale FSB_VTT Power Sequence
zz
zz
zRoHS Compliant and 100% Lead (Pb)-Free
5V/12V Synchronous Buck PWM DC/DC and Linear Power
Controller
General Description
The RT9218 is a dual output with one synchronous buck
PWM and one linear controller. The part is proposed to
generate logic-supply voltages for PC based systems. The
high-performance device includes internal soft-start,
frequency-compensation networks, power good signaling
with specific sequence, and it comes all of the logic control,
output adjustment, power monitoring and protection
functions into a small footprint package. The part is
operated at fixed 300kHz frequeny providing an optimum
compromise between efficiency, external component size,
and cost. The linear controller is implemented to drive an
external MOSFET for regulation and it's adjustable by
setting external resistors. Moreover the specific internal
PGOOD sequence and indicator is also implemented to
conform to Intel® new platform requirement on FSB_VTT
power plane. An adjustable over-current protection (OCP)
is proposed to monitor the voltage drop across the RDS(ON)
of the lower MOSFET for synchronous buck PWM DC/
DC controller.
Ordering Information
Applications
zGraphic Card
zMotherboard, Desktop Servers
zIA Equipments
zTelecomm Equipments
zHigh Power DC-DC Regulators
Pin Configurations
(TOP VIEW)
SOP-14
NC
DRV
GND
UGATE
NC
OPS
LGATE
NC
FBL
PGOOD
BOOT
FB
PHASE
VCC
2
3
411
12
13
14
5
6
78
9
10
Note :
Richtek products are :
` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes.
Package Type
S : SOP-14
RT9218
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
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DS9218-09 April 2011www.richtek.com
Typical Application Circuit
2%)(0.8V
voltage reference Internal:V
)
R2
R1
(1VLV
)
R6
R5
(1VSV
REF
REFOUT
REFOUT
±
+×=
+×=
RT9218
PHASE
OPS
UGATE
BOOT
GND
LGATE
FB
FBL
14
13
11
10
1
2
5
4
NC 8
DRV
6NC
NC
3
V
CC
12V
PGOOD
VCC
12 Disable
9
LVOUT
PHASE
7
V
IN
5 to 12V
SV
OUT
PHASE
V
CC
12V
1000uF x 2 1uF x 2 1uF
0.1uF
1N4148
3904
ROCSET
1000uF x 2
32R
68R
1k/NC 0.1uF/NC
8k
4k
470uF
2.2uH
1uF
10R
C7
C1 to C2 C3 to C4
Q1
MU
Q2
ML
C5 to C6
L1
Q3
D1 C8
C9
R1
R2
R3
C10
C11R4
R5
R6
Q4
2.2
R
BOOT
2.2
R
UGATE
R
C
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DS9218-09 April 2011 www.richtek.com
Functional Pin Description
UGA TE (Pin 2)
Upper gate driver output. Connect to gate of the high-
side power N-MOSFET. This pin is monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET has turned off.
BOOT (Pin 1)
Bootstrap supply pin for the upper gate driver. Connect
the bootstrap capacitor between BOOT pin and the PHASE
pin. The bootstrap capacitor provides the charge to turn
on the upper MOSFET.
PHASE (Pin 14)
Connect this pin to the source of the upper MOSFET and
the drain of the lower MOSFET.
OPS (OCSET, POR a nd Shut-Down) (Pin 13)
This pin provides multi-function of the over-current setting,
UGATE turn-on POR sensing, and shut-down features.
Connecting a resistor (ROCSET) between OPS and PHASE
pins sets the over-current trip point.
Pulling the pin to ground resets the device and all external
MOSFETs are turned off allowing the output voltage power
rails to float.
This pin is also used to detect VIN in power on stage and
issues an internal POR signal.
LGA TE (Pin 4)
Lower gate drive output. Connect to gate of the low-side
power N-MOSFET. This pin is monitored by the adaptive
shoot-through protection circuitry to determine when the
lower MOSFET has turned off.
FB (Pin 12)
Switcher feedback voltage. This pin is the inverting input
of the error amplifier. FB senses the switcher output
through an external resistor divider network.
VCC (Pin 1 1)
Connect this pin to a well-decoupled 5V or 12V bias
supply. It is also the positive supply for the lower gate
driver, LGATE.
GND (Pin 3)
Both signal and power ground for the IC. All voltage levels
are measured with respect to this pin. Ties the pin directly
to the low-side MOSFET source and ground plane with
the lowest impedance.
DRV (Pin 5)
Connect this pin to the base/gate of an external transistor/
MOSFET. This pin provides the drive for the linear
regulator's pass transistor/MOSFET.
FBL (Pin 9)
Linear regulator feedback voltage. This pin is the inverting
input of the error amplifier and protection monitor. Connect
this pin to the external resistor divider network of the linear
regulator.
PGOOD (Pin 10)
PGOOD is an open-drain output used to indicate that the
regulator is within normal operating voltage ranges and
it's implemented with a specific sequence as following
chart.
NC (Pin 6,7,8)
No internal connection.
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Timing Diagram
Specific Power Sequence for LDO
90%
80%
1-10ms
<1ms
FSB_VTT (1.2V @ 5Am p)
VTT_GD
Function Block Diagram
Gate Control
Logic
Oscillator
(300k/600kHz)
EO
UV_L
GM
0.64V
DRV
GND
UGATE
OPS
LGATE
FBL
PGOOD BOOT
FB
PHASE
VCC
+
-
+
-
Soft-Start
&
Fault Logic
UV_S
+
-
0.64V +
-
+
-
VCC
0.8VREF
Power On
Reset
Reference
Bias & Regulators
(3V_Logic & 3VDD_Analog) 1.5V
0.15V
+
-
PH_M
+
-
EN
++
-
+
OC
3V
0.4V
40uA
+
-
VCC
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Electrical Characteristics
(VCC = 5V/12V, TA = 25°C, unless otherwise specified)
Absolute Maximum Ratings (Note 1)
zSupply Voltage, VCC ------------------------------------------------------------------------------------ 16V
zBOOT, VBOOT - VPHASE ---------------------------------------------------------------------------------- 16V
zPHASE to GND
DC ----------------------------------------------------------------------------------------------------------- −5V to 15V
< 200ns ---------------------------------------------------------------------------------------------------- −10V to 30V
zBOOT to PHASE ---------------------------------------------------------------------------------------- 15V
zBOOT to GND
DC ----------------------------------------------------------------------------------------------------------- −0.3V to VCC+15V
< 200ns ---------------------------------------------------------------------------------------------------- −0.3V to 42V
zUGATE ----------------------------------------------------------------------------------------------------- VPHASE − 0.3V to VBOOT + 0.3V
zLGATE ----------------------------------------------------------------------------------------------------- GND − 0.3V to VVCC + 0.3V
zInput, Output or I/O Voltage --------------------------------------------------------------------------- GND − 0.3V to 7V
zPackage Thermal Resistance (Note 2)
SOP-14, θJA ----------------------------------------------------------------------------------------------- 127.67°C/W
zJunction Temperature ----------------------------------------------------------------------------------- 150°C
zLead Temperature (Soldering, 10 sec.) ------------------------------------------------------------- 260°C
zStorage Temperature Range --------------------------------------------------------------------------- −40°C to 150°C
zESD Susceptibility (Note 3)
HBM (Human Body Mode) ----------------------------------------------------------------------------- 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------ 200V
Parameter Symbol Test Conditions Min Typ Max Unit
VCC Supply Current
Nominal Supply Current ICC UGATE and LGATE Open -- 6 15 mA
Power-On Reset
POR Threshold VCCRTH VCC Rising -- 4.1 4.5 V
Hysteresis VCCHYS 0.35 0.5 -- V
Switcher Reference
Reference Voltage VREF VCC = 12V 0.784 0.8 0.816 V
Oscillato r
Free Running Frequency fOSC VCC = 12V 250 300 350 kHz
Ramp Amplitude ΔVOSC -- 1.5 --
VP-P
To be continued
Recommended Operating Conditions (Note 4)
zSupply Voltage, VCC ------------------------------------------------------------------------------------ 5V ± 5%,12V ± 10%
zJunction Temperature Range -------------------------------------------------------------------------- −40°C to 125°C
zAmbient Temperature Range -------------------------------------------------------------------------- −40°C to 85°C
RT9218
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DS9218-09 April 2011www.richtek.com
Parameter Symbol Test Conditions Min Typ Max Unit
Erro r Amplifier (GM)
E/A Transconductance gm -- 0.2 -- ms
Open Loop DC Gain AO -- 90 -- dB
Linear Reg ulator
DRV Driver Source IDS
V
DRV = 6V -- 1.4 -- mA
Reference Voltage VREFREG VCC = 12V 0.784 0.8 0.816 V
PWM Controller Gate Drivers (VCC = 12V)
Upper Gate Source IUGATE VBOOT − VPHASE = 12V
VUGATE − VPHASE = 6V 0.6 1 -- A
Upper Gate Sink RUG ATE VBOOT − VPHASE = 12V
VUGATE − VPHASE = 1V -- 4 --
Ω
Lower Gate Source ILGATE V
CC = 12V, VLGATE = 6V 0.6 1 -- A
Lower Gate Sink RLGATE V
CC = 12V, VLGATE = 1V -- 3 4 Ω
Dead Time TDT -- -- 100 ns
Protection
FB Under-Voltage Trip ΔFBUVT FB Falling 70 75 80 %
FBL Under-Voltage Trip ΔFBLUVT FB and FBL Falling 70 75 80 %
OC Current Source IOC V
PHASE = 0V -- 40 -- μA
Soft-Start Interval TSS -- 3.5 -- ms
Power Good
Power Good Rising Threshold VCC = 12V -- 90 -- %
Power Good Hysteresis VCC = 12V -- 10 -- %
PG Sink Capability VCC = 12V, 1mA -- 0.2 0.4 V
Power Good Rising Delay VCC = 12V 1 3 10 ms
Power Good Falling Delay VCC = 12V -- 15 -- μs
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are
for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
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Typical Operating Characteristics
POR vs. Temperature
3.5
3.75
4
4.25
4.5
4.75
-40 -10 20 50 80 110 140
Temperature
POR Rising or Falling (V)
Falling
Rising
Efficiency vs . Output Current
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
1
0 5 10 15 20 25
Output Current (A)
Efficiency(%)
VCC = 5V
VIN = 5V
OCP
Time (5us/Div)
IL
(10V/Div)
(10A/Div)
UGATE
VCC = 12V, VIN = 5V
IOCSET= 20A
ROCSET = 15kΩ
Efficiency vs . Output Current
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
1
0 5 10 15 20 25
Output Current (A)
Efficiency(%)
VCC = 12V
VIN = 5V
(VOUT = 2.5V, unless otherwise specified )
Reference Voltage vs. Temperature
0.798
0.8
0.802
0.804
0.806
0.808
0.81
0.812
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature
Reference Voltage (V)
(°C)
VCC = 12V
VIN = 5V
Frequ e nc y v s . Te m p e ratu re
250
270
290
310
330
350
-40 -10 20 50 80 110 140
Temperature
Frequency (kHz
)
(°C)
Falling
Rising
(°C)
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Dead Time (Falling)
Time (10ns/Div)
UGATE
LGATE
PHASE
VCC = 12V
VIN = 5V
IOUT= 25A
Dead Time (Rising)
Time (25ns/Div)
UGATE
LGATE
PHASE
VCC = VIN = 5V
IOUT= 25A
Power On
Time (500us/Div)
IOUT
UGATE
(10V/Div)
(500mV/Div)
(2A/Div)
SVOUT
Power Off
Time (5ms/Div)
UGATE
SVOUT
VCC
VIN
VCC Switching
Time (10ms/Div)
VCC
IOUT
UGATE
(20V/Div)
(10V/Div)
(100mV/Div)
(10A/Div)
SVOUT
VCC = 12Vto 5V
IOUT= 10A
VIN = 5V
VCC Switching
Time (10ms/Div)
VCC
IOUT
UGATE
(20V/Div)
(10V/Div)
(100mV/Div)
(10A/Div)
SVOUT
VCC = 5V to 12V
IOUT= 10A, VIN = 5V
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Transient Response (Falling)
Time (25us/Div)
L = 2.2uH
C = 2000uF
VCC = VIN = 12V
IOUT= 15A to 0A
f = 1/20ms
SR = 2.5A/us
SVOUT
(100mV/Div)
IL
(10A/Div)
UGATE
(10V/Div)
Transient Response (Rising)
Time (5us/Div)
SVOUT
(100mV/Div)
IL
(10A/Div)
UGATE
(10V/Div)
L = 2.2uH
C = 2000uF
VCC = VIN = 12V
IOUT= 0A to 15A
f = 1/20ms, SR = 2.5A/us
Soft Start & PGOOD
Time (10ms/Div)
IL
PGOOD (1V/Div)
(500mV/Div)
(2A/Div)
SVOUT
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Application Information
Inductor Selection
The selection of output inductor is based on the
considerations of efficiency, output power and operating
frequency. Low inductance value has smaller size, but
results in low efficiency, large ripple current and high output
ripple voltage. Generally, an inductor that limits the ripple
current (ΔIL) between 20% and 50% of output current is
appropriate. Figure 1 shows the typical topology of
synchronous step-down converter and its related
waveforms.
VL
VIN - VOUT
- VOUT
iL
IL = IOUT
ΔIL
iS1
iS2
TS
TON TOFF
Vg1
Vg2
Figure 1. The waveforms of synchronous step-down
converter
OUT
L
IN OUT
IN
OUT
IN OUT
IN L
VΔID
VV L ; Δt; D
ΔtfsV
V
L(V V )
VfsΔI
−= = =
=− ×
××
According to Figure 1 the ripple current of inductor can be
calculated as follows :
(1)
Where :
VIN = Maximum input voltage
VOUT = Output Voltage
Δt = S1 turn on time
ΔIL = Inductor current ripple
fS = Switching frequency
D = Duty Cycle
rC = Equivalent series resistor of output capacitor
Output Ca pacitor
The selection of output capacitor depends on the output
ripple voltage requirement. Practically, the output ripple
voltage is a function of both capacitance value and the
equivalent series resistance (ESR) rC. Figure 2 shows
the related waveforms of output capacitor.
L
dt =dt L
VOUT
=
VOR
iL
iC
diL
ΔIL
1/2
0
0
ΔIL x rc
VOC
t1 t2
ΔVOC
ΔIL
VIN-VOUT
TS
IOUT
diL
Figure 2. The related waveforms of output capacitor
+
S1
S2
VIN
iS1
iS2
IOUT
VOUT
+
-
RL
rC
COUT
iC
VOR
+
-
VOC
+
-
VL
+-
LIL
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The AC impedance of output capacitor at operating
frequency is quite smaller than the load impedance, so
the ripple current (ΔIL) of the inductor current flows mainly
through output capacitor. The output ripple voltage is
described as :
2
t2
t1
S
OL
OUT
LLOUT
O
LOUT
OCOROUT
D)T(1
C
V
8
1
rcΔIΔIΔV
dtic
C
1
rcΔIΔV
ΔVΔVΔV
−+××=
+×=
+=
∫
where ΔVOR is caused by ESR and ΔVOC by capacitance.
For electrolytic capacitor application, typically 90 to 95%
of the output voltage ripple is contributed by the ESR of
output capacitor. So Equation (4) could be simplified as :
ΔVOUT = ΔIL x rc
(2)
(3)
(4)
(5)
Users could connect capacitors in parallel to get calculated
ESR.
Input Capacitor
The selection of input capacitor is mainly based on its
maximum ripple current capability. The buck converter
draws pulsewise current from the input capacitor during
the on time of S1 as shown in Figure 1. The RMS value of
ripple current flowing through the input capacitor is
described as :
(A) D)D(1IIrms OUT −= (6)
The input capacitor must be cable of handling this ripple
current. Sometime, for higher efficiency the low ESR
capacitor is necessarily.
PWM Loop Stability
RT9218 is a voltage mode buck converter using the high
gain error amplifier with transconductance (OTA,
Operational Transconductance Amplifier).
The transconductance :
dVm
dI
GM OUT
=
The mid-frequency gain :
OUT
IN
OUT
OUTINOUTOUTOUT
GMZ
dV
dV
G
ZGMdVZdIdV
==
==
ZOUT is the shut impedance at the output node to ground
(see Figure 3 and Figure 4),
VOUT
C2
C1
R1
GM
VOUT
RO
+
GM
+
-
EA+
EA-
Figure 3. A Type 2 error-amplifier with shut network to
ground
Figure 4. Equivalent circuit
Pole and Zero :
We can see the open loop gain and the Figure 3 whole
loop gain in Figure 5.
A
B
FZ FP
Gain = GMR1
Open Loop, Unloaded Gain
Closed Loop, Unloaded Gain
100 1000 10k 100k
Frequency (Hz)
Gain (dB)
Figure 5. Gain with the Figure 2 circuit
RT9218 internal compensation loop :
GM = 0.2ms, R1 = 75kΩ, C1 = 2.5nF, C2 = 10pF
11
Z
21
PCR2
1
F ;
CR2
1
F×
=
×
=
ππ
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OPS (Over Current Setting, VIN_POR and Shutdown)
1.OCP
Sense the low-side MOSFET's RDS(ON) to set over-current trip point.
Connecting a resistor (ROCSET) from this pin to the source of the upper MOSFET and the drain of the lower MOSFET
sets the over-current trip point. ROCSET, an internal 40μA current source, and the lower MOSFET on resistance, RDS(ON),
set the converter over-current trip point (IOCSET) according to the following equation :
OPS pin function is similar to RC charging or discharging circuit, so the over-current trip point is very sensitive to
parasitic capacitance (ex. shut-down MOSFET) and the duty ratio.
Below Figures say those effect. And test conditions are Rocset = 15kΩ (over -current trip point = 20.6A), Low-side
MOSFET is IR3707.
OCP
Time (5μs/Div)
UGATE
(10V/Div)
IL (10A/Div)
OPS (200mV/Div)
VIN = 5V, VCC = 12V
VOUT = 1.5V
OCP
Time (2.5μs/Div)
UGATE
(10V/Div)
IL (10A/Div)
VIN = 12V, VCC = 12V
VOUT = 1.5V
OPS
(200mV/Div)
OCP
Time (2.5μs/Div)
UGATE (10V/Div)
IL (10A/Div)
VIN = 12V, VCC = 12V
VOUT = 1.5V
OCP
Time (5μs/Div)
UGATE (10V/Div)
IL (10A/Div)
VIN = 5V, VCC = 12V
VOUT = 1.5V
MOSFET lower the of
0.4VR40uA
I
DS(ON)
OCSET
OCSET R
−×
=
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2. VIN_POR
UGATE will continuously generate a 10kHz colck with
1% duty cycle before VIN is ready. VIN is recognized ready
by detecting VOPS crossing 1.5V four times (rising &
falling). ROCSET must be kept lower than 37.5kΩ for large
ROCSET will keep VOPS always higher than 1.5V. Figure 6
shows the detail actions of OCP and POR. It is highly
recommend-ed that ROCSET be lower than 30kΩ.
3. Shutdown
Pulling low the OPS pin by a small single transistor can
shutdown the RT9218 PWM controller as shown in typical
application circuit.
Soft Start
A built-in soft-start is used to prevent surge current from
power supply input during power on. The soft-start voltage
is controlled by an internal digital counter. It clamps the
ramping of reference voltage at the input of error amplifier
and the pulse-width of the output driver slowly. The typical
soft-start duration is 3ms.
1) Mode 1 (SS< Vramp_valley)
Initially the COMP stays in the positive saturation. When
SS< VRAMP_Valley, there is no non-inverting input available
to produce duty width. So there is no PWM signal and
VOUT is zero.
2) Mode 2 (VRAMP_Valley< SS< Cross-over)
When SS>VRAMP_Valley, SS takes over the non-inverting
input and produce the PWM signal and the increasing
duty width according to its magnitude above the ramp
signal. The output follows the ramp signal, SS. However
while VOUT increases, the difference between VOUT and
SSE (SS − VGS) is reduced and COMP leaves the
saturation and declines. The takeover of SS lasts until it
meets the COMP. During this interval, since the feedback
path is broken, the converter is operated in the open loop.
3) Mode3 ( Cross-over< SS < VGS + VREF)
When the Comp takes over the non-inverting input for PWM
Amplifier and when SSE (SS − VGS) < VREF, the output of
the converter follows the ramp input, SSE (SS − VGS).
Before the crossover, the output follows SS signal. And
when Comp takes over SS, the output is expected to follow
SSE (SS − VGS). Therefore the deviation of VGS is
represented as the falling of VOUT for a short while. The
COMP is observed to keep its decline when it passes the
cross-over, which shortens the duty width and hence the
falling of VOUT happens.
Since there is a feedback loop for the error amplifier, the
output’s response to the ramp input, SSE (SS − VGS) is
lower than that in Mode 2.
4) Mode 4 (SS > VGS + VREF)
When SS > VGS + VREF, the output of the converter follows
the desired VREF signal and the soft start is completed
now.
COMP
VCORE
SSE_Internal
SS_Internal
Cross-over
VRAMP_Valley
Figure 6. OCP and VIN_POR actions
-
+
+
-
OC
VIN POR_H
PHASE
UGATE
OPS
PHASE_M 1.5V
10pF Q2
ROCSET
Cparasitic DISABLE
1st 2nd 3rd 4th OPS
waveform
(1) Internal Counter will count (VOPS > 1.5V)
four times (rising & falling) to recognize
VIN is ready.
(2) ROCSET can be set too large. Or can
detect VIN is ready (counter = 1, not equal 4)
3V
0.4V
40uA
+
-
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There are two sets of critical components in a DC-DC
converter using the RT9218. The switching power
components are most critical because they switch large
amounts of energy, and as such, they tend to generate
equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bypass current.
The power components and the PWM controller should
be placed firstly. Place the input capacitors, especially
the high-frequency ceramic decoupling capacitors, close
to the power switches. Place the output inductor and
output capacitors between the MOSFETs and the load.
Also locate the PWM controller near by MOSFETs.
A multi-layer printed circuit board is recommended.
PWM Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency and radiate noise, that results
in over-voltage stress on devices. Careful component
placement layout and printed circuit design can minimize
the voltage spikes induced in the converter. Consider, as
an example, the turn-off transition of the upper MOSFET
prior to turn-off, the upper MOSFET was carrying the full
load current. During turn-off, current stops flowing in the
upper MOSFET and is picked up by the low side MOSFET
or schottky diode. Any inductance in the switched current
path generates a large voltage spike during the switching
interval. Careful component selections, layout of the
critical components, and use shorter and wider PCB traces
help in minimizing the magnitude of voltage spikes.
Figure 7. UV and OC trigger hiccup mode
0A
0V
2V
4V
Internal
SS
Inductor Current
T1 T2 T3
TIME
COUNT = 1 COUNT = 2
OVERLOAD
APPLIED
T0 T4
COUNT = 3 COUNT = 4
Figure 8, UV_FB trigger VIN power sensing
Power Off
Time (10ms/Div)
FB
UGATE (20V/Div)
VOUT
VIN
(500mV/Div)
(2V/Div)
(2V/Div)
VIN Power
Sensing
UV
IOUT = 2A
LDO Power Sequence
In VGA field, the MOSFET of LVOUT is sourced by external
voltage not by SVOUT.
This connection may trigger UV protection to shutdown
RT9218, but using the typical application circuit won't have
this issue. See figure 9 using OPS pin to control the power
sequence.
VIN_SW (5V/12V)
VIN_LDO (3.3V)
OPS_Disable
EnableShutdown
Figure 9. LDO power sequence
Under Voltage Protection
The voltage at FB and FBL pin is monitored and protected
against UV (under voltage). The UV threshold is the FB
or FBL under 75%. UV detection has 30μs triggered delay.
When OC or UV_FBL is trigged, a hiccup restart
sequence will be initialized, as shown in Figure 7 Only 4
times of trigger are allowed to latch off. Hiccup is disabled
during soft-start interval, but UV_FB has some difference
from OC and UV_FBL, it will always trigger VIN power
sensing after 4 times hiccup, as shown in Figure 8.
RT9218
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DS9218-09 April 2011 www.richtek.com
Figure 10. The connections of the critical components in the converter
+
+
LOAD
+
VCC GND
RT9218FB
LGATE
UGATE
IL
IQ1
VOUT
Q2
Q1
IQ2
5V/12V
GND
Figure 10 shows the connections of the critical components in the converter. Note that the capacitors CIN and COUT each
of them represents numerous physical capacitors. Use a dedicated grounding plane and use vias to ground all critical
components to this layer. Apply another solid layer as a power plane and cut this plane into smaller islands of common
voltage levels. The power plane should support the input power and output power nodes. Use copper filled polygons on
the top and bottom circuit layers for the PHASE node, but it is not necessary to oversize this particular island. Since the
PHASE node is subjected to very high dV/dt voltages, the stray capacitance formed between these island and the
surrounding circuitry will tend to couple switching noise. Use the remaining printed circuit layers for small signal
routing. The PCB traces between the PWM controller and the gate of MOSFET and also the traces connecting source
of MOSFETs should be sized to carry 2A peak currents.
Below PCB gerber files are our test board for your reference :
RT9218
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DS9218-09 April 2011www.richtek.com
RT9218
17
DS9218-09 April 2011 www.richtek.com
According to our test experience, you must still notice two items to avoid noise coupling :
1.The ground plane should not be separated.
2.VCC rail adding the LC filter is recommended.
RT9218
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DS9218-09 April 2011www.richtek.com
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
Richtek Technology Corporation
Headquarter
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 95, Minchiuan Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8862)86672399 Fax: (8862)86672377
Email: marketing@richtek.com
Outline Dimension
A
B
F
J
D
C
I
H
M
Dimensions In Mi ll imet e rs Dimensions In Inch e s
Symbol Min Max Min Max
A 8.534 8.738 0.336 0.344
B 3.810 3.988 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.508 0.013 0.020
F 1.194 1.346 0.047 0.053
H 0.178 0.254 0.007 0.010
I 0.102 0.254 0.004 0.010
J 5.791 6.198 0.228 0.244
M 0.406 1.270 0.016 0.050
14–Lead SOP Plastic Package
